71  * Args:     dram_info   ddr3 training information struct
102 	DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n");  in ddr3_pbs_tx()
113 	DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n");  in ddr3_pbs_tx()
120 		DEBUG_PBS_C("DDR3 - PBS TX - Working with pattern - ",  in ddr3_pbs_tx()
166 					DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n");  in ddr3_pbs_tx()
168 					DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n");  in ddr3_pbs_tx()
191 					DEBUG_PBS_S("DDR3 - PBS Tx - Pbs Rep Loop is ");  in ddr3_pbs_tx()
198 					DEBUG_PBS_S("DDR3 - PBS Tx - Set all PBS values to MIN\n");  in ddr3_pbs_tx()
215 					DEBUG_PBS_S("DDR3 - PBS Tx - ADLL shift right one phase before fail\n");  in ddr3_pbs_tx()
223 					DEBUG_PBS_S("DDR3 - PBS Tx - perform PBS for each bit\n");  in ddr3_pbs_tx()
238 					DEBUG_PBS_S("DDR3 - PBS Tx - FAIL - Adll reach max value\n");  in ddr3_pbs_tx()
242 				DEBUG_PBS_FULL_C("DDR3 - PBS TX - values for iteration - ",  in ddr3_pbs_tx()
249 					DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
291 		DEBUG_PBS_C("DDR3 - PBS TX - values for current pattern - ",  in ddr3_pbs_tx()
298 			DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
319 		DEBUG_PBS_C("DDR3 - PBS TX - Average for pattern - ",  in ddr3_pbs_tx()
343 	DEBUG_PBS_S("DDR3 - PBS TX - Average for all patterns:\n");  in ddr3_pbs_tx()
349 		DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_tx()
390 	DEBUG_PBS_S("DDR3 - PBS Tx - PBS TX ended successfuly\n");  in ddr3_pbs_tx()
398  * Args:     dram_info            ddr3 training information struct
491 		DEBUG_PBS_FULL_S("DDR3 - PBS Tx - Shift DQ - Adll value reached maximum\n");  in ddr3_tx_shift_dqs_adll_step_before_fail()
515  * Args:     dram_info   ddr3 training information struct
545 	DEBUG_PBS_S("DDR3 - PBS RX - Starting PBS RX procedure\n");  in ddr3_pbs_rx()
556 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - SW Override Enabled\n");  in ddr3_pbs_rx()
563 		DEBUG_PBS_FULL_C("DDR3 - PBS RX - Working with pattern - ",  in ddr3_pbs_rx()
608 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Enabled\n");  in ddr3_pbs_rx()
610 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Disabled\n");  in ddr3_pbs_rx()
632 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Pbs Rep Loop is ");  in ddr3_pbs_rx()
662 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift RX DQS to first fail\n");  in ddr3_pbs_rx()
668 						DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_rx_shift_dqs_to_first_fail failed.\n");  in ddr3_pbs_rx()
726 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - perform PBS for each bit\n");  in ddr3_pbs_rx()
732 						DEBUG_PBS_S("DDR3 - PBS Rx - ddr3_pbs_per_bit failed.");  in ddr3_pbs_rx()
741 					DEBUG_PBS_FULL_S("DDR3 - PBS Rx - FAIL - Algorithm failed doing RX PBS\n");  in ddr3_pbs_rx()
752 				DEBUG_PBS_FULL_C("DDR3 - PBS RX - values for iteration - ",  in ddr3_pbs_rx()
759 					DEBUG_PBS_FULL_S("DDR3 - PBS - PUP");  in ddr3_pbs_rx()
808 		DEBUG_PBS_FULL_C("DDR3 - PBS RX - Average for pattern - ",  in ddr3_pbs_rx()
823 		DEBUG_PBS_C("DDR3 - PBS RX - values for current pattern - ",  in ddr3_pbs_rx()
830 			DEBUG_PBS_S("DDR3 - PBS RX - PUP");  in ddr3_pbs_rx()
859 	DEBUG_PBS_S("DDR3 - PBS RX - Average for all patterns:\n");  in ddr3_pbs_rx()
865 		DEBUG_PBS_S("DDR3 - PBS - PUP");  in ddr3_pbs_rx()
902 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - ended successfuly\n");  in ddr3_pbs_rx()
910  * Args:     dram_info           ddr3 training information struct
953 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Starting...\n");  in ddr3_rx_shift_dqs_to_first_fail()
956 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Set DQS ADLL to Max for all PUPs\n");  in ddr3_rx_shift_dqs_to_first_fail()
971 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co…  in ddr3_rx_shift_dqs_to_first_fail()
980 				DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - fail on start with first deskew value\n");  in ddr3_rx_shift_dqs_to_first_fail()
997 				DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - DQS deskew reached maximum value\n");  in ddr3_rx_shift_dqs_to_first_fail()
1002 		DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - Inc DQS deskew for PUPs: ");  in ddr3_rx_shift_dqs_to_first_fail()
1017 	DEBUG_PBS_FULL_S("DDR3 - PBS RX - Shift DQS - ADLL shift one step before fail\n");  in ddr3_rx_shift_dqs_to_first_fail()
1029 …DEBUG_PBS_S("DDR3 - PBS Rx - Shift DQS - MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP(ddr3_sdram_co…  in ddr3_rx_shift_dqs_to_first_fail()
1062 			DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift DQS - Adll reach min value\n");  in ddr3_rx_shift_dqs_to_first_fail()
1093 	DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Lock PBS value for all remaining PUPs bits, pup ");  in lock_pups()
1173 	DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Started\n");  in ddr3_pbs_per_bit()
1204 				DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - All pups are locked for DQ ");  in ddr3_pbs_per_bit()
1255 						DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PbsCurrVal: ");  in ddr3_pbs_per_bit()
1288 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit -  All bit in all pups are successfully locked\n");  in ddr3_pbs_per_bit()
1294 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - PBS deskew elements reach max\n");  in ddr3_pbs_per_bit()
1299 			DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - StartOver: ");  in ddr3_pbs_per_bit()
1314 						DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - skipping lock of pup (first loop of pbs)",  in ddr3_pbs_per_bit()
1320 …DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - Locking pup %d (even though it wasn't supposed to be locked…  in ddr3_pbs_per_bit()
1326 					DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Locking remaning DQs for pup - ");  in ddr3_pbs_per_bit()
1354 					DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - Pup ");  in ddr3_pbs_per_bit()
1363 				DEBUG_PBS_FULL_S("DDR3 - PBS Per bit - false fail - returning to start\n");  in ddr3_pbs_per_bit()
1378 						DEBUG_PBS_FULL_C("DDR3 - PBS Per bit - First fail in pup ",  in ddr3_pbs_per_bit()
1425 	DEBUG_PBS_FULL_S("DDR3 - PBS - ddr3_set_pbs_results:\n");  in ddr3_set_pbs_results()
1450 		DEBUG_PBS_FULL_S("DDR3 - PBS - PUP");  in ddr3_set_pbs_results()