169 	u32 min_write_recovery_time;		/* DDR3/2 only */
170 	u32 min_write_to_read_cmd_delay;	/* DDR3/2 only */
171 	u32 min_read_to_prech_cmd_delay;	/* DDR3/2 only */
173 	u32 min_refresh_recovery;		/* DDR3/2 only */
255 	/* Check if DDR3 */  in ddr3_spd_init()
260 	/* No byte for error check in DDR3 SPD, use DDR2 convention */  in ddr3_spd_init()
329 	 * DDR3 device uiDensity val are: (device capacity/8) *  in ddr3_spd_init()
332 	/* Jedec SPD DDR3 - page 7, Save spd_data in Mb  - 2048=2GB */  in ddr3_spd_init()
366 	/* No byte for refresh interval in DDR3 SPD, use DDR2 convention */  in ddr3_spd_init()
387 	/* DDR3 include 2 byte of CAS support */  in ddr3_spd_init()
402 	 * For DDR3 and DDR2 includes Write Recovery Time field.  in ddr3_spd_init()
441 	 * For DDR3 and DDR2 includes Internal Write To Read Command Delay  in ddr3_spd_init()
449 	 * For DDR3 and DDR2 includes Internal Read To Precharge Command Delay  in ddr3_spd_init()
457 	 * For DDR3 includes Minimum Activate to Activate/Refresh Command  in ddr3_spd_init()
482 		DEBUG_INIT_C("DDR3 Training Sequence - Registered DIMM vendor ID 0x",  in ddr3_spd_init()
513 		DEBUG_INIT_S("DDR3 Dimm Compare - DIMM type does not match - FAIL\n");  in ddr3_spd_sum_init()
518 		DEBUG_INIT_S("DDR3 Dimm Compare - ECC does not match. ECC is disabled\n");  in ddr3_spd_sum_init()
521 		DEBUG_INIT_S("DDR3 Dimm Compare - DRAM bus width does not match - FAIL\n");  in ddr3_spd_sum_init()
615 		DEBUG_INIT_S("DDR3 Training Sequence - No DIMMs detected\n");
617 		DEBUG_INIT_S("DDR3 Training Sequence - FAILED (Wrong DIMMs Setup)\n");
621 		DEBUG_INIT_C("DDR3 Training Sequence - Number of DIMMs detected: ",
647 		DEBUG_INIT_C("DDR3 Training Sequence - Number of CS exceed limit -  ",
682 		DEBUG_INIT_C("DDR3 Training Sequence - Number of enabled CS exceed limit -  ",
687 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
709 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
719 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");
721 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");
726 		DEBUG_INIT_S("DDR3 Training Sequence - FAIL - Illegal R-DIMM setup\n");
730 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");
732 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");
742 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");
744 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
747 	DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
753 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");
755 		DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
767 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - RefreshInterval/Hclk = ", tmp, 4);
794 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRAS-1 = ", tmp, 1);
803 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRCD-1 = ", tmp, 1);
811 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRP-1 = ", tmp, 1);
819 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWR-1 = ", tmp, 1);
827 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tWTR-1 = ", tmp, 1);
835 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRRD-1 = ", tmp, 1);
843 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRTP-1 = ", tmp, 1);
860 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tRFC-1 = ", tmp, 1);
875 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW = ", tmp, 1);
884 	DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - tFAW-4*tRRD = ", tmp, 1);
954 	/*{0x0000142C}  -   DDR3 Timing Register */
1042 	DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Sample Delays = ", reg,
1054 	DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Read Data Ready Delays = ", reg, 1);
1145 	/*{0x000015E0} - DDR3 Rank Control Register */
1161 				DEBUG_INIT_FULL_C("DDR3 - SPD-SET - Setting Address Mirroring for CS = ",
1194 		DEBUG_INIT_S("DDR3 Training Sequence - Registered DIMM detected\n");