Lines Matching full:ddr3
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
134 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw()
143 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw()
168 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw()
172 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Error\n"); in ddr3_write_leveling_hw()
196 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Starting\n"); in ddr3_wl_supplement()
224 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled\n"); in ddr3_wl_supplement()
416 DEBUG_WL_C("DDR3 - Write Leveling Hi-Freq Supplement - didn't work for Cs - ", in ddr3_wl_supplement()
459 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully\n"); in ddr3_wl_supplement()
478 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw_reg_dimm()
481 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
572 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw_reg_dimm()
579 ("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw_reg_dimm()
603 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
644 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw_reg_dimm()
665 DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n"); in ddr3_write_leveling_sw()
685 /* 0x15D0 - DDR3 MR0 Register */ in ddr3_write_leveling_sw()
701 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw()
709 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw()
723 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw()
726 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Refresh X9\n"); in ddr3_write_leveling_sw()
744 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw()
753 reg_write(REG_DDR3_MR1_ADDR, reg); /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
771 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw()
792 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw()
794 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -", in ddr3_write_leveling_sw()
805 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
843 /* 0x15D0 - DDR3 MR1 Register */ in ddr3_write_leveling_sw()
867 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw()
889 DEBUG_WL_S("DDR3 - Write Leveling - Starting SW WL procedure\n"); in ddr3_write_leveling_sw_reg_dimm()
920 /* 0x15D0 - DDR3 MR0 Register */ in ddr3_write_leveling_sw_reg_dimm()
936 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Qoff and RTT Values are set for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
944 DEBUG_WL_FULL_S("DDR3 - Write Leveling - SW Override Enabled\n"); in ddr3_write_leveling_sw_reg_dimm()
956 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Starting working with Cs - ", in ddr3_write_leveling_sw_reg_dimm()
960 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Refresh X9\n"); in ddr3_write_leveling_sw_reg_dimm()
981 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Configure MR1 for current Cs: WL-on,OB-on\n"); in ddr3_write_leveling_sw_reg_dimm()
993 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
1012 DEBUG_WL_FULL_C("DDR3 - Write Leveling single Cs - FAILED - Cs - ", in ddr3_write_leveling_sw_reg_dimm()
1027 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw_reg_dimm()
1029 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -", in ddr3_write_leveling_sw_reg_dimm()
1037 /* 0x15D4 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
1075 /* 0x15D0 - DDR3 MR1 Register */ in ddr3_write_leveling_sw_reg_dimm()
1109 DEBUG_WL_FULL_S("DDR3 - Write Leveling - Finished WL procedure for all Cs\n"); in ddr3_write_leveling_sw_reg_dimm()
1134 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - WL for Cs - ", in ddr3_write_leveling_single_cs()
1171 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - ODT Asserted for current Cs\n"); in ddr3_write_leveling_single_cs()
1187 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Current Cs\n"); in ddr3_write_leveling_single_cs()
1190 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Driving DQS high for one cycle\n"); in ddr3_write_leveling_single_cs()
1218 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Shift DQS + Octet Leveling\n"); in ddr3_write_leveling_single_cs()
1229 DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge: Phase = "); in ddr3_write_leveling_single_cs()
1258 DEBUG_WL_FULL_C("DDR3 - Write Leveling Single Cs - Seek Edge: Results = ", in ddr3_write_leveling_single_cs()
1294 DEBUG_WL_S("DDR3 - Write Leveling Single Cs - Seek Edge: All Locked\n"); in ddr3_write_leveling_single_cs()
1300 DEBUG_WL_C("DDR3 - Write Leveling - Results for CS - ", (u32) cs, 1); in ddr3_write_leveling_single_cs()
1302 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_single_cs()
1313 DEBUG_WL_S("DDR3 - Write Leveling - ERROR - not all PUPS were locked\n"); in ddr3_write_leveling_single_cs()
1336 * Perform DDR3 Control PUP Indirect Write