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/openbmc/u-boot/drivers/ddr/fsl/
H A Dfsl_ddr_gen4.c42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
47 * Dividing the initialization to two steps to deassert DDR reset signal
54 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
89 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
105 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen3.c16 * regs has the to-be-set values for DDR controller registers
17 * ctrl_num is the DDR controller number
21 * Dividing the initialization to two steps to deassert DDR reset signal
28 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Darm_ddr_gen3.c22 * regs has the to-be-set values for DDR controller registers
23 * ctrl_num is the DDR controller number
27 * Dividing the initialization to two steps to deassert DDR reset signal
34 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
67 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc86xx_ddr.c18 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
22 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
25 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen2.c19 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
34 * Set the DDR IO receiver to an acceptable bias point. in fsl_ddr_set_memctl_regs()
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c18 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
29 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
[all …]
H A Dctrl_regs.c8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
289 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
291 * Avoid writing for DDR I. The new PQ38 DDR controller
295 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c19 struct ccsr_ddr __iomem *ddr = in sdram_init() local
22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
[all …]
/openbmc/u-boot/board/sbc8641d/
H A Dsbc8641d.c51 debug (" DDR: "); in dram_init()
99 volatile struct ccsr_ddr *ddr = &immap->im_ddr1; in fixed_sdram() local
101 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
102 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; in fixed_sdram()
103 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
104 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; in fixed_sdram()
105 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
106 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; in fixed_sdram()
107 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
108 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; in fixed_sdram()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
42 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
48 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
127 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
158 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
170 debug("DDR: Module mem type is %02X\n", spd.mem_type); in spd_sdram()
182 printf("DDR: The number of physical bank is %02X\n", n_ranks); in spd_sdram()
[all …]
H A Decc.c18 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
20 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
24 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); in ecc_print_status()
29 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); in ecc_print_status()
31 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); in ecc_print_status()
33 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); in ecc_print_status()
38 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); in ecc_print_status()
40 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); in ecc_print_status()
42 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); in ecc_print_status()
46 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
28 {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
[all …]
/openbmc/u-boot/post/cpu/mpc83xx/
H A Decc.c23 static inline void ecc_clear(ddr83xx_t *ddr) in ecc_clear() argument
26 __raw_writel(0, &ddr->capture_address); in ecc_clear()
27 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
28 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
29 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
30 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
33 out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT); in ecc_clear()
36 out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\ in ecc_clear()
50 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
62 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
[all …]
H A Dqca,ath79-ddr-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
7 title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to
14 flush the FIFO between various devices and the DDR. This is mainly used by
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
[all …]
/openbmc/u-boot/board/sbc8548/
H A Dddr.c59 * existed on earlier boards; the workaround moved the DDR
79 printf("DDR: failed to read SPD from addr %u\n", i2c_address); in get_spd()
91 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
94 out_be32(&ddr->cs0_bnds, 0x0000007f); in fixed_sdram()
95 out_be32(&ddr->cs1_bnds, 0x008000ff); in fixed_sdram()
96 out_be32(&ddr->cs2_bnds, 0x00000000); in fixed_sdram()
97 out_be32(&ddr->cs3_bnds, 0x00000000); in fixed_sdram()
99 out_be32(&ddr->cs0_config, 0x80010101); in fixed_sdram()
100 out_be32(&ddr->cs1_config, 0x80010101); in fixed_sdram()
101 out_be32(&ddr->cs2_config, 0x00000000); in fixed_sdram()
[all …]
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c22 struct ccsr_ddr __iomem *ddr = in sdram_init() local
25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/imx8mp/sys/
H A Dmetrics.json3 "BriefDescription": "bytes of all masters read from ddr",
11 "BriefDescription": "bytes of all masters write to ddr",
19 "BriefDescription": "bytes of a53 core read from ddr",
27 "BriefDescription": "bytes of a53 core write to ddr",
35 "BriefDescription": "bytes of supermix(m7) core read from ddr",
43 "BriefDescription": "bytes of supermix(m7) write to ddr",
51 "BriefDescription": "bytes of gpu 3d read from ddr",
59 "BriefDescription": "bytes of gpu 3d write to ddr",
67 "BriefDescription": "bytes of gpu 2d read from ddr",
75 "BriefDescription": "bytes of gpu 2d write to ddr",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr-pmu
[all …]
/openbmc/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c48 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; in ddrmc_init() local
51 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
53 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
54 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
56 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
57 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
58 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
59 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
60 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/openbmc/u-boot/board/mpc8308_p1m/
H A Dsdram.c36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
40 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
48 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
49 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/openbmc/u-boot/board/freescale/mpc8308rdb/
H A Dsdram.c40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
44 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
52 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A Dsdram.c57 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
58 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
61 im->ddr.cs_config[1] = 0; in fixed_sdram()
63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
64 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
66 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
70 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; in fixed_sdram()
72 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
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