Lines Matching full:ddr

19 	struct ccsr_ddr __iomem *ddr =  in sdram_init()  local
22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); in sdram_init()
35 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); in sdram_init()
36 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); in sdram_init()
38 __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); in sdram_init()
39 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); in sdram_init()
40 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); in sdram_init()
42 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
43 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
44 __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); in sdram_init()
46 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
48 __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); in sdram_init()
49 __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); in sdram_init()
50 __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); in sdram_init()
51 __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); in sdram_init()
52 __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); in sdram_init()
53 __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); in sdram_init()
54 __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); in sdram_init()
55 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); in sdram_init()
56 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); in sdram_init()
58 __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); in sdram_init()
59 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); in sdram_init()
60 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); in sdram_init()
62 puts("Not a valid DDR Freq Found! Please Reset\n"); in sdram_init()
68 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); in sdram_init()