23 static inline void ecc_clear(ddr83xx_t *ddr)  in ecc_clear()  argument
26 	__raw_writel(0, &ddr->capture_address);  in ecc_clear()
27 	__raw_writel(0, &ddr->capture_data_hi);  in ecc_clear()
28 	__raw_writel(0, &ddr->capture_data_lo);  in ecc_clear()
29 	__raw_writel(0, &ddr->capture_ecc);  in ecc_clear()
30 	__raw_writel(0, &ddr->capture_attributes);  in ecc_clear()
33 	out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);  in ecc_clear()
36 	out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\  in ecc_clear()
50 	ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr;  in ecc_post_test()  local
62 	if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) {  in ecc_post_test()
63 		debug("DDR's ECC is not enabled, skipping the ECC POST.\n");  in ecc_post_test()
79 		ecc_clear(ddr);  in ecc_post_test()
82 		setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);  in ecc_post_test()
88 			__raw_writel(1 << errbit, &ddr->data_err_inject_lo);  in ecc_post_test()
89 			__raw_writel(0, &ddr->data_err_inject_hi);  in ecc_post_test()
91 			__raw_writel(0, &ddr->data_err_inject_lo);  in ecc_post_test()
92 			__raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi);  in ecc_post_test()
102 		clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);  in ecc_post_test()
110 		if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) ||  in ecc_post_test()
111 			(__raw_readl(&ddr->data_err_inject_hi) !=  in ecc_post_test()
112 			(__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) ||  in ecc_post_test()
113 			(__raw_readl(&ddr->data_err_inject_lo) !=  in ecc_post_test()
114 			(__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) {  in ecc_post_test()
119 				ddr->data_err_inject_hi,  in ecc_post_test()
120 				ddr->data_err_inject_lo,  in ecc_post_test()
124 			printf("ERR_DETECT Reg: %08x\n", ddr->err_detect);  in ecc_post_test()
126 				ddr->capture_data_hi, ddr->capture_data_lo);  in ecc_post_test()
140 	ecc_clear(ddr);  in ecc_post_test()