Lines Matching full:ddr
16 * regs has the to-be-set values for DDR controller registers
17 * ctrl_num is the DDR controller number
21 * Dividing the initialization to two steps to deassert DDR reset signal
28 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
58 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
93 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
95 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
98 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
99 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
100 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
103 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
108 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
109 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
110 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
114 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
115 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
116 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
117 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
118 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
119 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
120 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
121 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
122 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
123 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
124 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
125 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
126 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
127 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
128 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
129 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
130 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
131 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
132 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
133 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
141 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
143 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
146 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
147 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
148 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
149 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
152 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
154 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); in fsl_ddr_set_memctl_regs()
155 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); in fsl_ddr_set_memctl_regs()
158 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
164 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
165 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
166 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
168 out_be32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
173 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
178 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
179 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
185 * control register is set. Because all DDR components are connected to in fsl_ddr_set_memctl_regs()
199 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
203 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
204 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
205 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
206 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
208 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
209 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
210 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
211 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
212 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
213 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); in fsl_ddr_set_memctl_regs()
214 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
217 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
222 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
231 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
233 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
242 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
251 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
253 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
262 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
271 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
273 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
282 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
291 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
293 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
302 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
311 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
313 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
324 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
327 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
328 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
329 out_be32(&ddr->debug[2], 0x0); in fsl_ddr_set_memctl_regs()
330 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
331 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
333 out_be32(&ddr->debug[12], save1); in fsl_ddr_set_memctl_regs()
334 out_be32(&ddr->debug[21], save2); in fsl_ddr_set_memctl_regs()
335 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
340 * For 8572 DDR1 erratum - DDR controller may enter illegal state in fsl_ddr_set_memctl_regs()
346 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) in fsl_ddr_set_memctl_regs()
347 && in_be32(&ddr->sdram_cfg) & 0x80000) { in fsl_ddr_set_memctl_regs()
349 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
364 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
366 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
369 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
370 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
376 * the DDR clock setup and the DDR config enable. in fsl_ddr_set_memctl_regs()
386 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
389 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
392 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
395 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
420 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
432 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
445 clrbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
446 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
450 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
452 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
455 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
456 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
461 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
464 out_be32(&ddr->debug[5], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
465 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); in fsl_ddr_set_memctl_regs()
468 out_be32(&ddr->debug[6], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
469 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); in fsl_ddr_set_memctl_regs()
472 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
473 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
476 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
480 clrbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
481 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
484 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
486 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
490 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
491 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
494 while (in_be32(&ddr->debug[1]) & 0x400) in fsl_ddr_set_memctl_regs()
502 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
504 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
509 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
527 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ in fsl_ddr_set_memctl_regs()
530 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
533 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
537 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
540 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
544 clrbits_be32(&ddr->sdram_cfg, 0x2); in fsl_ddr_set_memctl_regs()
550 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()