51 	debug ("    DDR: ");  in dram_init()
99 	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;  in fixed_sdram()  local
101 	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;  in fixed_sdram()
102 	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;  in fixed_sdram()
103 	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;  in fixed_sdram()
104 	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;  in fixed_sdram()
105 	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
106 	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;  in fixed_sdram()
107 	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;  in fixed_sdram()
108 	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;  in fixed_sdram()
109 	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;  in fixed_sdram()
110 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;  in fixed_sdram()
111 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
112 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
113 	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;  in fixed_sdram()
114 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;  in fixed_sdram()
115 	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;  in fixed_sdram()
116 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;  in fixed_sdram()
117 	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;  in fixed_sdram()
118 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
119 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;  in fixed_sdram()
120 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;  in fixed_sdram()
126 	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;  in fixed_sdram()
130 	ddr = &immap->im_ddr2;  in fixed_sdram()
132 	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;  in fixed_sdram()
133 	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;  in fixed_sdram()
134 	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;  in fixed_sdram()
135 	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;  in fixed_sdram()
136 	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;  in fixed_sdram()
137 	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;  in fixed_sdram()
138 	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;  in fixed_sdram()
139 	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;  in fixed_sdram()
140 	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;  in fixed_sdram()
141 	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;  in fixed_sdram()
142 	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;  in fixed_sdram()
143 	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;  in fixed_sdram()
144 	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;  in fixed_sdram()
145 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;  in fixed_sdram()
146 	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;  in fixed_sdram()
147 	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;  in fixed_sdram()
148 	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;  in fixed_sdram()
149 	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;  in fixed_sdram()
150 	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;  in fixed_sdram()
151 	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;  in fixed_sdram()
157 	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;  in fixed_sdram()