Lines Matching full:ddr
42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
47 * Dividing the initialization to two steps to deassert DDR reset signal
54 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
89 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
105 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
112 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
114 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
118 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
119 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
121 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
125 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
130 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
135 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
138 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
140 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
141 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
145 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
148 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
150 ddr_out32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
151 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
155 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
156 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
157 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
158 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
159 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
160 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
161 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); in fsl_ddr_set_memctl_regs()
162 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); in fsl_ddr_set_memctl_regs()
163 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); in fsl_ddr_set_memctl_regs()
164 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
165 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
166 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); in fsl_ddr_set_memctl_regs()
167 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); in fsl_ddr_set_memctl_regs()
168 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); in fsl_ddr_set_memctl_regs()
169 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); in fsl_ddr_set_memctl_regs()
170 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); in fsl_ddr_set_memctl_regs()
171 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
172 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
173 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
174 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
175 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
176 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
177 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
178 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
179 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); in fsl_ddr_set_memctl_regs()
180 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); in fsl_ddr_set_memctl_regs()
181 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); in fsl_ddr_set_memctl_regs()
182 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); in fsl_ddr_set_memctl_regs()
183 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); in fsl_ddr_set_memctl_regs()
184 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); in fsl_ddr_set_memctl_regs()
185 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); in fsl_ddr_set_memctl_regs()
186 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); in fsl_ddr_set_memctl_regs()
187 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
189 ddr_out32(&ddr->sdram_interval, in fsl_ddr_set_memctl_regs()
192 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
194 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
195 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
203 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
205 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
208 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
209 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
210 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
211 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); in fsl_ddr_set_memctl_regs()
212 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); in fsl_ddr_set_memctl_regs()
213 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); in fsl_ddr_set_memctl_regs()
214 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); in fsl_ddr_set_memctl_regs()
217 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
219 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); in fsl_ddr_set_memctl_regs()
220 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); in fsl_ddr_set_memctl_regs()
223 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
228 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
229 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
230 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
231 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
238 ddr_out32(&ddr->ddr_sdram_rcw_2, in fsl_ddr_set_memctl_regs()
241 ddr_out32(&ddr->err_disable, regs->err_disable | in fsl_ddr_set_memctl_regs()
245 ddr_out32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
247 ddr_out32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
252 ddr_out32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
260 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
263 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
265 ddr_out32(&ddr->debug[28], temp32); in fsl_ddr_set_memctl_regs()
266 ddr_out32(&ddr->debug[25], 0x9000); in fsl_ddr_set_memctl_regs()
269 ddr_out32(&ddr->debug[37], 1 << 31); in fsl_ddr_set_memctl_regs()
271 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
281 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
286 temp32 = ddr_in32(&ddr->debug[25]); in fsl_ddr_set_memctl_regs()
289 ddr_out32(&ddr->debug[25], temp32); in fsl_ddr_set_memctl_regs()
295 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
296 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000); in fsl_ddr_set_memctl_regs()
302 * control register is set. Because all DDR components are connected to in fsl_ddr_set_memctl_regs()
316 ddr_out32(&ddr->sdram_cfg, temp32); in fsl_ddr_set_memctl_regs()
320 * the DDR clock setup and the DDR config enable. in fsl_ddr_set_memctl_regs()
331 temp32 = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
333 ddr_out32(&ddr->sdram_cfg_2, temp32); in fsl_ddr_set_memctl_regs()
337 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
340 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()
342 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
351 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && in fsl_ddr_set_memctl_regs()
358 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
379 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
384 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
389 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
394 ddr_out32(&ddr->sdram_md_cntl, 0); in fsl_ddr_set_memctl_regs()
395 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
397 ddr_out32(&ddr->debug[28], temp32); in fsl_ddr_set_memctl_regs()
398 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ in fsl_ddr_set_memctl_regs()
401 while (!(ddr_in32(&ddr->debug[1]) & 0x2) && in fsl_ddr_set_memctl_regs()
408 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
420 set_wait_for_bits_clear(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
429 ddr_out32(&ddr->err_disable, in fsl_ddr_set_memctl_regs()
434 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
457 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
466 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
477 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds); in fsl_ddr_set_memctl_regs()
479 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds); in fsl_ddr_set_memctl_regs()
481 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds); in fsl_ddr_set_memctl_regs()
483 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds); in fsl_ddr_set_memctl_regs()
487 ddr_out32(&ddr->cs0_config, regs->cs[0].config); in fsl_ddr_set_memctl_regs()
491 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
497 temp32 = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
499 ddr_out32(&ddr->sdram_cfg_2, temp32); in fsl_ddr_set_memctl_regs()
513 cs0_config = ddr_in32(&ddr->cs0_config); in fsl_ddr_set_memctl_regs()
514 cs0_bnds = ddr_in32(&ddr->cs0_bnds); in fsl_ddr_set_memctl_regs()
515 cs1_bnds = ddr_in32(&ddr->cs1_bnds); in fsl_ddr_set_memctl_regs()
516 cs2_bnds = ddr_in32(&ddr->cs2_bnds); in fsl_ddr_set_memctl_regs()
517 cs3_bnds = ddr_in32(&ddr->cs3_bnds); in fsl_ddr_set_memctl_regs()
520 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
521 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
522 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
523 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
525 ddr_out32(&ddr->mtp1, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
526 ddr_out32(&ddr->mtp2, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
527 ddr_out32(&ddr->mtp3, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
528 ddr_out32(&ddr->mtp4, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
529 ddr_out32(&ddr->mtp5, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
530 ddr_out32(&ddr->mtp6, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
531 ddr_out32(&ddr->mtp7, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
532 ddr_out32(&ddr->mtp8, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
533 ddr_out32(&ddr->mtp9, BIST_PATTERN1); in fsl_ddr_set_memctl_regs()
534 ddr_out32(&ddr->mtp10, BIST_PATTERN2); in fsl_ddr_set_memctl_regs()
536 ddr_out32(&ddr->mtcr, mtcr); in fsl_ddr_set_memctl_regs()
541 mtcr = ddr_in32(&ddr->mtcr); in fsl_ddr_set_memctl_regs()
547 err_detect = ddr_in32(&ddr->err_detect); in fsl_ddr_set_memctl_regs()
548 err_sbe = ddr_in32(&ddr->err_sbe); in fsl_ddr_set_memctl_regs()
560 ddr_out32(&ddr->cs0_bnds, cs0_bnds); in fsl_ddr_set_memctl_regs()
561 ddr_out32(&ddr->cs1_bnds, cs1_bnds); in fsl_ddr_set_memctl_regs()
562 ddr_out32(&ddr->cs2_bnds, cs2_bnds); in fsl_ddr_set_memctl_regs()
563 ddr_out32(&ddr->cs3_bnds, cs3_bnds); in fsl_ddr_set_memctl_regs()