1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 28bd522ceSDave Liu /* 38bd522ceSDave Liu * Copyright (C) 2007 Freescale Semiconductor, Inc. 48bd522ceSDave Liu * 58bd522ceSDave Liu * Authors: Nick.Spence@freescale.com 68bd522ceSDave Liu * Wilson.Lo@freescale.com 78bd522ceSDave Liu * scottwood@freescale.com 88bd522ceSDave Liu */ 98bd522ceSDave Liu 108bd522ceSDave Liu #include <common.h> 118bd522ceSDave Liu #include <mpc83xx.h> 128bd522ceSDave Liu #include <spd_sdram.h> 138bd522ceSDave Liu 148bd522ceSDave Liu #include <asm/bitops.h> 158bd522ceSDave Liu #include <asm/io.h> 168bd522ceSDave Liu 178bd522ceSDave Liu #include <asm/processor.h> 188bd522ceSDave Liu 198bd522ceSDave Liu DECLARE_GLOBAL_DATA_PTR; 208bd522ceSDave Liu resume_from_sleep(void)218bd522ceSDave Liustatic void resume_from_sleep(void) 228bd522ceSDave Liu { 238bd522ceSDave Liu u32 magic = *(u32 *)0; 248bd522ceSDave Liu 258bd522ceSDave Liu typedef void (*func_t)(void); 268bd522ceSDave Liu func_t resume = *(func_t *)4; 278bd522ceSDave Liu 288bd522ceSDave Liu if (magic == 0xf5153ae5) 298bd522ceSDave Liu resume(); 308bd522ceSDave Liu 318bd522ceSDave Liu gd->flags &= ~GD_FLG_SILENT; 328bd522ceSDave Liu puts("\nResume from sleep failed: bad magic word\n"); 338bd522ceSDave Liu } 348bd522ceSDave Liu 358bd522ceSDave Liu /* Fixed sdram init -- doesn't use serial presence detect. 368bd522ceSDave Liu * 378bd522ceSDave Liu * This is useful for faster booting in configs where the RAM is unlikely 388bd522ceSDave Liu * to be changed, or for things like NAND booting where space is tight. 398bd522ceSDave Liu */ 402e95004dSAnton Vorontsov #ifndef CONFIG_SYS_RAMBOOT fixed_sdram(void)418bd522ceSDave Liustatic long fixed_sdram(void) 428bd522ceSDave Liu { 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; 458bd522ceSDave Liu u32 msize_log2 = __ilog2(msize); 468bd522ceSDave Liu 476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 488bd522ceSDave Liu im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; 508bd522ceSDave Liu 518bd522ceSDave Liu /* 528bd522ceSDave Liu * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], 538bd522ceSDave Liu * or the DDR2 controller may fail to initialize correctly. 548bd522ceSDave Liu */ 552e95004dSAnton Vorontsov __udelay(50000); 568bd522ceSDave Liu 578bd522ceSDave Liu im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; 598bd522ceSDave Liu 608bd522ceSDave Liu /* Currently we use only one CS, so disable the other bank. */ 618bd522ceSDave Liu im->ddr.cs_config[1] = 0; 628bd522ceSDave Liu 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 688bd522ceSDave Liu 698bd522ceSDave Liu if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; 718bd522ceSDave Liu else 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 738bd522ceSDave Liu 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 778bd522ceSDave Liu 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 798bd522ceSDave Liu sync(); 808bd522ceSDave Liu 818bd522ceSDave Liu /* enable DDR controller */ 828bd522ceSDave Liu im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 838bd522ceSDave Liu sync(); 848bd522ceSDave Liu 858bd522ceSDave Liu return msize; 868bd522ceSDave Liu } 872e95004dSAnton Vorontsov #else fixed_sdram(void)882e95004dSAnton Vorontsovstatic long fixed_sdram(void) 892e95004dSAnton Vorontsov { 902e95004dSAnton Vorontsov return CONFIG_SYS_DDR_SIZE * 1024 * 1024; 912e95004dSAnton Vorontsov } 922e95004dSAnton Vorontsov #endif /* CONFIG_SYS_RAMBOOT */ 938bd522ceSDave Liu dram_init(void)94f1683aa7SSimon Glassint dram_init(void) 958bd522ceSDave Liu { 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; 978bd522ceSDave Liu u32 msize; 988bd522ceSDave Liu 998bd522ceSDave Liu if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 100088454cdSSimon Glass return -ENXIO; 1018bd522ceSDave Liu 1028bd522ceSDave Liu /* DDR SDRAM */ 1038bd522ceSDave Liu msize = fixed_sdram(); 1048bd522ceSDave Liu 1058bd522ceSDave Liu if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) 1068bd522ceSDave Liu resume_from_sleep(); 1078bd522ceSDave Liu 108088454cdSSimon Glass /* set total bus SDRAM size(bytes) -- DDR */ 109088454cdSSimon Glass gd->ram_size = msize; 110088454cdSSimon Glass 111088454cdSSimon Glass return 0; 1128bd522ceSDave Liu } 113