18 	struct ccsr_ddr __iomem *ddr =  in fsl_ddr_set_memctl_regs()  local
28 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
29 			out_be32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
32 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
33 			out_be32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
36 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
37 			out_be32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
40 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
41 			out_be32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
45 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);  in fsl_ddr_set_memctl_regs()
46 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
47 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);  in fsl_ddr_set_memctl_regs()
48 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
50 	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);  in fsl_ddr_set_memctl_regs()
55 	 * the DDR clock setup and the DDR config enable.  in fsl_ddr_set_memctl_regs()
60 	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);  in fsl_ddr_set_memctl_regs()
74 	struct ccsr_ddr __iomem *ddr =  in ddr_enable_ecc()  local
82 	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);  in ddr_enable_ecc()
83 	ddr->err_disable = 0x00000000;  in ddr_enable_ecc()
85 	debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);  in ddr_enable_ecc()