| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
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| H A D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
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| H A D | arm,corstone1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
21 a secure SoC for a range of rich IoT applications, for example gateways, smart
[all …]
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| H A D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
14 with a Snoop Control Unit. The register range is usually 256 (0x100)
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
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| H A D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
[all …]
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| H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
23 as a generic platform to test different FPGA designs, and has
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
[all …]
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| /openbmc/linux/arch/arm64/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
260 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
301 # VA_BITS - PAGE_SHIFT - 3
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
428 A/D updates can occur after a PTE has been marked invalid.
432 at stage-2.
440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
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| /openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/ |
| H A D | 0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch | 3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 Makefile.all.am | 6 +++---
18 helgrind/tests/Makefile.am | 6 +++---
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| H A D | use-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch | 3 Date: Tue, 19 Jan 2016 16:00:00 -0800
4 Subject: [PATCH] use appropriate -march/-mcpu/-mfpu for ARM test apps
7 -march/-mcpu/-mfpu flags to support the instructions being tested.
12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
14 over-ride that).
18 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
20 Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
21 ---
22 none/tests/arm/Makefile.am | 6 ++++--
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
[all …]
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| /openbmc/linux/Documentation/translations/zh_TW/arch/arm64/ |
| H A D | silicon-errata.txt | 1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
41 A 類：無可行補救措施的嚴重缺陷。
50 情況下，爲將 A 類缺陷當作 C 類處理，可能需要用類似的手段。這些手段被
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
[all …]
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| /openbmc/linux/Documentation/translations/zh_CN/arch/arm64/ |
| H A D | silicon-errata.txt | 1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
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| /openbmc/qemu/docs/system/arm/ |
| H A D | mps2.rst | 1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
6 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
19 Cortex-M3 as documented in Arm Application Note AN385
20 ``mps2-an386``
21 Cortex-M4 as documented in Arm Application Note AN386
[all …]
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| H A D | virt.rst | 4 The ``virt`` board is a platform which does not correspond to any
7 a guest such as Linux and do not care about reproducing the
8 idiosyncrasies and limitations of a particular bit of real-world
11 This is a "versioned" board model, so as well as the ``virt`` machine
13 changes between QEMU versions) a version is provided that guarantees
16 ``virt-5.0`` machine type will behave like the ``virt`` machine from
17 the QEMU 5.0 release, and migration should work between ``virt-5.0``
18 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
20 the non-versioned ``virt`` machine type.
27 - PCI/PCIe devices
[all …]
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| H A D | stm32.rst | 1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
21 The following machines are based on this ARM Cortex-M4F chip :
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | Kconfig | 11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
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| /openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8-2a/ |
| H A D | tune-cortexa75-cortexa55.inc | 2 # Tune Settings for big.LITTLE Cortex-A75 - Cortex-A55
4 DEFAULTTUNE ?= "cortexa75-cortexa55"
6 TUNEVALID[cortexa75-cortexa55] = "Enable big.LITTLE Cortex-A75.Cortex-A55 specific processor optimi…
7 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa75-cortexa55", "cortexa75-cortex…
8 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa75-cortexa55", " -mcpu=cortex-a75.cortex-a5…
10 require conf/machine/include/arm/arch-armv8-2a.inc
12 AVAILTUNES += "cortexa75-cortexa55 cortexa75-cortexa55-cryp…
13 ARMPKGARCH:tune-cortexa75-cortexa55 = "cortexa75-cortexa55"
14 ARMPKGARCH:tune-cortexa75-cortexa55-crypto = "cortexa75-cortexa55-crypto"
15 # We do not want -march since -mcpu is added above to cover for it
[all …]
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| H A D | tune-cortexa76-cortexa55.inc | 2 # Tune Settings for big.LITTLE Cortex-A76 - Cortex-A55
4 DEFAULTTUNE ?= "cortexa76-cortexa55"
6 TUNEVALID[cortexa76-cortexa55] = "Enable big.LITTLE Cortex-A76.Cortex-A55 specific processor optimi…
7 MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES", "cortexa76-cortexa55", "cortexa76-cortex…
8 …ARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa76-cortexa55", " -mcpu=cortex-a76.cortex-a5…
10 require conf/machine/include/arm/arch-armv8-2a.inc
12 AVAILTUNES += "cortexa76-cortexa55 cortexa76-cortexa55-cryp…
13 ARMPKGARCH:tune-cortexa76-cortexa55 = "cortexa76-cortexa55"
14 ARMPKGARCH:tune-cortexa76-cortexa55-crypto = "cortexa76-cortexa55-crypto"
15 # We do not want -march since -mcpu is added above to cover for it
[all …]
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
150 The ARM series is a line of low-power-consumption RISC chip designs
152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
153 manufactured, but legacy ARM-based PC hardware remains popular in
154 Europe. There is an ARM Linux project with a web page at
163 relocations, which have been around for a long time, but were not
164 supported in LLD until version 14. The combined range is -/+ 256 MiB,
181 size. This works well for buffers up to a few hundreds kilobytes, but
182 for larger buffers it just a waste of address space. Drivers which has
184 virtual space with just a few allocations.
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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| /openbmc/linux/arch/arm/mach-versatile/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | silicon-errata.rst | 10 so-called "errata", which can cause it to deviate from the architecture
15 Category A A critical error without a viable workaround.
16 Category B A significant or critical error with an acceptable
18 Category C A minor error that is not expected to occur under normal
27 treatment in the operating system. For example, avoiding a particular
28 sequence of code, or configuring the processor in a particular way. A
30 a Category A erratum into a Category C erratum. These are collectively
32 cases (e.g. those cases that both require a non-secure workaround *and*
36 the erratum in question, a Kconfig entry is added under "Kernel
37 Features" -> "ARM errata workarounds via the alternatives framework".
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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| /openbmc/linux/arch/arm/boot/dts/arm/ |
| H A D | arm-realview-eb-a9mp.dts | 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
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| /openbmc/linux/arch/arm64/kernel/ |
| H A D | cpu_errata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range()
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range()
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in is_affected_midr_range()
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); in is_affected_midr_range_list()
55 return model == entry->midr_range.model; in is_kryo_midr()
70 * a consistent CTR_EL0 to make sure that applications behaves in has_mismatched_cache_type()
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : in has_mismatched_cache_type()
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. in has_mismatched_cache_type()
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