Lines Matching +full:cortex +full:- +full:a
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
88 - apple,avalanche
89 - apple,blizzard
90 - apple,icestorm
91 - apple,firestorm
92 - arm,arm710t
93 - arm,arm720t
94 - arm,arm740t
95 - arm,arm7ej-s
96 - arm,arm7tdmi
97 - arm,arm7tdmi-s
98 - arm,arm9es
99 - arm,arm9ej-s
100 - arm,arm920t
101 - arm,arm922t
102 - arm,arm925
103 - arm,arm926e-s
104 - arm,arm926ej-s
105 - arm,arm940t
106 - arm,arm946e-s
107 - arm,arm966e-s
108 - arm,arm968e-s
109 - arm,arm9tdmi
110 - arm,arm1020e
111 - arm,arm1020t
112 - arm,arm1022e
113 - arm,arm1026ej-s
114 - arm,arm1136j-s
115 - arm,arm1136jf-s
116 - arm,arm1156t2-s
117 - arm,arm1156t2f-s
118 - arm,arm1176jzf
119 - arm,arm1176jz-s
120 - arm,arm1176jzf-s
121 - arm,arm11mpcore
122 - arm,armv8 # Only for s/w models
123 - arm,cortex-a5
124 - arm,cortex-a7
125 - arm,cortex-a8
126 - arm,cortex-a9
127 - arm,cortex-a12
128 - arm,cortex-a15
129 - arm,cortex-a17
130 - arm,cortex-a32
131 - arm,cortex-a34
132 - arm,cortex-a35
133 - arm,cortex-a53
134 - arm,cortex-a55
135 - arm,cortex-a57
136 - arm,cortex-a65
137 - arm,cortex-a72
138 - arm,cortex-a73
139 - arm,cortex-a75
140 - arm,cortex-a76
141 - arm,cortex-a77
142 - arm,cortex-a78
143 - arm,cortex-a78ae
144 - arm,cortex-a78c
145 - arm,cortex-a510
146 - arm,cortex-a520
147 - arm,cortex-a710
148 - arm,cortex-a715
149 - arm,cortex-a720
150 - arm,cortex-m0
151 - arm,cortex-m0+
152 - arm,cortex-m1
153 - arm,cortex-m3
154 - arm,cortex-m4
155 - arm,cortex-r4
156 - arm,cortex-r5
157 - arm,cortex-r7
158 - arm,cortex-r52
159 - arm,cortex-x1
160 - arm,cortex-x1c
161 - arm,cortex-x2
162 - arm,cortex-x3
163 - arm,cortex-x4
164 - arm,neoverse-e1
165 - arm,neoverse-n1
166 - arm,neoverse-n2
167 - arm,neoverse-v1
168 - brcm,brahma-b15
169 - brcm,brahma-b53
170 - brcm,vulcan
171 - cavium,thunder
172 - cavium,thunder2
173 - faraday,fa526
174 - intel,sa110
175 - intel,sa1100
176 - marvell,feroceon
177 - marvell,mohawk
178 - marvell,pj4a
179 - marvell,pj4b
180 - marvell,sheeva-v5
181 - marvell,sheeva-v7
182 - nvidia,tegra132-denver
183 - nvidia,tegra186-denver
184 - nvidia,tegra194-carmel
185 - qcom,krait
186 - qcom,kryo
187 - qcom,kryo240
188 - qcom,kryo250
189 - qcom,kryo260
190 - qcom,kryo280
191 - qcom,kryo360
192 - qcom,kryo385
193 - qcom,kryo468
194 - qcom,kryo485
195 - qcom,kryo560
196 - qcom,kryo570
197 - qcom,kryo660
198 - qcom,kryo685
199 - qcom,kryo780
200 - qcom,scorpion
202 enable-method:
205 # On ARM v8 64-bit this property is required
206 - enum:
207 - psci
208 - spin-table
209 # On ARM 32-bit systems this property is optional
210 - enum:
211 - actions,s500-smp
212 - allwinner,sun6i-a31
213 - allwinner,sun8i-a23
214 - allwinner,sun9i-a80-smp
215 - allwinner,sun8i-a83t-smp
216 - amlogic,meson8-smp
217 - amlogic,meson8b-smp
218 - arm,realview-smp
219 - aspeed,ast2600-smp
220 - brcm,bcm11351-cpu-method
221 - brcm,bcm23550
222 - brcm,bcm2836-smp
223 - brcm,bcm63138
224 - brcm,bcm-nsp-smp
225 - brcm,brahma-b15
226 - marvell,armada-375-smp
227 - marvell,armada-380-smp
228 - marvell,armada-390-smp
229 - marvell,armada-xp-smp
230 - marvell,98dx3236-smp
231 - marvell,mmp3-smp
232 - mediatek,mt6589-smp
233 - mediatek,mt81xx-tz-smp
234 - qcom,gcc-msm8660
235 - qcom,kpss-acc-v1
236 - qcom,kpss-acc-v2
237 - qcom,msm8226-smp
238 - qcom,msm8909-smp
239 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
240 - qcom,msm8916-smp
241 - renesas,apmu
242 - renesas,r9a06g032-smp
243 - rockchip,rk3036-smp
244 - rockchip,rk3066-smp
245 - socionext,milbeaut-m10v-smp
246 - ste,dbx500-smp
247 - ti,am3352
248 - ti,am4372
250 cpu-release-addr:
252 - $ref: /schemas/types.yaml#/definitions/uint32
253 - $ref: /schemas/types.yaml#/definitions/uint64
255 The DT specification defines this as 64-bit always, but some 32-bit Arm
256 systems have used a 32-bit value which must be supported.
257 Required for systems that have an "enable-method"
258 property value of "spin-table".
260 cpu-idle-states:
261 $ref: /schemas/types.yaml#/definitions/phandle-array
266 by this cpu (see ./idle-states.yaml).
268 capacity-dmips-mhz:
270 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
271 DMIPS/MHz, relative to highest capacity-dmips-mhz
274 cci-control-port: true
276 dynamic-power-coefficient:
279 A u32 value that represents the running time dynamic
287 calculate the dynamic power as below -
289 Pdyn = dynamic-power-coefficient * V^2 * f
293 performance-domains:
298 dvfs/performance-domain.yaml.
300 power-domains:
305 power-domain-names:
307 A list of power domain name strings sorted in the same order as the
308 power-domains property.
318 Required for systems that have an "enable-method" property
319 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
328 Required for systems that have an "enable-method" property
329 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
330 "qcom,msm8916-smp".
332 * arm/msm/qcom,kpss-acc.txt
339 Optional for systems that have an "enable-method"
340 property value of "rockchip,rk3066-smp"
342 the cpu-core power-domains.
344 secondary-boot-reg:
347 Required for systems that have an "enable-method" property value of
348 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
354 The secondary-boot-reg property is a u32 value that specifies the
356 code release a secondary CPU. The value written to the register is
361 # If the enable-method property contains one of those values
363 enable-method:
366 - brcm,bcm11351-cpu-method
367 - brcm,bcm23550
368 - brcm,bcm-nsp-smp
369 # and if enable-method is present
371 - enable-method
375 - secondary-boot-reg
378 - device_type
379 - reg
380 - compatible
383 rockchip,pmu: [enable-method]
388 - |
390 #size-cells = <0>;
391 #address-cells = <1>;
395 compatible = "arm,cortex-a15";
401 compatible = "arm,cortex-a15";
407 compatible = "arm,cortex-a7";
413 compatible = "arm,cortex-a7";
418 - |
419 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
421 #size-cells = <0>;
422 #address-cells = <1>;
426 compatible = "arm,cortex-a8";
431 - |
432 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
434 #size-cells = <0>;
435 #address-cells = <1>;
439 compatible = "arm,arm926ej-s";
444 - |
445 // Example 4 (ARM Cortex-A57 64-bit system):
447 #size-cells = <0>;
448 #address-cells = <2>;
452 compatible = "arm,cortex-a57";
454 enable-method = "spin-table";
455 cpu-release-addr = <0 0x20000000>;
460 compatible = "arm,cortex-a57";
462 enable-method = "spin-table";
463 cpu-release-addr = <0 0x20000000>;
468 compatible = "arm,cortex-a57";
470 enable-method = "spin-table";
471 cpu-release-addr = <0 0x20000000>;
476 compatible = "arm,cortex-a57";
478 enable-method = "spin-table";
479 cpu-release-addr = <0 0x20000000>;
484 compatible = "arm,cortex-a57";
486 enable-method = "spin-table";
487 cpu-release-addr = <0 0x20000000>;
492 compatible = "arm,cortex-a57";
494 enable-method = "spin-table";
495 cpu-release-addr = <0 0x20000000>;
500 compatible = "arm,cortex-a57";
502 enable-method = "spin-table";
503 cpu-release-addr = <0 0x20000000>;
508 compatible = "arm,cortex-a57";
510 enable-method = "spin-table";
511 cpu-release-addr = <0 0x20000000>;
516 compatible = "arm,cortex-a57";
518 enable-method = "spin-table";
519 cpu-release-addr = <0 0x20000000>;
524 compatible = "arm,cortex-a57";
526 enable-method = "spin-table";
527 cpu-release-addr = <0 0x20000000>;
532 compatible = "arm,cortex-a57";
534 enable-method = "spin-table";
535 cpu-release-addr = <0 0x20000000>;
540 compatible = "arm,cortex-a57";
542 enable-method = "spin-table";
543 cpu-release-addr = <0 0x20000000>;
548 compatible = "arm,cortex-a57";
550 enable-method = "spin-table";
551 cpu-release-addr = <0 0x20000000>;
556 compatible = "arm,cortex-a57";
558 enable-method = "spin-table";
559 cpu-release-addr = <0 0x20000000>;
564 compatible = "arm,cortex-a57";
566 enable-method = "spin-table";
567 cpu-release-addr = <0 0x20000000>;
572 compatible = "arm,cortex-a57";
574 enable-method = "spin-table";
575 cpu-release-addr = <0 0x20000000>;