14fb00d90SLinus Walleij# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24fb00d90SLinus Walleij%YAML 1.2 34fb00d90SLinus Walleij--- 44fb00d90SLinus Walleij$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml# 54fb00d90SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml# 64fb00d90SLinus Walleij 7dd3cb467SAndrew Lunntitle: ARM Versatile Express and Juno Boards 84fb00d90SLinus Walleij 94fb00d90SLinus Walleijmaintainers: 104fb00d90SLinus Walleij - Sudeep Holla <sudeep.holla@arm.com> 114fb00d90SLinus Walleij - Linus Walleij <linus.walleij@linaro.org> 124fb00d90SLinus Walleij 134fb00d90SLinus Walleijdescription: |+ 144fb00d90SLinus Walleij ARM's Versatile Express platform were built as reference designs for exploring 154fb00d90SLinus Walleij multicore Cortex-A class systems. The Versatile Express family contains both 164fb00d90SLinus Walleij 32 bit (Aarch32) and 64 bit (Aarch64) systems. 174fb00d90SLinus Walleij 184fb00d90SLinus Walleij The board consist of a motherboard and one or more daughterboards (tiles). The 194fb00d90SLinus Walleij motherboard provides a set of peripherals. Processor and RAM "live" on the 204fb00d90SLinus Walleij tiles. 214fb00d90SLinus Walleij 224fb00d90SLinus Walleij The motherboard and each core tile should be described by a separate Device 234fb00d90SLinus Walleij Tree source file, with the tile's description including the motherboard file 244fb00d90SLinus Walleij using an include directive. As the motherboard can be initialized in one of 254fb00d90SLinus Walleij two different configurations ("memory maps"), care must be taken to include 264fb00d90SLinus Walleij the correct one. 274fb00d90SLinus Walleij 284fb00d90SLinus Walleij When a new generation of boards were introduced under the name "Juno", these 294fb00d90SLinus Walleij shared to many common characteristics with the Versatile Express that the 304fb00d90SLinus Walleij "arm,vexpress" compatible was retained in the root node, and these are 314fb00d90SLinus Walleij included in this binding schema as well. 324fb00d90SLinus Walleij 334fb00d90SLinus Walleij The root node indicates the CPU SoC on the core tile, and this 344fb00d90SLinus Walleij is a daughterboard to the main motherboard. The name used in the compatible 354fb00d90SLinus Walleij string shall match the name given in the core tile's technical reference 364fb00d90SLinus Walleij manual, followed by "arm,vexpress" as an additional compatible value. If 374fb00d90SLinus Walleij further subvariants are released of the core tile, even more fine-granular 384fb00d90SLinus Walleij compatible strings with up to three compatible strings are used. 394fb00d90SLinus Walleij 404fb00d90SLinus Walleijproperties: 414fb00d90SLinus Walleij $nodename: 424fb00d90SLinus Walleij const: '/' 434fb00d90SLinus Walleij compatible: 444fb00d90SLinus Walleij oneOf: 454fb00d90SLinus Walleij - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores 464fb00d90SLinus Walleij in MPCore configuration in a test chip on the core tile. See ARM 474fb00d90SLinus Walleij DUI 0448I. This was the first Versatile Express platform. 484fb00d90SLinus Walleij items: 494fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca9 504fb00d90SLinus Walleij - const: arm,vexpress 514fb00d90SLinus Walleij - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores 524fb00d90SLinus Walleij in a test chip on the core tile. It is intended to evaluate NEON, FPU 534fb00d90SLinus Walleij and Jazelle support in the Cortex A5 family. See ARM DUI 0541C. 544fb00d90SLinus Walleij items: 554fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca5s 564fb00d90SLinus Walleij - const: arm,vexpress 574fb00d90SLinus Walleij - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU 584fb00d90SLinus Walleij cores in a MPCore configuration in a test chip on the core tile. See 594fb00d90SLinus Walleij ARM DUI 0604F. 604fb00d90SLinus Walleij items: 614fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca15 624fb00d90SLinus Walleij - const: arm,vexpress 634fb00d90SLinus Walleij - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex 644fb00d90SLinus Walleij A15 CPU cores in a test chip on the core tile. This is the first test 654fb00d90SLinus Walleij chip called "TC1". 664fb00d90SLinus Walleij items: 674fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca15,tc1 684fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca15 694fb00d90SLinus Walleij - const: arm,vexpress 704fb00d90SLinus Walleij - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15 714fb00d90SLinus Walleij CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration 724fb00d90SLinus Walleij in a test chip on the core tile. See ARM DDI 0503I. 734fb00d90SLinus Walleij items: 744fb00d90SLinus Walleij - const: arm,vexpress,v2p-ca15_a7 754fb00d90SLinus Walleij - const: arm,vexpress 764fb00d90SLinus Walleij - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU 774fb00d90SLinus Walleij cores in a test chip on the core tile. See ARM DDI 0498D. 784fb00d90SLinus Walleij items: 794fb00d90SLinus Walleij - const: arm,vexpress,v2f-1xv7,ca53x2 804fb00d90SLinus Walleij - const: arm,vexpress,v2f-1xv7 814fb00d90SLinus Walleij - const: arm,vexpress 824fb00d90SLinus Walleij - description: Arm Versatile Express Juno "r0" (the first Juno board, 834fb00d90SLinus Walleij V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on 844fb00d90SLinus Walleij AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53 854fb00d90SLinus Walleij cores in a big.LITTLE configuration. It also features the MALI T624 864fb00d90SLinus Walleij GPU. See ARM document 100113_0000_07_en. 874fb00d90SLinus Walleij items: 884fb00d90SLinus Walleij - const: arm,juno 894fb00d90SLinus Walleij - const: arm,vexpress 904fb00d90SLinus Walleij - description: Arm Versatile Express Juno r1 Development Platform 914fb00d90SLinus Walleij (V2M-Juno r1) was introduced mainly aimed at development of PCIe 924fb00d90SLinus Walleij based systems. Juno r1 also has support for AXI masters placed on 934fb00d90SLinus Walleij the TLX connectors to join the coherency domain. Otherwise it is the 944fb00d90SLinus Walleij same configuration as Juno r0. See ARM document 100122_0100_06_en. 954fb00d90SLinus Walleij items: 964fb00d90SLinus Walleij - const: arm,juno-r1 974fb00d90SLinus Walleij - const: arm,juno 984fb00d90SLinus Walleij - const: arm,vexpress 994fb00d90SLinus Walleij - description: Arm Versatile Express Juno r2 Development Platform 1004fb00d90SLinus Walleij (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See 1014fb00d90SLinus Walleij ARM document 100114_0200_04_en. 1024fb00d90SLinus Walleij items: 1034fb00d90SLinus Walleij - const: arm,juno-r2 1044fb00d90SLinus Walleij - const: arm,juno 1054fb00d90SLinus Walleij - const: arm,vexpress 1064fb00d90SLinus Walleij - description: Arm AEMv8a Versatile Express Real-Time System Model 1074fb00d90SLinus Walleij (VE RTSM) is a programmers view of the Versatile Express with Arm 1084fb00d90SLinus Walleij v8A hardware. See ARM DUI 0575D. 1094fb00d90SLinus Walleij items: 1104fb00d90SLinus Walleij - const: arm,rtsm_ve,aemv8a 1114fb00d90SLinus Walleij - const: arm,vexpress 1124fb00d90SLinus Walleij - description: Arm FVP (Fixed Virtual Platform) base model revision C 1134fb00d90SLinus Walleij See ARM Document 100964_1190_00_en. 1144fb00d90SLinus Walleij items: 1154fb00d90SLinus Walleij - const: arm,fvp-base-revc 1164fb00d90SLinus Walleij - const: arm,vexpress 1174fb00d90SLinus Walleij - description: Arm Foundation model for Aarch64 1184fb00d90SLinus Walleij items: 1194fb00d90SLinus Walleij - const: arm,foundation-aarch64 1204fb00d90SLinus Walleij - const: arm,vexpress 1214fb00d90SLinus Walleij 1224fb00d90SLinus Walleij arm,vexpress,position: 1234fb00d90SLinus Walleij description: When daughterboards are stacked on one site, their position 1244fb00d90SLinus Walleij in the stack be be described this attribute. 12502478c98SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 1263d21a460SRob Herring minimum: 0 1274fb00d90SLinus Walleij maximum: 3 1284fb00d90SLinus Walleij 1294fb00d90SLinus Walleij arm,vexpress,dcc: 1304fb00d90SLinus Walleij description: When describing tiles consisting of more than one DCC, its 1314fb00d90SLinus Walleij number can be specified with this attribute. 13202478c98SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 1333d21a460SRob Herring minimum: 0 1344fb00d90SLinus Walleij maximum: 3 1354fb00d90SLinus Walleij 1364fb00d90SLinus WalleijpatternProperties: 1374fb00d90SLinus Walleij "^bus@[0-9a-f]+$": 1384fb00d90SLinus Walleij description: Static Memory Bus (SMB) node, if this exists it describes 1394fb00d90SLinus Walleij the connection between the motherboard and any tiles. Sometimes the 1404fb00d90SLinus Walleij compatible is placed directly under this node, sometimes it is placed 1411b4e3ca2SRob Herring in a subnode named "motherboard-bus". Sometimes the compatible includes 1424fb00d90SLinus Walleij "arm,vexpress,v2?-p1" sometimes (on software models) is is just 1431b4e3ca2SRob Herring "simple-bus". If the compatible is placed in the "motherboard-bus" node, 1444fb00d90SLinus Walleij it is stricter and always has two compatibles. 1454fb00d90SLinus Walleij type: object 146*45698208SRob Herring $ref: /schemas/simple-bus.yaml 147e62fc182SRob Herring unevaluatedProperties: false 1484fb00d90SLinus Walleij 1494fb00d90SLinus Walleij properties: 1504fb00d90SLinus Walleij compatible: 1514fb00d90SLinus Walleij oneOf: 1524fb00d90SLinus Walleij - items: 1534fb00d90SLinus Walleij - enum: 1544fb00d90SLinus Walleij - arm,vexpress,v2m-p1 1554fb00d90SLinus Walleij - arm,vexpress,v2p-p1 1564fb00d90SLinus Walleij - const: simple-bus 1574fb00d90SLinus Walleij - const: simple-bus 1581b4e3ca2SRob Herring 1591b4e3ca2SRob Herring patternProperties: 1601b4e3ca2SRob Herring '^motherboard-bus@': 1614fb00d90SLinus Walleij type: object 1624fb00d90SLinus Walleij description: The motherboard description provides a single "motherboard" 1634fb00d90SLinus Walleij node using 2 address cells corresponding to the Static Memory Bus 1644fb00d90SLinus Walleij used between the motherboard and the tile. The first cell defines the 1654fb00d90SLinus Walleij Chip Select (CS) line number, the second cell address offset within 1664fb00d90SLinus Walleij the CS. All interrupt lines between the motherboard and the tile 1674fb00d90SLinus Walleij are active high and are described using single cell. 1684fb00d90SLinus Walleij properties: 1694fb00d90SLinus Walleij "#address-cells": 1704fb00d90SLinus Walleij const: 2 1714fb00d90SLinus Walleij "#size-cells": 1724fb00d90SLinus Walleij const: 1 1736f4276ecSRob Herring ranges: true 1746f4276ecSRob Herring 1754fb00d90SLinus Walleij compatible: 1764fb00d90SLinus Walleij items: 1774fb00d90SLinus Walleij - enum: 1784fb00d90SLinus Walleij - arm,vexpress,v2m-p1 1794fb00d90SLinus Walleij - arm,vexpress,v2p-p1 1804fb00d90SLinus Walleij - const: simple-bus 1814fb00d90SLinus Walleij arm,v2m-memory-map: 1824fb00d90SLinus Walleij description: This describes the memory map type. 18302478c98SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/string 1843d21a460SRob Herring enum: 1854fb00d90SLinus Walleij - rs1 1864fb00d90SLinus Walleij - rs2 1873d21a460SRob Herring 1886f4276ecSRob Herring arm,hbi: 18902478c98SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 1906f4276ecSRob Herring description: This indicates the ARM HBI (Hardware Board ID), this is 1916f4276ecSRob Herring ARM's unique board model ID, visible on the PCB's silkscreen. 1926f4276ecSRob Herring 1936f4276ecSRob Herring arm,vexpress,site: 1946f4276ecSRob Herring description: As Versatile Express can be configured in number of physically 1956f4276ecSRob Herring different setups, the device tree should describe platform topology. 1966f4276ecSRob Herring For this reason the root node and main motherboard node must define this 1976f4276ecSRob Herring property, describing the physical location of the children nodes. 1986f4276ecSRob Herring 0 means motherboard site, while 1 and 2 are daughterboard sites, and 1996f4276ecSRob Herring 0xf means "sisterboard" which is the site containing the main CPU tile. 20002478c98SKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 2016f4276ecSRob Herring minimum: 0 2026f4276ecSRob Herring maximum: 15 2036f4276ecSRob Herring 2044fb00d90SLinus Walleij required: 2054fb00d90SLinus Walleij - compatible 2066f4276ecSRob Herring 2076f4276ecSRob Herring additionalProperties: 2086f4276ecSRob Herring type: object 2096f4276ecSRob Herring 2104fb00d90SLinus Walleij required: 2114fb00d90SLinus Walleij - compatible 2124fb00d90SLinus Walleij 2134fb00d90SLinus WalleijallOf: 2144fb00d90SLinus Walleij - if: 2154fb00d90SLinus Walleij properties: 2164fb00d90SLinus Walleij compatible: 2174fb00d90SLinus Walleij contains: 2184fb00d90SLinus Walleij enum: 2194fb00d90SLinus Walleij - arm,vexpress,v2p-ca9 2204fb00d90SLinus Walleij - arm,vexpress,v2p-ca5s 2214fb00d90SLinus Walleij - arm,vexpress,v2p-ca15 2224fb00d90SLinus Walleij - arm,vexpress,v2p-ca15_a7 2234fb00d90SLinus Walleij - arm,vexpress,v2f-1xv7,ca53x2 2244fb00d90SLinus Walleij then: 2254fb00d90SLinus Walleij required: 2264fb00d90SLinus Walleij - arm,hbi 2274fb00d90SLinus Walleij 22862298364SRob HerringadditionalProperties: true 22962298364SRob Herring 2304fb00d90SLinus Walleij... 231