1Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``) 2================================================================== 3 4The QEMU Aspeed machines model BMCs of various OpenPOWER systems and 5Aspeed evaluation boards. They are based on different releases of the 6Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the 7AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 8with dual cores ARM Cortex-A7 CPUs (1.2GHz). 9 10The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, 11etc. 12 13AST2400 SoC based machines : 14 15- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC 16- ``quanta-q71l-bmc`` OpenBMC Quanta BMC 17- ``supermicrox11-bmc`` Supermicro X11 BMC 18 19AST2500 SoC based machines : 20 21- ``ast2500-evb`` Aspeed AST2500 Evaluation board 22- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC 23- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC 24- ``sonorapass-bmc`` OCP SonoraPass BMC 25- ``fp5280g2-bmc`` Inspur FP5280G2 BMC 26- ``g220a-bmc`` Bytedance G220A BMC 27- ``yosemitev2-bmc`` Facebook YosemiteV2 BMC 28- ``tiogapass-bmc`` Facebook Tiogapass BMC 29 30AST2600 SoC based machines : 31 32- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) 33- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC 34- ``rainier-bmc`` IBM Rainier POWER10 BMC 35- ``fuji-bmc`` Facebook Fuji BMC 36- ``montblanc-bmc`` Facebook Montblanc BMC 37- ``bletchley-bmc`` Facebook Bletchley BMC 38- ``fby35-bmc`` Facebook fby35 BMC 39- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC 40- ``qcom-firework-bmc`` Qualcomm Firework BMC 41 42Supported devices 43----------------- 44 45 * SMP (for the AST2600 Cortex-A7) 46 * Interrupt Controller (VIC) 47 * Timer Controller 48 * RTC Controller 49 * I2C Controller, including the new register interface of the AST2600 50 * System Control Unit (SCU) 51 * SRAM mapping 52 * X-DMA Controller (basic interface) 53 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 54 * SPI Memory Controller 55 * USB 2.0 Controller 56 * SD/MMC storage controllers 57 * SDRAM controller (dummy interface for basic settings and training) 58 * Watchdog Controller 59 * GPIO Controller (Master only) 60 * UART 61 * Ethernet controllers 62 * Front LEDs (PCA9552 on I2C bus) 63 * LPC Peripheral Controller (a subset of subdevices are supported) 64 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 65 * ADC 66 * Secure Boot Controller (AST2600) 67 * eMMC Boot Controller (dummy) 68 * PECI Controller (minimal) 69 * I3C Controller 70 71 72Missing devices 73--------------- 74 75 * Coprocessor support 76 * PWM and Fan Controller 77 * Slave GPIO Controller 78 * Super I/O Controller 79 * PCI-Express 1 Controller 80 * Graphic Display Controller 81 * MCTP Controller 82 * Mailbox Controller 83 * Virtual UART 84 * eSPI Controller 85 86Boot options 87------------ 88 89The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options 90to load a Linux kernel or from a firmware. Images can be downloaded from the 91OpenBMC jenkins : 92 93 https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ 94 95or directly from the OpenBMC GitHub release repository : 96 97 https://github.com/openbmc/openbmc/releases 98 99To boot a kernel directly from a Linux build tree: 100 101.. code-block:: bash 102 103 $ qemu-system-arm -M ast2600-evb -nographic \ 104 -kernel arch/arm/boot/zImage \ 105 -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ 106 -initrd rootfs.cpio 107 108To boot the machine from the flash image, use an MTD drive : 109 110.. code-block:: bash 111 112 $ qemu-system-arm -M romulus-bmc -nic user \ 113 -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd -nographic 114 115Options specific to Aspeed machines are : 116 117 * ``boot-emmc`` to set or unset boot from eMMC (AST2600 only). 118 119 * ``execute-in-place`` which emulates the boot from the CE0 flash 120 device by using the FMC controller to load the instructions, and 121 not simply from RAM. This takes a little longer. 122 123 * ``fmc-model`` to change the default FMC Flash model. FW needs 124 support for the chip model to boot. 125 126 * ``spi-model`` to change the default SPI Flash model. 127 128 * ``bmc-console`` to change the default console device. Most of the 129 machines use the ``UART5`` device for a boot console, which is 130 mapped on ``/dev/ttyS4`` under Linux, but it is not always the 131 case. 132 133To use other flash models, for instance a different FMC chip and a 134bigger (64M) SPI for the ``ast2500-evb`` machine, run : 135 136.. code-block:: bash 137 138 -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f 139 140When more flexibility is needed to define the flash devices, to use 141different flash models or define all flash devices (up to 8), the 142``-nodefaults`` QEMU option can be used to avoid creating the default 143flash devices. 144 145Flash devices should then be created from the command line and attached 146to a block device : 147 148.. code-block:: bash 149 150 $ qemu-system-arm -M ast2600-evb \ 151 -blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \ 152 -device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \ 153 -blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \ 154 -device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \ 155 -blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \ 156 -device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \ 157 -nographic -nodefaults 158 159In that case, the machine boots fetching instructions from the FMC0 160device. It is slower to start but closer to what HW does. Using the 161machine option ``execute-in-place`` has a similar effect. 162 163To change the boot console and use device ``UART3`` (``/dev/ttyS2`` 164under Linux), use : 165 166.. code-block:: bash 167 168 -M ast2500-evb,bmc-console=uart3 169 170Aspeed minibmc family boards (``ast1030-evb``) 171================================================================== 172 173The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation 174boards. They are based on different releases of the 175Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). 176 177The SoC comes with SRAM, SPI, I2C, etc. 178 179AST1030 SoC based machines : 180 181- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) 182 183Supported devices 184----------------- 185 186 * SMP (for the AST1030 Cortex-M4F) 187 * Interrupt Controller (VIC) 188 * Timer Controller 189 * I2C Controller 190 * System Control Unit (SCU) 191 * SRAM mapping 192 * Static Memory Controller (SMC or FMC) - Only SPI Flash support 193 * SPI Memory Controller 194 * USB 2.0 Controller 195 * Watchdog Controller 196 * GPIO Controller (Master only) 197 * UART 198 * LPC Peripheral Controller (a subset of subdevices are supported) 199 * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA 200 * ADC 201 * Secure Boot Controller 202 * PECI Controller (minimal) 203 204 205Missing devices 206--------------- 207 208 * PWM and Fan Controller 209 * Slave GPIO Controller 210 * Mailbox Controller 211 * Virtual UART 212 * eSPI Controller 213 * I3C Controller 214 215Boot options 216------------ 217 218The Aspeed machines can be started using the ``-kernel`` to load a 219Zephyr OS or from a firmware. Images can be downloaded from the 220ASPEED GitHub release repository : 221 222 https://github.com/AspeedTech-BMC/zephyr/releases 223 224To boot a kernel directly from a Zephyr build tree: 225 226.. code-block:: bash 227 228 $ qemu-system-arm -M ast1030-evb -nographic \ 229 -kernel zephyr.elf 230 231Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) 232================================================================== 233 234Facebook has a series of multi-node compute server designs named 235Yosemite. The most recent version released was 236`Yosemite v3 <https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf>`__. 237 238Yosemite v3.5 is an iteration on this design, and is very similar: there's a 239baseboard with a BMC, and 4 server slots. The new server board design termed 240"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to 241include various compute accelerators (video, inferencing, etc). At the moment, 242only the first server slot's BIC is included. 243 244Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds 245can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__ 246for an example. 247 248In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC 249runs `OpenBMC <https://github.com/facebook/openbmc>`__, and the BIC runs 250`OpenBIC <https://github.com/facebook/openbic>`__. 251 252Firmware images can be retrieved from the Github releases or built from the 253source code, see the README's for instructions on that. This image uses the 254"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. 255Some reference images can also be found here: 256 257.. code-block:: bash 258 259 $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd 260 $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf 261 262Since this machine has multiple SoC's, each with their own serial console, the 263recommended way to run it is to allocate a pseudoterminal for each serial 264console and let the monitor use stdio. Also, starting in a paused state is 265useful because it allows you to attach to the pseudoterminals before the boot 266process starts. 267 268.. code-block:: bash 269 270 $ qemu-system-arm -machine fby35 \ 271 -drive file=fby35.mtd,format=raw,if=mtd \ 272 -device loader,file=Y35BCL.elf,addr=0,cpu-num=2 \ 273 -serial pty -serial pty -serial mon:stdio \ 274 -display none -S 275 $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. 276 $ screen /dev/tty1 277 $ (qemu) c # Start the boot process once screen is setup. 278