arm64/kernel/cpu_errata.c

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
24 	if (!is_midr_in_range(midr, &entry->midr_range))  in is_affected_midr_range()
29 	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)  in is_affected_midr_range()
30 		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))  in is_affected_midr_range()
41 	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);  in is_affected_midr_range_list()
55 	return model == entry->midr_range.model;  in is_kryo_midr()
70 	 * a consistent CTR_EL0 to make sure that applications behaves  in has_mismatched_cache_type()
73 	 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :  in has_mismatched_cache_type()
82 	 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.  in has_mismatched_cache_type()
96 	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */  in cpu_enable_trap_ctr_access()
102 	if (cap->capability == ARM64_WORKAROUND_1542419)  in cpu_enable_trap_ctr_access()
135 	if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK)  in cpu_clear_bf16_from_user_emulation()
136 		regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;  in cpu_clear_bf16_from_user_emulation()
159 /* Errata affecting a range of revisions of  given model variant */
163 /* Errata affecting a single variant/revision of a model */
167 /* Errata affecting all variants/revisions of a given a model */
172 /* Errata affecting a list of midr ranges, with same work around */
240 		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
265 	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
275 	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
277 	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
303 	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
307 	/* Cortex-A53 r0p[01] : ARM errata 819472 */
316  * - 1188873 affects r0p0 to r2p0
317  * - 1418040 affects r0p0 to r3p1
320 	/* Cortex-A76 r0p0 to r3p1 */
322 	/* Neoverse-N1 r0p0 to r3p1 */
332 	/* Cortex-A53 r0p[01234] */
334 	/* Brahma-B53 r0p[0] */
345 		/* Cortex-A53 r0p[01234] */
351 		/* Brahma-B53 r0p[0] */
362 	/* Cortex A76 r0p0 to r2p0 */
370 	/* Cortex A55 r0p0 to r2p0 */
381 	/* Cortex-A76 r0p0 - r3p1 */
444 	/* Cortex-A520 r0p0 to r0p1 */
497 	/* Cortex-A57 r0p0 - r1p2 */
507 	/* Cortex-A57 r0p0 - r1p2 */
580 	/* Cortex-A73 all versions */
587 		.desc = "Spectre-v2",
595 	/* Must come after the Spectre-v2 entry */
596 		.desc = "Spectre-v3a",
604 		.desc = "Spectre-v4",
611 		.desc = "Spectre-BHB",
624 		 * also need the non-affected CPUs to be able to come
691 		 * driver and can be applied per-cpu. So, we can allow
692 		 * a late CPU to come online with this erratum.
734 		/* Cortex-A510 r0p0 - r0p2 */
744 		/* Cortex-A510 r0p0-r1p1 */
753 		/* Cortex-A510 r0p0 - r0p2 */
762 		/* Cortex-A510 r0p0 - r0p1 */
778 		/* Cortex-A510 r0p0 - r1p1 */
786 		.desc = "SSBS not fully self-synchronizing",
795 		/* Cortex-A520 r0p0 - r0p1 */