1 # SPDX-License-Identifier: GPL-2.0 2 config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_CURRENT_STACK_POINTER 10 select ARCH_HAS_DEBUG_VIRTUAL if MMU 11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 12 select ARCH_HAS_ELF_RANDOMIZE 13 select ARCH_HAS_FORTIFY_SOURCE 14 select ARCH_HAS_KEEPINITRD 15 select ARCH_HAS_KCOV 16 select ARCH_HAS_MEMBARRIER_SYNC_CORE 17 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 18 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_STACKWALK 22 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 23 select ARCH_HAS_STRICT_MODULE_RWX if MMU 24 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 25 select ARCH_HAS_SYNC_DMA_FOR_CPU 26 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAS_IOPORT 74 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 75 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 76 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 78 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 79 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 80 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 81 select HAVE_ARCH_MMAP_RND_BITS if MMU 82 select HAVE_ARCH_PFN_VALID 83 select HAVE_ARCH_SECCOMP 84 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 85 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 86 select HAVE_ARCH_TRACEHOOK 87 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 88 select HAVE_ARM_SMCCC if CPU_V7 89 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 90 select HAVE_CONTEXT_TRACKING_USER 91 select HAVE_C_RECORDMCOUNT 92 select HAVE_BUILDTIME_MCOUNT_SORT 93 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 94 select HAVE_DMA_CONTIGUOUS if MMU 95 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 96 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 97 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 98 select HAVE_EXIT_THREAD 99 select HAVE_FAST_GUP if ARM_LPAE 100 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 101 select HAVE_FUNCTION_ERROR_INJECTION 102 select HAVE_FUNCTION_GRAPH_TRACER 103 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 104 select HAVE_GCC_PLUGINS 105 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 106 select HAVE_IRQ_TIME_ACCOUNTING 107 select HAVE_KERNEL_GZIP 108 select HAVE_KERNEL_LZ4 109 select HAVE_KERNEL_LZMA 110 select HAVE_KERNEL_LZO 111 select HAVE_KERNEL_XZ 112 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 113 select HAVE_KRETPROBES if HAVE_KPROBES 114 select HAVE_MOD_ARCH_SPECIFIC 115 select HAVE_NMI 116 select HAVE_OPTPROBES if !THUMB2_KERNEL 117 select HAVE_PCI if MMU 118 select HAVE_PERF_EVENTS 119 select HAVE_PERF_REGS 120 select HAVE_PERF_USER_STACK_DUMP 121 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 122 select HAVE_REGS_AND_STACK_ACCESS_API 123 select HAVE_RSEQ 124 select HAVE_STACKPROTECTOR 125 select HAVE_SYSCALL_TRACEPOINTS 126 select HAVE_UID16 127 select HAVE_VIRT_CPU_ACCOUNTING_GEN 128 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 129 select IRQ_FORCED_THREADING 130 select LOCK_MM_AND_FIND_VMA 131 select MODULES_USE_ELF_REL 132 select NEED_DMA_MAP_STATE 133 select OF_EARLY_FLATTREE if OF 134 select OLD_SIGACTION 135 select OLD_SIGSUSPEND3 136 select PCI_DOMAINS_GENERIC if PCI 137 select PCI_SYSCALL if PCI 138 select PERF_USE_VMALLOC 139 select RTC_LIB 140 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 141 select SYS_SUPPORTS_APM_EMULATION 142 select THREAD_INFO_IN_TASK 143 select TIMER_OF if OF 144 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 145 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 146 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 147 # Above selects are sorted alphabetically; please add new ones 148 # according to that. Thanks. 149 help 150 The ARM series is a line of low-power-consumption RISC chip designs 151 licensed by ARM Ltd and targeted at embedded applications and 152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 153 manufactured, but legacy ARM-based PC hardware remains popular in 154 Europe. There is an ARM Linux project with a web page at 155 <http://www.arm.linux.org.uk/>. 156 157 config ARM_HAS_GROUP_RELOCS 158 def_bool y 159 depends on !LD_IS_LLD || LLD_VERSION >= 140000 160 depends on !COMPILE_TEST 161 help 162 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 163 relocations, which have been around for a long time, but were not 164 supported in LLD until version 14. The combined range is -/+ 256 MiB, 165 which is usually sufficient, but not for allyesconfig, so we disable 166 this feature when doing compile testing. 167 168 config ARM_DMA_USE_IOMMU 169 bool 170 select NEED_SG_DMA_LENGTH 171 172 if ARM_DMA_USE_IOMMU 173 174 config ARM_DMA_IOMMU_ALIGNMENT 175 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 176 range 4 9 177 default 8 178 help 179 DMA mapping framework by default aligns all buffers to the smallest 180 PAGE_SIZE order which is greater than or equal to the requested buffer 181 size. This works well for buffers up to a few hundreds kilobytes, but 182 for larger buffers it just a waste of address space. Drivers which has 183 relatively small addressing window (like 64Mib) might run out of 184 virtual space with just a few allocations. 185 186 With this parameter you can specify the maximum PAGE_SIZE order for 187 DMA IOMMU buffers. Larger buffers will be aligned only to this 188 specified order. The order is expressed as a power of two multiplied 189 by the PAGE_SIZE. 190 191 endif 192 193 config SYS_SUPPORTS_APM_EMULATION 194 bool 195 196 config HAVE_TCM 197 bool 198 select GENERIC_ALLOCATOR 199 200 config HAVE_PROC_CPU 201 bool 202 203 config NO_IOPORT_MAP 204 bool 205 206 config SBUS 207 bool 208 209 config STACKTRACE_SUPPORT 210 bool 211 default y 212 213 config LOCKDEP_SUPPORT 214 bool 215 default y 216 217 config ARCH_HAS_ILOG2_U32 218 bool 219 220 config ARCH_HAS_ILOG2_U64 221 bool 222 223 config ARCH_HAS_BANDGAP 224 bool 225 226 config FIX_EARLYCON_MEM 227 def_bool y if MMU 228 229 config GENERIC_HWEIGHT 230 bool 231 default y 232 233 config GENERIC_CALIBRATE_DELAY 234 bool 235 default y 236 237 config ARCH_MAY_HAVE_PC_FDC 238 bool 239 240 config ARCH_SUPPORTS_UPROBES 241 def_bool y 242 243 config GENERIC_ISA_DMA 244 bool 245 246 config FIQ 247 bool 248 249 config ARCH_MTD_XIP 250 bool 251 252 config ARM_PATCH_PHYS_VIRT 253 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 254 default y 255 depends on MMU 256 help 257 Patch phys-to-virt and virt-to-phys translation functions at 258 boot and module load time according to the position of the 259 kernel in system memory. 260 261 This can only be used with non-XIP MMU kernels where the base 262 of physical memory is at a 2 MiB boundary. 263 264 Only disable this option if you know that you do not require 265 this feature (eg, building a kernel for a single machine) and 266 you need to shrink the kernel to the minimal size. 267 268 config NEED_MACH_IO_H 269 bool 270 help 271 Select this when mach/io.h is required to provide special 272 definitions for this platform. The need for mach/io.h should 273 be avoided when possible. 274 275 config NEED_MACH_MEMORY_H 276 bool 277 help 278 Select this when mach/memory.h is required to provide special 279 definitions for this platform. The need for mach/memory.h should 280 be avoided when possible. 281 282 config PHYS_OFFSET 283 hex "Physical address of main memory" if MMU 284 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 285 default DRAM_BASE if !MMU 286 default 0x00000000 if ARCH_FOOTBRIDGE 287 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 288 default 0xa0000000 if ARCH_PXA 289 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 290 default 0 291 help 292 Please provide the physical address corresponding to the 293 location of main memory in your system. 294 295 config GENERIC_BUG 296 def_bool y 297 depends on BUG 298 299 config PGTABLE_LEVELS 300 int 301 default 3 if ARM_LPAE 302 default 2 303 304 menu "System Type" 305 306 config MMU 307 bool "MMU-based Paged Memory Management Support" 308 default y 309 help 310 Select if you want MMU-based virtualised addressing space 311 support by paged memory management. If unsure, say 'Y'. 312 313 config ARM_SINGLE_ARMV7M 314 def_bool !MMU 315 select ARM_NVIC 316 select CPU_V7M 317 select NO_IOPORT_MAP 318 319 config ARCH_MMAP_RND_BITS_MIN 320 default 8 321 322 config ARCH_MMAP_RND_BITS_MAX 323 default 14 if PAGE_OFFSET=0x40000000 324 default 15 if PAGE_OFFSET=0x80000000 325 default 16 326 327 config ARCH_MULTIPLATFORM 328 bool "Require kernel to be portable to multiple machines" if EXPERT 329 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 330 default y 331 help 332 In general, all Arm machines can be supported in a single 333 kernel image, covering either Armv4/v5 or Armv6/v7. 334 335 However, some configuration options require hardcoding machine 336 specific physical addresses or enable errata workarounds that may 337 break other machines. 338 339 Selecting N here allows using those options, including 340 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 341 342 menu "Platform selection" 343 depends on MMU 344 345 comment "CPU Core family selection" 346 347 config ARCH_MULTI_V4 348 bool "ARMv4 based platforms (FA526, StrongARM)" 349 depends on !ARCH_MULTI_V6_V7 350 # https://github.com/llvm/llvm-project/issues/50764 351 depends on !LD_IS_LLD || LLD_VERSION >= 160000 352 select ARCH_MULTI_V4_V5 353 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 354 355 config ARCH_MULTI_V4T 356 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 357 depends on !ARCH_MULTI_V6_V7 358 # https://github.com/llvm/llvm-project/issues/50764 359 depends on !LD_IS_LLD || LLD_VERSION >= 160000 360 select ARCH_MULTI_V4_V5 361 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 362 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 363 CPU_ARM925T || CPU_ARM940T) 364 365 config ARCH_MULTI_V5 366 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 367 depends on !ARCH_MULTI_V6_V7 368 select ARCH_MULTI_V4_V5 369 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 370 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 371 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 372 373 config ARCH_MULTI_V4_V5 374 bool 375 376 config ARCH_MULTI_V6 377 bool "ARMv6 based platforms (ARM11)" 378 select ARCH_MULTI_V6_V7 379 select CPU_V6K 380 381 config ARCH_MULTI_V7 382 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 383 default y 384 select ARCH_MULTI_V6_V7 385 select CPU_V7 386 select HAVE_SMP 387 388 config ARCH_MULTI_V6_V7 389 bool 390 select MIGHT_HAVE_CACHE_L2X0 391 392 config ARCH_MULTI_CPU_AUTO 393 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 394 select ARCH_MULTI_V5 395 396 endmenu 397 398 config ARCH_VIRT 399 bool "Dummy Virtual Machine" 400 depends on ARCH_MULTI_V7 401 select ARM_AMBA 402 select ARM_GIC 403 select ARM_GIC_V2M if PCI 404 select ARM_GIC_V3 405 select ARM_GIC_V3_ITS if PCI 406 select ARM_PSCI 407 select HAVE_ARM_ARCH_TIMER 408 409 config ARCH_AIROHA 410 bool "Airoha SoC Support" 411 depends on ARCH_MULTI_V7 412 select ARM_AMBA 413 select ARM_GIC 414 select ARM_GIC_V3 415 select ARM_PSCI 416 select HAVE_ARM_ARCH_TIMER 417 help 418 Support for Airoha EN7523 SoCs 419 420 # 421 # This is sorted alphabetically by mach-* pathname. However, plat-* 422 # Kconfigs may be included either alphabetically (according to the 423 # plat- suffix) or along side the corresponding mach-* source. 424 # 425 source "arch/arm/mach-actions/Kconfig" 426 427 source "arch/arm/mach-alpine/Kconfig" 428 429 source "arch/arm/mach-artpec/Kconfig" 430 431 source "arch/arm/mach-asm9260/Kconfig" 432 433 source "arch/arm/mach-aspeed/Kconfig" 434 435 source "arch/arm/mach-at91/Kconfig" 436 437 source "arch/arm/mach-axxia/Kconfig" 438 439 source "arch/arm/mach-bcm/Kconfig" 440 441 source "arch/arm/mach-berlin/Kconfig" 442 443 source "arch/arm/mach-clps711x/Kconfig" 444 445 source "arch/arm/mach-davinci/Kconfig" 446 447 source "arch/arm/mach-digicolor/Kconfig" 448 449 source "arch/arm/mach-dove/Kconfig" 450 451 source "arch/arm/mach-ep93xx/Kconfig" 452 453 source "arch/arm/mach-exynos/Kconfig" 454 455 source "arch/arm/mach-footbridge/Kconfig" 456 457 source "arch/arm/mach-gemini/Kconfig" 458 459 source "arch/arm/mach-highbank/Kconfig" 460 461 source "arch/arm/mach-hisi/Kconfig" 462 463 source "arch/arm/mach-hpe/Kconfig" 464 465 source "arch/arm/mach-imx/Kconfig" 466 467 source "arch/arm/mach-ixp4xx/Kconfig" 468 469 source "arch/arm/mach-keystone/Kconfig" 470 471 source "arch/arm/mach-lpc32xx/Kconfig" 472 473 source "arch/arm/mach-mediatek/Kconfig" 474 475 source "arch/arm/mach-meson/Kconfig" 476 477 source "arch/arm/mach-milbeaut/Kconfig" 478 479 source "arch/arm/mach-mmp/Kconfig" 480 481 source "arch/arm/mach-moxart/Kconfig" 482 483 source "arch/arm/mach-mstar/Kconfig" 484 485 source "arch/arm/mach-mv78xx0/Kconfig" 486 487 source "arch/arm/mach-mvebu/Kconfig" 488 489 source "arch/arm/mach-mxs/Kconfig" 490 491 source "arch/arm/mach-nomadik/Kconfig" 492 493 source "arch/arm/mach-npcm/Kconfig" 494 495 source "arch/arm/mach-nspire/Kconfig" 496 497 source "arch/arm/mach-omap1/Kconfig" 498 499 source "arch/arm/mach-omap2/Kconfig" 500 501 source "arch/arm/mach-orion5x/Kconfig" 502 503 source "arch/arm/mach-pxa/Kconfig" 504 505 source "arch/arm/mach-qcom/Kconfig" 506 507 source "arch/arm/mach-rda/Kconfig" 508 509 source "arch/arm/mach-realtek/Kconfig" 510 511 source "arch/arm/mach-rpc/Kconfig" 512 513 source "arch/arm/mach-rockchip/Kconfig" 514 515 source "arch/arm/mach-s3c/Kconfig" 516 517 source "arch/arm/mach-s5pv210/Kconfig" 518 519 source "arch/arm/mach-sa1100/Kconfig" 520 521 source "arch/arm/mach-shmobile/Kconfig" 522 523 source "arch/arm/mach-socfpga/Kconfig" 524 525 source "arch/arm/mach-spear/Kconfig" 526 527 source "arch/arm/mach-sti/Kconfig" 528 529 source "arch/arm/mach-stm32/Kconfig" 530 531 source "arch/arm/mach-sunplus/Kconfig" 532 533 source "arch/arm/mach-sunxi/Kconfig" 534 535 source "arch/arm/mach-tegra/Kconfig" 536 537 source "arch/arm/mach-uniphier/Kconfig" 538 539 source "arch/arm/mach-ux500/Kconfig" 540 541 source "arch/arm/mach-versatile/Kconfig" 542 543 source "arch/arm/mach-vt8500/Kconfig" 544 545 source "arch/arm/mach-zynq/Kconfig" 546 547 # ARMv7-M architecture 548 config ARCH_LPC18XX 549 bool "NXP LPC18xx/LPC43xx" 550 depends on ARM_SINGLE_ARMV7M 551 select ARCH_HAS_RESET_CONTROLLER 552 select ARM_AMBA 553 select CLKSRC_LPC32XX 554 select PINCTRL 555 help 556 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 557 high performance microcontrollers. 558 559 config ARCH_MPS2 560 bool "ARM MPS2 platform" 561 depends on ARM_SINGLE_ARMV7M 562 select ARM_AMBA 563 select CLKSRC_MPS2 564 help 565 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 566 with a range of available cores like Cortex-M3/M4/M7. 567 568 Please, note that depends which Application Note is used memory map 569 for the platform may vary, so adjustment of RAM base might be needed. 570 571 # Definitions to make life easier 572 config ARCH_ACORN 573 bool 574 575 config PLAT_ORION 576 bool 577 select CLKSRC_MMIO 578 select GENERIC_IRQ_CHIP 579 select IRQ_DOMAIN 580 581 config PLAT_ORION_LEGACY 582 bool 583 select PLAT_ORION 584 585 config PLAT_VERSATILE 586 bool 587 588 source "arch/arm/mm/Kconfig" 589 590 config IWMMXT 591 bool "Enable iWMMXt support" 592 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 593 default y if PXA27x || PXA3xx || ARCH_MMP 594 help 595 Enable support for iWMMXt context switching at run time if 596 running on a CPU that supports it. 597 598 if !MMU 599 source "arch/arm/Kconfig-nommu" 600 endif 601 602 config PJ4B_ERRATA_4742 603 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 604 depends on CPU_PJ4B && MACH_ARMADA_370 605 default y 606 help 607 When coming out of either a Wait for Interrupt (WFI) or a Wait for 608 Event (WFE) IDLE states, a specific timing sensitivity exists between 609 the retiring WFI/WFE instructions and the newly issued subsequent 610 instructions. This sensitivity can result in a CPU hang scenario. 611 Workaround: 612 The software must insert either a Data Synchronization Barrier (DSB) 613 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 614 instruction 615 616 config ARM_ERRATA_326103 617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 618 depends on CPU_V6 619 help 620 Executing a SWP instruction to read-only memory does not set bit 11 621 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 622 treat the access as a read, preventing a COW from occurring and 623 causing the faulting task to livelock. 624 625 config ARM_ERRATA_411920 626 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 627 depends on CPU_V6 || CPU_V6K 628 help 629 Invalidation of the Instruction Cache operation can 630 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 631 It does not affect the MPCore. This option enables the ARM Ltd. 632 recommended workaround. 633 634 config ARM_ERRATA_430973 635 bool "ARM errata: Stale prediction on replaced interworking branch" 636 depends on CPU_V7 637 help 638 This option enables the workaround for the 430973 Cortex-A8 639 r1p* erratum. If a code sequence containing an ARM/Thumb 640 interworking branch is replaced with another code sequence at the 641 same virtual address, whether due to self-modifying code or virtual 642 to physical address re-mapping, Cortex-A8 does not recover from the 643 stale interworking branch prediction. This results in Cortex-A8 644 executing the new code sequence in the incorrect ARM or Thumb state. 645 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 646 and also flushes the branch target cache at every context switch. 647 Note that setting specific bits in the ACTLR register may not be 648 available in non-secure mode. 649 650 config ARM_ERRATA_458693 651 bool "ARM errata: Processor deadlock when a false hazard is created" 652 depends on CPU_V7 653 depends on !ARCH_MULTIPLATFORM 654 help 655 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 656 erratum. For very specific sequences of memory operations, it is 657 possible for a hazard condition intended for a cache line to instead 658 be incorrectly associated with a different cache line. This false 659 hazard might then cause a processor deadlock. The workaround enables 660 the L1 caching of the NEON accesses and disables the PLD instruction 661 in the ACTLR register. Note that setting specific bits in the ACTLR 662 register may not be available in non-secure mode and thus is not 663 available on a multiplatform kernel. This should be applied by the 664 bootloader instead. 665 666 config ARM_ERRATA_460075 667 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 668 depends on CPU_V7 669 depends on !ARCH_MULTIPLATFORM 670 help 671 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 672 erratum. Any asynchronous access to the L2 cache may encounter a 673 situation in which recent store transactions to the L2 cache are lost 674 and overwritten with stale memory contents from external memory. The 675 workaround disables the write-allocate mode for the L2 cache via the 676 ACTLR register. Note that setting specific bits in the ACTLR register 677 may not be available in non-secure mode and thus is not available on 678 a multiplatform kernel. This should be applied by the bootloader 679 instead. 680 681 config ARM_ERRATA_742230 682 bool "ARM errata: DMB operation may be faulty" 683 depends on CPU_V7 && SMP 684 depends on !ARCH_MULTIPLATFORM 685 help 686 This option enables the workaround for the 742230 Cortex-A9 687 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 688 between two write operations may not ensure the correct visibility 689 ordering of the two writes. This workaround sets a specific bit in 690 the diagnostic register of the Cortex-A9 which causes the DMB 691 instruction to behave as a DSB, ensuring the correct behaviour of 692 the two writes. Note that setting specific bits in the diagnostics 693 register may not be available in non-secure mode and thus is not 694 available on a multiplatform kernel. This should be applied by the 695 bootloader instead. 696 697 config ARM_ERRATA_742231 698 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 699 depends on CPU_V7 && SMP 700 depends on !ARCH_MULTIPLATFORM 701 help 702 This option enables the workaround for the 742231 Cortex-A9 703 (r2p0..r2p2) erratum. Under certain conditions, specific to the 704 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 705 accessing some data located in the same cache line, may get corrupted 706 data due to bad handling of the address hazard when the line gets 707 replaced from one of the CPUs at the same time as another CPU is 708 accessing it. This workaround sets specific bits in the diagnostic 709 register of the Cortex-A9 which reduces the linefill issuing 710 capabilities of the processor. Note that setting specific bits in the 711 diagnostics register may not be available in non-secure mode and thus 712 is not available on a multiplatform kernel. This should be applied by 713 the bootloader instead. 714 715 config ARM_ERRATA_643719 716 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 717 depends on CPU_V7 && SMP 718 default y 719 help 720 This option enables the workaround for the 643719 Cortex-A9 (prior to 721 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 722 register returns zero when it should return one. The workaround 723 corrects this value, ensuring cache maintenance operations which use 724 it behave as intended and avoiding data corruption. 725 726 config ARM_ERRATA_720789 727 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 728 depends on CPU_V7 729 help 730 This option enables the workaround for the 720789 Cortex-A9 (prior to 731 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 732 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 733 As a consequence of this erratum, some TLB entries which should be 734 invalidated are not, resulting in an incoherency in the system page 735 tables. The workaround changes the TLB flushing routines to invalidate 736 entries regardless of the ASID. 737 738 config ARM_ERRATA_743622 739 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 740 depends on CPU_V7 741 depends on !ARCH_MULTIPLATFORM 742 help 743 This option enables the workaround for the 743622 Cortex-A9 744 (r2p*) erratum. Under very rare conditions, a faulty 745 optimisation in the Cortex-A9 Store Buffer may lead to data 746 corruption. This workaround sets a specific bit in the diagnostic 747 register of the Cortex-A9 which disables the Store Buffer 748 optimisation, preventing the defect from occurring. This has no 749 visible impact on the overall performance or power consumption of the 750 processor. Note that setting specific bits in the diagnostics register 751 may not be available in non-secure mode and thus is not available on a 752 multiplatform kernel. This should be applied by the bootloader instead. 753 754 config ARM_ERRATA_751472 755 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 756 depends on CPU_V7 757 depends on !ARCH_MULTIPLATFORM 758 help 759 This option enables the workaround for the 751472 Cortex-A9 (prior 760 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 761 completion of a following broadcasted operation if the second 762 operation is received by a CPU before the ICIALLUIS has completed, 763 potentially leading to corrupted entries in the cache or TLB. 764 Note that setting specific bits in the diagnostics register may 765 not be available in non-secure mode and thus is not available on 766 a multiplatform kernel. This should be applied by the bootloader 767 instead. 768 769 config ARM_ERRATA_754322 770 bool "ARM errata: possible faulty MMU translations following an ASID switch" 771 depends on CPU_V7 772 help 773 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 774 r3p*) erratum. A speculative memory access may cause a page table walk 775 which starts prior to an ASID switch but completes afterwards. This 776 can populate the micro-TLB with a stale entry which may be hit with 777 the new ASID. This workaround places two dsb instructions in the mm 778 switching code so that no page table walks can cross the ASID switch. 779 780 config ARM_ERRATA_754327 781 bool "ARM errata: no automatic Store Buffer drain" 782 depends on CPU_V7 && SMP 783 help 784 This option enables the workaround for the 754327 Cortex-A9 (prior to 785 r2p0) erratum. The Store Buffer does not have any automatic draining 786 mechanism and therefore a livelock may occur if an external agent 787 continuously polls a memory location waiting to observe an update. 788 This workaround defines cpu_relax() as smp_mb(), preventing correctly 789 written polling loops from denying visibility of updates to memory. 790 791 config ARM_ERRATA_364296 792 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 793 depends on CPU_V6 794 help 795 This options enables the workaround for the 364296 ARM1136 796 r0p2 erratum (possible cache data corruption with 797 hit-under-miss enabled). It sets the undocumented bit 31 in 798 the auxiliary control register and the FI bit in the control 799 register, thus disabling hit-under-miss without putting the 800 processor into full low interrupt latency mode. ARM11MPCore 801 is not affected. 802 803 config ARM_ERRATA_764369 804 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 805 depends on CPU_V7 && SMP 806 help 807 This option enables the workaround for erratum 764369 808 affecting Cortex-A9 MPCore with two or more processors (all 809 current revisions). Under certain timing circumstances, a data 810 cache line maintenance operation by MVA targeting an Inner 811 Shareable memory region may fail to proceed up to either the 812 Point of Coherency or to the Point of Unification of the 813 system. This workaround adds a DSB instruction before the 814 relevant cache maintenance functions and sets a specific bit 815 in the diagnostic control register of the SCU. 816 817 config ARM_ERRATA_764319 818 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 819 depends on CPU_V7 820 help 821 This option enables the workaround for the 764319 Cortex A-9 erratum. 822 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 823 unexpected Undefined Instruction exception when the DBGSWENABLE 824 external pin is set to 0, even when the CP14 accesses are performed 825 from a privileged mode. This work around catches the exception in a 826 way the kernel does not stop execution. 827 828 config ARM_ERRATA_775420 829 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 830 depends on CPU_V7 831 help 832 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 833 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 834 operation aborts with MMU exception, it might cause the processor 835 to deadlock. This workaround puts DSB before executing ISB if 836 an abort may occur on cache maintenance. 837 838 config ARM_ERRATA_798181 839 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 840 depends on CPU_V7 && SMP 841 help 842 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 843 adequately shooting down all use of the old entries. This 844 option enables the Linux kernel workaround for this erratum 845 which sends an IPI to the CPUs that are running the same ASID 846 as the one being invalidated. 847 848 config ARM_ERRATA_773022 849 bool "ARM errata: incorrect instructions may be executed from loop buffer" 850 depends on CPU_V7 851 help 852 This option enables the workaround for the 773022 Cortex-A15 853 (up to r0p4) erratum. In certain rare sequences of code, the 854 loop buffer may deliver incorrect instructions. This 855 workaround disables the loop buffer to avoid the erratum. 856 857 config ARM_ERRATA_818325_852422 858 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 859 depends on CPU_V7 860 help 861 This option enables the workaround for: 862 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 863 instruction might deadlock. Fixed in r0p1. 864 - Cortex-A12 852422: Execution of a sequence of instructions might 865 lead to either a data corruption or a CPU deadlock. Not fixed in 866 any Cortex-A12 cores yet. 867 This workaround for all both errata involves setting bit[12] of the 868 Feature Register. This bit disables an optimisation applied to a 869 sequence of 2 instructions that use opposing condition codes. 870 871 config ARM_ERRATA_821420 872 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 873 depends on CPU_V7 874 help 875 This option enables the workaround for the 821420 Cortex-A12 876 (all revs) erratum. In very rare timing conditions, a sequence 877 of VMOV to Core registers instructions, for which the second 878 one is in the shadow of a branch or abort, can lead to a 879 deadlock when the VMOV instructions are issued out-of-order. 880 881 config ARM_ERRATA_825619 882 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 883 depends on CPU_V7 884 help 885 This option enables the workaround for the 825619 Cortex-A12 886 (all revs) erratum. Within rare timing constraints, executing a 887 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 888 and Device/Strongly-Ordered loads and stores might cause deadlock 889 890 config ARM_ERRATA_857271 891 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 892 depends on CPU_V7 893 help 894 This option enables the workaround for the 857271 Cortex-A12 895 (all revs) erratum. Under very rare timing conditions, the CPU might 896 hang. The workaround is expected to have a < 1% performance impact. 897 898 config ARM_ERRATA_852421 899 bool "ARM errata: A17: DMB ST might fail to create order between stores" 900 depends on CPU_V7 901 help 902 This option enables the workaround for the 852421 Cortex-A17 903 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 904 execution of a DMB ST instruction might fail to properly order 905 stores from GroupA and stores from GroupB. 906 907 config ARM_ERRATA_852423 908 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 909 depends on CPU_V7 910 help 911 This option enables the workaround for: 912 - Cortex-A17 852423: Execution of a sequence of instructions might 913 lead to either a data corruption or a CPU deadlock. Not fixed in 914 any Cortex-A17 cores yet. 915 This is identical to Cortex-A12 erratum 852422. It is a separate 916 config option from the A12 erratum due to the way errata are checked 917 for and handled. 918 919 config ARM_ERRATA_857272 920 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 921 depends on CPU_V7 922 help 923 This option enables the workaround for the 857272 Cortex-A17 erratum. 924 This erratum is not known to be fixed in any A17 revision. 925 This is identical to Cortex-A12 erratum 857271. It is a separate 926 config option from the A12 erratum due to the way errata are checked 927 for and handled. 928 929 endmenu 930 931 source "arch/arm/common/Kconfig" 932 933 menu "Bus support" 934 935 config ISA 936 bool 937 help 938 Find out whether you have ISA slots on your motherboard. ISA is the 939 name of a bus system, i.e. the way the CPU talks to the other stuff 940 inside your box. Other bus systems are PCI, EISA, MicroChannel 941 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 942 newer boards don't support it. If you have ISA, say Y, otherwise N. 943 944 # Select ISA DMA interface 945 config ISA_DMA_API 946 bool 947 948 config ARM_ERRATA_814220 949 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 950 depends on CPU_V7 951 help 952 The v7 ARM states that all cache and branch predictor maintenance 953 operations that do not specify an address execute, relative to 954 each other, in program order. 955 However, because of this erratum, an L2 set/way cache maintenance 956 operation can overtake an L1 set/way cache maintenance operation. 957 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 958 r0p4, r0p5. 959 960 endmenu 961 962 menu "Kernel Features" 963 964 config HAVE_SMP 965 bool 966 help 967 This option should be selected by machines which have an SMP- 968 capable CPU. 969 970 The only effect of this option is to make the SMP-related 971 options available to the user for configuration. 972 973 config SMP 974 bool "Symmetric Multi-Processing" 975 depends on CPU_V6K || CPU_V7 976 depends on HAVE_SMP 977 depends on MMU || ARM_MPU 978 select IRQ_WORK 979 help 980 This enables support for systems with more than one CPU. If you have 981 a system with only one CPU, say N. If you have a system with more 982 than one CPU, say Y. 983 984 If you say N here, the kernel will run on uni- and multiprocessor 985 machines, but will use only one CPU of a multiprocessor machine. If 986 you say Y here, the kernel will run on many, but not all, 987 uniprocessor machines. On a uniprocessor machine, the kernel 988 will run faster if you say N here. 989 990 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 991 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 992 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 993 994 If you don't know what to do here, say N. 995 996 config SMP_ON_UP 997 bool "Allow booting SMP kernel on uniprocessor systems" 998 depends on SMP && MMU 999 default y 1000 help 1001 SMP kernels contain instructions which fail on non-SMP processors. 1002 Enabling this option allows the kernel to modify itself to make 1003 these instructions safe. Disabling it allows about 1K of space 1004 savings. 1005 1006 If you don't know what to do here, say Y. 1007 1008 1009 config CURRENT_POINTER_IN_TPIDRURO 1010 def_bool y 1011 depends on CPU_32v6K && !CPU_V6 1012 1013 config IRQSTACKS 1014 def_bool y 1015 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1016 select HAVE_SOFTIRQ_ON_OWN_STACK 1017 1018 config ARM_CPU_TOPOLOGY 1019 bool "Support cpu topology definition" 1020 depends on SMP && CPU_V7 1021 default y 1022 help 1023 Support ARM cpu topology definition. The MPIDR register defines 1024 affinity between processors which is then used to describe the cpu 1025 topology of an ARM System. 1026 1027 config SCHED_MC 1028 bool "Multi-core scheduler support" 1029 depends on ARM_CPU_TOPOLOGY 1030 help 1031 Multi-core scheduler support improves the CPU scheduler's decision 1032 making when dealing with multi-core CPU chips at a cost of slightly 1033 increased overhead in some places. If unsure say N here. 1034 1035 config SCHED_SMT 1036 bool "SMT scheduler support" 1037 depends on ARM_CPU_TOPOLOGY 1038 help 1039 Improves the CPU scheduler's decision making when dealing with 1040 MultiThreading at a cost of slightly increased overhead in some 1041 places. If unsure say N here. 1042 1043 config HAVE_ARM_SCU 1044 bool 1045 help 1046 This option enables support for the ARM snoop control unit 1047 1048 config HAVE_ARM_ARCH_TIMER 1049 bool "Architected timer support" 1050 depends on CPU_V7 1051 select ARM_ARCH_TIMER 1052 help 1053 This option enables support for the ARM architected timer 1054 1055 config HAVE_ARM_TWD 1056 bool 1057 help 1058 This options enables support for the ARM timer and watchdog unit 1059 1060 config MCPM 1061 bool "Multi-Cluster Power Management" 1062 depends on CPU_V7 && SMP 1063 help 1064 This option provides the common power management infrastructure 1065 for (multi-)cluster based systems, such as big.LITTLE based 1066 systems. 1067 1068 config MCPM_QUAD_CLUSTER 1069 bool 1070 depends on MCPM 1071 help 1072 To avoid wasting resources unnecessarily, MCPM only supports up 1073 to 2 clusters by default. 1074 Platforms with 3 or 4 clusters that use MCPM must select this 1075 option to allow the additional clusters to be managed. 1076 1077 config BIG_LITTLE 1078 bool "big.LITTLE support (Experimental)" 1079 depends on CPU_V7 && SMP 1080 select MCPM 1081 help 1082 This option enables support selections for the big.LITTLE 1083 system architecture. 1084 1085 config BL_SWITCHER 1086 bool "big.LITTLE switcher support" 1087 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1088 select CPU_PM 1089 help 1090 The big.LITTLE "switcher" provides the core functionality to 1091 transparently handle transition between a cluster of A15's 1092 and a cluster of A7's in a big.LITTLE system. 1093 1094 config BL_SWITCHER_DUMMY_IF 1095 tristate "Simple big.LITTLE switcher user interface" 1096 depends on BL_SWITCHER && DEBUG_KERNEL 1097 help 1098 This is a simple and dummy char dev interface to control 1099 the big.LITTLE switcher core code. It is meant for 1100 debugging purposes only. 1101 1102 choice 1103 prompt "Memory split" 1104 depends on MMU 1105 default VMSPLIT_3G 1106 help 1107 Select the desired split between kernel and user memory. 1108 1109 If you are not absolutely sure what you are doing, leave this 1110 option alone! 1111 1112 config VMSPLIT_3G 1113 bool "3G/1G user/kernel split" 1114 config VMSPLIT_3G_OPT 1115 depends on !ARM_LPAE 1116 bool "3G/1G user/kernel split (for full 1G low memory)" 1117 config VMSPLIT_2G 1118 bool "2G/2G user/kernel split" 1119 config VMSPLIT_1G 1120 bool "1G/3G user/kernel split" 1121 endchoice 1122 1123 config PAGE_OFFSET 1124 hex 1125 default PHYS_OFFSET if !MMU 1126 default 0x40000000 if VMSPLIT_1G 1127 default 0x80000000 if VMSPLIT_2G 1128 default 0xB0000000 if VMSPLIT_3G_OPT 1129 default 0xC0000000 1130 1131 config KASAN_SHADOW_OFFSET 1132 hex 1133 depends on KASAN 1134 default 0x1f000000 if PAGE_OFFSET=0x40000000 1135 default 0x5f000000 if PAGE_OFFSET=0x80000000 1136 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1137 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1138 default 0xffffffff 1139 1140 config NR_CPUS 1141 int "Maximum number of CPUs (2-32)" 1142 range 2 16 if DEBUG_KMAP_LOCAL 1143 range 2 32 if !DEBUG_KMAP_LOCAL 1144 depends on SMP 1145 default "4" 1146 help 1147 The maximum number of CPUs that the kernel can support. 1148 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1149 debugging is enabled, which uses half of the per-CPU fixmap 1150 slots as guard regions. 1151 1152 config HOTPLUG_CPU 1153 bool "Support for hot-pluggable CPUs" 1154 depends on SMP 1155 select GENERIC_IRQ_MIGRATION 1156 help 1157 Say Y here to experiment with turning CPUs off and on. CPUs 1158 can be controlled through /sys/devices/system/cpu. 1159 1160 config ARM_PSCI 1161 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1162 depends on HAVE_ARM_SMCCC 1163 select ARM_PSCI_FW 1164 help 1165 Say Y here if you want Linux to communicate with system firmware 1166 implementing the PSCI specification for CPU-centric power 1167 management operations described in ARM document number ARM DEN 1168 0022A ("Power State Coordination Interface System Software on 1169 ARM processors"). 1170 1171 config HZ_FIXED 1172 int 1173 default 128 if SOC_AT91RM9200 1174 default 0 1175 1176 choice 1177 depends on HZ_FIXED = 0 1178 prompt "Timer frequency" 1179 1180 config HZ_100 1181 bool "100 Hz" 1182 1183 config HZ_200 1184 bool "200 Hz" 1185 1186 config HZ_250 1187 bool "250 Hz" 1188 1189 config HZ_300 1190 bool "300 Hz" 1191 1192 config HZ_500 1193 bool "500 Hz" 1194 1195 config HZ_1000 1196 bool "1000 Hz" 1197 1198 endchoice 1199 1200 config HZ 1201 int 1202 default HZ_FIXED if HZ_FIXED != 0 1203 default 100 if HZ_100 1204 default 200 if HZ_200 1205 default 250 if HZ_250 1206 default 300 if HZ_300 1207 default 500 if HZ_500 1208 default 1000 1209 1210 config SCHED_HRTICK 1211 def_bool HIGH_RES_TIMERS 1212 1213 config THUMB2_KERNEL 1214 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1215 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1216 default y if CPU_THUMBONLY 1217 select ARM_UNWIND 1218 help 1219 By enabling this option, the kernel will be compiled in 1220 Thumb-2 mode. 1221 1222 If unsure, say N. 1223 1224 config ARM_PATCH_IDIV 1225 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1226 depends on CPU_32v7 1227 default y 1228 help 1229 The ARM compiler inserts calls to __aeabi_idiv() and 1230 __aeabi_uidiv() when it needs to perform division on signed 1231 and unsigned integers. Some v7 CPUs have support for the sdiv 1232 and udiv instructions that can be used to implement those 1233 functions. 1234 1235 Enabling this option allows the kernel to modify itself to 1236 replace the first two instructions of these library functions 1237 with the sdiv or udiv plus "bx lr" instructions when the CPU 1238 it is running on supports them. Typically this will be faster 1239 and less power intensive than running the original library 1240 code to do integer division. 1241 1242 config AEABI 1243 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1244 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1245 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1246 help 1247 This option allows for the kernel to be compiled using the latest 1248 ARM ABI (aka EABI). This is only useful if you are using a user 1249 space environment that is also compiled with EABI. 1250 1251 Since there are major incompatibilities between the legacy ABI and 1252 EABI, especially with regard to structure member alignment, this 1253 option also changes the kernel syscall calling convention to 1254 disambiguate both ABIs and allow for backward compatibility support 1255 (selected with CONFIG_OABI_COMPAT). 1256 1257 To use this you need GCC version 4.0.0 or later. 1258 1259 config OABI_COMPAT 1260 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1261 depends on AEABI && !THUMB2_KERNEL 1262 help 1263 This option preserves the old syscall interface along with the 1264 new (ARM EABI) one. It also provides a compatibility layer to 1265 intercept syscalls that have structure arguments which layout 1266 in memory differs between the legacy ABI and the new ARM EABI 1267 (only for non "thumb" binaries). This option adds a tiny 1268 overhead to all syscalls and produces a slightly larger kernel. 1269 1270 The seccomp filter system will not be available when this is 1271 selected, since there is no way yet to sensibly distinguish 1272 between calling conventions during filtering. 1273 1274 If you know you'll be using only pure EABI user space then you 1275 can say N here. If this option is not selected and you attempt 1276 to execute a legacy ABI binary then the result will be 1277 UNPREDICTABLE (in fact it can be predicted that it won't work 1278 at all). If in doubt say N. 1279 1280 config ARCH_SELECT_MEMORY_MODEL 1281 def_bool y 1282 1283 config ARCH_FLATMEM_ENABLE 1284 def_bool !(ARCH_RPC || ARCH_SA1100) 1285 1286 config ARCH_SPARSEMEM_ENABLE 1287 def_bool !ARCH_FOOTBRIDGE 1288 select SPARSEMEM_STATIC if SPARSEMEM 1289 1290 config HIGHMEM 1291 bool "High Memory Support" 1292 depends on MMU 1293 select KMAP_LOCAL 1294 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1295 help 1296 The address space of ARM processors is only 4 Gigabytes large 1297 and it has to accommodate user address space, kernel address 1298 space as well as some memory mapped IO. That means that, if you 1299 have a large amount of physical memory and/or IO, not all of the 1300 memory can be "permanently mapped" by the kernel. The physical 1301 memory that is not permanently mapped is called "high memory". 1302 1303 Depending on the selected kernel/user memory split, minimum 1304 vmalloc space and actual amount of RAM, you may not need this 1305 option which should result in a slightly faster kernel. 1306 1307 If unsure, say n. 1308 1309 config HIGHPTE 1310 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1311 depends on HIGHMEM 1312 default y 1313 help 1314 The VM uses one page of physical memory for each page table. 1315 For systems with a lot of processes, this can use a lot of 1316 precious low memory, eventually leading to low memory being 1317 consumed by page tables. Setting this option will allow 1318 user-space 2nd level page tables to reside in high memory. 1319 1320 config CPU_SW_DOMAIN_PAN 1321 bool "Enable use of CPU domains to implement privileged no-access" 1322 depends on MMU && !ARM_LPAE 1323 default y 1324 help 1325 Increase kernel security by ensuring that normal kernel accesses 1326 are unable to access userspace addresses. This can help prevent 1327 use-after-free bugs becoming an exploitable privilege escalation 1328 by ensuring that magic values (such as LIST_POISON) will always 1329 fault when dereferenced. 1330 1331 CPUs with low-vector mappings use a best-efforts implementation. 1332 Their lower 1MB needs to remain accessible for the vectors, but 1333 the remainder of userspace will become appropriately inaccessible. 1334 1335 config HW_PERF_EVENTS 1336 def_bool y 1337 depends on ARM_PMU 1338 1339 config ARM_MODULE_PLTS 1340 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1341 depends on MODULES 1342 select KASAN_VMALLOC if KASAN 1343 default y 1344 help 1345 Allocate PLTs when loading modules so that jumps and calls whose 1346 targets are too far away for their relative offsets to be encoded 1347 in the instructions themselves can be bounced via veneers in the 1348 module's PLT. This allows modules to be allocated in the generic 1349 vmalloc area after the dedicated module memory area has been 1350 exhausted. The modules will use slightly more memory, but after 1351 rounding up to page size, the actual memory footprint is usually 1352 the same. 1353 1354 Disabling this is usually safe for small single-platform 1355 configurations. If unsure, say y. 1356 1357 config ARCH_FORCE_MAX_ORDER 1358 int "Order of maximal physically contiguous allocations" 1359 default "11" if SOC_AM33XX 1360 default "8" if SA1111 1361 default "10" 1362 help 1363 The kernel page allocator limits the size of maximal physically 1364 contiguous allocations. The limit is called MAX_ORDER and it 1365 defines the maximal power of two of number of pages that can be 1366 allocated as a single contiguous block. This option allows 1367 overriding the default setting when ability to allocate very 1368 large blocks of physically contiguous memory is required. 1369 1370 Don't change if unsure. 1371 1372 config ALIGNMENT_TRAP 1373 def_bool CPU_CP15_MMU 1374 select HAVE_PROC_CPU if PROC_FS 1375 help 1376 ARM processors cannot fetch/store information which is not 1377 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1378 address divisible by 4. On 32-bit ARM processors, these non-aligned 1379 fetch/store instructions will be emulated in software if you say 1380 here, which has a severe performance impact. This is necessary for 1381 correct operation of some network protocols. With an IP-only 1382 configuration it is safe to say N, otherwise say Y. 1383 1384 config UACCESS_WITH_MEMCPY 1385 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1386 depends on MMU 1387 default y if CPU_FEROCEON 1388 help 1389 Implement faster copy_to_user and clear_user methods for CPU 1390 cores where a 8-word STM instruction give significantly higher 1391 memory write throughput than a sequence of individual 32bit stores. 1392 1393 A possible side effect is a slight increase in scheduling latency 1394 between threads sharing the same address space if they invoke 1395 such copy operations with large buffers. 1396 1397 However, if the CPU data cache is using a write-allocate mode, 1398 this option is unlikely to provide any performance gain. 1399 1400 config PARAVIRT 1401 bool "Enable paravirtualization code" 1402 help 1403 This changes the kernel so it can modify itself when it is run 1404 under a hypervisor, potentially improving performance significantly 1405 over full virtualization. 1406 1407 config PARAVIRT_TIME_ACCOUNTING 1408 bool "Paravirtual steal time accounting" 1409 select PARAVIRT 1410 help 1411 Select this option to enable fine granularity task steal time 1412 accounting. Time spent executing other tasks in parallel with 1413 the current vCPU is discounted from the vCPU power. To account for 1414 that, there can be a small performance impact. 1415 1416 If in doubt, say N here. 1417 1418 config XEN_DOM0 1419 def_bool y 1420 depends on XEN 1421 1422 config XEN 1423 bool "Xen guest support on ARM" 1424 depends on ARM && AEABI && OF 1425 depends on CPU_V7 && !CPU_V6 1426 depends on !GENERIC_ATOMIC64 1427 depends on MMU 1428 select ARCH_DMA_ADDR_T_64BIT 1429 select ARM_PSCI 1430 select SWIOTLB 1431 select SWIOTLB_XEN 1432 select PARAVIRT 1433 help 1434 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1435 1436 config CC_HAVE_STACKPROTECTOR_TLS 1437 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1438 1439 config STACKPROTECTOR_PER_TASK 1440 bool "Use a unique stack canary value for each task" 1441 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1442 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1443 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1444 default y 1445 help 1446 Due to the fact that GCC uses an ordinary symbol reference from 1447 which to load the value of the stack canary, this value can only 1448 change at reboot time on SMP systems, and all tasks running in the 1449 kernel's address space are forced to use the same canary value for 1450 the entire duration that the system is up. 1451 1452 Enable this option to switch to a different method that uses a 1453 different canary value for each task. 1454 1455 endmenu 1456 1457 menu "Boot options" 1458 1459 config USE_OF 1460 bool "Flattened Device Tree support" 1461 select IRQ_DOMAIN 1462 select OF 1463 help 1464 Include support for flattened device tree machine descriptions. 1465 1466 config ARCH_WANT_FLAT_DTB_INSTALL 1467 def_bool y 1468 1469 config ATAGS 1470 bool "Support for the traditional ATAGS boot data passing" 1471 default y 1472 help 1473 This is the traditional way of passing data to the kernel at boot 1474 time. If you are solely relying on the flattened device tree (or 1475 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1476 to remove ATAGS support from your kernel binary. 1477 1478 config DEPRECATED_PARAM_STRUCT 1479 bool "Provide old way to pass kernel parameters" 1480 depends on ATAGS 1481 help 1482 This was deprecated in 2001 and announced to live on for 5 years. 1483 Some old boot loaders still use this way. 1484 1485 # Compressed boot loader in ROM. Yes, we really want to ask about 1486 # TEXT and BSS so we preserve their values in the config files. 1487 config ZBOOT_ROM_TEXT 1488 hex "Compressed ROM boot loader base address" 1489 default 0x0 1490 help 1491 The physical address at which the ROM-able zImage is to be 1492 placed in the target. Platforms which normally make use of 1493 ROM-able zImage formats normally set this to a suitable 1494 value in their defconfig file. 1495 1496 If ZBOOT_ROM is not enabled, this has no effect. 1497 1498 config ZBOOT_ROM_BSS 1499 hex "Compressed ROM boot loader BSS address" 1500 default 0x0 1501 help 1502 The base address of an area of read/write memory in the target 1503 for the ROM-able zImage which must be available while the 1504 decompressor is running. It must be large enough to hold the 1505 entire decompressed kernel plus an additional 128 KiB. 1506 Platforms which normally make use of ROM-able zImage formats 1507 normally set this to a suitable value in their defconfig file. 1508 1509 If ZBOOT_ROM is not enabled, this has no effect. 1510 1511 config ZBOOT_ROM 1512 bool "Compressed boot loader in ROM/flash" 1513 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1514 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1515 help 1516 Say Y here if you intend to execute your compressed kernel image 1517 (zImage) directly from ROM or flash. If unsure, say N. 1518 1519 config ARM_APPENDED_DTB 1520 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1521 depends on OF 1522 help 1523 With this option, the boot code will look for a device tree binary 1524 (DTB) appended to zImage 1525 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1526 1527 This is meant as a backward compatibility convenience for those 1528 systems with a bootloader that can't be upgraded to accommodate 1529 the documented boot protocol using a device tree. 1530 1531 Beware that there is very little in terms of protection against 1532 this option being confused by leftover garbage in memory that might 1533 look like a DTB header after a reboot if no actual DTB is appended 1534 to zImage. Do not leave this option active in a production kernel 1535 if you don't intend to always append a DTB. Proper passing of the 1536 location into r2 of a bootloader provided DTB is always preferable 1537 to this option. 1538 1539 config ARM_ATAG_DTB_COMPAT 1540 bool "Supplement the appended DTB with traditional ATAG information" 1541 depends on ARM_APPENDED_DTB 1542 help 1543 Some old bootloaders can't be updated to a DTB capable one, yet 1544 they provide ATAGs with memory configuration, the ramdisk address, 1545 the kernel cmdline string, etc. Such information is dynamically 1546 provided by the bootloader and can't always be stored in a static 1547 DTB. To allow a device tree enabled kernel to be used with such 1548 bootloaders, this option allows zImage to extract the information 1549 from the ATAG list and store it at run time into the appended DTB. 1550 1551 choice 1552 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1553 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1554 1555 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1556 bool "Use bootloader kernel arguments if available" 1557 help 1558 Uses the command-line options passed by the boot loader instead of 1559 the device tree bootargs property. If the boot loader doesn't provide 1560 any, the device tree bootargs property will be used. 1561 1562 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1563 bool "Extend with bootloader kernel arguments" 1564 help 1565 The command-line arguments provided by the boot loader will be 1566 appended to the the device tree bootargs property. 1567 1568 endchoice 1569 1570 config CMDLINE 1571 string "Default kernel command string" 1572 default "" 1573 help 1574 On some architectures (e.g. CATS), there is currently no way 1575 for the boot loader to pass arguments to the kernel. For these 1576 architectures, you should supply some command-line options at build 1577 time by entering them here. As a minimum, you should specify the 1578 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1579 1580 choice 1581 prompt "Kernel command line type" if CMDLINE != "" 1582 default CMDLINE_FROM_BOOTLOADER 1583 1584 config CMDLINE_FROM_BOOTLOADER 1585 bool "Use bootloader kernel arguments if available" 1586 help 1587 Uses the command-line options passed by the boot loader. If 1588 the boot loader doesn't provide any, the default kernel command 1589 string provided in CMDLINE will be used. 1590 1591 config CMDLINE_EXTEND 1592 bool "Extend bootloader kernel arguments" 1593 help 1594 The command-line arguments provided by the boot loader will be 1595 appended to the default kernel command string. 1596 1597 config CMDLINE_FORCE 1598 bool "Always use the default kernel command string" 1599 help 1600 Always use the default kernel command string, even if the boot 1601 loader passes other arguments to the kernel. 1602 This is useful if you cannot or don't want to change the 1603 command-line options your boot loader passes to the kernel. 1604 endchoice 1605 1606 config XIP_KERNEL 1607 bool "Kernel Execute-In-Place from ROM" 1608 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1609 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1610 help 1611 Execute-In-Place allows the kernel to run from non-volatile storage 1612 directly addressable by the CPU, such as NOR flash. This saves RAM 1613 space since the text section of the kernel is not loaded from flash 1614 to RAM. Read-write sections, such as the data section and stack, 1615 are still copied to RAM. The XIP kernel is not compressed since 1616 it has to run directly from flash, so it will take more space to 1617 store it. The flash address used to link the kernel object files, 1618 and for storing it, is configuration dependent. Therefore, if you 1619 say Y here, you must know the proper physical address where to 1620 store the kernel image depending on your own flash memory usage. 1621 1622 Also note that the make target becomes "make xipImage" rather than 1623 "make zImage" or "make Image". The final kernel binary to put in 1624 ROM memory will be arch/arm/boot/xipImage. 1625 1626 If unsure, say N. 1627 1628 config XIP_PHYS_ADDR 1629 hex "XIP Kernel Physical Location" 1630 depends on XIP_KERNEL 1631 default "0x00080000" 1632 help 1633 This is the physical address in your flash memory the kernel will 1634 be linked for and stored to. This address is dependent on your 1635 own flash usage. 1636 1637 config XIP_DEFLATED_DATA 1638 bool "Store kernel .data section compressed in ROM" 1639 depends on XIP_KERNEL 1640 select ZLIB_INFLATE 1641 help 1642 Before the kernel is actually executed, its .data section has to be 1643 copied to RAM from ROM. This option allows for storing that data 1644 in compressed form and decompressed to RAM rather than merely being 1645 copied, saving some precious ROM space. A possible drawback is a 1646 slightly longer boot delay. 1647 1648 config ARCH_SUPPORTS_KEXEC 1649 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1650 1651 config ATAGS_PROC 1652 bool "Export atags in procfs" 1653 depends on ATAGS && KEXEC 1654 default y 1655 help 1656 Should the atags used to boot the kernel be exported in an "atags" 1657 file in procfs. Useful with kexec. 1658 1659 config ARCH_SUPPORTS_CRASH_DUMP 1660 def_bool y 1661 1662 config AUTO_ZRELADDR 1663 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1664 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1665 help 1666 ZRELADDR is the physical address where the decompressed kernel 1667 image will be placed. If AUTO_ZRELADDR is selected, the address 1668 will be determined at run-time, either by masking the current IP 1669 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1670 This assumes the zImage being placed in the first 128MB from 1671 start of memory. 1672 1673 config EFI_STUB 1674 bool 1675 1676 config EFI 1677 bool "UEFI runtime support" 1678 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1679 select UCS2_STRING 1680 select EFI_PARAMS_FROM_FDT 1681 select EFI_STUB 1682 select EFI_GENERIC_STUB 1683 select EFI_RUNTIME_WRAPPERS 1684 help 1685 This option provides support for runtime services provided 1686 by UEFI firmware (such as non-volatile variables, realtime 1687 clock, and platform reset). A UEFI stub is also provided to 1688 allow the kernel to be booted as an EFI application. This 1689 is only useful for kernels that may run on systems that have 1690 UEFI firmware. 1691 1692 config DMI 1693 bool "Enable support for SMBIOS (DMI) tables" 1694 depends on EFI 1695 default y 1696 help 1697 This enables SMBIOS/DMI feature for systems. 1698 1699 This option is only useful on systems that have UEFI firmware. 1700 However, even with this option, the resultant kernel should 1701 continue to boot on existing non-UEFI platforms. 1702 1703 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1704 i.e., the the practice of identifying the platform via DMI to 1705 decide whether certain workarounds for buggy hardware and/or 1706 firmware need to be enabled. This would require the DMI subsystem 1707 to be enabled much earlier than we do on ARM, which is non-trivial. 1708 1709 endmenu 1710 1711 menu "CPU Power Management" 1712 1713 source "drivers/cpufreq/Kconfig" 1714 1715 source "drivers/cpuidle/Kconfig" 1716 1717 endmenu 1718 1719 menu "Floating point emulation" 1720 1721 comment "At least one emulation must be selected" 1722 1723 config FPE_NWFPE 1724 bool "NWFPE math emulation" 1725 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1726 help 1727 Say Y to include the NWFPE floating point emulator in the kernel. 1728 This is necessary to run most binaries. Linux does not currently 1729 support floating point hardware so you need to say Y here even if 1730 your machine has an FPA or floating point co-processor podule. 1731 1732 You may say N here if you are going to load the Acorn FPEmulator 1733 early in the bootup. 1734 1735 config FPE_NWFPE_XP 1736 bool "Support extended precision" 1737 depends on FPE_NWFPE 1738 help 1739 Say Y to include 80-bit support in the kernel floating-point 1740 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1741 Note that gcc does not generate 80-bit operations by default, 1742 so in most cases this option only enlarges the size of the 1743 floating point emulator without any good reason. 1744 1745 You almost surely want to say N here. 1746 1747 config FPE_FASTFPE 1748 bool "FastFPE math emulation (EXPERIMENTAL)" 1749 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1750 help 1751 Say Y here to include the FAST floating point emulator in the kernel. 1752 This is an experimental much faster emulator which now also has full 1753 precision for the mantissa. It does not support any exceptions. 1754 It is very simple, and approximately 3-6 times faster than NWFPE. 1755 1756 It should be sufficient for most programs. It may be not suitable 1757 for scientific calculations, but you have to check this for yourself. 1758 If you do not feel you need a faster FP emulation you should better 1759 choose NWFPE. 1760 1761 config VFP 1762 bool "VFP-format floating point maths" 1763 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1764 help 1765 Say Y to include VFP support code in the kernel. This is needed 1766 if your hardware includes a VFP unit. 1767 1768 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1769 release notes and additional status information. 1770 1771 Say N if your target does not have VFP hardware. 1772 1773 config VFPv3 1774 bool 1775 depends on VFP 1776 default y if CPU_V7 1777 1778 config NEON 1779 bool "Advanced SIMD (NEON) Extension support" 1780 depends on VFPv3 && CPU_V7 1781 help 1782 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1783 Extension. 1784 1785 config KERNEL_MODE_NEON 1786 bool "Support for NEON in kernel mode" 1787 depends on NEON && AEABI 1788 help 1789 Say Y to include support for NEON in kernel mode. 1790 1791 endmenu 1792 1793 menu "Power management options" 1794 1795 source "kernel/power/Kconfig" 1796 1797 config ARCH_SUSPEND_POSSIBLE 1798 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1799 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1800 def_bool y 1801 1802 config ARM_CPU_SUSPEND 1803 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1804 depends on ARCH_SUSPEND_POSSIBLE 1805 1806 config ARCH_HIBERNATION_POSSIBLE 1807 bool 1808 depends on MMU 1809 default y if ARCH_SUSPEND_POSSIBLE 1810 1811 endmenu 1812 1813 source "arch/arm/Kconfig.assembler" 1814