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/openbmc/linux/drivers/clocksource/
H A Dingenic-ost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
11 #include <linux/mfd/ingenic-tcu.h>
25 * The TCU_REG_OST_CNT{L,R} from <linux/mfd/ingenic-tcu.h> are only for the
37 struct clk *clk; member
39 struct clocksource cs; member
46 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cntl()
47 return readl(ingenic_ost->regs + OST_REG_CNTL); in ingenic_ost_read_cntl()
52 /* Read using __iomem pointer instead of regmap to avoid locking */ in ingenic_ost_read_cnth()
53 return readl(ingenic_ost->regs + OST_REG_CNTH); in ingenic_ost_read_cnth()
[all …]
H A Dem_sti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
14 #include <linux/clk.h>
27 struct clk *clk; member
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
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H A Dtimer-sun5i.c1 // SPDX-License-Identifier: GPL-2.0
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
38 struct clk *clk; member
53 * When we disable a timer, we need to wait at least for 2 cycles of
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
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H A Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
8 #include <linux/clk.h>
47 struct clocksource cs; member
56 struct clk *clk; member
70 #define TSTR -1 /* shared register */
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
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H A Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
35 struct clk *clk; member
42 struct clk *cs_clk;
44 struct clocksource cs; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
61 static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs) in ingenic_tcu_timer_cs_read() argument
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
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H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
10 #include <linux/clk.h>
23 * This driver configures the 2 16/32-bit count-up timers as follows:
29 * The input frequency to the timer module for emulation is 2.5MHz which is
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33 * The input frequency to the timer module in silicon is configurable and
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
56 * work across most input frequency, but it may need to be more dynamic
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H A Dingenic-sysost.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/ingenic,sysost.h>
76 struct clk *clk, *percpu_timer_clk, *global_timer_clk; member
78 struct clocksource cs; member
95 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_percpu_timer_recalc_rate()
98 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_percpu_timer_recalc_rate()
109 const struct ingenic_ost_clk_info *info = ost_clk->info; in ingenic_ost_global_timer_recalc_rate()
112 prescale = readl(ost_clk->ost->base + info->ostccr_reg); in ingenic_ost_global_timer_recalc_rate()
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/openbmc/linux/drivers/memory/
H A Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
12 #include <linux/clk.h>
20 #include <linux/platform_data/ti-aemif.h>
84 * struct aemif_cs_data: structure to hold cs parameters
85 * @cs: chip-select number
98 u8 cs; member
112 * struct aemif_device: structure to hold device data
114 * @clk: source clock
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H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
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H A Datmel-ebi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
9 #include <linux/clk.h>
12 #include <linux/mfd/syscon/atmel-matrix.h>
13 #include <linux/mfd/syscon/atmel-smc.h>
17 #include <soc/at91/atmel-sfr.h>
22 int cs; member
50 struct clk *clk; member
54 struct clk *clk; member
82 atmel_smc_cs_conf_get(ebid->ebi->smc.regmap, conf->cs, in at91sam9_ebi_get_config()
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H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
137 struct clk *clk; member
148 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
152 * @reg_type: the register that have to be modified
153 * @reg_mask: the bit that have to be modified in the selected register
155 * @reset_val: the default value that have to be set in case the property
159 * @calculate: this callback is called to calculate for exemple a timing
172 const struct stm32_fmc2_prop *prop, int cs);
173 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
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/openbmc/u-boot/drivers/spi/
H A Dbcm63xx_hsspi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
6 * Copyright (C) 2000-2010 Broadcom Corporation
7 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
11 #include <clk.h>
38 /* SPI Ping-Pong Command registers */
47 /* SPI Ping-Pong Status registers */
79 /* SPI Ping-Pong FIFO registers */
84 /* SPI Ping-Pong FIFO OP register */
104 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, in bcm63xx_hsspi_cs_info() argument
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H A Datmel_spi.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <clk.h>
15 #include <asm/arch/clk.h>
37 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
45 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
72 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; in spi_setup_slave()
86 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); in spi_setup_slave()
90 as->regs = regs; in spi_setup_slave()
91 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS in spi_setup_slave()
92 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); in spi_setup_slave()
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H A Dmvebu_a3700_spi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <clk.h>
38 struct clk clk; member
41 static void spi_cs_activate(struct spi_reg *reg, int cs) in spi_cs_activate() argument
43 setbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs); in spi_cs_activate()
46 static void spi_cs_deactivate(struct spi_reg *reg, int cs) in spi_cs_deactivate() argument
48 clrbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs); in spi_cs_deactivate()
52 * spi_legacy_shift_byte() - triggers the real SPI transfer
53 * @bytelen: Indicate how many bytes to transfer.
54 * @dout: Buffer address of what to send.
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-dw-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
58 * gpios for cs 2,3 as defined in the device tree.
60 * cs: | 1 0
61 * bit: |---3-------2-------1-------0
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H A Dspi-bcm2835aux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Based on: spi-bcm2835.c
13 #include <linux/clk.h>
32 "time in us to run a transfer in polling mode - if zero no polling is used\n");
88 struct clk *clk; member
112 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname); in bcm2835aux_debugfs_create()
116 bs->debugfs_dir = dir; in bcm2835aux_debugfs_create()
120 &bs->count_transfer_polling); in bcm2835aux_debugfs_create()
122 &bs->count_transfer_irq); in bcm2835aux_debugfs_create()
124 &bs->count_transfer_irq_after_poll); in bcm2835aux_debugfs_create()
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H A Dspi-wpcm-fiu.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/clk.h>
10 #include <linux/spi/spi-mem.h>
48 * I observed a typical wait time of 16 iterations for a UMA transfer to
53 /* The memory-mapped view of flash is 16 MiB long */
59 struct clk *clk; member
68 writeb(opcode, fiu->regs + FIU_UMA_CODE); in wpcm_fiu_set_opcode()
73 writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); in wpcm_fiu_set_addr()
74 writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); in wpcm_fiu_set_addr()
75 writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); in wpcm_fiu_set_addr()
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H A Dspi-mpc512x-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Hongjun Chen <hong-jun.chen@freescale.com>
22 #include <linux/clk.h>
37 switch (mps->type) { \
39 struct mpc52xx_psc __iomem *psc = mps->psc; \
40 __ret = &psc->regname; \
44 struct mpc5125_psc __iomem *psc = mps->psc; \
45 __ret = &psc->regname; \
70 * if t is NULL then reset the values to the default values
75 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_transfer_setup() local
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H A Dspi-xlp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2003-2015 Broadcom Corporation
7 #include <linux/clk.h>
98 int cs; /* slave device chip select */ member
100 bool cmd_cont; /* cs active */
105 int cs, int regoff) in xlp_spi_reg_read() argument
107 return readl(priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_read()
110 static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs, in xlp_spi_reg_write() argument
113 writel(val, priv->base + regoff + cs * SPI_CS_OFFSET); in xlp_spi_reg_write()
119 writel(val, priv->base + regoff); in xlp_spi_sysctl_write()
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/openbmc/linux/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
29 * @ncycles: number of MCK clk cycles
32 * @msbfactor: factor applied to the MSB
33 * @encodedval: param used to store the encoding result
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c1 // SPDX-License-Identifier: GPL-2.0
72 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
81 * Desc: Finds CPU/DDR frequency ratio according to Sample@reset and table.
82 * Args: target_freq - target frequency
84 * Returns: freq_par - the ratio parameter
95 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
108 * Args: freq - target frequency
110 * Returns: MV_OK - success, MV_FAIL - fail
117 u32 cs = 0; in ddr3_dfs_high_2_low() local
119 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
39 /* ADV signal timings corresponding to GPMC_CONFIG3 */
47 /* WE signals timings corresponding to GPMC_CONFIG4 */
51 /* OE signals timings corresponding to GPMC_CONFIG4 */
57 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
79 u32 t_avdasu; /* address setup to ADV valid */
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/openbmc/qemu/hw/ssi/
H A Dbcm2835_spi.c6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
37 if (s->cs & BCM2835_SPI_CS_INTD && s->cs & BCM2835_SPI_CS_DONE) { in bcm2835_spi_update_int()
41 if (s->cs & BCM2835_SPI_CS_INTR && s->cs & BCM2835_SPI_CS_RXR) { in bcm2835_spi_update_int()
44 qemu_set_irq(s->irq, do_interrupt); in bcm2835_spi_update_int()
50 if (!fifo8_is_empty(&s->rx_fifo)) { in bcm2835_spi_update_rx_flags()
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/openbmc/linux/drivers/bus/
H A Dimx-weim.c11 #include <linux/clk.h>
16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
65 struct cs_timing cs[MAX_CS_COUNT]; member
75 { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
77 { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
79 { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
80 { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
82 { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
89 struct device_node *np = pdev->dev.of_node; in imx_weim_gpr_setup()
101 int cs = 0; in imx_weim_gpr_setup() local
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/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dimx-weim.txt5 wireless and mobile applications that use low-power technology.
11 - compatible: Should contain one of the following:
12 "fsl,imx1-weim"
13 "fsl,imx27-weim"
14 "fsl,imx51-weim"
15 "fsl,imx50-weim"
16 "fsl,imx6q-weim"
17 - reg: A resource specifier for the register space
19 - clocks: the clock, see the example below.
20 - #address-cells: Must be set to 2 to allow memory address translation
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