Lines Matching +full:cs +full:- +full:to +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
8 #include <linux/clk.h>
47 struct clocksource cs; member
56 struct clk *clk; member
70 #define TSTR -1 /* shared register */
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
122 iowrite16(value, ch->base + offs); in sh_tmu_write()
124 iowrite32(value, ch->base + offs); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
136 value |= 1 << ch->index; in sh_tmu_start_stop_ch()
138 value &= ~(1 << ch->index); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
149 ret = clk_enable(ch->tmu->clk); in __sh_tmu_enable()
151 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", in __sh_tmu_enable()
152 ch->index); in __sh_tmu_enable()
163 /* configure channel to parent clock / 4, irq off */ in __sh_tmu_enable()
174 if (ch->enable_count++ > 0) in sh_tmu_enable()
177 pm_runtime_get_sync(&ch->tmu->pdev->dev); in sh_tmu_enable()
178 dev_pm_syscore_device(&ch->tmu->pdev->dev, true); in sh_tmu_enable()
192 clk_disable(ch->tmu->clk); in __sh_tmu_disable()
197 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
200 if (--ch->enable_count > 0) in sh_tmu_disable()
205 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); in sh_tmu_disable()
206 pm_runtime_put(&ch->tmu->pdev->dev); in sh_tmu_disable()
238 if (clockevent_state_oneshot(&ch->ced)) in sh_tmu_interrupt()
244 ch->ced.event_handler(&ch->ced); in sh_tmu_interrupt()
248 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) in cs_to_sh_tmu() argument
250 return container_of(cs, struct sh_tmu_channel, cs); in cs_to_sh_tmu()
253 static u64 sh_tmu_clocksource_read(struct clocksource *cs) in sh_tmu_clocksource_read() argument
255 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_read()
260 static int sh_tmu_clocksource_enable(struct clocksource *cs) in sh_tmu_clocksource_enable() argument
262 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_enable()
265 if (WARN_ON(ch->cs_enabled)) in sh_tmu_clocksource_enable()
270 ch->cs_enabled = true; in sh_tmu_clocksource_enable()
275 static void sh_tmu_clocksource_disable(struct clocksource *cs) in sh_tmu_clocksource_disable() argument
277 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_disable()
279 if (WARN_ON(!ch->cs_enabled)) in sh_tmu_clocksource_disable()
283 ch->cs_enabled = false; in sh_tmu_clocksource_disable()
286 static void sh_tmu_clocksource_suspend(struct clocksource *cs) in sh_tmu_clocksource_suspend() argument
288 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_suspend()
290 if (!ch->cs_enabled) in sh_tmu_clocksource_suspend()
293 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
295 dev_pm_genpd_suspend(&ch->tmu->pdev->dev); in sh_tmu_clocksource_suspend()
299 static void sh_tmu_clocksource_resume(struct clocksource *cs) in sh_tmu_clocksource_resume() argument
301 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_resume()
303 if (!ch->cs_enabled) in sh_tmu_clocksource_resume()
306 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
307 dev_pm_genpd_resume(&ch->tmu->pdev->dev); in sh_tmu_clocksource_resume()
315 struct clocksource *cs = &ch->cs; in sh_tmu_register_clocksource() local
317 cs->name = name; in sh_tmu_register_clocksource()
318 cs->rating = 200; in sh_tmu_register_clocksource()
319 cs->read = sh_tmu_clocksource_read; in sh_tmu_register_clocksource()
320 cs->enable = sh_tmu_clocksource_enable; in sh_tmu_register_clocksource()
321 cs->disable = sh_tmu_clocksource_disable; in sh_tmu_register_clocksource()
322 cs->suspend = sh_tmu_clocksource_suspend; in sh_tmu_register_clocksource()
323 cs->resume = sh_tmu_clocksource_resume; in sh_tmu_register_clocksource()
324 cs->mask = CLOCKSOURCE_MASK(32); in sh_tmu_register_clocksource()
325 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_tmu_register_clocksource()
327 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", in sh_tmu_register_clocksource()
328 ch->index); in sh_tmu_register_clocksource()
330 clocksource_register_hz(cs, ch->tmu->rate); in sh_tmu_register_clocksource()
344 ch->periodic = (ch->tmu->rate + HZ/2) / HZ; in sh_tmu_clock_event_start()
345 sh_tmu_set_next(ch, ch->periodic, 1); in sh_tmu_clock_event_start()
367 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", in sh_tmu_clock_event_set_state()
368 ch->index, periodic ? "periodic" : "oneshot"); in sh_tmu_clock_event_set_state()
397 dev_pm_genpd_suspend(&ced_to_sh_tmu(ced)->tmu->pdev->dev); in sh_tmu_clock_event_suspend()
402 dev_pm_genpd_resume(&ced_to_sh_tmu(ced)->tmu->pdev->dev); in sh_tmu_clock_event_resume()
408 struct clock_event_device *ced = &ch->ced; in sh_tmu_register_clockevent()
411 ced->name = name; in sh_tmu_register_clockevent()
412 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_tmu_register_clockevent()
413 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_tmu_register_clockevent()
414 ced->rating = 200; in sh_tmu_register_clockevent()
415 ced->cpumask = cpu_possible_mask; in sh_tmu_register_clockevent()
416 ced->set_next_event = sh_tmu_clock_event_next; in sh_tmu_register_clockevent()
417 ced->set_state_shutdown = sh_tmu_clock_event_shutdown; in sh_tmu_register_clockevent()
418 ced->set_state_periodic = sh_tmu_clock_event_set_periodic; in sh_tmu_register_clockevent()
419 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; in sh_tmu_register_clockevent()
420 ced->suspend = sh_tmu_clock_event_suspend; in sh_tmu_register_clockevent()
421 ced->resume = sh_tmu_clock_event_resume; in sh_tmu_register_clockevent()
423 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", in sh_tmu_register_clockevent()
424 ch->index); in sh_tmu_register_clockevent()
426 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); in sh_tmu_register_clockevent()
428 ret = request_irq(ch->irq, sh_tmu_interrupt, in sh_tmu_register_clockevent()
430 dev_name(&ch->tmu->pdev->dev), ch); in sh_tmu_register_clockevent()
432 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", in sh_tmu_register_clockevent()
433 ch->index, ch->irq); in sh_tmu_register_clockevent()
442 ch->tmu->has_clockevent = true; in sh_tmu_register()
445 ch->tmu->has_clocksource = true; in sh_tmu_register()
460 ch->tmu = tmu; in sh_tmu_channel_setup()
461 ch->index = index; in sh_tmu_channel_setup()
463 if (tmu->model == SH_TMU_SH3) in sh_tmu_channel_setup()
464 ch->base = tmu->mapbase + 4 + ch->index * 12; in sh_tmu_channel_setup()
466 ch->base = tmu->mapbase + 8 + ch->index * 12; in sh_tmu_channel_setup()
468 ch->irq = platform_get_irq(tmu->pdev, index); in sh_tmu_channel_setup()
469 if (ch->irq < 0) in sh_tmu_channel_setup()
470 return ch->irq; in sh_tmu_channel_setup()
472 ch->cs_enabled = false; in sh_tmu_channel_setup()
473 ch->enable_count = 0; in sh_tmu_channel_setup()
475 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), in sh_tmu_channel_setup()
483 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); in sh_tmu_map_memory()
485 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n"); in sh_tmu_map_memory()
486 return -ENXIO; in sh_tmu_map_memory()
489 tmu->mapbase = ioremap(res->start, resource_size(res)); in sh_tmu_map_memory()
490 if (tmu->mapbase == NULL) in sh_tmu_map_memory()
491 return -ENXIO; in sh_tmu_map_memory()
498 struct device_node *np = tmu->pdev->dev.of_node; in sh_tmu_parse_dt()
500 tmu->model = SH_TMU; in sh_tmu_parse_dt()
501 tmu->num_channels = 3; in sh_tmu_parse_dt()
503 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); in sh_tmu_parse_dt()
505 if (tmu->num_channels != 2 && tmu->num_channels != 3) { in sh_tmu_parse_dt()
506 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n", in sh_tmu_parse_dt()
507 tmu->num_channels); in sh_tmu_parse_dt()
508 return -EINVAL; in sh_tmu_parse_dt()
519 tmu->pdev = pdev; in sh_tmu_setup()
521 raw_spin_lock_init(&tmu->lock); in sh_tmu_setup()
523 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_tmu_setup()
527 } else if (pdev->dev.platform_data) { in sh_tmu_setup()
528 const struct platform_device_id *id = pdev->id_entry; in sh_tmu_setup()
529 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_tmu_setup()
531 tmu->model = id->driver_data; in sh_tmu_setup()
532 tmu->num_channels = hweight8(cfg->channels_mask); in sh_tmu_setup()
534 dev_err(&tmu->pdev->dev, "missing platform data\n"); in sh_tmu_setup()
535 return -ENXIO; in sh_tmu_setup()
539 tmu->clk = clk_get(&tmu->pdev->dev, "fck"); in sh_tmu_setup()
540 if (IS_ERR(tmu->clk)) { in sh_tmu_setup()
541 dev_err(&tmu->pdev->dev, "cannot get clock\n"); in sh_tmu_setup()
542 return PTR_ERR(tmu->clk); in sh_tmu_setup()
545 ret = clk_prepare(tmu->clk); in sh_tmu_setup()
550 ret = clk_enable(tmu->clk); in sh_tmu_setup()
554 tmu->rate = clk_get_rate(tmu->clk) / 4; in sh_tmu_setup()
555 clk_disable(tmu->clk); in sh_tmu_setup()
560 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n"); in sh_tmu_setup()
565 tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels), in sh_tmu_setup()
567 if (tmu->channels == NULL) { in sh_tmu_setup()
568 ret = -ENOMEM; in sh_tmu_setup()
576 for (i = 0; i < tmu->num_channels; ++i) { in sh_tmu_setup()
577 ret = sh_tmu_channel_setup(&tmu->channels[i], i, in sh_tmu_setup()
588 kfree(tmu->channels); in sh_tmu_setup()
589 iounmap(tmu->mapbase); in sh_tmu_setup()
591 clk_unprepare(tmu->clk); in sh_tmu_setup()
593 clk_put(tmu->clk); in sh_tmu_setup()
603 pm_runtime_set_active(&pdev->dev); in sh_tmu_probe()
604 pm_runtime_enable(&pdev->dev); in sh_tmu_probe()
608 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_tmu_probe()
614 return -ENOMEM; in sh_tmu_probe()
619 pm_runtime_idle(&pdev->dev); in sh_tmu_probe()
627 if (tmu->has_clockevent || tmu->has_clocksource) in sh_tmu_probe()
628 pm_runtime_irq_safe(&pdev->dev); in sh_tmu_probe()
630 pm_runtime_idle(&pdev->dev); in sh_tmu_probe()
636 { "sh-tmu", SH_TMU },
637 { "sh-tmu-sh3", SH_TMU_SH3 },