Lines Matching +full:cs +full:- +full:to +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
8 #include <linux/clk.h>
24 #include "spi-dw.h"
30 struct clk *clk; member
31 struct clk *pclk;
57 * Elba SoC does not use ssi, pin override is used for cs 0,1 and
58 * gpios for cs 2,3 as defined in the device tree.
60 * cs: | 1 0
61 * bit: |---3-------2-------1-------0
65 #define ELBA_SPICS_OFFSET(cs) ((cs) << 1) argument
66 #define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) argument
67 #define ELBA_SPICS_SET(cs, val) \ argument
68 ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
71 * The Designware SPI controller (referred to as master in the documentation)
73 * selects then needs to be either driven as GPIOs or, for the first 4 using
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
81 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_mscc_set_cs()
82 u32 cs = spi_get_chipselect(spi, 0); in dw_spi_mscc_set_cs() local
84 if (cs < 4) { in dw_spi_mscc_set_cs()
88 sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); in dw_spi_mscc_set_cs()
90 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_set_cs()
102 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); in dw_spi_mscc_init()
104 return -ENOMEM; in dw_spi_mscc_init()
106 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1); in dw_spi_mscc_init()
107 if (IS_ERR(dwsmscc->spi_mst)) { in dw_spi_mscc_init()
108 dev_err(&pdev->dev, "SPI_MST region map failed\n"); in dw_spi_mscc_init()
109 return PTR_ERR(dwsmscc->spi_mst); in dw_spi_mscc_init()
112 dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon); in dw_spi_mscc_init()
113 if (IS_ERR(dwsmscc->syscon)) in dw_spi_mscc_init()
114 return PTR_ERR(dwsmscc->syscon); in dw_spi_mscc_init()
116 /* Deassert all CS */ in dw_spi_mscc_init()
117 writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); in dw_spi_mscc_init()
120 regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, in dw_spi_mscc_init()
124 dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; in dw_spi_mscc_init()
125 dwsmmio->priv = dwsmscc; in dw_spi_mscc_init()
133 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon", in dw_spi_mscc_ocelot_init()
140 return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon", in dw_spi_mscc_jaguar2_init()
145 * The Designware SPI controller (referred to as master in the
147 * is empty. The chip selects then needs to be driven by a CS override
152 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_sparx5_set_cs()
154 struct dw_spi_mscc *dwsmscc = dwsmmio->priv; in dw_spi_sparx5_set_cs()
155 u8 cs = spi_get_chipselect(spi, 0); in dw_spi_sparx5_set_cs() local
158 /* CS override drive enable */ in dw_spi_sparx5_set_cs()
159 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1); in dw_spi_sparx5_set_cs()
161 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs)); in dw_spi_sparx5_set_cs()
165 /* CS value */ in dw_spi_sparx5_set_cs()
166 regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0); in dw_spi_sparx5_set_cs()
169 /* CS override drive disable */ in dw_spi_sparx5_set_cs()
170 regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0); in dw_spi_sparx5_set_cs()
179 const char *syscon_name = "microchip,sparx5-cpu-syscon"; in dw_spi_mscc_sparx5_init()
180 struct device *dev = &pdev->dev; in dw_spi_mscc_sparx5_init()
185 return -EOPNOTSUPP; in dw_spi_mscc_sparx5_init()
190 return -ENOMEM; in dw_spi_mscc_sparx5_init()
192 dwsmscc->syscon = in dw_spi_mscc_sparx5_init()
194 if (IS_ERR(dwsmscc->syscon)) { in dw_spi_mscc_sparx5_init()
196 return PTR_ERR(dwsmscc->syscon); in dw_spi_mscc_sparx5_init()
199 dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs; in dw_spi_mscc_sparx5_init()
200 dwsmmio->priv = dwsmscc; in dw_spi_mscc_sparx5_init()
208 dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE; in dw_spi_alpine_init()
216 dw_spi_dma_setup_generic(&dwsmmio->dws); in dw_spi_pssi_init()
224 dwsmmio->dws.ip = DW_HSSI_ID; in dw_spi_hssi_init()
226 dw_spi_dma_setup_generic(&dwsmmio->dws); in dw_spi_hssi_init()
234 dwsmmio->dws.ip = DW_HSSI_ID; in dw_spi_intel_init()
240 * DMA-based mem ops are not configured for this device and are not tested.
248 * result in data corruption. The suggested workaround is to never in dw_spi_mountevans_imc_init()
250 * fifo_len is set to 31. in dw_spi_mountevans_imc_init()
252 dwsmmio->dws.fifo_len = 31; in dw_spi_mountevans_imc_init()
262 * documented to have a 32 word deep TX and RX FIFO, which in dw_spi_canaan_k210_init()
263 * spi_hw_init() detects. However, when the RX FIFO is filled up to in dw_spi_canaan_k210_init()
265 * problem by force setting fifo_len to 31. in dw_spi_canaan_k210_init()
267 dwsmmio->dws.fifo_len = 31; in dw_spi_canaan_k210_init()
272 static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable) in dw_spi_elba_override_cs() argument
274 regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), in dw_spi_elba_override_cs()
275 ELBA_SPICS_SET(cs, enable)); in dw_spi_elba_override_cs()
280 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_elba_set_cs()
282 struct regmap *syscon = dwsmmio->priv; in dw_spi_elba_set_cs()
283 u8 cs; in dw_spi_elba_set_cs() local
285 cs = spi_get_chipselect(spi, 0); in dw_spi_elba_set_cs()
286 if (cs < 2) in dw_spi_elba_set_cs()
290 * The DW SPI controller needs a native CS bit selected to start in dw_spi_elba_set_cs()
295 spi_set_chipselect(spi, 0, cs); in dw_spi_elba_set_cs()
303 syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), in dw_spi_elba_init()
304 "amd,pensando-elba-syscon"); in dw_spi_elba_init()
306 return dev_err_probe(&pdev->dev, PTR_ERR(syscon), in dw_spi_elba_init()
309 dwsmmio->priv = syscon; in dw_spi_elba_init()
310 dwsmmio->dws.set_cs = dw_spi_elba_set_cs; in dw_spi_elba_init()
325 dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio), in dw_spi_mmio_probe()
328 return -ENOMEM; in dw_spi_mmio_probe()
330 dws = &dwsmmio->dws; in dw_spi_mmio_probe()
333 dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); in dw_spi_mmio_probe()
334 if (IS_ERR(dws->regs)) in dw_spi_mmio_probe()
335 return PTR_ERR(dws->regs); in dw_spi_mmio_probe()
337 dws->paddr = mem->start; in dw_spi_mmio_probe()
339 dws->irq = platform_get_irq(pdev, 0); in dw_spi_mmio_probe()
340 if (dws->irq < 0) in dw_spi_mmio_probe()
341 return dws->irq; /* -ENXIO */ in dw_spi_mmio_probe()
343 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); in dw_spi_mmio_probe()
344 if (IS_ERR(dwsmmio->clk)) in dw_spi_mmio_probe()
345 return PTR_ERR(dwsmmio->clk); in dw_spi_mmio_probe()
346 ret = clk_prepare_enable(dwsmmio->clk); in dw_spi_mmio_probe()
350 /* Optional clock needed to access the registers */ in dw_spi_mmio_probe()
351 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); in dw_spi_mmio_probe()
352 if (IS_ERR(dwsmmio->pclk)) { in dw_spi_mmio_probe()
353 ret = PTR_ERR(dwsmmio->pclk); in dw_spi_mmio_probe()
356 ret = clk_prepare_enable(dwsmmio->pclk); in dw_spi_mmio_probe()
361 dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi"); in dw_spi_mmio_probe()
362 if (IS_ERR(dwsmmio->rstc)) { in dw_spi_mmio_probe()
363 ret = PTR_ERR(dwsmmio->rstc); in dw_spi_mmio_probe()
366 reset_control_deassert(dwsmmio->rstc); in dw_spi_mmio_probe()
368 dws->bus_num = pdev->id; in dw_spi_mmio_probe()
370 dws->max_freq = clk_get_rate(dwsmmio->clk); in dw_spi_mmio_probe()
372 if (device_property_read_u32(&pdev->dev, "reg-io-width", in dw_spi_mmio_probe()
373 &dws->reg_io_width)) in dw_spi_mmio_probe()
374 dws->reg_io_width = 4; in dw_spi_mmio_probe()
378 device_property_read_u32(&pdev->dev, "num-cs", &num_cs); in dw_spi_mmio_probe()
380 dws->num_cs = num_cs; in dw_spi_mmio_probe()
382 init_func = device_get_match_data(&pdev->dev); in dw_spi_mmio_probe()
389 pm_runtime_enable(&pdev->dev); in dw_spi_mmio_probe()
391 ret = dw_spi_add_host(&pdev->dev, dws); in dw_spi_mmio_probe()
399 pm_runtime_disable(&pdev->dev); in dw_spi_mmio_probe()
400 clk_disable_unprepare(dwsmmio->pclk); in dw_spi_mmio_probe()
402 clk_disable_unprepare(dwsmmio->clk); in dw_spi_mmio_probe()
403 reset_control_assert(dwsmmio->rstc); in dw_spi_mmio_probe()
412 dw_spi_remove_host(&dwsmmio->dws); in dw_spi_mmio_remove()
413 pm_runtime_disable(&pdev->dev); in dw_spi_mmio_remove()
414 clk_disable_unprepare(dwsmmio->pclk); in dw_spi_mmio_remove()
415 clk_disable_unprepare(dwsmmio->clk); in dw_spi_mmio_remove()
416 reset_control_assert(dwsmmio->rstc); in dw_spi_mmio_remove()
420 { .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
421 { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
422 { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
423 { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
424 { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
425 { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
426 { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
427 { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
429 .compatible = "intel,mountevans-imc-ssi",
432 { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
433 { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
434 { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
458 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
459 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");