1 // SPDX-License-Identifier: GPL-2.0+
12 #include <clk.h>
38 	struct clk clk;  member
41 static void spi_cs_activate(struct spi_reg *reg, int cs)  in spi_cs_activate()  argument
43 	setbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);  in spi_cs_activate()
46 static void spi_cs_deactivate(struct spi_reg *reg, int cs)  in spi_cs_deactivate()  argument
48 	clrbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);  in spi_cs_deactivate()
52  * spi_legacy_shift_byte() - triggers the real SPI transfer
53  * @bytelen:	Indicate how many bytes to transfer.
54  * @dout:	Buffer address of what to send.
55  * @din:	Buffer address of where to receive.
58  * will shift out char buffer from @dout, and shift in char buffer to
62  * However, it is not its responisbility to set the transfer type to
63  * one-byte. Also, it does not guarantee that it will work if transfer
64  * type becomes two-byte. See spi_set_legacy() for details.
66  * In legacy mode, simply write to the SPI_DOUT register will trigger
69  * If @dout == NULL, which means no actual data needs to be sent out,
70  * then the function will shift out 0x00 in order to shift in data.
74  * The number of transfers to be triggerred is decided by @bytelen.
76  * Return:	0 - cool
77  *		-ETIMEDOUT - XFER_RDY flag timeout
96 		ret = wait_for_bit_le32(&reg->ctrl,  in spi_legacy_shift_byte()
108 		writel(pending_dout, &reg->dout);  in spi_legacy_shift_byte()
111 			ret = wait_for_bit_le32(&reg->ctrl,  in spi_legacy_shift_byte()
118 			*din_8 = (u8)readl(&reg->din);  in spi_legacy_shift_byte()
127 		bytelen--;  in spi_legacy_shift_byte()
136 	struct udevice *bus = dev->parent;  in mvebu_spi_xfer()
138 	struct spi_reg *reg = plat->spireg;  in mvebu_spi_xfer()
147 	/* Activate CS */  in mvebu_spi_xfer()
149 		debug("SPI: activate cs.\n");  in mvebu_spi_xfer()
160 	/* Deactivate CS */  in mvebu_spi_xfer()
162 		ret = wait_for_bit_le32(&reg->ctrl,  in mvebu_spi_xfer()
168 		debug("SPI: deactivate cs.\n");  in mvebu_spi_xfer()
178 	struct spi_reg *reg = plat->spireg;  in mvebu_spi_set_speed()
181 	data = readl(&reg->cfg);  in mvebu_spi_set_speed()
183 	prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);  in mvebu_spi_set_speed()
192 	writel(data, &reg->cfg);  in mvebu_spi_set_speed()
200 	struct spi_reg *reg = plat->spireg;  in mvebu_spi_set_mode()
208 		setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);  in mvebu_spi_set_mode()
210 		clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);  in mvebu_spi_set_mode()
212 		setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);  in mvebu_spi_set_mode()
214 		clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);  in mvebu_spi_set_mode()
222 	struct spi_reg *reg = plat->spireg;  in mvebu_spi_probe()
227 	 * Settings SPI controller to be working in legacy mode, which  in mvebu_spi_probe()
233 	data = readl(&reg->cfg);  in mvebu_spi_probe()
234 	writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);  in mvebu_spi_probe()
235 	ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,  in mvebu_spi_probe()
246 	writel(data, &reg->cfg);  in mvebu_spi_probe()
256 	plat->spireg = (struct spi_reg *)devfdt_get_addr(bus);  in mvebu_spi_ofdata_to_platdata()
258 	ret = clk_get_by_index(bus, 0, &plat->clk);  in mvebu_spi_ofdata_to_platdata()
271 	clk_free(&plat->clk);  in mvebu_spi_remove()
281 	 * cs_info is not needed, since we require all chip selects to be
287 	{ .compatible = "marvell,armada-3700-spi" },