1 // SPDX-License-Identifier: GPL-2.0
7  * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
38 	struct clk		*clk;  member
53  * When we disable a timer, we need to wait at least for 2 cycles of
60 	u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1));  in sun5i_clkevt_sync()
62 	while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)  in sun5i_clkevt_sync()
68 	u32 val = readl(ce->base + TIMER_CTL_REG(timer));  in sun5i_clkevt_time_stop()
69 	writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));  in sun5i_clkevt_time_stop()
76 	writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));  in sun5i_clkevt_time_setup()
81 	u32 val = readl(ce->base + TIMER_CTL_REG(timer));  in sun5i_clkevt_time_start()
89 	       ce->base + TIMER_CTL_REG(timer));  in sun5i_clkevt_time_start()
114 	sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy);  in sun5i_clkevt_set_periodic()
125 	sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);  in sun5i_clkevt_next_event()
135 	writel(0x1, ce->base + TIMER_IRQ_ST_REG);  in sun5i_timer_interrupt()
136 	ce->clkevt.event_handler(&ce->clkevt);  in sun5i_timer_interrupt()
143 	struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc);  in sun5i_clksrc_read()  local
145 	return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1));  in sun5i_clksrc_read()
152 	struct sun5i_timer *cs = nb_to_sun5i_timer(nb);  in sun5i_rate_cb()  local
156 		clocksource_unregister(&cs->clksrc);  in sun5i_rate_cb()
160 		clocksource_register_hz(&cs->clksrc, ndata->new_rate);  in sun5i_rate_cb()
161 		clockevents_update_freq(&cs->clkevt, ndata->new_rate);  in sun5i_rate_cb()
162 		cs->ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);  in sun5i_rate_cb()
175 	struct sun5i_timer *cs = platform_get_drvdata(pdev);  in sun5i_setup_clocksource()  local
176 	void __iomem *base = cs->base;  in sun5i_setup_clocksource()
183 	cs->clksrc.name = pdev->dev.of_node->name;  in sun5i_setup_clocksource()
184 	cs->clksrc.rating = 340;  in sun5i_setup_clocksource()
185 	cs->clksrc.read = sun5i_clksrc_read;  in sun5i_setup_clocksource()
186 	cs->clksrc.mask = CLOCKSOURCE_MASK(32);  in sun5i_setup_clocksource()
187 	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in sun5i_setup_clocksource()
189 	ret = clocksource_register_hz(&cs->clksrc, rate);  in sun5i_setup_clocksource()
191 		dev_err(&pdev->dev, "Couldn't register clock source.\n");  in sun5i_setup_clocksource()
201 	struct device *dev = &pdev->dev;  in sun5i_setup_clockevent()
203 	void __iomem *base = ce->base;  in sun5i_setup_clockevent()
207 	ce->clkevt.name = dev->of_node->name;  in sun5i_setup_clockevent()
208 	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;  in sun5i_setup_clockevent()
209 	ce->clkevt.set_next_event = sun5i_clkevt_next_event;  in sun5i_setup_clockevent()
210 	ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;  in sun5i_setup_clockevent()
211 	ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;  in sun5i_setup_clockevent()
212 	ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;  in sun5i_setup_clockevent()
213 	ce->clkevt.tick_resume = sun5i_clkevt_shutdown;  in sun5i_setup_clockevent()
214 	ce->clkevt.rating = 340;  in sun5i_setup_clockevent()
215 	ce->clkevt.irq = irq;  in sun5i_setup_clockevent()
216 	ce->clkevt.cpumask = cpu_possible_mask;  in sun5i_setup_clockevent()
222 	clockevents_config_and_register(&ce->clkevt, rate,  in sun5i_setup_clockevent()
229 		dev_err(dev, "Unable to register interrupt\n");  in sun5i_setup_clockevent()
238 	struct device *dev = &pdev->dev;  in sun5i_timer_probe()
242 	struct clk *clk;  in sun5i_timer_probe()  local
248 		return -ENOMEM;  in sun5i_timer_probe()
264 	clk = devm_clk_get_enabled(dev, NULL);  in sun5i_timer_probe()
265 	if (IS_ERR(clk)) {  in sun5i_timer_probe()
267 		return PTR_ERR(clk);  in sun5i_timer_probe()
270 	rate = clk_get_rate(clk);  in sun5i_timer_probe()
273 		return -EINVAL;  in sun5i_timer_probe()
276 	st->base = timer_base;  in sun5i_timer_probe()
277 	st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);  in sun5i_timer_probe()
278 	st->clk = clk;  in sun5i_timer_probe()
279 	st->clk_rate_cb.notifier_call = sun5i_rate_cb;  in sun5i_timer_probe()
280 	st->clk_rate_cb.next = NULL;  in sun5i_timer_probe()
282 	ret = devm_clk_notifier_register(dev, clk, &st->clk_rate_cb);  in sun5i_timer_probe()
284 		dev_err(dev, "Unable to register clock notifier.\n");  in sun5i_timer_probe()
303 	clocksource_unregister(&st->clksrc);  in sun5i_timer_probe()
311 	clocksource_unregister(&st->clksrc);  in sun5i_timer_remove()
315 	{ .compatible = "allwinner,sun5i-a13-hstimer" },
316 	{ .compatible = "allwinner,sun7i-a20-hstimer" },
325 		.name	= "sun5i-timer",