1 // SPDX-License-Identifier: GPL-2.0+
5  * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
6  *	Copyright (C) 2000-2010 Broadcom Corporation
7  *	Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
11 #include <clk.h>
38 /* SPI Ping-Pong Command registers */
47 /* SPI Ping-Pong Status registers */
79 /* SPI Ping-Pong FIFO registers */
84 /* SPI Ping-Pong FIFO OP register */
104 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,  in bcm63xx_hsspi_cs_info()  argument
109 	if (cs >= priv->num_cs) {  in bcm63xx_hsspi_cs_info()
110 		printf("no cs %u\n", cs);  in bcm63xx_hsspi_cs_info()
111 		return -ENODEV;  in bcm63xx_hsspi_cs_info()
123 		setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);  in bcm63xx_hsspi_set_mode()
125 		clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);  in bcm63xx_hsspi_set_mode()
134 	priv->speed = speed;  in bcm63xx_hsspi_set_speed()
145 	set = DIV_ROUND_UP(priv->clk_rate, priv->speed);  in bcm63xx_hsspi_activate_cs()
149 	writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));  in bcm63xx_hsspi_activate_cs()
158 	if (plat->mode & SPI_CPHA)  in bcm63xx_hsspi_activate_cs()
163 	/* async clk */  in bcm63xx_hsspi_activate_cs()
164 	if (priv->speed > SPI_MAX_SYNC_CLOCK)  in bcm63xx_hsspi_activate_cs()
167 	clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);  in bcm63xx_hsspi_activate_cs()
173 	/* invert cs polarity */  in bcm63xx_hsspi_activate_cs()
174 	if (priv->cs_pols & BIT(plat->cs))  in bcm63xx_hsspi_activate_cs()
175 		clr |= BIT(plat->cs);  in bcm63xx_hsspi_activate_cs()
177 		set |= BIT(plat->cs);  in bcm63xx_hsspi_activate_cs()
179 	/* invert dummy cs polarity */  in bcm63xx_hsspi_activate_cs()
180 	if (priv->cs_pols & BIT(!plat->cs))  in bcm63xx_hsspi_activate_cs()
181 		clr |= BIT(!plat->cs);  in bcm63xx_hsspi_activate_cs()
183 		set |= BIT(!plat->cs);  in bcm63xx_hsspi_activate_cs()
185 	clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);  in bcm63xx_hsspi_activate_cs()
190 	/* restore cs polarities */  in bcm63xx_hsspi_deactivate_cs()
191 	clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,  in bcm63xx_hsspi_deactivate_cs()
192 			priv->cs_pols);  in bcm63xx_hsspi_deactivate_cs()
196  * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
198  * However, it provides a mechanism to prepend write transfers prior to read
200  * SPI-connected flashes since reading requires prepending a write transfer of
201  * 5 bytes. On the other hand it also provides a way to invert each CS
206  * polarity of both the desired CS and another dummy CS when the bus is
207  * claimed. This way, the dummy CS is restored to its inactive value when
208  * transfers are issued and the desired CS is preserved in its active value
210  * allows keeping CS active between trasnfers even if the HW doesn't give
216 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);  in bcm63xx_hsspi_xfer()
237 		step_size -= HSSPI_FIFO_OP_SIZE;  in bcm63xx_hsspi_xfer()
240 	if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||  in bcm63xx_hsspi_xfer()
241 	    (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))  in bcm63xx_hsspi_xfer()
248 	if (plat->mode & SPI_3WIRE)  in bcm63xx_hsspi_xfer()
250 	writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));  in bcm63xx_hsspi_xfer()
259 			memcpy_toio(priv->regs + HSSPI_FIFO_BASE +  in bcm63xx_hsspi_xfer()
266 			  priv->regs + HSSPI_FIFO_OP_REG);  in bcm63xx_hsspi_xfer()
270 		val |= (plat->cs << SPI_CMD_PFL_SHIFT) &  in bcm63xx_hsspi_xfer()
272 		val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &  in bcm63xx_hsspi_xfer()
274 		writel_be(val, priv->regs + SPI_CMD_REG);  in bcm63xx_hsspi_xfer()
277 		ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,  in bcm63xx_hsspi_xfer()
287 			memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,  in bcm63xx_hsspi_xfer()
292 		data_bytes -= curr_step;  in bcm63xx_hsspi_xfer()
309 	{ .compatible = "brcm,bcm6328-hsspi", },
315 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);  in bcm63xx_hsspi_child_pre_probe()
318 	/* check cs */  in bcm63xx_hsspi_child_pre_probe()
319 	if (plat->cs >= priv->num_cs) {  in bcm63xx_hsspi_child_pre_probe()
320 		printf("no cs %u\n", plat->cs);  in bcm63xx_hsspi_child_pre_probe()
321 		return -ENODEV;  in bcm63xx_hsspi_child_pre_probe()
324 	/* cs polarity */  in bcm63xx_hsspi_child_pre_probe()
325 	if (plat->mode & SPI_CS_HIGH)  in bcm63xx_hsspi_child_pre_probe()
326 		priv->cs_pols |= BIT(plat->cs);  in bcm63xx_hsspi_child_pre_probe()
328 		priv->cs_pols &= ~BIT(plat->cs);  in bcm63xx_hsspi_child_pre_probe()
337 	struct clk clk;  in bcm63xx_hsspi_probe()  local
340 	priv->regs = dev_remap_addr(dev);  in bcm63xx_hsspi_probe()
341 	if (!priv->regs)  in bcm63xx_hsspi_probe()
342 		return -EINVAL;  in bcm63xx_hsspi_probe()
344 	priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);  in bcm63xx_hsspi_probe()
347 	ret = clk_get_by_name(dev, "hsspi", &clk);  in bcm63xx_hsspi_probe()
351 	ret = clk_enable(&clk);  in bcm63xx_hsspi_probe()
355 	ret = clk_free(&clk);  in bcm63xx_hsspi_probe()
360 	ret = clk_get_by_name(dev, "pll", &clk);  in bcm63xx_hsspi_probe()
364 	priv->clk_rate = clk_get_rate(&clk);  in bcm63xx_hsspi_probe()
366 	ret = clk_free(&clk);  in bcm63xx_hsspi_probe()
384 	writel_be(0, priv->regs + SPI_IR_MASK_REG);  in bcm63xx_hsspi_probe()
387 	writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);  in bcm63xx_hsspi_probe()
389 	/* enable clk gate */  in bcm63xx_hsspi_probe()
390 	setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);  in bcm63xx_hsspi_probe()
392 	/* read default cs polarities */  in bcm63xx_hsspi_probe()
393 	priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &  in bcm63xx_hsspi_probe()