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12

/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
21 pinctrl-0 = <&duart_pins_a>;
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 partition@0 {
32 reg = <0x0 0x300000>;
37 reg = <0x300000 0x80000>;
42 reg = <0x380000 0x80000>;
47 reg = <0x400000 0x80000>;
52 reg = <0x480000 0x80000>;
57 reg = <0x500000 0x800000>;
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cc108.dts29 memory@0 {
31 reg = <0x0 0x20000000>;
36 #phy-cells = <0>;
41 #phy-cells = <0>;
58 is-dual = <0>;
60 flash@0 { /* 16 MB */
62 reg = <0x0>;
68 partition@0 {
70 reg = <0x0 0x400000>; /* 4MB */
74 reg = <0x400000 0x400000>; /* 4MB */
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-io.h23 iwl_trans_set_bits_mask(trans, reg, mask, 0); in iwl_clear_bit()
44 iwl_write_prph_delay(trans, ofs, val, 0); in iwl_write_prph()
61 * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm6115-tlmm.yaml65 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
107 reg = <0x500000 0x400000>,
108 <0x900000 0x400000>,
109 <0xd00000 0x400000>;
116 gpio-ranges = <&tlmm 0 0 114>;
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sm-k26-revA.dts48 memory@0 {
50 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
59 reg = <0x0 0x7ff00000 0x0 0x100000>;
93 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
131 &qspi { /* MIO 0-5 - U143 */
133 spi_flash: flash@0 { /* MT25QU512A */
137 reg = <0>;
147 partition@0 {
149 reg = <0x0 0x80000>; /* 512KB */
155 reg = <0x80000 0x80000>; /* 512KB */
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dls1088a_common.h29 #define LS1088ARDB_PB_BOARD 0x4A
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
42 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
43 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
53 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
55 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
75 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
86 * During booting, IFC is mapped at the region of 0x30000000.
[all …]
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
75 flash@0 {
77 reg = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml23 pattern: "^iommu@[0-9a-f]*"
156 minimum: 0
506 reg = <0xba5e0000 0x10000>;
508 interrupts = <0 32 4>,
509 <0 33 4>,
510 <0 34 4>, /* This is the first context interrupt */
511 <0 35 4>,
512 <0 36 4>,
513 <0 37 4>;
517 /* device with two stream IDs, 0 and 7 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 clocks = <&kryocc 0>;
67 reg = <0x0 0x1>;
71 clocks = <&kryocc 0>;
81 reg = <0x0 0x100>;
100 reg = <0x0 0x101>;
[all …]
H A Dmsm8998.dtsi15 qcom,msm-id = <292 0x0>;
25 reg = <0x0 0x80000000 0x0 0x0>;
34 reg = <0x0 0x85800000 0x0 0x600000>;
39 reg = <0x0 0x85e00000 0x0 0x100000>;
44 reg = <0x0 0x86000000 0x0 0x200000>;
49 reg = <0x0 0x86200000 0x0 0x2d00000>;
55 reg = <0x0 0x88f00000 0x0 0x200000>;
63 reg = <0x0 0x8ab00000 0x0 0x700000>;
68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]
/openbmc/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_cmds.h28 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
29 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
30 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
32 u32 embedded; /* dword 0 */
50 MCC_STATUS_SUCCESS = 0,
63 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
64 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
65 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
66 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab,
67 MCC_ADDL_STATUS_INVALID_SIGNATURE = 0x56,
[all …]
/openbmc/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc31 { "MMID", 89, 0 },
32 { "DDR", 104, 0 },
33 { "176", 176, 0 },
34 { "208", 208, 0 },
35 { "INTERRUPT", 226, 0 },
36 { "INTCLEAR", 227, 0 },
37 { "CCOUNT", 234, 0 },
38 { "PRID", 235, 0 },
39 { "ICOUNT", 236, 0 },
40 { "CCOMPARE0", 240, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]

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