Lines Matching +full:0 +full:xd00000
3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "PTEVADDR", 83, 0 },
42 { "MMID", 89, 0 },
43 { "DDR", 104, 0 },
44 { "176", 176, 0 },
45 { "208", 208, 0 },
46 { "INTERRUPT", 226, 0 },
47 { "INTCLEAR", 227, 0 },
48 { "CCOUNT", 234, 0 },
49 { "PRID", 235, 0 },
50 { "ICOUNT", 236, 0 },
51 { "CCOMPARE0", 240, 0 },
52 { "CCOMPARE1", 241, 0 },
53 { "CCOMPARE2", 242, 0 },
54 { "VECBASE", 231, 0 },
55 { "EPC1", 177, 0 },
56 { "EPC2", 178, 0 },
57 { "EPC3", 179, 0 },
58 { "EPC4", 180, 0 },
59 { "EPC5", 181, 0 },
60 { "EPC6", 182, 0 },
61 { "EPC7", 183, 0 },
62 { "EXCSAVE1", 209, 0 },
63 { "EXCSAVE2", 210, 0 },
64 { "EXCSAVE3", 211, 0 },
65 { "EXCSAVE4", 212, 0 },
66 { "EXCSAVE5", 213, 0 },
67 { "EXCSAVE6", 214, 0 },
68 { "EXCSAVE7", 215, 0 },
69 { "EPS2", 194, 0 },
70 { "EPS3", 195, 0 },
71 { "EPS4", 196, 0 },
72 { "EPS5", 197, 0 },
73 { "EPS6", 198, 0 },
74 { "EPS7", 199, 0 },
75 { "EXCCAUSE", 232, 0 },
76 { "DEPC", 192, 0 },
77 { "EXCVADDR", 238, 0 },
78 { "WINDOWBASE", 72, 0 },
79 { "WINDOWSTART", 73, 0 },
80 { "SAR", 3, 0 },
81 { "LITBASE", 5, 0 },
82 { "PS", 230, 0 },
83 { "MISC0", 244, 0 },
84 { "MISC1", 245, 0 },
85 { "INTENABLE", 228, 0 },
86 { "DBREAKA0", 144, 0 },
87 { "DBREAKC0", 160, 0 },
88 { "DBREAKA1", 145, 0 },
89 { "DBREAKC1", 161, 0 },
90 { "IBREAKA0", 128, 0 },
91 { "IBREAKA1", 129, 0 },
92 { "IBREAKENABLE", 96, 0 },
93 { "ICOUNTLEVEL", 237, 0 },
94 { "DEBUGCAUSE", 233, 0 },
95 { "RASID", 90, 0 },
96 { "ITLBCFG", 91, 0 },
97 { "DTLBCFG", 92, 0 },
98 { "CPENABLE", 224, 0 },
99 { "SCOMPARE1", 12, 0 },
100 { "ATOMCTL", 99, 0 },
113 { "LCOUNT", 32, 0 },
114 { "PC", 32, 0 },
115 { "ICOUNT", 32, 0 },
116 { "DDR", 32, 0 },
117 { "INTERRUPT", 22, 0 },
118 { "CCOUNT", 32, 0 },
119 { "XTSYNC", 1, 0 },
120 { "VECBASE", 22, 0 },
121 { "EPC1", 32, 0 },
122 { "EPC2", 32, 0 },
123 { "EPC3", 32, 0 },
124 { "EPC4", 32, 0 },
125 { "EPC5", 32, 0 },
126 { "EPC6", 32, 0 },
127 { "EPC7", 32, 0 },
128 { "EXCSAVE1", 32, 0 },
129 { "EXCSAVE2", 32, 0 },
130 { "EXCSAVE3", 32, 0 },
131 { "EXCSAVE4", 32, 0 },
132 { "EXCSAVE5", 32, 0 },
133 { "EXCSAVE6", 32, 0 },
134 { "EXCSAVE7", 32, 0 },
135 { "EPS2", 15, 0 },
136 { "EPS3", 15, 0 },
137 { "EPS4", 15, 0 },
138 { "EPS5", 15, 0 },
139 { "EPS6", 15, 0 },
140 { "EPS7", 15, 0 },
141 { "EXCCAUSE", 6, 0 },
142 { "PSINTLEVEL", 4, 0 },
143 { "PSUM", 1, 0 },
144 { "PSWOE", 1, 0 },
145 { "PSRING", 2, 0 },
146 { "PSEXCM", 1, 0 },
147 { "DEPC", 32, 0 },
148 { "EXCVADDR", 32, 0 },
149 { "WindowBase", 3, 0 },
150 { "WindowStart", 8, 0 },
151 { "PSCALLINC", 2, 0 },
152 { "PSOWB", 4, 0 },
153 { "LBEG", 32, 0 },
154 { "LEND", 32, 0 },
155 { "SAR", 6, 0 },
156 { "THREADPTR", 32, 0 },
157 { "LITBADDR", 20, 0 },
158 { "LITBEN", 1, 0 },
159 { "MISC0", 32, 0 },
160 { "MISC1", 32, 0 },
161 { "ACC", 40, 0 },
162 { "InOCDMode", 1, 0 },
163 { "INTENABLE", 22, 0 },
164 { "DBREAKA0", 32, 0 },
165 { "DBREAKC0", 8, 0 },
166 { "DBREAKA1", 32, 0 },
167 { "DBREAKC1", 8, 0 },
168 { "IBREAKA0", 32, 0 },
169 { "IBREAKA1", 32, 0 },
170 { "IBREAKENABLE", 2, 0 },
171 { "ICOUNTLEVEL", 4, 0 },
172 { "DEBUGCAUSE", 6, 0 },
173 { "DBNUM", 4, 0 },
174 { "CCOMPARE0", 32, 0 },
175 { "CCOMPARE1", 32, 0 },
176 { "CCOMPARE2", 32, 0 },
177 { "ASID3", 8, 0 },
178 { "ASID2", 8, 0 },
179 { "ASID1", 8, 0 },
180 { "INSTPGSZID6", 1, 0 },
181 { "INSTPGSZID5", 1, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID6", 1, 0 },
184 { "DATAPGSZID5", 1, 0 },
185 { "DATAPGSZID4", 2, 0 },
186 { "PTBASE", 10, 0 },
187 { "CPENABLE", 8, 0 },
188 { "SCOMPARE1", 32, 0 },
189 { "ATOMCTL", 6, 0 },
282 unsigned tie_t = 0;
283 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
292 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
298 unsigned tie_t = 0;
299 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
308 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
314 unsigned tie_t = 0;
315 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
324 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
330 unsigned tie_t = 0;
331 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
340 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
346 unsigned tie_t = 0;
347 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
356 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
362 unsigned tie_t = 0;
363 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
372 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
378 unsigned tie_t = 0;
379 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
388 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
394 unsigned tie_t = 0;
395 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
404 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
410 unsigned tie_t = 0;
411 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
412 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
421 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
423 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
429 unsigned tie_t = 0;
430 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
431 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
440 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
442 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
448 unsigned tie_t = 0;
449 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
458 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
464 unsigned tie_t = 0;
465 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
474 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
480 unsigned tie_t = 0;
481 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
490 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
496 unsigned tie_t = 0;
497 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
506 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
512 unsigned tie_t = 0;
513 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
522 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
528 unsigned tie_t = 0;
529 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
538 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
544 unsigned tie_t = 0;
545 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
554 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
560 unsigned tie_t = 0;
561 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
570 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
576 unsigned tie_t = 0;
577 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
586 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
592 unsigned tie_t = 0;
593 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
602 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
608 unsigned tie_t = 0;
609 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
618 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
624 unsigned tie_t = 0;
625 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
634 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
640 unsigned tie_t = 0;
641 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
650 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
656 unsigned tie_t = 0;
657 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
666 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
672 unsigned tie_t = 0;
673 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
682 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
688 unsigned tie_t = 0;
689 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
698 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
704 unsigned tie_t = 0;
705 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
706 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
715 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
717 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
723 unsigned tie_t = 0;
724 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
733 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
739 unsigned tie_t = 0;
740 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
749 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
755 unsigned tie_t = 0;
756 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
765 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
771 unsigned tie_t = 0;
772 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
773 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
782 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
784 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
790 unsigned tie_t = 0;
791 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
800 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
806 unsigned tie_t = 0;
807 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
816 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
822 unsigned tie_t = 0;
823 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
832 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
838 unsigned tie_t = 0;
839 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
848 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
854 unsigned tie_t = 0;
855 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
864 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
870 unsigned tie_t = 0;
871 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
872 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
881 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
883 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
889 unsigned tie_t = 0;
890 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
891 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
900 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
902 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
908 unsigned tie_t = 0;
909 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
910 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
919 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
921 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
927 unsigned tie_t = 0;
928 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
937 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
943 unsigned tie_t = 0;
944 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
945 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
954 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
956 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
962 unsigned tie_t = 0;
963 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
964 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
973 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
975 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
981 unsigned tie_t = 0;
982 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
983 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
992 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
994 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1000 unsigned tie_t = 0;
1001 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1002 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1011 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1013 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1019 unsigned tie_t = 0;
1020 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1021 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1030 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1032 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1038 unsigned tie_t = 0;
1039 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1048 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1054 unsigned tie_t = 0;
1055 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1064 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1070 unsigned tie_t = 0;
1071 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1080 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1086 unsigned tie_t = 0;
1087 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1088 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1097 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1099 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1105 unsigned tie_t = 0;
1106 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1115 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1121 unsigned tie_t = 0;
1122 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1131 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1137 unsigned tie_t = 0;
1138 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1147 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1153 unsigned tie_t = 0;
1154 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1163 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1169 unsigned tie_t = 0;
1170 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1179 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1185 unsigned tie_t = 0;
1186 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1195 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1201 unsigned tie_t = 0;
1202 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1211 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1217 unsigned tie_t = 0;
1218 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1227 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1233 unsigned tie_t = 0;
1234 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1243 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1249 unsigned tie_t = 0;
1250 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1259 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1265 unsigned tie_t = 0;
1266 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1267 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1276 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1278 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1284 unsigned tie_t = 0;
1285 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1286 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1295 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1297 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1303 unsigned tie_t = 0;
1304 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1305 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1314 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1316 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1322 unsigned tie_t = 0;
1323 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1324 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1333 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1335 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1341 unsigned tie_t = 0;
1342 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1351 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1357 unsigned tie_t = 0;
1358 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1367 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1373 unsigned tie_t = 0;
1374 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1383 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1389 unsigned tie_t = 0;
1390 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1399 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1405 unsigned tie_t = 0;
1406 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1415 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1421 unsigned tie_t = 0;
1422 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1431 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1437 unsigned tie_t = 0;
1438 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1439 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1448 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1450 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1456 unsigned tie_t = 0;
1457 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1458 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1467 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1469 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1475 unsigned tie_t = 0;
1476 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1477 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1486 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1488 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1494 unsigned tie_t = 0;
1495 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1504 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1510 unsigned tie_t = 0;
1511 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1520 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1533 return 0;
1557 return 0;
1661 { "IMPWIRE", 32, 0, 0, 'i' }
1673 0xffffffff,
1674 0x1,
1675 0x2,
1676 0x3,
1677 0x4,
1678 0x5,
1679 0x6,
1680 0x7,
1681 0x8,
1682 0x9,
1683 0xa,
1684 0xb,
1685 0xc,
1686 0xd,
1687 0xe,
1688 0xf,
1689 0
1694 0xffffffff,
1695 0x1,
1696 0x2,
1697 0x3,
1698 0x4,
1699 0x5,
1700 0x6,
1701 0x7,
1702 0x8,
1703 0xa,
1704 0xc,
1705 0x10,
1706 0x20,
1707 0x40,
1708 0x80,
1709 0x100,
1710 0
1715 0x8000,
1716 0x10000,
1717 0x2,
1718 0x3,
1719 0x4,
1720 0x5,
1721 0x6,
1722 0x7,
1723 0x8,
1724 0xa,
1725 0xc,
1726 0x10,
1727 0x20,
1728 0x40,
1729 0x80,
1730 0x100,
1731 0
1741 offset_0 = *valp & 0x3ffff;
1742 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1744 return 0;
1752 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1754 return 0;
1760 *valp -= (pc & ~0x3);
1761 return 0;
1767 *valp += (pc & ~0x3);
1768 return 0;
1775 imm12_0 = *valp & 0xfff;
1778 return 0;
1786 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1788 return 0;
1795 mn_0 = *valp & 0xf;
1798 return 0;
1806 mn_0 = (simm4_0 & 0xf);
1808 return 0;
1814 return 0;
1820 return (*valp & ~0xf) != 0;
1826 return 0;
1832 return (*valp & ~0xf) != 0;
1838 return 0;
1844 return (*valp & ~0xf) != 0;
1850 return 0;
1856 return (*valp & ~0x1f) != 0;
1862 return 0;
1868 return (*valp & ~0x1f) != 0;
1874 return 0;
1880 return (*valp & ~0x1f) != 0;
1886 return 0;
1892 return (*valp & ~0x1f) != 0;
1898 return 0;
1904 return (*valp & ~0x1f) != 0;
1911 r_0 = *valp & 0xf;
1912 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1914 return 0;
1922 r_0 = ((immrx4_0 >> 2) & 0xf);
1924 return 0;
1931 r_0 = *valp & 0xf;
1934 return 0;
1942 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1944 return 0;
1951 imm7_0 = *valp & 0x7f;
1952 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1954 return 0;
1962 imm7_0 = (simm7_0 & 0x7f);
1964 return 0;
1971 imm6_0 = *valp & 0x3f;
1972 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1974 return 0;
1982 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1984 return 0;
1991 return 0;
1998 return 0;
2005 t_0 = *valp & 0xf;
2006 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
2008 return 0;
2018 case 0xffffffff: t_0 = 0; break;
2019 case 0x1: t_0 = 0x1; break;
2020 case 0x2: t_0 = 0x2; break;
2021 case 0x3: t_0 = 0x3; break;
2022 case 0x4: t_0 = 0x4; break;
2023 case 0x5: t_0 = 0x5; break;
2024 case 0x6: t_0 = 0x6; break;
2025 case 0x7: t_0 = 0x7; break;
2026 case 0x8: t_0 = 0x8; break;
2027 case 0x9: t_0 = 0x9; break;
2028 case 0xa: t_0 = 0xa; break;
2029 case 0xb: t_0 = 0xb; break;
2030 case 0xc: t_0 = 0xc; break;
2031 case 0xd: t_0 = 0xd; break;
2032 case 0xe: t_0 = 0xe; break;
2033 default: t_0 = 0xf; break;
2036 return 0;
2043 r_0 = *valp & 0xf;
2044 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
2046 return 0;
2056 case 0xffffffff: r_0 = 0; break;
2057 case 0x1: r_0 = 0x1; break;
2058 case 0x2: r_0 = 0x2; break;
2059 case 0x3: r_0 = 0x3; break;
2060 case 0x4: r_0 = 0x4; break;
2061 case 0x5: r_0 = 0x5; break;
2062 case 0x6: r_0 = 0x6; break;
2063 case 0x7: r_0 = 0x7; break;
2064 case 0x8: r_0 = 0x8; break;
2065 case 0xa: r_0 = 0x9; break;
2066 case 0xc: r_0 = 0xa; break;
2067 case 0x10: r_0 = 0xb; break;
2068 case 0x20: r_0 = 0xc; break;
2069 case 0x40: r_0 = 0xd; break;
2070 case 0x80: r_0 = 0xe; break;
2071 default: r_0 = 0xf; break;
2074 return 0;
2081 r_0 = *valp & 0xf;
2082 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2084 return 0;
2094 case 0x8000: r_0 = 0; break;
2095 case 0x10000: r_0 = 0x1; break;
2096 case 0x2: r_0 = 0x2; break;
2097 case 0x3: r_0 = 0x3; break;
2098 case 0x4: r_0 = 0x4; break;
2099 case 0x5: r_0 = 0x5; break;
2100 case 0x6: r_0 = 0x6; break;
2101 case 0x7: r_0 = 0x7; break;
2102 case 0x8: r_0 = 0x8; break;
2103 case 0xa: r_0 = 0x9; break;
2104 case 0xc: r_0 = 0xa; break;
2105 case 0x10: r_0 = 0xb; break;
2106 case 0x20: r_0 = 0xc; break;
2107 case 0x40: r_0 = 0xd; break;
2108 case 0x80: r_0 = 0xe; break;
2109 default: r_0 = 0xf; break;
2112 return 0;
2119 imm8_0 = *valp & 0xff;
2122 return 0;
2130 imm8_0 = (uimm8_0 & 0xff);
2132 return 0;
2139 imm8_0 = *valp & 0xff;
2142 return 0;
2150 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2152 return 0;
2159 imm8_0 = *valp & 0xff;
2162 return 0;
2170 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2172 return 0;
2179 op2_0 = *valp & 0xf;
2182 return 0;
2190 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2192 return 0;
2199 imm8_0 = *valp & 0xff;
2202 return 0;
2210 imm8_0 = (simm8_0 & 0xff);
2212 return 0;
2219 imm8_0 = *valp & 0xff;
2222 return 0;
2230 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2232 return 0;
2239 imm12b_0 = *valp & 0xfff;
2242 return 0;
2250 imm12b_0 = (simm12b_0 & 0xfff);
2252 return 0;
2259 sal_0 = *valp & 0x1f;
2260 msalp32_0 = 0x20 - sal_0;
2262 return 0;
2270 sal_0 = (0x20 - msalp32_0) & 0x1f;
2272 return 0;
2279 op2_0 = *valp & 0xf;
2280 op2p1_0 = op2_0 + 0x1;
2282 return 0;
2290 op2_0 = (op2p1_0 - 0x1) & 0xf;
2292 return 0;
2299 imm8_0 = *valp & 0xff;
2300 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2302 return 0;
2310 imm8_0 = (label8_0 - 0x4) & 0xff;
2312 return 0;
2319 return 0;
2326 return 0;
2333 imm8_0 = *valp & 0xff;
2334 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2336 return 0;
2344 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2346 return 0;
2353 return 0;
2360 return 0;
2367 imm12_0 = *valp & 0xfff;
2368 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2370 return 0;
2378 imm12_0 = (label12_0 - 0x4) & 0xfff;
2380 return 0;
2387 return 0;
2394 return 0;
2401 offset_0 = *valp & 0x3ffff;
2402 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2404 return 0;
2412 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2414 return 0;
2421 return 0;
2428 return 0;
2435 imm16_0 = *valp & 0xffff;
2436 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2438 return 0;
2446 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2448 return 0;
2454 *valp -= ((pc + 3) & ~0x3);
2455 return 0;
2461 *valp += ((pc + 3) & ~0x3);
2462 return 0;
2468 return 0;
2474 return (*valp & ~0x3) != 0;
2481 return 0;
2488 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2496 return 0;
2502 return (*valp & ~0x3) != 0;
2508 return 0;
2514 return (*valp & ~0x3) != 0;
2520 return 0;
2526 return (*valp & ~0x3) != 0;
2532 return 0;
2538 return (*valp & ~0x3) != 0;
2544 return 0;
2550 return (*valp & ~0x3) != 0;
2557 t_0 = *valp & 0xf;
2560 return 0;
2568 t_0 = immt_0 & 0xf;
2570 return 0;
2577 s_0 = *valp & 0xf;
2580 return 0;
2588 s_0 = imms_0 & 0xf;
2590 return 0;
2597 t_0 = *valp & 0xf;
2598 tp7_0 = t_0 + 0x7;
2600 return 0;
2608 t_0 = (tp7_0 - 0x7) & 0xf;
2610 return 0;
2617 xt_wbr15_imm_0 = *valp & 0x7fff;
2618 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2620 return 0;
2628 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2630 return 0;
2637 return 0;
2644 return 0;
2651 xt_wbr18_imm_0 = *valp & 0x3ffff;
2652 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2654 return 0;
2662 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2664 return 0;
2671 return 0;
2678 return 0;
2682 { "soffsetx4", FIELD_offset, -1, 0,
2686 { "uimm12x8", FIELD_imm12, -1, 0,
2687 0,
2689 0, 0 },
2690 { "simm4", FIELD_mn, -1, 0,
2691 0,
2693 0, 0 },
2697 0, 0 },
2701 0, 0 },
2705 0, 0 },
2709 0, 0 },
2713 0, 0 },
2717 0, 0 },
2721 0, 0 },
2725 0, 0 },
2729 0, 0 },
2730 { "immrx4", FIELD_r, -1, 0,
2731 0,
2733 0, 0 },
2734 { "lsi4x4", FIELD_r, -1, 0,
2735 0,
2737 0, 0 },
2738 { "simm7", FIELD_imm7, -1, 0,
2739 0,
2741 0, 0 },
2742 { "uimm6", FIELD_imm6, -1, 0,
2746 { "ai4const", FIELD_t, -1, 0,
2747 0,
2749 0, 0 },
2750 { "b4const", FIELD_r, -1, 0,
2751 0,
2753 0, 0 },
2754 { "b4constu", FIELD_r, -1, 0,
2755 0,
2757 0, 0 },
2758 { "uimm8", FIELD_imm8, -1, 0,
2759 0,
2761 0, 0 },
2762 { "uimm8x2", FIELD_imm8, -1, 0,
2763 0,
2765 0, 0 },
2766 { "uimm8x4", FIELD_imm8, -1, 0,
2767 0,
2769 0, 0 },
2770 { "uimm4x16", FIELD_op2, -1, 0,
2771 0,
2773 0, 0 },
2774 { "simm8", FIELD_imm8, -1, 0,
2775 0,
2777 0, 0 },
2778 { "simm8x256", FIELD_imm8, -1, 0,
2779 0,
2781 0, 0 },
2782 { "simm12b", FIELD_imm12b, -1, 0,
2783 0,
2785 0, 0 },
2786 { "msalp32", FIELD_sal, -1, 0,
2787 0,
2789 0, 0 },
2790 { "op2p1", FIELD_op2, -1, 0,
2791 0,
2793 0, 0 },
2794 { "label8", FIELD_imm8, -1, 0,
2798 { "ulabel8", FIELD_imm8, -1, 0,
2802 { "label12", FIELD_imm12, -1, 0,
2806 { "soffset", FIELD_offset, -1, 0,
2810 { "uimm16x4", FIELD_imm16, -1, 0,
2817 0, 0 },
2821 0, 0 },
2825 0, 0 },
2829 0, 0 },
2833 0, 0 },
2837 0, 0 },
2841 0, 0 },
2842 { "immt", FIELD_t, -1, 0,
2843 0,
2845 0, 0 },
2846 { "imms", FIELD_s, -1, 0,
2847 0,
2849 0, 0 },
2850 { "tp7", FIELD_t, -1, 0,
2851 0,
2853 0, 0 },
2854 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2858 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2862 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2863 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2864 { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
2865 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2866 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2867 { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
2868 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2869 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2870 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2871 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2872 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2873 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2874 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2875 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2876 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2877 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2878 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2879 { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
2880 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2881 { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
2882 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2883 { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
2884 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2885 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2886 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2887 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2888 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2889 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2890 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2891 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2892 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2893 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2894 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2895 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2896 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2897 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
2898 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
2899 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
2900 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
2901 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
2902 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
2903 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
2904 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
2905 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
2906 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
2907 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
2908 { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 },
2909 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
5886 { 0, 0 /* xt_iclass_excw */,
5887 0, 0, 0, 0 },
5888 { 0, 0 /* xt_iclass_rfe */,
5889 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5890 { 0, 0 /* xt_iclass_rfde */,
5891 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5892 { 0, 0 /* xt_iclass_syscall */,
5893 0, 0, 0, 0 },
5894 { 0, 0 /* xt_iclass_simcall */,
5895 0, 0, 0, 0 },
5897 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5899 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5901 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5903 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5905 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5907 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5909 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5911 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5913 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5915 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5916 { 0, 0 /* xt_iclass_rfwou */,
5917 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5919 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
5921 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
5923 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5925 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5927 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5929 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5931 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5933 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5935 0, 0, 0, 0 },
5937 0, 0, 0, 0 },
5939 0, 0, 0, 0 },
5940 { 0, 0 /* xt_iclass_ill_n */,
5941 0, 0, 0, 0 },
5943 0, 0, 0, 0 },
5945 0, 0, 0, 0 },
5947 0, 0, 0, 0 },
5948 { 0, 0 /* xt_iclass_nopn */,
5949 0, 0, 0, 0 },
5951 0, 0, 0, 0 },
5953 0, 0, 0, 0 },
5955 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
5957 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
5959 0, 0, 0, 0 },
5961 0, 0, 0, 0 },
5963 0, 0, 0, 0 },
5965 0, 0, 0, 0 },
5967 0, 0, 0, 0 },
5969 0, 0, 0, 0 },
5971 0, 0, 0, 0 },
5973 0, 0, 0, 0 },
5975 0, 0, 0, 0 },
5977 0, 0, 0, 0 },
5979 0, 0, 0, 0 },
5981 0, 0, 0, 0 },
5982 { 0, 0 /* xt_iclass_ill */,
5983 0, 0, 0, 0 },
5985 0, 0, 0, 0 },
5987 0, 0, 0, 0 },
5989 0, 0, 0, 0 },
5991 0, 0, 0, 0 },
5993 0, 0, 0, 0 },
5995 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
5997 0, 0, 0, 0 },
5999 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
6001 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
6003 0, 0, 0, 0 },
6005 0, 0, 0, 0 },
6007 0, 0, 0, 0 },
6008 { 0, 0 /* xt_iclass_nop */,
6009 0, 0, 0, 0 },
6011 0, 0, 0, 0 },
6013 0, 0, 0, 0 },
6015 0, 0, 0, 0 },
6017 0, 0, 0, 0 },
6019 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
6021 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
6023 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
6025 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
6027 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
6029 0, 0, 0, 0 },
6031 0, 0, 0, 0 },
6033 0, 0, 0, 0 },
6034 { 0, 0 /* xt_iclass_memw */,
6035 0, 0, 0, 0 },
6036 { 0, 0 /* xt_iclass_extw */,
6037 0, 0, 0, 0 },
6038 { 0, 0 /* xt_iclass_isync */,
6039 0, 0, 0, 0 },
6040 { 0, 0 /* xt_iclass_sync */,
6041 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
6043 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
6045 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
6047 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
6049 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
6051 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
6053 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
6055 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
6057 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
6059 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
6061 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
6063 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
6065 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
6067 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
6069 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
6071 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
6073 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
6075 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
6077 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
6079 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
6081 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
6083 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
6085 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
6087 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
6089 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
6091 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
6093 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
6095 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
6097 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
6099 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
6101 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
6103 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
6105 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
6107 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
6109 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
6111 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
6113 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
6115 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
6117 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
6119 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
6121 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
6123 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
6125 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
6127 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
6129 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
6131 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
6133 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
6135 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
6137 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
6139 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
6141 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
6143 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
6145 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
6147 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
6149 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
6151 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
6153 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
6155 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
6157 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
6159 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
6161 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
6163 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
6165 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
6167 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
6169 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
6171 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
6173 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
6175 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
6177 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
6179 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
6181 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
6183 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
6185 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
6187 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
6189 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
6191 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
6193 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
6195 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
6197 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
6199 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
6201 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
6203 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
6205 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
6207 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
6209 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
6211 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
6213 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
6215 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
6217 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
6219 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
6221 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
6223 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
6225 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
6227 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
6229 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
6231 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
6233 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
6235 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
6237 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
6239 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
6241 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
6243 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
6245 0, 0, 0, 0 },
6247 0, 0, 0, 0 },
6249 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
6251 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
6253 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
6255 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
6257 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
6259 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
6261 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
6263 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
6265 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
6267 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
6269 0, 0, 0, 0 },
6271 0, 0, 0, 0 },
6273 0, 0, 0, 0 },
6275 0, 0, 0, 0 },
6277 0, 0, 0, 0 },
6279 0, 0, 0, 0 },
6281 0, 0, 0, 0 },
6283 0, 0, 0, 0 },
6285 0, 0, 0, 0 },
6287 0, 0, 0, 0 },
6289 0, 0, 0, 0 },
6291 0, 0, 0, 0 },
6293 0, 0, 0, 0 },
6295 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
6297 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
6299 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
6301 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
6303 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
6305 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
6307 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
6309 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
6311 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
6313 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
6315 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
6317 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
6319 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
6321 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
6323 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
6325 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
6327 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
6329 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
6331 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
6333 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
6335 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
6337 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
6339 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
6341 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
6343 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
6345 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
6347 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
6349 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
6351 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
6353 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
6355 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
6357 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
6359 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
6361 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
6363 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
6365 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
6367 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
6369 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
6371 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
6373 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
6375 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
6377 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
6379 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
6381 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
6383 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
6385 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
6387 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
6389 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
6391 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
6393 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
6394 { 0, 0 /* xt_iclass_rfdd */,
6395 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
6397 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
6399 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
6401 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
6403 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
6405 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
6407 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
6409 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
6411 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
6413 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
6415 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
6417 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
6419 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
6421 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
6423 0, 0, 0, 0 },
6425 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
6427 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
6429 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
6431 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
6433 0, 0, 0, 0 },
6435 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
6437 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
6439 0, 0, 0, 0 },
6441 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
6443 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
6445 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
6447 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
6449 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
6451 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
6453 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
6455 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
6457 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
6459 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
6461 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
6463 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
6465 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
6467 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
6469 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
6471 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
6473 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
6475 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
6477 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
6479 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
6481 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
6482 { 0, 0 /* xt_iclass_ldpte */,
6483 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
6484 { 0, 0 /* xt_iclass_hwwitlba */,
6485 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
6486 { 0, 0 /* xt_iclass_hwwdtlba */,
6487 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
6489 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
6491 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
6493 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
6495 0, 0, 0, 0 },
6497 0, 0, 0, 0 },
6499 0, 0, 0, 0 },
6501 0, 0, 0, 0 },
6503 0, 0, 0, 0 },
6505 0, 0, 0, 0 },
6507 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6509 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6511 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6513 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6515 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
6517 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
6519 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
6521 0, 0, 0, 0 },
6522 { 0, 0 /* xt_iclass_rer */,
6523 2, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
6524 { 0, 0 /* xt_iclass_wer */,
6525 2, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
6527 2, Iclass_rur_expstate_stateArgs, 0, 0 },
6529 2, Iclass_wur_expstate_stateArgs, 0, 0 },
6533 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6535 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6537 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6875 slotbuf[0] = 0x2080;
6881 slotbuf[0] = 0x3000;
6887 slotbuf[0] = 0x3200;
6893 slotbuf[0] = 0x5000;
6899 slotbuf[0] = 0x5100;
6905 slotbuf[0] = 0x35;
6911 slotbuf[0] = 0x25;
6917 slotbuf[0] = 0x15;
6923 slotbuf[0] = 0xf0;
6929 slotbuf[0] = 0xe0;
6935 slotbuf[0] = 0xd0;
6941 slotbuf[0] = 0x36;
6947 slotbuf[0] = 0x1000;
6953 slotbuf[0] = 0x408000;
6959 slotbuf[0] = 0x90;
6965 slotbuf[0] = 0xf01d;
6971 slotbuf[0] = 0x3400;
6977 slotbuf[0] = 0x3500;
6983 slotbuf[0] = 0x90000;
6989 slotbuf[0] = 0x490000;
6995 slotbuf[0] = 0x34800;
7001 slotbuf[0] = 0x134800;
7007 slotbuf[0] = 0x614800;
7013 slotbuf[0] = 0x34900;
7019 slotbuf[0] = 0x134900;
7025 slotbuf[0] = 0x614900;
7031 slotbuf[0] = 0xa;
7037 slotbuf[0] = 0xb;
7043 slotbuf[0] = 0x8c;
7049 slotbuf[0] = 0xcc;
7055 slotbuf[0] = 0xf06d;
7061 slotbuf[0] = 0x8;
7067 slotbuf[0] = 0xd;
7073 slotbuf[0] = 0xc;
7079 slotbuf[0] = 0xf03d;
7085 slotbuf[0] = 0xf00d;
7091 slotbuf[0] = 0x9;
7097 slotbuf[0] = 0xe30e70;
7103 slotbuf[0] = 0xf3e700;
7109 slotbuf[0] = 0xc002;
7115 slotbuf[0] = 0xd002;
7121 slotbuf[0] = 0x800000;
7127 slotbuf[0] = 0xc00000;
7133 slotbuf[0] = 0x900000;
7139 slotbuf[0] = 0xa00000;
7145 slotbuf[0] = 0xb00000;
7151 slotbuf[0] = 0xd00000;
7157 slotbuf[0] = 0xe00000;
7163 slotbuf[0] = 0xf00000;
7169 slotbuf[0] = 0x100000;
7175 slotbuf[0] = 0x200000;
7181 slotbuf[0] = 0x300000;
7187 slotbuf[0] = 0x26;
7193 slotbuf[0] = 0x66;
7199 slotbuf[0] = 0xe6;
7205 slotbuf[0] = 0xa6;
7211 slotbuf[0] = 0x6007;
7217 slotbuf[0] = 0xe007;
7223 slotbuf[0] = 0xf6;
7229 slotbuf[0] = 0xb6;
7235 slotbuf[0] = 0x1007;
7241 slotbuf[0] = 0x9007;
7247 slotbuf[0] = 0xa007;
7253 slotbuf[0] = 0x2007;
7259 slotbuf[0] = 0xb007;
7265 slotbuf[0] = 0x3007;
7271 slotbuf[0] = 0x8007;
7277 slotbuf[0] = 0x7;
7283 slotbuf[0] = 0x4007;
7289 slotbuf[0] = 0xc007;
7295 slotbuf[0] = 0x5007;
7301 slotbuf[0] = 0xd007;
7307 slotbuf[0] = 0x16;
7313 slotbuf[0] = 0x56;
7319 slotbuf[0] = 0xd6;
7325 slotbuf[0] = 0x96;
7331 slotbuf[0] = 0x5;
7337 slotbuf[0] = 0xc0;
7343 slotbuf[0] = 0x40000;
7349 slotbuf[0] = 0;
7355 slotbuf[0] = 0x6;
7361 slotbuf[0] = 0xa0;
7367 slotbuf[0] = 0x1002;
7373 slotbuf[0] = 0x9002;
7379 slotbuf[0] = 0x2002;
7385 slotbuf[0] = 0x1;
7391 slotbuf[0] = 0x2;
7397 slotbuf[0] = 0x8076;
7403 slotbuf[0] = 0x9076;
7409 slotbuf[0] = 0xa076;
7415 slotbuf[0] = 0xa002;
7421 slotbuf[0] = 0x830000;
7427 slotbuf[0] = 0x930000;
7433 slotbuf[0] = 0xa30000;
7439 slotbuf[0] = 0xb30000;
7445 slotbuf[0] = 0x600000;
7451 slotbuf[0] = 0x600100;
7457 slotbuf[0] = 0x20f0;
7463 slotbuf[0] = 0x80;
7469 slotbuf[0] = 0x5002;
7475 slotbuf[0] = 0x6002;
7481 slotbuf[0] = 0x4002;
7487 slotbuf[0] = 0x400000;
7493 slotbuf[0] = 0x401000;
7499 slotbuf[0] = 0x402000;
7505 slotbuf[0] = 0x403000;
7511 slotbuf[0] = 0x404000;
7517 slotbuf[0] = 0xa10000;
7523 slotbuf[0] = 0x810000;
7529 slotbuf[0] = 0x910000;
7535 slotbuf[0] = 0xb10000;
7541 slotbuf[0] = 0x10000;
7547 slotbuf[0] = 0x210000;
7553 slotbuf[0] = 0x410000;
7559 slotbuf[0] = 0x20c0;
7565 slotbuf[0] = 0x20d0;
7571 slotbuf[0] = 0x2000;
7577 slotbuf[0] = 0x2010;
7583 slotbuf[0] = 0x2020;
7589 slotbuf[0] = 0x2030;
7595 slotbuf[0] = 0x6000;
7601 slotbuf[0] = 0x30100;
7607 slotbuf[0] = 0x130100;
7613 slotbuf[0] = 0x610100;
7619 slotbuf[0] = 0x30200;
7625 slotbuf[0] = 0x130200;
7631 slotbuf[0] = 0x610200;
7637 slotbuf[0] = 0x30000;
7643 slotbuf[0] = 0x130000;
7649 slotbuf[0] = 0x610000;
7655 slotbuf[0] = 0x30300;
7661 slotbuf[0] = 0x130300;
7667 slotbuf[0] = 0x610300;
7673 slotbuf[0] = 0x30500;
7679 slotbuf[0] = 0x130500;
7685 slotbuf[0] = 0x610500;
7691 slotbuf[0] = 0x3b000;
7697 slotbuf[0] = 0x13b000;
7703 slotbuf[0] = 0x3d000;
7709 slotbuf[0] = 0x3e600;
7715 slotbuf[0] = 0x13e600;
7721 slotbuf[0] = 0x61e600;
7727 slotbuf[0] = 0x3b100;
7733 slotbuf[0] = 0x13b100;
7739 slotbuf[0] = 0x61b100;
7745 slotbuf[0] = 0x3d100;
7751 slotbuf[0] = 0x13d100;
7757 slotbuf[0] = 0x61d100;
7763 slotbuf[0] = 0x3b200;
7769 slotbuf[0] = 0x13b200;
7775 slotbuf[0] = 0x61b200;
7781 slotbuf[0] = 0x3d200;
7787 slotbuf[0] = 0x13d200;
7793 slotbuf[0] = 0x61d200;
7799 slotbuf[0] = 0x3b300;
7805 slotbuf[0] = 0x13b300;
7811 slotbuf[0] = 0x61b300;
7817 slotbuf[0] = 0x3d300;
7823 slotbuf[0] = 0x13d300;
7829 slotbuf[0] = 0x61d300;
7835 slotbuf[0] = 0x3b400;
7841 slotbuf[0] = 0x13b400;
7847 slotbuf[0] = 0x61b400;
7853 slotbuf[0] = 0x3d400;
7859 slotbuf[0] = 0x13d400;
7865 slotbuf[0] = 0x61d400;
7871 slotbuf[0] = 0x3b500;
7877 slotbuf[0] = 0x13b500;
7883 slotbuf[0] = 0x61b500;
7889 slotbuf[0] = 0x3d500;
7895 slotbuf[0] = 0x13d500;
7901 slotbuf[0] = 0x61d500;
7907 slotbuf[0] = 0x3b600;
7913 slotbuf[0] = 0x13b600;
7919 slotbuf[0] = 0x61b600;
7925 slotbuf[0] = 0x3d600;
7931 slotbuf[0] = 0x13d600;
7937 slotbuf[0] = 0x61d600;
7943 slotbuf[0] = 0x3b700;
7949 slotbuf[0] = 0x13b700;
7955 slotbuf[0] = 0x61b700;
7961 slotbuf[0] = 0x3d700;
7967 slotbuf[0] = 0x13d700;
7973 slotbuf[0] = 0x61d700;
7979 slotbuf[0] = 0x3c200;
7985 slotbuf[0] = 0x13c200;
7991 slotbuf[0] = 0x61c200;
7997 slotbuf[0] = 0x3c300;
8003 slotbuf[0] = 0x13c300;
8009 slotbuf[0] = 0x61c300;
8015 slotbuf[0] = 0x3c400;
8021 slotbuf[0] = 0x13c400;
8027 slotbuf[0] = 0x61c400;
8033 slotbuf[0] = 0x3c500;
8039 slotbuf[0] = 0x13c500;
8045 slotbuf[0] = 0x61c500;
8051 slotbuf[0] = 0x3c600;
8057 slotbuf[0] = 0x13c600;
8063 slotbuf[0] = 0x61c600;
8069 slotbuf[0] = 0x3c700;
8075 slotbuf[0] = 0x13c700;
8081 slotbuf[0] = 0x61c700;
8087 slotbuf[0] = 0x3ee00;
8093 slotbuf[0] = 0x13ee00;
8099 slotbuf[0] = 0x61ee00;
8105 slotbuf[0] = 0x3c000;
8111 slotbuf[0] = 0x13c000;
8117 slotbuf[0] = 0x61c000;
8123 slotbuf[0] = 0x3e800;
8129 slotbuf[0] = 0x13e800;
8135 slotbuf[0] = 0x61e800;
8141 slotbuf[0] = 0x3f400;
8147 slotbuf[0] = 0x13f400;
8153 slotbuf[0] = 0x61f400;
8159 slotbuf[0] = 0x3f500;
8165 slotbuf[0] = 0x13f500;
8171 slotbuf[0] = 0x61f500;
8177 slotbuf[0] = 0x3eb00;
8183 slotbuf[0] = 0x3e700;
8189 slotbuf[0] = 0x13e700;
8195 slotbuf[0] = 0x61e700;
8201 slotbuf[0] = 0xc10000;
8207 slotbuf[0] = 0xd10000;
8213 slotbuf[0] = 0x820000;
8219 slotbuf[0] = 0x740004;
8225 slotbuf[0] = 0x750004;
8231 slotbuf[0] = 0x760004;
8237 slotbuf[0] = 0x770004;
8243 slotbuf[0] = 0x700004;
8249 slotbuf[0] = 0x710004;
8255 slotbuf[0] = 0x720004;
8261 slotbuf[0] = 0x730004;
8267 slotbuf[0] = 0x340004;
8273 slotbuf[0] = 0x350004;
8279 slotbuf[0] = 0x360004;
8285 slotbuf[0] = 0x370004;
8291 slotbuf[0] = 0x640004;
8297 slotbuf[0] = 0x650004;
8303 slotbuf[0] = 0x660004;
8309 slotbuf[0] = 0x670004;
8315 slotbuf[0] = 0x240004;
8321 slotbuf[0] = 0x250004;
8327 slotbuf[0] = 0x260004;
8333 slotbuf[0] = 0x270004;
8339 slotbuf[0] = 0x780004;
8345 slotbuf[0] = 0x790004;
8351 slotbuf[0] = 0x7a0004;
8357 slotbuf[0] = 0x7b0004;
8363 slotbuf[0] = 0x7c0004;
8369 slotbuf[0] = 0x7d0004;
8375 slotbuf[0] = 0x7e0004;
8381 slotbuf[0] = 0x7f0004;
8387 slotbuf[0] = 0x380004;
8393 slotbuf[0] = 0x390004;
8399 slotbuf[0] = 0x3a0004;
8405 slotbuf[0] = 0x3b0004;
8411 slotbuf[0] = 0x3c0004;
8417 slotbuf[0] = 0x3d0004;
8423 slotbuf[0] = 0x3e0004;
8429 slotbuf[0] = 0x3f0004;
8435 slotbuf[0] = 0x680004;
8441 slotbuf[0] = 0x690004;
8447 slotbuf[0] = 0x6a0004;
8453 slotbuf[0] = 0x6b0004;
8459 slotbuf[0] = 0x6c0004;
8465 slotbuf[0] = 0x6d0004;
8471 slotbuf[0] = 0x6e0004;
8477 slotbuf[0] = 0x6f0004;
8483 slotbuf[0] = 0x280004;
8489 slotbuf[0] = 0x290004;
8495 slotbuf[0] = 0x2a0004;
8501 slotbuf[0] = 0x2b0004;
8507 slotbuf[0] = 0x2c0004;
8513 slotbuf[0] = 0x2d0004;
8519 slotbuf[0] = 0x2e0004;
8525 slotbuf[0] = 0x2f0004;
8531 slotbuf[0] = 0x580004;
8537 slotbuf[0] = 0x480004;
8543 slotbuf[0] = 0x590004;
8549 slotbuf[0] = 0x490004;
8555 slotbuf[0] = 0x5a0004;
8561 slotbuf[0] = 0x4a0004;
8567 slotbuf[0] = 0x5b0004;
8573 slotbuf[0] = 0x4b0004;
8579 slotbuf[0] = 0x180004;
8585 slotbuf[0] = 0x80004;
8591 slotbuf[0] = 0x190004;
8597 slotbuf[0] = 0x90004;
8603 slotbuf[0] = 0x1a0004;
8609 slotbuf[0] = 0xa0004;
8615 slotbuf[0] = 0x1b0004;
8621 slotbuf[0] = 0xb0004;
8627 slotbuf[0] = 0x900004;
8633 slotbuf[0] = 0x800004;
8639 slotbuf[0] = 0x32000;
8645 slotbuf[0] = 0x132000;
8651 slotbuf[0] = 0x612000;
8657 slotbuf[0] = 0x32100;
8663 slotbuf[0] = 0x132100;
8669 slotbuf[0] = 0x612100;
8675 slotbuf[0] = 0x32200;
8681 slotbuf[0] = 0x132200;
8687 slotbuf[0] = 0x612200;
8693 slotbuf[0] = 0x32300;
8699 slotbuf[0] = 0x132300;
8705 slotbuf[0] = 0x612300;
8711 slotbuf[0] = 0x31000;
8717 slotbuf[0] = 0x131000;
8723 slotbuf[0] = 0x611000;
8729 slotbuf[0] = 0x31100;
8735 slotbuf[0] = 0x131100;
8741 slotbuf[0] = 0x611100;
8747 slotbuf[0] = 0x3010;
8753 slotbuf[0] = 0x7000;
8759 slotbuf[0] = 0x3e200;
8765 slotbuf[0] = 0x13e200;
8771 slotbuf[0] = 0x13e300;
8777 slotbuf[0] = 0x3e400;
8783 slotbuf[0] = 0x13e400;
8789 slotbuf[0] = 0x61e400;
8795 slotbuf[0] = 0x4000;
8801 slotbuf[0] = 0xf02d;
8807 slotbuf[0] = 0x39000;
8813 slotbuf[0] = 0x139000;
8819 slotbuf[0] = 0x619000;
8825 slotbuf[0] = 0x3a000;
8831 slotbuf[0] = 0x13a000;
8837 slotbuf[0] = 0x61a000;
8843 slotbuf[0] = 0x39100;
8849 slotbuf[0] = 0x139100;
8855 slotbuf[0] = 0x619100;
8861 slotbuf[0] = 0x3a100;
8867 slotbuf[0] = 0x13a100;
8873 slotbuf[0] = 0x61a100;
8879 slotbuf[0] = 0x38000;
8885 slotbuf[0] = 0x138000;
8891 slotbuf[0] = 0x618000;
8897 slotbuf[0] = 0x38100;
8903 slotbuf[0] = 0x138100;
8909 slotbuf[0] = 0x618100;
8915 slotbuf[0] = 0x36000;
8921 slotbuf[0] = 0x136000;
8927 slotbuf[0] = 0x616000;
8933 slotbuf[0] = 0x3e900;
8939 slotbuf[0] = 0x13e900;
8945 slotbuf[0] = 0x61e900;
8951 slotbuf[0] = 0x3ec00;
8957 slotbuf[0] = 0x13ec00;
8963 slotbuf[0] = 0x61ec00;
8969 slotbuf[0] = 0x3ed00;
8975 slotbuf[0] = 0x13ed00;
8981 slotbuf[0] = 0x61ed00;
8987 slotbuf[0] = 0x36800;
8993 slotbuf[0] = 0x136800;
8999 slotbuf[0] = 0x616800;
9005 slotbuf[0] = 0xf1e000;
9011 slotbuf[0] = 0xf1e010;
9017 slotbuf[0] = 0x135900;
9023 slotbuf[0] = 0x3ea00;
9029 slotbuf[0] = 0x13ea00;
9035 slotbuf[0] = 0x61ea00;
9041 slotbuf[0] = 0x3f000;
9047 slotbuf[0] = 0x13f000;
9053 slotbuf[0] = 0x61f000;
9059 slotbuf[0] = 0x3f100;
9065 slotbuf[0] = 0x13f100;
9071 slotbuf[0] = 0x61f100;
9077 slotbuf[0] = 0x3f200;
9083 slotbuf[0] = 0x13f200;
9089 slotbuf[0] = 0x61f200;
9095 slotbuf[0] = 0x70c2;
9101 slotbuf[0] = 0x70e2;
9107 slotbuf[0] = 0x70d2;
9113 slotbuf[0] = 0x270d2;
9119 slotbuf[0] = 0x370d2;
9125 slotbuf[0] = 0x70f2;
9131 slotbuf[0] = 0xf10000;
9137 slotbuf[0] = 0xf12000;
9143 slotbuf[0] = 0xf11000;
9149 slotbuf[0] = 0xf13000;
9155 slotbuf[0] = 0x7042;
9161 slotbuf[0] = 0x7052;
9167 slotbuf[0] = 0x47082;
9173 slotbuf[0] = 0x57082;
9179 slotbuf[0] = 0x7062;
9185 slotbuf[0] = 0x7072;
9191 slotbuf[0] = 0x7002;
9197 slotbuf[0] = 0x7012;
9203 slotbuf[0] = 0x7022;
9209 slotbuf[0] = 0x7032;
9215 slotbuf[0] = 0x7082;
9221 slotbuf[0] = 0x27082;
9227 slotbuf[0] = 0x37082;
9233 slotbuf[0] = 0xf19000;
9239 slotbuf[0] = 0xf18000;
9245 slotbuf[0] = 0x135300;
9251 slotbuf[0] = 0x35300;
9257 slotbuf[0] = 0x615300;
9263 slotbuf[0] = 0x35a00;
9269 slotbuf[0] = 0x135a00;
9275 slotbuf[0] = 0x615a00;
9281 slotbuf[0] = 0x35b00;
9287 slotbuf[0] = 0x135b00;
9293 slotbuf[0] = 0x615b00;
9299 slotbuf[0] = 0x35c00;
9305 slotbuf[0] = 0x135c00;
9311 slotbuf[0] = 0x615c00;
9317 slotbuf[0] = 0x50c000;
9323 slotbuf[0] = 0x50d000;
9329 slotbuf[0] = 0x50b000;
9335 slotbuf[0] = 0x50f000;
9341 slotbuf[0] = 0x50e000;
9347 slotbuf[0] = 0x504000;
9353 slotbuf[0] = 0x505000;
9359 slotbuf[0] = 0x503000;
9365 slotbuf[0] = 0x507000;
9371 slotbuf[0] = 0x506000;
9377 slotbuf[0] = 0xf1f000;
9383 slotbuf[0] = 0x501000;
9389 slotbuf[0] = 0x509000;
9395 slotbuf[0] = 0x3e000;
9401 slotbuf[0] = 0x13e000;
9407 slotbuf[0] = 0x61e000;
9413 slotbuf[0] = 0x330000;
9419 slotbuf[0] = 0x430000;
9425 slotbuf[0] = 0x530000;
9431 slotbuf[0] = 0x630000;
9437 slotbuf[0] = 0x730000;
9443 slotbuf[0] = 0x40e000;
9449 slotbuf[0] = 0x40f000;
9455 slotbuf[0] = 0x230000;
9461 slotbuf[0] = 0xb002;
9467 slotbuf[0] = 0xf002;
9473 slotbuf[0] = 0xe002;
9479 slotbuf[0] = 0x30c00;
9485 slotbuf[0] = 0x130c00;
9491 slotbuf[0] = 0x610c00;
9497 slotbuf[0] = 0x36300;
9503 slotbuf[0] = 0x136300;
9509 slotbuf[0] = 0x616300;
9515 slotbuf[0] = 0xc20000;
9521 slotbuf[0] = 0xd20000;
9527 slotbuf[0] = 0xe20000;
9533 slotbuf[0] = 0xf20000;
9539 slotbuf[0] = 0x406000;
9545 slotbuf[0] = 0x407000;
9551 slotbuf[0] = 0xe30e60;
9557 slotbuf[0] = 0xf3e600;
9563 slotbuf[0] = 0xe0000;
9569 slotbuf[0] = 0xe1000;
9575 slotbuf[0] = 0xe1200;
9581 slotbuf[0] = 0xe2000;
9585 Opcode_excw_Slot_inst_encode, 0, 0
9589 Opcode_rfe_Slot_inst_encode, 0, 0
9593 Opcode_rfde_Slot_inst_encode, 0, 0
9597 Opcode_syscall_Slot_inst_encode, 0, 0
9601 Opcode_simcall_Slot_inst_encode, 0, 0
9605 Opcode_call12_Slot_inst_encode, 0, 0
9609 Opcode_call8_Slot_inst_encode, 0, 0
9613 Opcode_call4_Slot_inst_encode, 0, 0
9617 Opcode_callx12_Slot_inst_encode, 0, 0
9621 Opcode_callx8_Slot_inst_encode, 0, 0
9625 Opcode_callx4_Slot_inst_encode, 0, 0
9629 Opcode_entry_Slot_inst_encode, 0, 0
9633 Opcode_movsp_Slot_inst_encode, 0, 0
9637 Opcode_rotw_Slot_inst_encode, 0, 0
9641 Opcode_retw_Slot_inst_encode, 0, 0
9645 0, 0, Opcode_retw_n_Slot_inst16b_encode
9649 Opcode_rfwo_Slot_inst_encode, 0, 0
9653 Opcode_rfwu_Slot_inst_encode, 0, 0
9657 Opcode_l32e_Slot_inst_encode, 0, 0
9661 Opcode_s32e_Slot_inst_encode, 0, 0
9665 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9669 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9673 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9677 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9681 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9685 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9689 0, Opcode_add_n_Slot_inst16a_encode, 0
9693 0, Opcode_addi_n_Slot_inst16a_encode, 0
9697 0, 0, Opcode_beqz_n_Slot_inst16b_encode
9701 0, 0, Opcode_bnez_n_Slot_inst16b_encode
9705 0, 0, Opcode_ill_n_Slot_inst16b_encode
9709 0, Opcode_l32i_n_Slot_inst16a_encode, 0
9713 0, 0, Opcode_mov_n_Slot_inst16b_encode
9717 0, 0, Opcode_movi_n_Slot_inst16b_encode
9721 0, 0, Opcode_nop_n_Slot_inst16b_encode
9725 0, 0, Opcode_ret_n_Slot_inst16b_encode
9729 0, Opcode_s32i_n_Slot_inst16a_encode, 0
9733 Opcode_rur_threadptr_Slot_inst_encode, 0, 0
9737 Opcode_wur_threadptr_Slot_inst_encode, 0, 0
9741 Opcode_addi_Slot_inst_encode, 0, 0
9745 Opcode_addmi_Slot_inst_encode, 0, 0
9749 Opcode_add_Slot_inst_encode, 0, 0
9753 Opcode_sub_Slot_inst_encode, 0, 0
9757 Opcode_addx2_Slot_inst_encode, 0, 0
9761 Opcode_addx4_Slot_inst_encode, 0, 0
9765 Opcode_addx8_Slot_inst_encode, 0, 0
9769 Opcode_subx2_Slot_inst_encode, 0, 0
9773 Opcode_subx4_Slot_inst_encode, 0, 0
9777 Opcode_subx8_Slot_inst_encode, 0, 0
9781 Opcode_and_Slot_inst_encode, 0, 0
9785 Opcode_or_Slot_inst_encode, 0, 0
9789 Opcode_xor_Slot_inst_encode, 0, 0
9793 Opcode_beqi_Slot_inst_encode, 0, 0
9797 Opcode_bnei_Slot_inst_encode, 0, 0
9801 Opcode_bgei_Slot_inst_encode, 0, 0
9805 Opcode_blti_Slot_inst_encode, 0, 0
9809 Opcode_bbci_Slot_inst_encode, 0, 0
9813 Opcode_bbsi_Slot_inst_encode, 0, 0
9817 Opcode_bgeui_Slot_inst_encode, 0, 0
9821 Opcode_bltui_Slot_inst_encode, 0, 0
9825 Opcode_beq_Slot_inst_encode, 0, 0
9829 Opcode_bne_Slot_inst_encode, 0, 0
9833 Opcode_bge_Slot_inst_encode, 0, 0
9837 Opcode_blt_Slot_inst_encode, 0, 0
9841 Opcode_bgeu_Slot_inst_encode, 0, 0
9845 Opcode_bltu_Slot_inst_encode, 0, 0
9849 Opcode_bany_Slot_inst_encode, 0, 0
9853 Opcode_bnone_Slot_inst_encode, 0, 0
9857 Opcode_ball_Slot_inst_encode, 0, 0
9861 Opcode_bnall_Slot_inst_encode, 0, 0
9865 Opcode_bbc_Slot_inst_encode, 0, 0
9869 Opcode_bbs_Slot_inst_encode, 0, 0
9873 Opcode_beqz_Slot_inst_encode, 0, 0
9877 Opcode_bnez_Slot_inst_encode, 0, 0
9881 Opcode_bgez_Slot_inst_encode, 0, 0
9885 Opcode_bltz_Slot_inst_encode, 0, 0
9889 Opcode_call0_Slot_inst_encode, 0, 0
9893 Opcode_callx0_Slot_inst_encode, 0, 0
9897 Opcode_extui_Slot_inst_encode, 0, 0
9901 Opcode_ill_Slot_inst_encode, 0, 0
9905 Opcode_j_Slot_inst_encode, 0, 0
9909 Opcode_jx_Slot_inst_encode, 0, 0
9913 Opcode_l16ui_Slot_inst_encode, 0, 0
9917 Opcode_l16si_Slot_inst_encode, 0, 0
9921 Opcode_l32i_Slot_inst_encode, 0, 0
9925 Opcode_l32r_Slot_inst_encode, 0, 0
9929 Opcode_l8ui_Slot_inst_encode, 0, 0
9933 Opcode_loop_Slot_inst_encode, 0, 0
9937 Opcode_loopnez_Slot_inst_encode, 0, 0
9941 Opcode_loopgtz_Slot_inst_encode, 0, 0
9945 Opcode_movi_Slot_inst_encode, 0, 0
9949 Opcode_moveqz_Slot_inst_encode, 0, 0
9953 Opcode_movnez_Slot_inst_encode, 0, 0
9957 Opcode_movltz_Slot_inst_encode, 0, 0
9961 Opcode_movgez_Slot_inst_encode, 0, 0
9965 Opcode_neg_Slot_inst_encode, 0, 0
9969 Opcode_abs_Slot_inst_encode, 0, 0
9973 Opcode_nop_Slot_inst_encode, 0, 0
9977 Opcode_ret_Slot_inst_encode, 0, 0
9981 Opcode_s16i_Slot_inst_encode, 0, 0
9985 Opcode_s32i_Slot_inst_encode, 0, 0
9989 Opcode_s8i_Slot_inst_encode, 0, 0
9993 Opcode_ssr_Slot_inst_encode, 0, 0
9997 Opcode_ssl_Slot_inst_encode, 0, 0
10001 Opcode_ssa8l_Slot_inst_encode, 0, 0
10005 Opcode_ssa8b_Slot_inst_encode, 0, 0
10009 Opcode_ssai_Slot_inst_encode, 0, 0
10013 Opcode_sll_Slot_inst_encode, 0, 0
10017 Opcode_src_Slot_inst_encode, 0, 0
10021 Opcode_srl_Slot_inst_encode, 0, 0
10025 Opcode_sra_Slot_inst_encode, 0, 0
10029 Opcode_slli_Slot_inst_encode, 0, 0
10033 Opcode_srai_Slot_inst_encode, 0, 0
10037 Opcode_srli_Slot_inst_encode, 0, 0
10041 Opcode_memw_Slot_inst_encode, 0, 0
10045 Opcode_extw_Slot_inst_encode, 0, 0
10049 Opcode_isync_Slot_inst_encode, 0, 0
10053 Opcode_rsync_Slot_inst_encode, 0, 0
10057 Opcode_esync_Slot_inst_encode, 0, 0
10061 Opcode_dsync_Slot_inst_encode, 0, 0
10065 Opcode_rsil_Slot_inst_encode, 0, 0
10069 Opcode_rsr_lend_Slot_inst_encode, 0, 0
10073 Opcode_wsr_lend_Slot_inst_encode, 0, 0
10077 Opcode_xsr_lend_Slot_inst_encode, 0, 0
10081 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
10085 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
10089 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
10093 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
10097 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
10101 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
10105 Opcode_rsr_sar_Slot_inst_encode, 0, 0
10109 Opcode_wsr_sar_Slot_inst_encode, 0, 0
10113 Opcode_xsr_sar_Slot_inst_encode, 0, 0
10117 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
10121 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
10125 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
10129 Opcode_rsr_176_Slot_inst_encode, 0, 0
10133 Opcode_wsr_176_Slot_inst_encode, 0, 0
10137 Opcode_rsr_208_Slot_inst_encode, 0, 0
10141 Opcode_rsr_ps_Slot_inst_encode, 0, 0
10145 Opcode_wsr_ps_Slot_inst_encode, 0, 0
10149 Opcode_xsr_ps_Slot_inst_encode, 0, 0
10153 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
10157 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
10161 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
10165 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
10169 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
10173 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
10177 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
10181 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
10185 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
10189 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
10193 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
10197 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
10201 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
10205 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
10209 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
10213 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
10217 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
10221 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
10225 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
10229 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
10233 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
10237 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
10241 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
10245 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
10249 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
10253 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
10257 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
10261 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
10265 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
10269 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
10273 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
10277 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
10281 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
10285 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
10289 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
10293 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
10297 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
10301 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
10305 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
10309 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
10313 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
10317 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
10321 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
10325 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
10329 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
10333 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
10337 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
10341 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
10345 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
10349 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
10353 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
10357 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
10361 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
10365 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
10369 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
10373 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
10377 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
10381 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
10385 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
10389 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
10393 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
10397 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
10401 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
10405 Opcode_rsr_depc_Slot_inst_encode, 0, 0
10409 Opcode_wsr_depc_Slot_inst_encode, 0, 0
10413 Opcode_xsr_depc_Slot_inst_encode, 0, 0
10417 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
10421 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
10425 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
10429 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
10433 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
10437 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
10441 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
10445 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
10449 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
10453 Opcode_rsr_prid_Slot_inst_encode, 0, 0
10457 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
10461 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
10465 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
10469 Opcode_mul16u_Slot_inst_encode, 0, 0
10473 Opcode_mul16s_Slot_inst_encode, 0, 0
10477 Opcode_mull_Slot_inst_encode, 0, 0
10481 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
10485 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
10489 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
10493 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
10497 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
10501 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
10505 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
10509 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
10513 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
10517 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
10521 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
10525 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
10529 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
10533 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
10537 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
10541 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
10545 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
10549 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
10553 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
10557 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
10561 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
10565 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
10569 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
10573 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
10577 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
10581 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
10585 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
10589 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
10593 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
10597 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
10601 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
10605 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
10609 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
10613 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
10617 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
10621 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
10625 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
10629 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
10633 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10637 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10641 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10645 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10649 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10653 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10657 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10661 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10665 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10669 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10673 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10677 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10681 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10685 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10689 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10693 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10697 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10701 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10705 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10709 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10713 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10717 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10721 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10725 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10729 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10733 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10737 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10741 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10745 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10749 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10753 Opcode_lddec_Slot_inst_encode, 0, 0
10757 Opcode_ldinc_Slot_inst_encode, 0, 0
10761 Opcode_rsr_m0_Slot_inst_encode, 0, 0
10765 Opcode_wsr_m0_Slot_inst_encode, 0, 0
10769 Opcode_xsr_m0_Slot_inst_encode, 0, 0
10773 Opcode_rsr_m1_Slot_inst_encode, 0, 0
10777 Opcode_wsr_m1_Slot_inst_encode, 0, 0
10781 Opcode_xsr_m1_Slot_inst_encode, 0, 0
10785 Opcode_rsr_m2_Slot_inst_encode, 0, 0
10789 Opcode_wsr_m2_Slot_inst_encode, 0, 0
10793 Opcode_xsr_m2_Slot_inst_encode, 0, 0
10797 Opcode_rsr_m3_Slot_inst_encode, 0, 0
10801 Opcode_wsr_m3_Slot_inst_encode, 0, 0
10805 Opcode_xsr_m3_Slot_inst_encode, 0, 0
10809 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10813 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10817 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10821 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10825 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10829 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10833 Opcode_rfi_Slot_inst_encode, 0, 0
10837 Opcode_waiti_Slot_inst_encode, 0, 0
10841 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10845 Opcode_wsr_intset_Slot_inst_encode, 0, 0
10849 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10853 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10857 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10861 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10865 Opcode_break_Slot_inst_encode, 0, 0
10869 0, 0, Opcode_break_n_Slot_inst16b_encode
10873 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10877 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10881 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10885 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10889 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10893 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10897 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10901 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10905 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10909 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10913 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10917 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10921 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10925 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10929 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10933 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10937 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10941 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10945 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10949 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10953 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10957 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10961 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10965 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10969 Opcode_rsr_icount_Slot_inst_encode, 0, 0
10973 Opcode_wsr_icount_Slot_inst_encode, 0, 0
10977 Opcode_xsr_icount_Slot_inst_encode, 0, 0
10981 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10985 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10989 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10993 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10997 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
11001 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
11005 Opcode_rfdo_Slot_inst_encode, 0, 0
11009 Opcode_rfdd_Slot_inst_encode, 0, 0
11013 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
11017 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
11021 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
11025 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
11029 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
11033 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
11037 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
11041 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
11045 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
11049 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
11053 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
11057 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
11061 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
11065 Opcode_ipf_Slot_inst_encode, 0, 0
11069 Opcode_ihi_Slot_inst_encode, 0, 0
11073 Opcode_ipfl_Slot_inst_encode, 0, 0
11077 Opcode_ihu_Slot_inst_encode, 0, 0
11081 Opcode_iiu_Slot_inst_encode, 0, 0
11085 Opcode_iii_Slot_inst_encode, 0, 0
11089 Opcode_lict_Slot_inst_encode, 0, 0
11093 Opcode_licw_Slot_inst_encode, 0, 0
11097 Opcode_sict_Slot_inst_encode, 0, 0
11101 Opcode_sicw_Slot_inst_encode, 0, 0
11105 Opcode_dhwb_Slot_inst_encode, 0, 0
11109 Opcode_dhwbi_Slot_inst_encode, 0, 0
11113 Opcode_diwb_Slot_inst_encode, 0, 0
11117 Opcode_diwbi_Slot_inst_encode, 0, 0
11121 Opcode_dhi_Slot_inst_encode, 0, 0
11125 Opcode_dii_Slot_inst_encode, 0, 0
11129 Opcode_dpfr_Slot_inst_encode, 0, 0
11133 Opcode_dpfw_Slot_inst_encode, 0, 0
11137 Opcode_dpfro_Slot_inst_encode, 0, 0
11141 Opcode_dpfwo_Slot_inst_encode, 0, 0
11145 Opcode_dpfl_Slot_inst_encode, 0, 0
11149 Opcode_dhu_Slot_inst_encode, 0, 0
11153 Opcode_diu_Slot_inst_encode, 0, 0
11157 Opcode_sdct_Slot_inst_encode, 0, 0
11161 Opcode_ldct_Slot_inst_encode, 0, 0
11165 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
11169 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
11173 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
11177 Opcode_rsr_rasid_Slot_inst_encode, 0, 0
11181 Opcode_wsr_rasid_Slot_inst_encode, 0, 0
11185 Opcode_xsr_rasid_Slot_inst_encode, 0, 0
11189 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
11193 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
11197 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
11201 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
11205 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
11209 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
11213 Opcode_idtlb_Slot_inst_encode, 0, 0
11217 Opcode_pdtlb_Slot_inst_encode, 0, 0
11221 Opcode_rdtlb0_Slot_inst_encode, 0, 0
11225 Opcode_rdtlb1_Slot_inst_encode, 0, 0
11229 Opcode_wdtlb_Slot_inst_encode, 0, 0
11233 Opcode_iitlb_Slot_inst_encode, 0, 0
11237 Opcode_pitlb_Slot_inst_encode, 0, 0
11241 Opcode_ritlb0_Slot_inst_encode, 0, 0
11245 Opcode_ritlb1_Slot_inst_encode, 0, 0
11249 Opcode_witlb_Slot_inst_encode, 0, 0
11253 Opcode_ldpte_Slot_inst_encode, 0, 0
11257 Opcode_hwwitlba_Slot_inst_encode, 0, 0
11261 Opcode_hwwdtlba_Slot_inst_encode, 0, 0
11265 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
11269 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
11273 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
11277 Opcode_clamps_Slot_inst_encode, 0, 0
11281 Opcode_min_Slot_inst_encode, 0, 0
11285 Opcode_max_Slot_inst_encode, 0, 0
11289 Opcode_minu_Slot_inst_encode, 0, 0
11293 Opcode_maxu_Slot_inst_encode, 0, 0
11297 Opcode_nsa_Slot_inst_encode, 0, 0
11301 Opcode_nsau_Slot_inst_encode, 0, 0
11305 Opcode_sext_Slot_inst_encode, 0, 0
11309 Opcode_l32ai_Slot_inst_encode, 0, 0
11313 Opcode_s32ri_Slot_inst_encode, 0, 0
11317 Opcode_s32c1i_Slot_inst_encode, 0, 0
11321 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
11325 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
11329 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
11333 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
11337 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
11341 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
11345 Opcode_quou_Slot_inst_encode, 0, 0
11349 Opcode_quos_Slot_inst_encode, 0, 0
11353 Opcode_remu_Slot_inst_encode, 0, 0
11357 Opcode_rems_Slot_inst_encode, 0, 0
11361 Opcode_rer_Slot_inst_encode, 0, 0
11365 Opcode_wer_Slot_inst_encode, 0, 0
11369 Opcode_rur_expstate_Slot_inst_encode, 0, 0
11373 Opcode_wur_expstate_Slot_inst_encode, 0, 0
11377 Opcode_read_impwire_Slot_inst_encode, 0, 0
11381 Opcode_setb_expstate_Slot_inst_encode, 0, 0
11385 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
11389 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
11397 0,
11398 Opcode_excw_encode_fns, 0, 0 },
11401 Opcode_rfe_encode_fns, 0, 0 },
11404 Opcode_rfde_encode_fns, 0, 0 },
11406 0,
11407 Opcode_syscall_encode_fns, 0, 0 },
11409 0,
11410 Opcode_simcall_encode_fns, 0, 0 },
11413 Opcode_call12_encode_fns, 0, 0 },
11416 Opcode_call8_encode_fns, 0, 0 },
11419 Opcode_call4_encode_fns, 0, 0 },
11422 Opcode_callx12_encode_fns, 0, 0 },
11425 Opcode_callx8_encode_fns, 0, 0 },
11428 Opcode_callx4_encode_fns, 0, 0 },
11430 0,
11431 Opcode_entry_encode_fns, 0, 0 },
11433 0,
11434 Opcode_movsp_encode_fns, 0, 0 },
11436 0,
11437 Opcode_rotw_encode_fns, 0, 0 },
11440 Opcode_retw_encode_fns, 0, 0 },
11443 Opcode_retw_n_encode_fns, 0, 0 },
11446 Opcode_rfwo_encode_fns, 0, 0 },
11449 Opcode_rfwu_encode_fns, 0, 0 },
11451 0,
11452 Opcode_l32e_encode_fns, 0, 0 },
11454 0,
11455 Opcode_s32e_encode_fns, 0, 0 },
11457 0,
11458 Opcode_rsr_windowbase_encode_fns, 0, 0 },
11460 0,
11461 Opcode_wsr_windowbase_encode_fns, 0, 0 },
11463 0,
11464 Opcode_xsr_windowbase_encode_fns, 0, 0 },
11466 0,
11467 Opcode_rsr_windowstart_encode_fns, 0, 0 },
11469 0,
11470 Opcode_wsr_windowstart_encode_fns, 0, 0 },
11472 0,
11473 Opcode_xsr_windowstart_encode_fns, 0, 0 },
11475 0,
11476 Opcode_add_n_encode_fns, 0, 0 },
11478 0,
11479 Opcode_addi_n_encode_fns, 0, 0 },
11482 Opcode_beqz_n_encode_fns, 0, 0 },
11485 Opcode_bnez_n_encode_fns, 0, 0 },
11487 0,
11488 Opcode_ill_n_encode_fns, 0, 0 },
11490 0,
11491 Opcode_l32i_n_encode_fns, 0, 0 },
11493 0,
11494 Opcode_mov_n_encode_fns, 0, 0 },
11496 0,
11497 Opcode_movi_n_encode_fns, 0, 0 },
11499 0,
11500 Opcode_nop_n_encode_fns, 0, 0 },
11503 Opcode_ret_n_encode_fns, 0, 0 },
11505 0,
11506 Opcode_s32i_n_encode_fns, 0, 0 },
11508 0,
11509 Opcode_rur_threadptr_encode_fns, 0, 0 },
11511 0,
11512 Opcode_wur_threadptr_encode_fns, 0, 0 },
11514 0,
11515 Opcode_addi_encode_fns, 0, 0 },
11517 0,
11518 Opcode_addmi_encode_fns, 0, 0 },
11520 0,
11521 Opcode_add_encode_fns, 0, 0 },
11523 0,
11524 Opcode_sub_encode_fns, 0, 0 },
11526 0,
11527 Opcode_addx2_encode_fns, 0, 0 },
11529 0,
11530 Opcode_addx4_encode_fns, 0, 0 },
11532 0,
11533 Opcode_addx8_encode_fns, 0, 0 },
11535 0,
11536 Opcode_subx2_encode_fns, 0, 0 },
11538 0,
11539 Opcode_subx4_encode_fns, 0, 0 },
11541 0,
11542 Opcode_subx8_encode_fns, 0, 0 },
11544 0,
11545 Opcode_and_encode_fns, 0, 0 },
11547 0,
11548 Opcode_or_encode_fns, 0, 0 },
11550 0,
11551 Opcode_xor_encode_fns, 0, 0 },
11554 Opcode_beqi_encode_fns, 0, 0 },
11557 Opcode_bnei_encode_fns, 0, 0 },
11560 Opcode_bgei_encode_fns, 0, 0 },
11563 Opcode_blti_encode_fns, 0, 0 },
11566 Opcode_bbci_encode_fns, 0, 0 },
11569 Opcode_bbsi_encode_fns, 0, 0 },
11572 Opcode_bgeui_encode_fns, 0, 0 },
11575 Opcode_bltui_encode_fns, 0, 0 },
11578 Opcode_beq_encode_fns, 0, 0 },
11581 Opcode_bne_encode_fns, 0, 0 },
11584 Opcode_bge_encode_fns, 0, 0 },
11587 Opcode_blt_encode_fns, 0, 0 },
11590 Opcode_bgeu_encode_fns, 0, 0 },
11593 Opcode_bltu_encode_fns, 0, 0 },
11596 Opcode_bany_encode_fns, 0, 0 },
11599 Opcode_bnone_encode_fns, 0, 0 },
11602 Opcode_ball_encode_fns, 0, 0 },
11605 Opcode_bnall_encode_fns, 0, 0 },
11608 Opcode_bbc_encode_fns, 0, 0 },
11611 Opcode_bbs_encode_fns, 0, 0 },
11614 Opcode_beqz_encode_fns, 0, 0 },
11617 Opcode_bnez_encode_fns, 0, 0 },
11620 Opcode_bgez_encode_fns, 0, 0 },
11623 Opcode_bltz_encode_fns, 0, 0 },
11626 Opcode_call0_encode_fns, 0, 0 },
11629 Opcode_callx0_encode_fns, 0, 0 },
11631 0,
11632 Opcode_extui_encode_fns, 0, 0 },
11634 0,
11635 Opcode_ill_encode_fns, 0, 0 },
11638 Opcode_j_encode_fns, 0, 0 },
11641 Opcode_jx_encode_fns, 0, 0 },
11643 0,
11644 Opcode_l16ui_encode_fns, 0, 0 },
11646 0,
11647 Opcode_l16si_encode_fns, 0, 0 },
11649 0,
11650 Opcode_l32i_encode_fns, 0, 0 },
11652 0,
11653 Opcode_l32r_encode_fns, 0, 0 },
11655 0,
11656 Opcode_l8ui_encode_fns, 0, 0 },
11659 Opcode_loop_encode_fns, 0, 0 },
11662 Opcode_loopnez_encode_fns, 0, 0 },
11665 Opcode_loopgtz_encode_fns, 0, 0 },
11667 0,
11668 Opcode_movi_encode_fns, 0, 0 },
11670 0,
11671 Opcode_moveqz_encode_fns, 0, 0 },
11673 0,
11674 Opcode_movnez_encode_fns, 0, 0 },
11676 0,
11677 Opcode_movltz_encode_fns, 0, 0 },
11679 0,
11680 Opcode_movgez_encode_fns, 0, 0 },
11682 0,
11683 Opcode_neg_encode_fns, 0, 0 },
11685 0,
11686 Opcode_abs_encode_fns, 0, 0 },
11688 0,
11689 Opcode_nop_encode_fns, 0, 0 },
11692 Opcode_ret_encode_fns, 0, 0 },
11694 0,
11695 Opcode_s16i_encode_fns, 0, 0 },
11697 0,
11698 Opcode_s32i_encode_fns, 0, 0 },
11700 0,
11701 Opcode_s8i_encode_fns, 0, 0 },
11703 0,
11704 Opcode_ssr_encode_fns, 0, 0 },
11706 0,
11707 Opcode_ssl_encode_fns, 0, 0 },
11709 0,
11710 Opcode_ssa8l_encode_fns, 0, 0 },
11712 0,
11713 Opcode_ssa8b_encode_fns, 0, 0 },
11715 0,
11716 Opcode_ssai_encode_fns, 0, 0 },
11718 0,
11719 Opcode_sll_encode_fns, 0, 0 },
11721 0,
11722 Opcode_src_encode_fns, 0, 0 },
11724 0,
11725 Opcode_srl_encode_fns, 0, 0 },
11727 0,
11728 Opcode_sra_encode_fns, 0, 0 },
11730 0,
11731 Opcode_slli_encode_fns, 0, 0 },
11733 0,
11734 Opcode_srai_encode_fns, 0, 0 },
11736 0,
11737 Opcode_srli_encode_fns, 0, 0 },
11739 0,
11740 Opcode_memw_encode_fns, 0, 0 },
11742 0,
11743 Opcode_extw_encode_fns, 0, 0 },
11745 0,
11746 Opcode_isync_encode_fns, 0, 0 },
11748 0,
11749 Opcode_rsync_encode_fns, 0, 0 },
11751 0,
11752 Opcode_esync_encode_fns, 0, 0 },
11754 0,
11755 Opcode_dsync_encode_fns, 0, 0 },
11757 0,
11758 Opcode_rsil_encode_fns, 0, 0 },
11760 0,
11761 Opcode_rsr_lend_encode_fns, 0, 0 },
11763 0,
11764 Opcode_wsr_lend_encode_fns, 0, 0 },
11766 0,
11767 Opcode_xsr_lend_encode_fns, 0, 0 },
11769 0,
11770 Opcode_rsr_lcount_encode_fns, 0, 0 },
11772 0,
11773 Opcode_wsr_lcount_encode_fns, 0, 0 },
11775 0,
11776 Opcode_xsr_lcount_encode_fns, 0, 0 },
11778 0,
11779 Opcode_rsr_lbeg_encode_fns, 0, 0 },
11781 0,
11782 Opcode_wsr_lbeg_encode_fns, 0, 0 },
11784 0,
11785 Opcode_xsr_lbeg_encode_fns, 0, 0 },
11787 0,
11788 Opcode_rsr_sar_encode_fns, 0, 0 },
11790 0,
11791 Opcode_wsr_sar_encode_fns, 0, 0 },
11793 0,
11794 Opcode_xsr_sar_encode_fns, 0, 0 },
11796 0,
11797 Opcode_rsr_litbase_encode_fns, 0, 0 },
11799 0,
11800 Opcode_wsr_litbase_encode_fns, 0, 0 },
11802 0,
11803 Opcode_xsr_litbase_encode_fns, 0, 0 },
11805 0,
11806 Opcode_rsr_176_encode_fns, 0, 0 },
11808 0,
11809 Opcode_wsr_176_encode_fns, 0, 0 },
11811 0,
11812 Opcode_rsr_208_encode_fns, 0, 0 },
11814 0,
11815 Opcode_rsr_ps_encode_fns, 0, 0 },
11817 0,
11818 Opcode_wsr_ps_encode_fns, 0, 0 },
11820 0,
11821 Opcode_xsr_ps_encode_fns, 0, 0 },
11823 0,
11824 Opcode_rsr_epc1_encode_fns, 0, 0 },
11826 0,
11827 Opcode_wsr_epc1_encode_fns, 0, 0 },
11829 0,
11830 Opcode_xsr_epc1_encode_fns, 0, 0 },
11832 0,
11833 Opcode_rsr_excsave1_encode_fns, 0, 0 },
11835 0,
11836 Opcode_wsr_excsave1_encode_fns, 0, 0 },
11838 0,
11839 Opcode_xsr_excsave1_encode_fns, 0, 0 },
11841 0,
11842 Opcode_rsr_epc2_encode_fns, 0, 0 },
11844 0,
11845 Opcode_wsr_epc2_encode_fns, 0, 0 },
11847 0,
11848 Opcode_xsr_epc2_encode_fns, 0, 0 },
11850 0,
11851 Opcode_rsr_excsave2_encode_fns, 0, 0 },
11853 0,
11854 Opcode_wsr_excsave2_encode_fns, 0, 0 },
11856 0,
11857 Opcode_xsr_excsave2_encode_fns, 0, 0 },
11859 0,
11860 Opcode_rsr_epc3_encode_fns, 0, 0 },
11862 0,
11863 Opcode_wsr_epc3_encode_fns, 0, 0 },
11865 0,
11866 Opcode_xsr_epc3_encode_fns, 0, 0 },
11868 0,
11869 Opcode_rsr_excsave3_encode_fns, 0, 0 },
11871 0,
11872 Opcode_wsr_excsave3_encode_fns, 0, 0 },
11874 0,
11875 Opcode_xsr_excsave3_encode_fns, 0, 0 },
11877 0,
11878 Opcode_rsr_epc4_encode_fns, 0, 0 },
11880 0,
11881 Opcode_wsr_epc4_encode_fns, 0, 0 },
11883 0,
11884 Opcode_xsr_epc4_encode_fns, 0, 0 },
11886 0,
11887 Opcode_rsr_excsave4_encode_fns, 0, 0 },
11889 0,
11890 Opcode_wsr_excsave4_encode_fns, 0, 0 },
11892 0,
11893 Opcode_xsr_excsave4_encode_fns, 0, 0 },
11895 0,
11896 Opcode_rsr_epc5_encode_fns, 0, 0 },
11898 0,
11899 Opcode_wsr_epc5_encode_fns, 0, 0 },
11901 0,
11902 Opcode_xsr_epc5_encode_fns, 0, 0 },
11904 0,
11905 Opcode_rsr_excsave5_encode_fns, 0, 0 },
11907 0,
11908 Opcode_wsr_excsave5_encode_fns, 0, 0 },
11910 0,
11911 Opcode_xsr_excsave5_encode_fns, 0, 0 },
11913 0,
11914 Opcode_rsr_epc6_encode_fns, 0, 0 },
11916 0,
11917 Opcode_wsr_epc6_encode_fns, 0, 0 },
11919 0,
11920 Opcode_xsr_epc6_encode_fns, 0, 0 },
11922 0,
11923 Opcode_rsr_excsave6_encode_fns, 0, 0 },
11925 0,
11926 Opcode_wsr_excsave6_encode_fns, 0, 0 },
11928 0,
11929 Opcode_xsr_excsave6_encode_fns, 0, 0 },
11931 0,
11932 Opcode_rsr_epc7_encode_fns, 0, 0 },
11934 0,
11935 Opcode_wsr_epc7_encode_fns, 0, 0 },
11937 0,
11938 Opcode_xsr_epc7_encode_fns, 0, 0 },
11940 0,
11941 Opcode_rsr_excsave7_encode_fns, 0, 0 },
11943 0,
11944 Opcode_wsr_excsave7_encode_fns, 0, 0 },
11946 0,
11947 Opcode_xsr_excsave7_encode_fns, 0, 0 },
11949 0,
11950 Opcode_rsr_eps2_encode_fns, 0, 0 },
11952 0,
11953 Opcode_wsr_eps2_encode_fns, 0, 0 },
11955 0,
11956 Opcode_xsr_eps2_encode_fns, 0, 0 },
11958 0,
11959 Opcode_rsr_eps3_encode_fns, 0, 0 },
11961 0,
11962 Opcode_wsr_eps3_encode_fns, 0, 0 },
11964 0,
11965 Opcode_xsr_eps3_encode_fns, 0, 0 },
11967 0,
11968 Opcode_rsr_eps4_encode_fns, 0, 0 },
11970 0,
11971 Opcode_wsr_eps4_encode_fns, 0, 0 },
11973 0,
11974 Opcode_xsr_eps4_encode_fns, 0, 0 },
11976 0,
11977 Opcode_rsr_eps5_encode_fns, 0, 0 },
11979 0,
11980 Opcode_wsr_eps5_encode_fns, 0, 0 },
11982 0,
11983 Opcode_xsr_eps5_encode_fns, 0, 0 },
11985 0,
11986 Opcode_rsr_eps6_encode_fns, 0, 0 },
11988 0,
11989 Opcode_wsr_eps6_encode_fns, 0, 0 },
11991 0,
11992 Opcode_xsr_eps6_encode_fns, 0, 0 },
11994 0,
11995 Opcode_rsr_eps7_encode_fns, 0, 0 },
11997 0,
11998 Opcode_wsr_eps7_encode_fns, 0, 0 },
12000 0,
12001 Opcode_xsr_eps7_encode_fns, 0, 0 },
12003 0,
12004 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
12006 0,
12007 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
12009 0,
12010 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
12012 0,
12013 Opcode_rsr_depc_encode_fns, 0, 0 },
12015 0,
12016 Opcode_wsr_depc_encode_fns, 0, 0 },
12018 0,
12019 Opcode_xsr_depc_encode_fns, 0, 0 },
12021 0,
12022 Opcode_rsr_exccause_encode_fns, 0, 0 },
12024 0,
12025 Opcode_wsr_exccause_encode_fns, 0, 0 },
12027 0,
12028 Opcode_xsr_exccause_encode_fns, 0, 0 },
12030 0,
12031 Opcode_rsr_misc0_encode_fns, 0, 0 },
12033 0,
12034 Opcode_wsr_misc0_encode_fns, 0, 0 },
12036 0,
12037 Opcode_xsr_misc0_encode_fns, 0, 0 },
12039 0,
12040 Opcode_rsr_misc1_encode_fns, 0, 0 },
12042 0,
12043 Opcode_wsr_misc1_encode_fns, 0, 0 },
12045 0,
12046 Opcode_xsr_misc1_encode_fns, 0, 0 },
12048 0,
12049 Opcode_rsr_prid_encode_fns, 0, 0 },
12051 0,
12052 Opcode_rsr_vecbase_encode_fns, 0, 0 },
12054 0,
12055 Opcode_wsr_vecbase_encode_fns, 0, 0 },
12057 0,
12058 Opcode_xsr_vecbase_encode_fns, 0, 0 },
12060 0,
12061 Opcode_mul16u_encode_fns, 0, 0 },
12063 0,
12064 Opcode_mul16s_encode_fns, 0, 0 },
12066 0,
12067 Opcode_mull_encode_fns, 0, 0 },
12069 0,
12070 Opcode_mul_aa_ll_encode_fns, 0, 0 },
12072 0,
12073 Opcode_mul_aa_hl_encode_fns, 0, 0 },
12075 0,
12076 Opcode_mul_aa_lh_encode_fns, 0, 0 },
12078 0,
12079 Opcode_mul_aa_hh_encode_fns, 0, 0 },
12081 0,
12082 Opcode_umul_aa_ll_encode_fns, 0, 0 },
12084 0,
12085 Opcode_umul_aa_hl_encode_fns, 0, 0 },
12087 0,
12088 Opcode_umul_aa_lh_encode_fns, 0, 0 },
12090 0,
12091 Opcode_umul_aa_hh_encode_fns, 0, 0 },
12093 0,
12094 Opcode_mul_ad_ll_encode_fns, 0, 0 },
12096 0,
12097 Opcode_mul_ad_hl_encode_fns, 0, 0 },
12099 0,
12100 Opcode_mul_ad_lh_encode_fns, 0, 0 },
12102 0,
12103 Opcode_mul_ad_hh_encode_fns, 0, 0 },
12105 0,
12106 Opcode_mul_da_ll_encode_fns, 0, 0 },
12108 0,
12109 Opcode_mul_da_hl_encode_fns, 0, 0 },
12111 0,
12112 Opcode_mul_da_lh_encode_fns, 0, 0 },
12114 0,
12115 Opcode_mul_da_hh_encode_fns, 0, 0 },
12117 0,
12118 Opcode_mul_dd_ll_encode_fns, 0, 0 },
12120 0,
12121 Opcode_mul_dd_hl_encode_fns, 0, 0 },
12123 0,
12124 Opcode_mul_dd_lh_encode_fns, 0, 0 },
12126 0,
12127 Opcode_mul_dd_hh_encode_fns, 0, 0 },
12129 0,
12130 Opcode_mula_aa_ll_encode_fns, 0, 0 },
12132 0,
12133 Opcode_mula_aa_hl_encode_fns, 0, 0 },
12135 0,
12136 Opcode_mula_aa_lh_encode_fns, 0, 0 },
12138 0,
12139 Opcode_mula_aa_hh_encode_fns, 0, 0 },
12141 0,
12142 Opcode_muls_aa_ll_encode_fns, 0, 0 },
12144 0,
12145 Opcode_muls_aa_hl_encode_fns, 0, 0 },
12147 0,
12148 Opcode_muls_aa_lh_encode_fns, 0, 0 },
12150 0,
12151 Opcode_muls_aa_hh_encode_fns, 0, 0 },
12153 0,
12154 Opcode_mula_ad_ll_encode_fns, 0, 0 },
12156 0,
12157 Opcode_mula_ad_hl_encode_fns, 0, 0 },
12159 0,
12160 Opcode_mula_ad_lh_encode_fns, 0, 0 },
12162 0,
12163 Opcode_mula_ad_hh_encode_fns, 0, 0 },
12165 0,
12166 Opcode_muls_ad_ll_encode_fns, 0, 0 },
12168 0,
12169 Opcode_muls_ad_hl_encode_fns, 0, 0 },
12171 0,
12172 Opcode_muls_ad_lh_encode_fns, 0, 0 },
12174 0,
12175 Opcode_muls_ad_hh_encode_fns, 0, 0 },
12177 0,
12178 Opcode_mula_da_ll_encode_fns, 0, 0 },
12180 0,
12181 Opcode_mula_da_hl_encode_fns, 0, 0 },
12183 0,
12184 Opcode_mula_da_lh_encode_fns, 0, 0 },
12186 0,
12187 Opcode_mula_da_hh_encode_fns, 0, 0 },
12189 0,
12190 Opcode_muls_da_ll_encode_fns, 0, 0 },
12192 0,
12193 Opcode_muls_da_hl_encode_fns, 0, 0 },
12195 0,
12196 Opcode_muls_da_lh_encode_fns, 0, 0 },
12198 0,
12199 Opcode_muls_da_hh_encode_fns, 0, 0 },
12201 0,
12202 Opcode_mula_dd_ll_encode_fns, 0, 0 },
12204 0,
12205 Opcode_mula_dd_hl_encode_fns, 0, 0 },
12207 0,
12208 Opcode_mula_dd_lh_encode_fns, 0, 0 },
12210 0,
12211 Opcode_mula_dd_hh_encode_fns, 0, 0 },
12213 0,
12214 Opcode_muls_dd_ll_encode_fns, 0, 0 },
12216 0,
12217 Opcode_muls_dd_hl_encode_fns, 0, 0 },
12219 0,
12220 Opcode_muls_dd_lh_encode_fns, 0, 0 },
12222 0,
12223 Opcode_muls_dd_hh_encode_fns, 0, 0 },
12225 0,
12226 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
12228 0,
12229 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
12231 0,
12232 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
12234 0,
12235 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
12237 0,
12238 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
12240 0,
12241 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
12243 0,
12244 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
12246 0,
12247 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
12249 0,
12250 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
12252 0,
12253 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
12255 0,
12256 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
12258 0,
12259 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
12261 0,
12262 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
12264 0,
12265 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
12267 0,
12268 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
12270 0,
12271 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
12273 0,
12274 Opcode_lddec_encode_fns, 0, 0 },
12276 0,
12277 Opcode_ldinc_encode_fns, 0, 0 },
12279 0,
12280 Opcode_rsr_m0_encode_fns, 0, 0 },
12282 0,
12283 Opcode_wsr_m0_encode_fns, 0, 0 },
12285 0,
12286 Opcode_xsr_m0_encode_fns, 0, 0 },
12288 0,
12289 Opcode_rsr_m1_encode_fns, 0, 0 },
12291 0,
12292 Opcode_wsr_m1_encode_fns, 0, 0 },
12294 0,
12295 Opcode_xsr_m1_encode_fns, 0, 0 },
12297 0,
12298 Opcode_rsr_m2_encode_fns, 0, 0 },
12300 0,
12301 Opcode_wsr_m2_encode_fns, 0, 0 },
12303 0,
12304 Opcode_xsr_m2_encode_fns, 0, 0 },
12306 0,
12307 Opcode_rsr_m3_encode_fns, 0, 0 },
12309 0,
12310 Opcode_wsr_m3_encode_fns, 0, 0 },
12312 0,
12313 Opcode_xsr_m3_encode_fns, 0, 0 },
12315 0,
12316 Opcode_rsr_acclo_encode_fns, 0, 0 },
12318 0,
12319 Opcode_wsr_acclo_encode_fns, 0, 0 },
12321 0,
12322 Opcode_xsr_acclo_encode_fns, 0, 0 },
12324 0,
12325 Opcode_rsr_acchi_encode_fns, 0, 0 },
12327 0,
12328 Opcode_wsr_acchi_encode_fns, 0, 0 },
12330 0,
12331 Opcode_xsr_acchi_encode_fns, 0, 0 },
12334 Opcode_rfi_encode_fns, 0, 0 },
12336 0,
12337 Opcode_waiti_encode_fns, 0, 0 },
12339 0,
12340 Opcode_rsr_interrupt_encode_fns, 0, 0 },
12342 0,
12343 Opcode_wsr_intset_encode_fns, 0, 0 },
12345 0,
12346 Opcode_wsr_intclear_encode_fns, 0, 0 },
12348 0,
12349 Opcode_rsr_intenable_encode_fns, 0, 0 },
12351 0,
12352 Opcode_wsr_intenable_encode_fns, 0, 0 },
12354 0,
12355 Opcode_xsr_intenable_encode_fns, 0, 0 },
12357 0,
12358 Opcode_break_encode_fns, 0, 0 },
12360 0,
12361 Opcode_break_n_encode_fns, 0, 0 },
12363 0,
12364 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
12366 0,
12367 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
12369 0,
12370 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
12372 0,
12373 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
12375 0,
12376 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
12378 0,
12379 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
12381 0,
12382 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
12384 0,
12385 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
12387 0,
12388 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
12390 0,
12391 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
12393 0,
12394 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
12396 0,
12397 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
12399 0,
12400 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
12402 0,
12403 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
12405 0,
12406 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
12408 0,
12409 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
12411 0,
12412 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
12414 0,
12415 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
12417 0,
12418 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
12420 0,
12421 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
12423 0,
12424 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
12426 0,
12427 Opcode_rsr_debugcause_encode_fns, 0, 0 },
12429 0,
12430 Opcode_wsr_debugcause_encode_fns, 0, 0 },
12432 0,
12433 Opcode_xsr_debugcause_encode_fns, 0, 0 },
12435 0,
12436 Opcode_rsr_icount_encode_fns, 0, 0 },
12438 0,
12439 Opcode_wsr_icount_encode_fns, 0, 0 },
12441 0,
12442 Opcode_xsr_icount_encode_fns, 0, 0 },
12444 0,
12445 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
12447 0,
12448 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
12450 0,
12451 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
12453 0,
12454 Opcode_rsr_ddr_encode_fns, 0, 0 },
12456 0,
12457 Opcode_wsr_ddr_encode_fns, 0, 0 },
12459 0,
12460 Opcode_xsr_ddr_encode_fns, 0, 0 },
12463 Opcode_rfdo_encode_fns, 0, 0 },
12466 Opcode_rfdd_encode_fns, 0, 0 },
12468 0,
12469 Opcode_wsr_mmid_encode_fns, 0, 0 },
12471 0,
12472 Opcode_rsr_ccount_encode_fns, 0, 0 },
12474 0,
12475 Opcode_wsr_ccount_encode_fns, 0, 0 },
12477 0,
12478 Opcode_xsr_ccount_encode_fns, 0, 0 },
12480 0,
12481 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
12483 0,
12484 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
12486 0,
12487 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
12489 0,
12490 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
12492 0,
12493 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
12495 0,
12496 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
12498 0,
12499 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
12501 0,
12502 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
12504 0,
12505 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
12507 0,
12508 Opcode_ipf_encode_fns, 0, 0 },
12510 0,
12511 Opcode_ihi_encode_fns, 0, 0 },
12513 0,
12514 Opcode_ipfl_encode_fns, 0, 0 },
12516 0,
12517 Opcode_ihu_encode_fns, 0, 0 },
12519 0,
12520 Opcode_iiu_encode_fns, 0, 0 },
12522 0,
12523 Opcode_iii_encode_fns, 0, 0 },
12525 0,
12526 Opcode_lict_encode_fns, 0, 0 },
12528 0,
12529 Opcode_licw_encode_fns, 0, 0 },
12531 0,
12532 Opcode_sict_encode_fns, 0, 0 },
12534 0,
12535 Opcode_sicw_encode_fns, 0, 0 },
12537 0,
12538 Opcode_dhwb_encode_fns, 0, 0 },
12540 0,
12541 Opcode_dhwbi_encode_fns, 0, 0 },
12543 0,
12544 Opcode_diwb_encode_fns, 0, 0 },
12546 0,
12547 Opcode_diwbi_encode_fns, 0, 0 },
12549 0,
12550 Opcode_dhi_encode_fns, 0, 0 },
12552 0,
12553 Opcode_dii_encode_fns, 0, 0 },
12555 0,
12556 Opcode_dpfr_encode_fns, 0, 0 },
12558 0,
12559 Opcode_dpfw_encode_fns, 0, 0 },
12561 0,
12562 Opcode_dpfro_encode_fns, 0, 0 },
12564 0,
12565 Opcode_dpfwo_encode_fns, 0, 0 },
12567 0,
12568 Opcode_dpfl_encode_fns, 0, 0 },
12570 0,
12571 Opcode_dhu_encode_fns, 0, 0 },
12573 0,
12574 Opcode_diu_encode_fns, 0, 0 },
12576 0,
12577 Opcode_sdct_encode_fns, 0, 0 },
12579 0,
12580 Opcode_ldct_encode_fns, 0, 0 },
12582 0,
12583 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
12585 0,
12586 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
12588 0,
12589 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
12591 0,
12592 Opcode_rsr_rasid_encode_fns, 0, 0 },
12594 0,
12595 Opcode_wsr_rasid_encode_fns, 0, 0 },
12597 0,
12598 Opcode_xsr_rasid_encode_fns, 0, 0 },
12600 0,
12601 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
12603 0,
12604 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
12606 0,
12607 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
12609 0,
12610 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
12612 0,
12613 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
12615 0,
12616 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
12618 0,
12619 Opcode_idtlb_encode_fns, 0, 0 },
12621 0,
12622 Opcode_pdtlb_encode_fns, 0, 0 },
12624 0,
12625 Opcode_rdtlb0_encode_fns, 0, 0 },
12627 0,
12628 Opcode_rdtlb1_encode_fns, 0, 0 },
12630 0,
12631 Opcode_wdtlb_encode_fns, 0, 0 },
12633 0,
12634 Opcode_iitlb_encode_fns, 0, 0 },
12636 0,
12637 Opcode_pitlb_encode_fns, 0, 0 },
12639 0,
12640 Opcode_ritlb0_encode_fns, 0, 0 },
12642 0,
12643 Opcode_ritlb1_encode_fns, 0, 0 },
12645 0,
12646 Opcode_witlb_encode_fns, 0, 0 },
12648 0,
12649 Opcode_ldpte_encode_fns, 0, 0 },
12652 Opcode_hwwitlba_encode_fns, 0, 0 },
12654 0,
12655 Opcode_hwwdtlba_encode_fns, 0, 0 },
12657 0,
12658 Opcode_rsr_cpenable_encode_fns, 0, 0 },
12660 0,
12661 Opcode_wsr_cpenable_encode_fns, 0, 0 },
12663 0,
12664 Opcode_xsr_cpenable_encode_fns, 0, 0 },
12666 0,
12667 Opcode_clamps_encode_fns, 0, 0 },
12669 0,
12670 Opcode_min_encode_fns, 0, 0 },
12672 0,
12673 Opcode_max_encode_fns, 0, 0 },
12675 0,
12676 Opcode_minu_encode_fns, 0, 0 },
12678 0,
12679 Opcode_maxu_encode_fns, 0, 0 },
12681 0,
12682 Opcode_nsa_encode_fns, 0, 0 },
12684 0,
12685 Opcode_nsau_encode_fns, 0, 0 },
12687 0,
12688 Opcode_sext_encode_fns, 0, 0 },
12690 0,
12691 Opcode_l32ai_encode_fns, 0, 0 },
12693 0,
12694 Opcode_s32ri_encode_fns, 0, 0 },
12696 0,
12697 Opcode_s32c1i_encode_fns, 0, 0 },
12699 0,
12700 Opcode_rsr_scompare1_encode_fns, 0, 0 },
12702 0,
12703 Opcode_wsr_scompare1_encode_fns, 0, 0 },
12705 0,
12706 Opcode_xsr_scompare1_encode_fns, 0, 0 },
12708 0,
12709 Opcode_rsr_atomctl_encode_fns, 0, 0 },
12711 0,
12712 Opcode_wsr_atomctl_encode_fns, 0, 0 },
12714 0,
12715 Opcode_xsr_atomctl_encode_fns, 0, 0 },
12717 0,
12718 Opcode_quou_encode_fns, 0, 0 },
12720 0,
12721 Opcode_quos_encode_fns, 0, 0 },
12723 0,
12724 Opcode_remu_encode_fns, 0, 0 },
12726 0,
12727 Opcode_rems_encode_fns, 0, 0 },
12729 0,
12730 Opcode_rer_encode_fns, 0, 0 },
12732 0,
12733 Opcode_wer_encode_fns, 0, 0 },
12735 0,
12736 Opcode_rur_expstate_encode_fns, 0, 0 },
12738 0,
12739 Opcode_wur_expstate_encode_fns, 0, 0 },
12741 0,
12742 Opcode_read_impwire_encode_fns, 0, 0 },
12744 0,
12745 Opcode_setb_expstate_encode_fns, 0, 0 },
12747 0,
12748 Opcode_clrb_expstate_encode_fns, 0, 0 },
12750 0,
12751 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
13217 case 0:
13220 case 0:
13223 case 0:
13226 case 0:
13229 case 0:
13230 if (Field_s_Slot_inst_get (insn) == 0 &&
13231 Field_n_Slot_inst_get (insn) == 0)
13237 case 0:
13248 case 0:
13263 if (Field_s_Slot_inst_get (insn) == 0)
13267 case 0:
13289 case 0:
13292 case 0:
13311 case 0:
13312 if (Field_t_Slot_inst_get (insn) == 0)
13316 if (Field_t_Slot_inst_get (insn) == 0)
13324 if (Field_t_Slot_inst_get (insn) == 0)
13338 case 0:
13339 if (Field_t_Slot_inst_get (insn) == 0)
13343 if (Field_t_Slot_inst_get (insn) == 0)
13347 if (Field_t_Slot_inst_get (insn) == 0)
13351 if (Field_t_Slot_inst_get (insn) == 0)
13355 if (Field_thi3_Slot_inst_get (insn) == 0)
13363 if (Field_s_Slot_inst_get (insn) == 0)
13380 if (Field_t_Slot_inst_get (insn) == 0)
13394 if (Field_t_Slot_inst_get (insn) == 0)
13408 case 0:
13435 case 0:
13446 case 0:
13577 if (Field_s_Slot_inst_get (insn) == 0)
13581 if (Field_t_Slot_inst_get (insn) == 0)
13585 if (Field_s_Slot_inst_get (insn) == 0)
13595 case 0:
13608 if (Field_t_Slot_inst_get (insn) == 0)
13637 case 0:
13640 case 0:
13779 case 0:
13961 case 0:
13970 case 0:
13971 if (Field_s_Slot_inst_get (insn) == 0 &&
13972 Field_op2_Slot_inst_get (insn) == 0 &&
13977 if (Field_s3to1_Slot_inst_get (insn) == 0 &&
13978 Field_op2_Slot_inst_get (insn) == 0 &&
13982 Field_op2_Slot_inst_get (insn) == 0 &&
13987 if (Field_op2_Slot_inst_get (insn) == 0 &&
13998 case 0:
14013 case 0:
14032 case 0:
14049 case 0:
14082 case 0:
14086 if (Field_t3_Slot_inst_get (insn) == 0 &&
14087 Field_tlo_Slot_inst_get (insn) == 0 &&
14088 Field_r3_Slot_inst_get (insn) == 0)
14092 if (Field_t3_Slot_inst_get (insn) == 0 &&
14093 Field_tlo_Slot_inst_get (insn) == 0 &&
14094 Field_r3_Slot_inst_get (insn) == 0)
14098 if (Field_t3_Slot_inst_get (insn) == 0 &&
14099 Field_tlo_Slot_inst_get (insn) == 0 &&
14100 Field_r3_Slot_inst_get (insn) == 0)
14104 if (Field_t3_Slot_inst_get (insn) == 0 &&
14105 Field_tlo_Slot_inst_get (insn) == 0 &&
14106 Field_r3_Slot_inst_get (insn) == 0)
14115 if (Field_t3_Slot_inst_get (insn) == 0 &&
14116 Field_tlo_Slot_inst_get (insn) == 0 &&
14117 Field_r3_Slot_inst_get (insn) == 0)
14121 if (Field_t3_Slot_inst_get (insn) == 0 &&
14122 Field_tlo_Slot_inst_get (insn) == 0 &&
14123 Field_r3_Slot_inst_get (insn) == 0)
14127 if (Field_t3_Slot_inst_get (insn) == 0 &&
14128 Field_tlo_Slot_inst_get (insn) == 0 &&
14129 Field_r3_Slot_inst_get (insn) == 0)
14133 if (Field_t3_Slot_inst_get (insn) == 0 &&
14134 Field_tlo_Slot_inst_get (insn) == 0 &&
14135 Field_r3_Slot_inst_get (insn) == 0)
14144 if (Field_s_Slot_inst_get (insn) == 0 &&
14145 Field_w_Slot_inst_get (insn) == 0 &&
14146 Field_r3_Slot_inst_get (insn) == 0 &&
14147 Field_t3_Slot_inst_get (insn) == 0 &&
14148 Field_tlo_Slot_inst_get (insn) == 0)
14152 if (Field_s_Slot_inst_get (insn) == 0 &&
14153 Field_w_Slot_inst_get (insn) == 0 &&
14154 Field_r3_Slot_inst_get (insn) == 0 &&
14155 Field_t3_Slot_inst_get (insn) == 0 &&
14156 Field_tlo_Slot_inst_get (insn) == 0)
14160 if (Field_s_Slot_inst_get (insn) == 0 &&
14161 Field_w_Slot_inst_get (insn) == 0 &&
14162 Field_r3_Slot_inst_get (insn) == 0 &&
14163 Field_t3_Slot_inst_get (insn) == 0 &&
14164 Field_tlo_Slot_inst_get (insn) == 0)
14168 if (Field_s_Slot_inst_get (insn) == 0 &&
14169 Field_w_Slot_inst_get (insn) == 0 &&
14170 Field_r3_Slot_inst_get (insn) == 0 &&
14171 Field_t3_Slot_inst_get (insn) == 0 &&
14172 Field_tlo_Slot_inst_get (insn) == 0)
14176 if (Field_s_Slot_inst_get (insn) == 0 &&
14177 Field_w_Slot_inst_get (insn) == 0 &&
14178 Field_r3_Slot_inst_get (insn) == 0 &&
14179 Field_t3_Slot_inst_get (insn) == 0 &&
14180 Field_tlo_Slot_inst_get (insn) == 0)
14184 if (Field_s_Slot_inst_get (insn) == 0 &&
14185 Field_w_Slot_inst_get (insn) == 0 &&
14186 Field_r3_Slot_inst_get (insn) == 0 &&
14187 Field_t3_Slot_inst_get (insn) == 0 &&
14188 Field_tlo_Slot_inst_get (insn) == 0)
14192 if (Field_s_Slot_inst_get (insn) == 0 &&
14193 Field_w_Slot_inst_get (insn) == 0 &&
14194 Field_r3_Slot_inst_get (insn) == 0 &&
14195 Field_t3_Slot_inst_get (insn) == 0 &&
14196 Field_tlo_Slot_inst_get (insn) == 0)
14200 if (Field_s_Slot_inst_get (insn) == 0 &&
14201 Field_w_Slot_inst_get (insn) == 0 &&
14202 Field_r3_Slot_inst_get (insn) == 0 &&
14203 Field_t3_Slot_inst_get (insn) == 0 &&
14204 Field_tlo_Slot_inst_get (insn) == 0)
14208 if (Field_s_Slot_inst_get (insn) == 0 &&
14209 Field_w_Slot_inst_get (insn) == 0 &&
14210 Field_r3_Slot_inst_get (insn) == 0 &&
14211 Field_t3_Slot_inst_get (insn) == 0 &&
14212 Field_tlo_Slot_inst_get (insn) == 0)
14216 if (Field_s_Slot_inst_get (insn) == 0 &&
14217 Field_w_Slot_inst_get (insn) == 0 &&
14218 Field_r3_Slot_inst_get (insn) == 0 &&
14219 Field_t3_Slot_inst_get (insn) == 0 &&
14220 Field_tlo_Slot_inst_get (insn) == 0)
14224 if (Field_s_Slot_inst_get (insn) == 0 &&
14225 Field_w_Slot_inst_get (insn) == 0 &&
14226 Field_r3_Slot_inst_get (insn) == 0 &&
14227 Field_t3_Slot_inst_get (insn) == 0 &&
14228 Field_tlo_Slot_inst_get (insn) == 0)
14232 if (Field_s_Slot_inst_get (insn) == 0 &&
14233 Field_w_Slot_inst_get (insn) == 0 &&
14234 Field_r3_Slot_inst_get (insn) == 0 &&
14235 Field_t3_Slot_inst_get (insn) == 0 &&
14236 Field_tlo_Slot_inst_get (insn) == 0)
14245 if (Field_r_Slot_inst_get (insn) == 0 &&
14246 Field_t3_Slot_inst_get (insn) == 0 &&
14247 Field_tlo_Slot_inst_get (insn) == 0)
14251 if (Field_r_Slot_inst_get (insn) == 0 &&
14252 Field_t3_Slot_inst_get (insn) == 0 &&
14253 Field_tlo_Slot_inst_get (insn) == 0)
14257 if (Field_r_Slot_inst_get (insn) == 0 &&
14258 Field_t3_Slot_inst_get (insn) == 0 &&
14259 Field_tlo_Slot_inst_get (insn) == 0)
14263 if (Field_r_Slot_inst_get (insn) == 0 &&
14264 Field_t3_Slot_inst_get (insn) == 0 &&
14265 Field_tlo_Slot_inst_get (insn) == 0)
14269 if (Field_r_Slot_inst_get (insn) == 0 &&
14270 Field_t3_Slot_inst_get (insn) == 0 &&
14271 Field_tlo_Slot_inst_get (insn) == 0)
14275 if (Field_r_Slot_inst_get (insn) == 0 &&
14276 Field_t3_Slot_inst_get (insn) == 0 &&
14277 Field_tlo_Slot_inst_get (insn) == 0)
14281 if (Field_r_Slot_inst_get (insn) == 0 &&
14282 Field_t3_Slot_inst_get (insn) == 0 &&
14283 Field_tlo_Slot_inst_get (insn) == 0)
14287 if (Field_r_Slot_inst_get (insn) == 0 &&
14288 Field_t3_Slot_inst_get (insn) == 0 &&
14289 Field_tlo_Slot_inst_get (insn) == 0)
14293 if (Field_r_Slot_inst_get (insn) == 0 &&
14294 Field_t3_Slot_inst_get (insn) == 0 &&
14295 Field_tlo_Slot_inst_get (insn) == 0)
14299 if (Field_r_Slot_inst_get (insn) == 0 &&
14300 Field_t3_Slot_inst_get (insn) == 0 &&
14301 Field_tlo_Slot_inst_get (insn) == 0)
14305 if (Field_r_Slot_inst_get (insn) == 0 &&
14306 Field_t3_Slot_inst_get (insn) == 0 &&
14307 Field_tlo_Slot_inst_get (insn) == 0)
14311 if (Field_r_Slot_inst_get (insn) == 0 &&
14312 Field_t3_Slot_inst_get (insn) == 0 &&
14313 Field_tlo_Slot_inst_get (insn) == 0)
14322 if (Field_r3_Slot_inst_get (insn) == 0)
14326 if (Field_r3_Slot_inst_get (insn) == 0)
14330 if (Field_r3_Slot_inst_get (insn) == 0)
14334 if (Field_r3_Slot_inst_get (insn) == 0)
14343 if (Field_r3_Slot_inst_get (insn) == 0)
14347 if (Field_r3_Slot_inst_get (insn) == 0)
14351 if (Field_r3_Slot_inst_get (insn) == 0)
14355 if (Field_r3_Slot_inst_get (insn) == 0)
14364 if (Field_s_Slot_inst_get (insn) == 0 &&
14365 Field_w_Slot_inst_get (insn) == 0 &&
14366 Field_r3_Slot_inst_get (insn) == 0)
14370 if (Field_s_Slot_inst_get (insn) == 0 &&
14371 Field_w_Slot_inst_get (insn) == 0 &&
14372 Field_r3_Slot_inst_get (insn) == 0)
14376 if (Field_s_Slot_inst_get (insn) == 0 &&
14377 Field_w_Slot_inst_get (insn) == 0 &&
14378 Field_r3_Slot_inst_get (insn) == 0)
14382 if (Field_s_Slot_inst_get (insn) == 0 &&
14383 Field_w_Slot_inst_get (insn) == 0 &&
14384 Field_r3_Slot_inst_get (insn) == 0)
14388 if (Field_s_Slot_inst_get (insn) == 0 &&
14389 Field_w_Slot_inst_get (insn) == 0 &&
14390 Field_r3_Slot_inst_get (insn) == 0)
14394 if (Field_s_Slot_inst_get (insn) == 0 &&
14395 Field_w_Slot_inst_get (insn) == 0 &&
14396 Field_r3_Slot_inst_get (insn) == 0)
14400 if (Field_s_Slot_inst_get (insn) == 0 &&
14401 Field_w_Slot_inst_get (insn) == 0 &&
14402 Field_r3_Slot_inst_get (insn) == 0)
14406 if (Field_s_Slot_inst_get (insn) == 0 &&
14407 Field_w_Slot_inst_get (insn) == 0 &&
14408 Field_r3_Slot_inst_get (insn) == 0)
14412 if (Field_s_Slot_inst_get (insn) == 0 &&
14413 Field_w_Slot_inst_get (insn) == 0 &&
14414 Field_r3_Slot_inst_get (insn) == 0)
14418 if (Field_s_Slot_inst_get (insn) == 0 &&
14419 Field_w_Slot_inst_get (insn) == 0 &&
14420 Field_r3_Slot_inst_get (insn) == 0)
14424 if (Field_s_Slot_inst_get (insn) == 0 &&
14425 Field_w_Slot_inst_get (insn) == 0 &&
14426 Field_r3_Slot_inst_get (insn) == 0)
14430 if (Field_s_Slot_inst_get (insn) == 0 &&
14431 Field_w_Slot_inst_get (insn) == 0 &&
14432 Field_r3_Slot_inst_get (insn) == 0)
14440 case 0:
14441 if (Field_r_Slot_inst_get (insn) == 0)
14445 if (Field_r_Slot_inst_get (insn) == 0)
14449 if (Field_r_Slot_inst_get (insn) == 0)
14453 if (Field_r_Slot_inst_get (insn) == 0)
14457 if (Field_r_Slot_inst_get (insn) == 0)
14461 if (Field_r_Slot_inst_get (insn) == 0)
14465 if (Field_r_Slot_inst_get (insn) == 0)
14469 if (Field_r_Slot_inst_get (insn) == 0)
14473 if (Field_r_Slot_inst_get (insn) == 0)
14477 if (Field_r_Slot_inst_get (insn) == 0)
14481 if (Field_r_Slot_inst_get (insn) == 0)
14485 if (Field_r_Slot_inst_get (insn) == 0)
14489 if (Field_r_Slot_inst_get (insn) == 0)
14493 if (Field_r_Slot_inst_get (insn) == 0)
14497 if (Field_r_Slot_inst_get (insn) == 0)
14501 if (Field_r_Slot_inst_get (insn) == 0)
14507 if (Field_op1_Slot_inst_get (insn) == 0 &&
14508 Field_t_Slot_inst_get (insn) == 0 &&
14509 Field_rhi_Slot_inst_get (insn) == 0)
14513 if (Field_op1_Slot_inst_get (insn) == 0 &&
14514 Field_t_Slot_inst_get (insn) == 0 &&
14515 Field_rhi_Slot_inst_get (insn) == 0)
14523 case 0:
14536 case 0:
14541 case 0:
14554 case 0:
14567 case 0:
14591 case 0:
14635 case 0:
14640 case 0:
14651 case 0:
14656 case 0:
14663 if (Field_s_Slot_inst16b_get (insn) == 0)
14667 if (Field_s_Slot_inst16b_get (insn) == 0)
14702 slotbuf[0] = (insn[0] & 0xffffff);
14709 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
14716 slotbuf[0] = (insn[0] & 0xffff);
14723 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
14730 slotbuf[0] = (insn[0] & 0xffff);
14737 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
14769 0,
14770 0,
14771 0,
14772 0,
14773 0,
14774 0,
14775 0,
14776 0,
14829 0,
14830 0,
14831 0,
14832 0,
14833 0,
14834 0,
14835 0,
14836 0,
14863 0,
14864 0,
14865 0,
14866 0,
14868 0,
14869 0,
14870 0,
14871 0,
14872 0,
14874 0,
14875 0,
14877 0,
14878 0,
14879 0,
14880 0,
14881 0,
14882 0,
14883 0,
14886 0,
14888 0,
14897 0,
14898 0,
14899 0,
14900 0,
14901 0,
14902 0,
14903 0,
14904 0,
14905 0,
14906 0,
14907 0,
14923 0,
14924 0,
14925 0,
14926 0,
14928 0,
14929 0,
14930 0,
14931 0,
14932 0,
14934 0,
14935 0,
14937 0,
14938 0,
14939 0,
14940 0,
14941 0,
14942 0,
14943 0,
14946 0,
14948 0,
14957 0,
14958 0,
14959 0,
14960 0,
14961 0,
14962 0,
14963 0,
14964 0,
14965 0,
14966 0,
14967 0,
14983 0,
14984 0,
14985 0,
14986 0,
14988 0,
14989 0,
14990 0,
14991 0,
14992 0,
14994 0,
14995 0,
14997 0,
14998 0,
14999 0,
15000 0,
15001 0,
15002 0,
15003 0,
15006 0,
15008 0,
15017 0,
15018 0,
15019 0,
15020 0,
15021 0,
15022 0,
15023 0,
15024 0,
15025 0,
15026 0,
15027 0,
15043 0,
15044 0,
15045 0,
15046 0,
15048 0,
15049 0,
15050 0,
15051 0,
15052 0,
15054 0,
15055 0,
15057 0,
15058 0,
15059 0,
15060 0,
15061 0,
15062 0,
15063 0,
15066 0,
15068 0,
15077 0,
15078 0,
15079 0,
15080 0,
15081 0,
15082 0,
15083 0,
15084 0,
15085 0,
15086 0,
15087 0,
15101 { "Inst", "x24", 0,
15105 { "Inst16a", "x16a", 0,
15109 { "Inst16b", "x16b", 0,
15121 insn[0] = 0;
15127 insn[0] = 0x8;
15133 insn[0] = 0xc;
15136 static int Format_x24_slots[] = { 0 };
15152 if ((insn[0] & 0x8) == 0)
15153 return 0; /* x24 */
15154 if ((insn[0] & 0xc) == 0x8)
15156 if ((insn[0] & 0xe) == 0xc)
15183 int op0 = insn[0] & 0xf;
15191 0 /* little-endian */,
15192 3 /* insn_size */, 0,
15198 452, opcodes, 0,
15200 NUM_STATES, states, 0,
15201 NUM_SYSREGS, sysregs, 0,
15202 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
15203 1, interfaces, 0,
15204 0, funcUnits, 0