Lines Matching +full:0 +full:xd00000
18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
36 #define CONFIG_ENV_SIZE 0x20000
62 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
63 #define SPD_EEPROM_ADDRESS 0x51
64 #define CONFIG_SYS_SPD_BUS_NUM 0
71 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
96 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
97 FTIM0_NOR_TEADC(0x5) | \
98 FTIM0_NOR_TAVDS(0x6) | \
99 FTIM0_NOR_TEAHC(0x5))
100 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
101 FTIM1_NOR_TRAD_NOR(0x1a) | \
102 FTIM1_NOR_TSEQRAD_NOR(0x13))
103 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
104 FTIM2_NOR_TCH(0x8) | \
105 FTIM2_NOR_TWPH(0xe) | \
106 FTIM2_NOR_TWP(0x1c))
107 #define CONFIG_SYS_NOR_FTIM3 0x04000000
108 #define CONFIG_SYS_IFC_CCR 0x01000000
121 CONFIG_SYS_FLASH_BASE + 0x40000000}
129 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
147 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
148 FTIM0_NAND_TWP(0x18) | \
149 FTIM0_NAND_TWCHT(0x07) | \
150 FTIM0_NAND_TWH(0x0a))
151 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
152 FTIM1_NAND_TWBE(0x39) | \
153 FTIM1_NAND_TRR(0x0e) | \
154 FTIM1_NAND_TRP(0x18))
155 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
156 FTIM2_NAND_TREH(0x0a) | \
157 FTIM2_NAND_TWHRE(0x1e))
158 #define CONFIG_SYS_NAND_FTIM3 0x0
168 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
170 #define QIXIS_QMAP_MASK 0xe0
172 #define QIXIS_LBMAP_MASK 0x0f
173 #define QIXIS_LBMAP_SHIFT 0
174 #define QIXIS_LBMAP_DFLTBANK 0x0e
175 #define QIXIS_LBMAP_ALTBANK 0x2e
176 #define QIXIS_LBMAP_SD 0x00
177 #define QIXIS_LBMAP_EMMC 0x00
178 #define QIXIS_LBMAP_IFC 0x00
179 #define QIXIS_LBMAP_SD_QSPI 0x0e
180 #define QIXIS_LBMAP_QSPI 0x0e
181 #define QIXIS_RCW_SRC_IFC 0x25
182 #define QIXIS_RCW_SRC_SD 0x40
183 #define QIXIS_RCW_SRC_EMMC 0x41
184 #define QIXIS_RCW_SRC_QSPI 0x62
185 #define QIXIS_RST_CTL_RESET 0x41
186 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
187 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
188 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
189 #define QIXIS_RST_FORCE_MEM 0x01
190 #define QIXIS_STAT_PRES1 0xb
191 #define QIXIS_SDID_MASK 0x07
192 #define QIXIS_ESDHC_NO_ADAPTER 0x7
194 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
206 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
211 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
212 FTIM0_GPCM_TEADC(0x0e) | \
213 FTIM0_GPCM_TEAHC(0x0e))
214 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
215 FTIM1_GPCM_TRAD(0x3f))
216 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
217 FTIM2_GPCM_TCH(0xf) | \
218 FTIM2_GPCM_TWP(0x3E))
219 #define SYS_FPGA_CS_FTIM3 0x0
322 #define I2C_MUX_PCA_ADDR_PRI 0x77
323 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
324 #define I2C_RETIMER_ADDR 0x18
325 #define I2C_RETIMER_ADDR2 0x19
326 #define I2C_MUX_CH_DEFAULT 0x8
327 #define I2C_MUX_CH5 0xD
329 #define I2C_MUX_CH_VOL_MONITOR 0xA
332 #define I2C_VOL_MONITOR_ADDR 0x63
333 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
334 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
336 #define I2C_SVDD_MONITOR_ADDR 0x4F
349 #define PMBUS_CMD_PAGE 0x0
350 #define PMBUS_CMD_READ_VOUT 0x8B
351 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
352 #define PMBUS_CMD_VOUT_COMMAND 0x21
354 #define PWM_CHANNEL0 0x0
361 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
367 #define CONFIG_SYS_EEPROM_BUS_NUM 0
368 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
391 #define CONFIG_SYS_MEMTEST_START 0x80000000
392 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
411 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
412 "loadaddr=0x90100000\0" \
413 "kernel_addr=0x100000\0" \
414 "ramdisk_addr=0x800000\0" \
415 "ramdisk_size=0x2000000\0" \
416 "fdt_high=0xa0000000\0" \
417 "initrd_high=0xffffffffffffffff\0" \
418 "kernel_start=0x1000000\0" \
419 "kernel_load=0xa0000000\0" \
420 "kernel_size=0x2800000\0" \
421 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
422 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
423 "sf read 0xa0e00000 0xe00000 0x100000;" \
424 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
425 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
426 "mcmemsize=0x70000000 \0"
430 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
431 "sf read 0x80100000 0xE00000 0x100000;" \
432 "fsl_mc start mc 0x80000000 0x80100000\0"
434 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
435 "mmc read 0x80100000 0x7000 0x800;" \
436 "fsl_mc start mc 0x80000000 0x80100000\0"
438 "fsl_mc start mc 0x580A00000 0x580E00000\0"
442 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
443 "loadaddr=0x90100000\0" \
444 "kernel_addr=0x100000\0" \
445 "kernel_addr_sd=0x800\0" \
446 "ramdisk_addr=0x800000\0" \
447 "ramdisk_size=0x2000000\0" \
448 "fdt_high=0xa0000000\0" \
449 "initrd_high=0xffffffffffffffff\0" \
450 "kernel_start=0x1000000\0" \
451 "kernel_start_sd=0x8000\0" \
452 "kernel_load=0xa0000000\0" \
453 "kernel_size=0x2800000\0" \
454 "kernel_size_sd=0x14000\0" \
455 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
456 "sf read 0x80100000 0xE00000 0x100000;" \
457 "fsl_mc start mc 0x80000000 0x80100000\0" \
458 "mcmemsize=0x70000000 \0"
459 #define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
460 "sf read 0x80001000 0xd00000 0x100000;"\
461 " fsl_mc lazyapply dpl 0x80001000 &&" \
464 #define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
465 " fsl_mc lazyapply dpl 0x80001000 &&" \
468 #define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
475 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
476 "loadaddr=0x90100000\0" \
477 "kernel_addr=0x100000\0" \
478 "ramdisk_addr=0x800000\0" \
479 "ramdisk_size=0x2000000\0" \
480 "fdt_high=0xa0000000\0" \
481 "initrd_high=0xffffffffffffffff\0" \
482 "kernel_start=0x1000000\0" \
483 "kernel_load=0xa0000000\0" \
484 "kernel_size=0x2800000\0" \
485 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
486 "sf read 0x80100000 0xE00000 0x100000;" \
487 "fsl_mc start mc 0x80000000 0x80100000\0" \
488 "mcmemsize=0x70000000 \0"
492 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
493 "loadaddr=0x90100000\0" \
494 "kernel_addr=0x800\0" \
495 "ramdisk_addr=0x800000\0" \
496 "ramdisk_size=0x2000000\0" \
497 "fdt_high=0xa0000000\0" \
498 "initrd_high=0xffffffffffffffff\0" \
499 "kernel_start=0x8000\0" \
500 "kernel_load=0xa0000000\0" \
501 "kernel_size=0x14000\0" \
502 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
503 "mmc read 0x80100000 0x7000 0x800;" \
504 "fsl_mc start mc 0x80000000 0x80100000\0" \
505 "mcmemsize=0x70000000 \0"
509 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
510 "loadaddr=0x90100000\0" \
511 "kernel_addr=0x100000\0" \
512 "ramdisk_addr=0x800000\0" \
513 "ramdisk_size=0x2000000\0" \
514 "fdt_high=0xa0000000\0" \
515 "initrd_high=0xffffffffffffffff\0" \
516 "kernel_start=0x1000000\0" \
517 "kernel_load=0xa0000000\0" \
518 "kernel_size=0x2800000\0" \
519 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
520 "mcmemsize=0x70000000 \0"
532 #define RGMII_PHY1_ADDR 0x1
533 #define RGMII_PHY2_ADDR 0x2
534 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
535 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
536 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
537 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
539 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
540 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
541 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
542 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
543 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
544 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
545 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
546 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
547 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
548 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
549 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
550 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
551 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
552 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
553 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
554 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
562 func(USB, usb, 0) \
563 func(MMC, mmc, 0) \
564 func(SCSI, scsi, 0) \