Lines Matching +full:0 +full:xd00000
31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "PTEVADDR", 83, 0 },
42 { "MMID", 89, 0 },
43 { "DDR", 104, 0 },
44 { "CONFIGID0", 176, 0 },
45 { "CONFIGID1", 208, 0 },
46 { "INTERRUPT", 226, 0 },
47 { "INTCLEAR", 227, 0 },
48 { "CCOUNT", 234, 0 },
49 { "PRID", 235, 0 },
50 { "ICOUNT", 236, 0 },
51 { "CCOMPARE0", 240, 0 },
52 { "CCOMPARE1", 241, 0 },
53 { "CCOMPARE2", 242, 0 },
54 { "VECBASE", 231, 0 },
55 { "EPC1", 177, 0 },
56 { "EPC2", 178, 0 },
57 { "EPC3", 179, 0 },
58 { "EPC4", 180, 0 },
59 { "EPC5", 181, 0 },
60 { "EPC6", 182, 0 },
61 { "EPC7", 183, 0 },
62 { "EXCSAVE1", 209, 0 },
63 { "EXCSAVE2", 210, 0 },
64 { "EXCSAVE3", 211, 0 },
65 { "EXCSAVE4", 212, 0 },
66 { "EXCSAVE5", 213, 0 },
67 { "EXCSAVE6", 214, 0 },
68 { "EXCSAVE7", 215, 0 },
69 { "EPS2", 194, 0 },
70 { "EPS3", 195, 0 },
71 { "EPS4", 196, 0 },
72 { "EPS5", 197, 0 },
73 { "EPS6", 198, 0 },
74 { "EPS7", 199, 0 },
75 { "EXCCAUSE", 232, 0 },
76 { "DEPC", 192, 0 },
77 { "EXCVADDR", 238, 0 },
78 { "WINDOWBASE", 72, 0 },
79 { "WINDOWSTART", 73, 0 },
80 { "SAR", 3, 0 },
81 { "PS", 230, 0 },
82 { "MISC0", 244, 0 },
83 { "MISC1", 245, 0 },
84 { "INTENABLE", 228, 0 },
85 { "DBREAKA0", 144, 0 },
86 { "DBREAKC0", 160, 0 },
87 { "DBREAKA1", 145, 0 },
88 { "DBREAKC1", 161, 0 },
89 { "IBREAKA0", 128, 0 },
90 { "IBREAKA1", 129, 0 },
91 { "IBREAKENABLE", 96, 0 },
92 { "ICOUNTLEVEL", 237, 0 },
93 { "DEBUGCAUSE", 233, 0 },
94 { "RASID", 90, 0 },
95 { "ITLBCFG", 91, 0 },
96 { "DTLBCFG", 92, 0 },
97 { "CPENABLE", 224, 0 },
98 { "SCOMPARE1", 12, 0 },
99 { "ATOMCTL", 99, 0 },
100 { "ERACCESS", 95, 0 },
115 { "LCOUNT", 32, 0 },
116 { "PC", 32, 0 },
117 { "ICOUNT", 32, 0 },
118 { "DDR", 32, 0 },
119 { "INTERRUPT", 22, 0 },
120 { "CCOUNT", 32, 0 },
121 { "XTSYNC", 1, 0 },
122 { "VECBASE", 22, 0 },
123 { "EPC1", 32, 0 },
124 { "EPC2", 32, 0 },
125 { "EPC3", 32, 0 },
126 { "EPC4", 32, 0 },
127 { "EPC5", 32, 0 },
128 { "EPC6", 32, 0 },
129 { "EPC7", 32, 0 },
130 { "EXCSAVE1", 32, 0 },
131 { "EXCSAVE2", 32, 0 },
132 { "EXCSAVE3", 32, 0 },
133 { "EXCSAVE4", 32, 0 },
134 { "EXCSAVE5", 32, 0 },
135 { "EXCSAVE6", 32, 0 },
136 { "EXCSAVE7", 32, 0 },
137 { "EPS2", 15, 0 },
138 { "EPS3", 15, 0 },
139 { "EPS4", 15, 0 },
140 { "EPS5", 15, 0 },
141 { "EPS6", 15, 0 },
142 { "EPS7", 15, 0 },
143 { "EXCCAUSE", 6, 0 },
144 { "PSINTLEVEL", 4, 0 },
145 { "PSUM", 1, 0 },
146 { "PSWOE", 1, 0 },
147 { "PSRING", 2, 0 },
148 { "PSEXCM", 1, 0 },
149 { "DEPC", 32, 0 },
150 { "EXCVADDR", 32, 0 },
151 { "WindowBase", 3, 0 },
152 { "WindowStart", 8, 0 },
153 { "PSCALLINC", 2, 0 },
154 { "PSOWB", 4, 0 },
155 { "LBEG", 32, 0 },
156 { "LEND", 32, 0 },
157 { "SAR", 6, 0 },
158 { "THREADPTR", 32, 0 },
159 { "MISC0", 32, 0 },
160 { "MISC1", 32, 0 },
161 { "ACC", 40, 0 },
162 { "InOCDMode", 1, 0 },
163 { "INTENABLE", 22, 0 },
164 { "DBREAKA0", 32, 0 },
165 { "DBREAKC0", 8, 0 },
166 { "DBREAKA1", 32, 0 },
167 { "DBREAKC1", 8, 0 },
168 { "IBREAKA0", 32, 0 },
169 { "IBREAKA1", 32, 0 },
170 { "IBREAKENABLE", 2, 0 },
171 { "ICOUNTLEVEL", 4, 0 },
172 { "DEBUGCAUSE", 6, 0 },
173 { "DBNUM", 4, 0 },
174 { "CCOMPARE0", 32, 0 },
175 { "CCOMPARE1", 32, 0 },
176 { "CCOMPARE2", 32, 0 },
177 { "ASID3", 8, 0 },
178 { "ASID2", 8, 0 },
179 { "ASID1", 8, 0 },
180 { "INSTPGSZID6", 1, 0 },
181 { "INSTPGSZID5", 1, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID6", 1, 0 },
184 { "DATAPGSZID5", 1, 0 },
185 { "DATAPGSZID4", 2, 0 },
186 { "PTBASE", 10, 0 },
187 { "CPENABLE", 8, 0 },
188 { "SCOMPARE1", 32, 0 },
189 { "ATOMCTL", 6, 0 },
190 { "ERACCESS", 16, 0 },
191 { "RoundMode", 2, 0 },
192 { "InvalidEnable", 1, 0 },
193 { "DivZeroEnable", 1, 0 },
194 { "OverflowEnable", 1, 0 },
195 { "UnderflowEnable", 1, 0 },
196 { "InexactEnable", 1, 0 },
202 { "FPreserved20", 20, 0 },
203 { "FPreserved20a", 20, 0 },
204 { "FPreserved5", 5, 0 },
205 { "FPreserved7", 7, 0 },
312 unsigned tie_t = 0;
313 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
322 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
328 unsigned tie_t = 0;
329 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
338 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
344 unsigned tie_t = 0;
345 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
354 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
360 unsigned tie_t = 0;
361 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
370 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
376 unsigned tie_t = 0;
377 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
386 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
392 unsigned tie_t = 0;
393 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
402 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
408 unsigned tie_t = 0;
409 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
418 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
424 unsigned tie_t = 0;
425 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
434 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
440 unsigned tie_t = 0;
441 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
442 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
451 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
453 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
459 unsigned tie_t = 0;
460 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
461 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
470 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
472 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
478 unsigned tie_t = 0;
479 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
488 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
494 unsigned tie_t = 0;
495 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
504 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
510 unsigned tie_t = 0;
511 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
520 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
526 unsigned tie_t = 0;
527 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
536 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
542 unsigned tie_t = 0;
543 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
552 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
558 unsigned tie_t = 0;
559 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
568 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
574 unsigned tie_t = 0;
575 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
584 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
590 unsigned tie_t = 0;
591 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
600 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
606 unsigned tie_t = 0;
607 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
616 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
622 unsigned tie_t = 0;
623 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
632 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
638 unsigned tie_t = 0;
639 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
648 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
654 unsigned tie_t = 0;
655 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
664 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
670 unsigned tie_t = 0;
671 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
680 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
686 unsigned tie_t = 0;
687 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
696 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
702 unsigned tie_t = 0;
703 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
712 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
718 unsigned tie_t = 0;
719 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
728 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
734 unsigned tie_t = 0;
735 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
736 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
745 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
747 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
753 unsigned tie_t = 0;
754 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
763 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
769 unsigned tie_t = 0;
770 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
779 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
785 unsigned tie_t = 0;
786 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
795 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
801 unsigned tie_t = 0;
802 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
811 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
817 unsigned tie_t = 0;
818 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
827 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
833 unsigned tie_t = 0;
834 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
835 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
844 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
846 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
852 unsigned tie_t = 0;
853 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
862 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
868 unsigned tie_t = 0;
869 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
878 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
884 unsigned tie_t = 0;
885 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
894 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
900 unsigned tie_t = 0;
901 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
910 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
916 unsigned tie_t = 0;
917 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
926 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
932 unsigned tie_t = 0;
933 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
942 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
948 unsigned tie_t = 0;
949 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
958 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
964 unsigned tie_t = 0;
965 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
966 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
975 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
977 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
983 unsigned tie_t = 0;
984 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
985 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
994 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
996 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1002 unsigned tie_t = 0;
1003 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1004 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1013 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1015 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1021 unsigned tie_t = 0;
1022 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1031 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1037 unsigned tie_t = 0;
1038 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1039 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1048 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1050 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1056 unsigned tie_t = 0;
1057 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1066 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1072 unsigned tie_t = 0;
1073 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1074 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1083 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1085 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1091 unsigned tie_t = 0;
1092 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1101 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1107 unsigned tie_t = 0;
1108 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1117 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1123 unsigned tie_t = 0;
1124 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1133 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1139 unsigned tie_t = 0;
1140 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1149 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1155 unsigned tie_t = 0;
1156 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1165 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1171 unsigned tie_t = 0;
1172 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1181 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1187 unsigned tie_t = 0;
1188 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1197 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1203 unsigned tie_t = 0;
1204 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1213 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1219 unsigned tie_t = 0;
1220 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1229 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1235 unsigned tie_t = 0;
1236 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1245 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1251 unsigned tie_t = 0;
1252 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1253 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1262 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1264 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1270 unsigned tie_t = 0;
1271 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1272 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1281 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1283 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1289 unsigned tie_t = 0;
1290 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1299 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1305 unsigned tie_t = 0;
1306 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1315 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1321 unsigned tie_t = 0;
1322 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1331 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1337 unsigned tie_t = 0;
1338 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1347 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1353 unsigned tie_t = 0;
1354 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1363 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1369 unsigned tie_t = 0;
1370 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1379 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1385 unsigned tie_t = 0;
1386 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
1395 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
1401 unsigned tie_t = 0;
1402 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1411 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1417 unsigned tie_t = 0;
1418 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
1427 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
1433 unsigned tie_t = 0;
1434 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1443 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1449 unsigned tie_t = 0;
1450 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1459 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1465 unsigned tie_t = 0;
1466 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1475 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1481 unsigned tie_t = 0;
1482 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1491 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1497 unsigned tie_t = 0;
1498 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1507 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1513 unsigned tie_t = 0;
1514 tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27);
1523 insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4);
1536 return 0;
1560 return 0;
1584 return 0;
1590 return 0;
1596 return 0;
1602 return 0;
1720 { "IMPWIRE", 32, 0, 0, 'i' }
1732 0xffffffff,
1733 0x1,
1734 0x2,
1735 0x3,
1736 0x4,
1737 0x5,
1738 0x6,
1739 0x7,
1740 0x8,
1741 0x9,
1742 0xa,
1743 0xb,
1744 0xc,
1745 0xd,
1746 0xe,
1747 0xf,
1748 0
1753 0xffffffff,
1754 0x1,
1755 0x2,
1756 0x3,
1757 0x4,
1758 0x5,
1759 0x6,
1760 0x7,
1761 0x8,
1762 0xa,
1763 0xc,
1764 0x10,
1765 0x20,
1766 0x40,
1767 0x80,
1768 0x100,
1769 0
1774 0x8000,
1775 0x10000,
1776 0x2,
1777 0x3,
1778 0x4,
1779 0x5,
1780 0x6,
1781 0x7,
1782 0x8,
1783 0xa,
1784 0xc,
1785 0x10,
1786 0x20,
1787 0x40,
1788 0x80,
1789 0x100,
1790 0
1795 0xff & 0xff,
1796 0xfd & 0xff,
1797 0xfb & 0xff,
1798 0xf9 & 0xff,
1799 0xf7 & 0xff,
1800 0xf5 & 0xff,
1801 0xf4 & 0xff,
1802 0xf2 & 0xff,
1803 0xf0 & 0xff,
1804 0xee & 0xff,
1805 0xed & 0xff,
1806 0xeb & 0xff,
1807 0xe9 & 0xff,
1808 0xe8 & 0xff,
1809 0xe6 & 0xff,
1810 0xe4 & 0xff,
1811 0xe3 & 0xff,
1812 0xe1 & 0xff,
1813 0xe0 & 0xff,
1814 0xde & 0xff,
1815 0xdd & 0xff,
1816 0xdb & 0xff,
1817 0xda & 0xff,
1818 0xd8 & 0xff,
1819 0xd7 & 0xff,
1820 0xd5 & 0xff,
1821 0xd4 & 0xff,
1822 0xd3 & 0xff,
1823 0xd1 & 0xff,
1824 0xd0 & 0xff,
1825 0xcf & 0xff,
1826 0xcd & 0xff,
1827 0xcc & 0xff,
1828 0xcb & 0xff,
1829 0xca & 0xff,
1830 0xc8 & 0xff,
1831 0xc7 & 0xff,
1832 0xc6 & 0xff,
1833 0xc5 & 0xff,
1834 0xc4 & 0xff,
1835 0xc2 & 0xff,
1836 0xc1 & 0xff,
1837 0xc0 & 0xff,
1838 0xbf & 0xff,
1839 0xbe & 0xff,
1840 0xbd & 0xff,
1841 0xbc & 0xff,
1842 0xbb & 0xff,
1843 0xba & 0xff,
1844 0xb9 & 0xff,
1845 0xb8 & 0xff,
1846 0xb7 & 0xff,
1847 0xb6 & 0xff,
1848 0xb5 & 0xff,
1849 0xb4 & 0xff,
1850 0xb3 & 0xff,
1851 0xb2 & 0xff,
1852 0xb1 & 0xff,
1853 0xb0 & 0xff,
1854 0xaf & 0xff,
1855 0xae & 0xff,
1856 0xad & 0xff,
1857 0xac & 0xff,
1858 0xab & 0xff,
1859 0xaa & 0xff,
1860 0xa9 & 0xff,
1861 0xa8 & 0xff,
1862 0xa8 & 0xff,
1863 0xa7 & 0xff,
1864 0xa6 & 0xff,
1865 0xa5 & 0xff,
1866 0xa4 & 0xff,
1867 0xa3 & 0xff,
1868 0xa3 & 0xff,
1869 0xa2 & 0xff,
1870 0xa1 & 0xff,
1871 0xa0 & 0xff,
1872 0x9f & 0xff,
1873 0x9f & 0xff,
1874 0x9e & 0xff,
1875 0x9d & 0xff,
1876 0x9c & 0xff,
1877 0x9c & 0xff,
1878 0x9b & 0xff,
1879 0x9a & 0xff,
1880 0x99 & 0xff,
1881 0x99 & 0xff,
1882 0x98 & 0xff,
1883 0x97 & 0xff,
1884 0x97 & 0xff,
1885 0x96 & 0xff,
1886 0x95 & 0xff,
1887 0x95 & 0xff,
1888 0x94 & 0xff,
1889 0x93 & 0xff,
1890 0x93 & 0xff,
1891 0x92 & 0xff,
1892 0x91 & 0xff,
1893 0x91 & 0xff,
1894 0x90 & 0xff,
1895 0x8f & 0xff,
1896 0x8f & 0xff,
1897 0x8e & 0xff,
1898 0x8e & 0xff,
1899 0x8d & 0xff,
1900 0x8c & 0xff,
1901 0x8c & 0xff,
1902 0x8b & 0xff,
1903 0x8b & 0xff,
1904 0x8a & 0xff,
1905 0x89 & 0xff,
1906 0x89 & 0xff,
1907 0x88 & 0xff,
1908 0x88 & 0xff,
1909 0x87 & 0xff,
1910 0x87 & 0xff,
1911 0x86 & 0xff,
1912 0x85 & 0xff,
1913 0x85 & 0xff,
1914 0x84 & 0xff,
1915 0x84 & 0xff,
1916 0x83 & 0xff,
1917 0x83 & 0xff,
1918 0x82 & 0xff,
1919 0x82 & 0xff,
1920 0x81 & 0xff,
1921 0x81 & 0xff,
1922 0x81 & 0xff,
1923 0
1928 0xb4 & 0xff,
1929 0xb3 & 0xff,
1930 0xb2 & 0xff,
1931 0xb0 & 0xff,
1932 0xaf & 0xff,
1933 0xae & 0xff,
1934 0xac & 0xff,
1935 0xab & 0xff,
1936 0xaa & 0xff,
1937 0xa9 & 0xff,
1938 0xa8 & 0xff,
1939 0xa7 & 0xff,
1940 0xa6 & 0xff,
1941 0xa5 & 0xff,
1942 0xa3 & 0xff,
1943 0xa2 & 0xff,
1944 0xa1 & 0xff,
1945 0xa0 & 0xff,
1946 0x9f & 0xff,
1947 0x9e & 0xff,
1948 0x9e & 0xff,
1949 0x9d & 0xff,
1950 0x9c & 0xff,
1951 0x9b & 0xff,
1952 0x9a & 0xff,
1953 0x99 & 0xff,
1954 0x98 & 0xff,
1955 0x97 & 0xff,
1956 0x97 & 0xff,
1957 0x96 & 0xff,
1958 0x95 & 0xff,
1959 0x94 & 0xff,
1960 0x93 & 0xff,
1961 0x93 & 0xff,
1962 0x92 & 0xff,
1963 0x91 & 0xff,
1964 0x90 & 0xff,
1965 0x90 & 0xff,
1966 0x8f & 0xff,
1967 0x8e & 0xff,
1968 0x8e & 0xff,
1969 0x8d & 0xff,
1970 0x8c & 0xff,
1971 0x8c & 0xff,
1972 0x8b & 0xff,
1973 0x8a & 0xff,
1974 0x8a & 0xff,
1975 0x89 & 0xff,
1976 0x89 & 0xff,
1977 0x88 & 0xff,
1978 0x87 & 0xff,
1979 0x87 & 0xff,
1980 0x86 & 0xff,
1981 0x86 & 0xff,
1982 0x85 & 0xff,
1983 0x84 & 0xff,
1984 0x84 & 0xff,
1985 0x83 & 0xff,
1986 0x83 & 0xff,
1987 0x82 & 0xff,
1988 0x82 & 0xff,
1989 0x81 & 0xff,
1990 0x81 & 0xff,
1991 0x80 & 0xff,
1992 0xff & 0xff,
1993 0xfd & 0xff,
1994 0xfb & 0xff,
1995 0xf9 & 0xff,
1996 0xf7 & 0xff,
1997 0xf6 & 0xff,
1998 0xf4 & 0xff,
1999 0xf2 & 0xff,
2000 0xf1 & 0xff,
2001 0xef & 0xff,
2002 0xed & 0xff,
2003 0xec & 0xff,
2004 0xea & 0xff,
2005 0xe9 & 0xff,
2006 0xe7 & 0xff,
2007 0xe6 & 0xff,
2008 0xe4 & 0xff,
2009 0xe3 & 0xff,
2010 0xe1 & 0xff,
2011 0xe0 & 0xff,
2012 0xdf & 0xff,
2013 0xdd & 0xff,
2014 0xdc & 0xff,
2015 0xdb & 0xff,
2016 0xda & 0xff,
2017 0xd8 & 0xff,
2018 0xd7 & 0xff,
2019 0xd6 & 0xff,
2020 0xd5 & 0xff,
2021 0xd4 & 0xff,
2022 0xd3 & 0xff,
2023 0xd2 & 0xff,
2024 0xd0 & 0xff,
2025 0xcf & 0xff,
2026 0xce & 0xff,
2027 0xcd & 0xff,
2028 0xcc & 0xff,
2029 0xcb & 0xff,
2030 0xca & 0xff,
2031 0xc9 & 0xff,
2032 0xc8 & 0xff,
2033 0xc7 & 0xff,
2034 0xc6 & 0xff,
2035 0xc6 & 0xff,
2036 0xc5 & 0xff,
2037 0xc4 & 0xff,
2038 0xc3 & 0xff,
2039 0xc2 & 0xff,
2040 0xc1 & 0xff,
2041 0xc0 & 0xff,
2042 0xbf & 0xff,
2043 0xbf & 0xff,
2044 0xbe & 0xff,
2045 0xbd & 0xff,
2046 0xbc & 0xff,
2047 0xbb & 0xff,
2048 0xbb & 0xff,
2049 0xba & 0xff,
2050 0xb9 & 0xff,
2051 0xb8 & 0xff,
2052 0xb8 & 0xff,
2053 0xb7 & 0xff,
2054 0xb6 & 0xff,
2055 0xb5 & 0xff,
2056 0
2061 0x3fc & 0x3ff,
2062 0x3f4 & 0x3ff,
2063 0x3ec & 0x3ff,
2064 0x3e5 & 0x3ff,
2065 0x3dd & 0x3ff,
2066 0x3d6 & 0x3ff,
2067 0x3cf & 0x3ff,
2068 0x3c7 & 0x3ff,
2069 0x3c0 & 0x3ff,
2070 0x3b9 & 0x3ff,
2071 0x3b2 & 0x3ff,
2072 0x3ac & 0x3ff,
2073 0x3a5 & 0x3ff,
2074 0x39e & 0x3ff,
2075 0x398 & 0x3ff,
2076 0x391 & 0x3ff,
2077 0x38b & 0x3ff,
2078 0x385 & 0x3ff,
2079 0x37f & 0x3ff,
2080 0x378 & 0x3ff,
2081 0x373 & 0x3ff,
2082 0x36c & 0x3ff,
2083 0x367 & 0x3ff,
2084 0x361 & 0x3ff,
2085 0x35c & 0x3ff,
2086 0x356 & 0x3ff,
2087 0x350 & 0x3ff,
2088 0x34b & 0x3ff,
2089 0x345 & 0x3ff,
2090 0x340 & 0x3ff,
2091 0x33b & 0x3ff,
2092 0x335 & 0x3ff,
2093 0x330 & 0x3ff,
2094 0x32c & 0x3ff,
2095 0x327 & 0x3ff,
2096 0x322 & 0x3ff,
2097 0x31c & 0x3ff,
2098 0x318 & 0x3ff,
2099 0x314 & 0x3ff,
2100 0x30e & 0x3ff,
2101 0x30a & 0x3ff,
2102 0x306 & 0x3ff,
2103 0x300 & 0x3ff,
2104 0x2fc & 0x3ff,
2105 0x2f8 & 0x3ff,
2106 0x2f4 & 0x3ff,
2107 0x2f0 & 0x3ff,
2108 0x2ea & 0x3ff,
2109 0x2e6 & 0x3ff,
2110 0x2e2 & 0x3ff,
2111 0x2de & 0x3ff,
2112 0x2da & 0x3ff,
2113 0x2d6 & 0x3ff,
2114 0x2d2 & 0x3ff,
2115 0x2ce & 0x3ff,
2116 0x2ca & 0x3ff,
2117 0x2c6 & 0x3ff,
2118 0x2c2 & 0x3ff,
2119 0x2be & 0x3ff,
2120 0x2ba & 0x3ff,
2121 0x2b8 & 0x3ff,
2122 0x2b4 & 0x3ff,
2123 0x2b0 & 0x3ff,
2124 0x2ac & 0x3ff,
2125 0x2a8 & 0x3ff,
2126 0x2a6 & 0x3ff,
2127 0x2a2 & 0x3ff,
2128 0x29e & 0x3ff,
2129 0x29c & 0x3ff,
2130 0x298 & 0x3ff,
2131 0x294 & 0x3ff,
2132 0x290 & 0x3ff,
2133 0x28e & 0x3ff,
2134 0x28a & 0x3ff,
2135 0x288 & 0x3ff,
2136 0x284 & 0x3ff,
2137 0x280 & 0x3ff,
2138 0x27e & 0x3ff,
2139 0x27a & 0x3ff,
2140 0x278 & 0x3ff,
2141 0x274 & 0x3ff,
2142 0x272 & 0x3ff,
2143 0x26e & 0x3ff,
2144 0x26c & 0x3ff,
2145 0x268 & 0x3ff,
2146 0x266 & 0x3ff,
2147 0x264 & 0x3ff,
2148 0x260 & 0x3ff,
2149 0x25e & 0x3ff,
2150 0x25a & 0x3ff,
2151 0x258 & 0x3ff,
2152 0x254 & 0x3ff,
2153 0x252 & 0x3ff,
2154 0x250 & 0x3ff,
2155 0x24c & 0x3ff,
2156 0x24a & 0x3ff,
2157 0x248 & 0x3ff,
2158 0x246 & 0x3ff,
2159 0x242 & 0x3ff,
2160 0x240 & 0x3ff,
2161 0x23e & 0x3ff,
2162 0x23c & 0x3ff,
2163 0x238 & 0x3ff,
2164 0x236 & 0x3ff,
2165 0x234 & 0x3ff,
2166 0x232 & 0x3ff,
2167 0x230 & 0x3ff,
2168 0x22c & 0x3ff,
2169 0x22a & 0x3ff,
2170 0x228 & 0x3ff,
2171 0x226 & 0x3ff,
2172 0x224 & 0x3ff,
2173 0x220 & 0x3ff,
2174 0x21e & 0x3ff,
2175 0x21c & 0x3ff,
2176 0x21a & 0x3ff,
2177 0x218 & 0x3ff,
2178 0x216 & 0x3ff,
2179 0x214 & 0x3ff,
2180 0x212 & 0x3ff,
2181 0x210 & 0x3ff,
2182 0x20e & 0x3ff,
2183 0x20c & 0x3ff,
2184 0x208 & 0x3ff,
2185 0x208 & 0x3ff,
2186 0x204 & 0x3ff,
2187 0x204 & 0x3ff,
2188 0x201 & 0x3ff,
2189 0
2194 0x1a5 & 0x3ff,
2195 0x1a0 & 0x3ff,
2196 0x19a & 0x3ff,
2197 0x195 & 0x3ff,
2198 0x18f & 0x3ff,
2199 0x18a & 0x3ff,
2200 0x185 & 0x3ff,
2201 0x180 & 0x3ff,
2202 0x17a & 0x3ff,
2203 0x175 & 0x3ff,
2204 0x170 & 0x3ff,
2205 0x16b & 0x3ff,
2206 0x166 & 0x3ff,
2207 0x161 & 0x3ff,
2208 0x15d & 0x3ff,
2209 0x158 & 0x3ff,
2210 0x153 & 0x3ff,
2211 0x14e & 0x3ff,
2212 0x14a & 0x3ff,
2213 0x145 & 0x3ff,
2214 0x140 & 0x3ff,
2215 0x13c & 0x3ff,
2216 0x138 & 0x3ff,
2217 0x133 & 0x3ff,
2218 0x12f & 0x3ff,
2219 0x12a & 0x3ff,
2220 0x126 & 0x3ff,
2221 0x122 & 0x3ff,
2222 0x11e & 0x3ff,
2223 0x11a & 0x3ff,
2224 0x115 & 0x3ff,
2225 0x111 & 0x3ff,
2226 0x10d & 0x3ff,
2227 0x109 & 0x3ff,
2228 0x105 & 0x3ff,
2229 0x101 & 0x3ff,
2230 0xfd & 0x3ff,
2231 0xfa & 0x3ff,
2232 0xf6 & 0x3ff,
2233 0xf2 & 0x3ff,
2234 0xee & 0x3ff,
2235 0xea & 0x3ff,
2236 0xe7 & 0x3ff,
2237 0xe3 & 0x3ff,
2238 0xdf & 0x3ff,
2239 0xdc & 0x3ff,
2240 0xd8 & 0x3ff,
2241 0xd5 & 0x3ff,
2242 0xd1 & 0x3ff,
2243 0xce & 0x3ff,
2244 0xca & 0x3ff,
2245 0xc7 & 0x3ff,
2246 0xc3 & 0x3ff,
2247 0xc0 & 0x3ff,
2248 0xbd & 0x3ff,
2249 0xb9 & 0x3ff,
2250 0xb6 & 0x3ff,
2251 0xb3 & 0x3ff,
2252 0xb0 & 0x3ff,
2253 0xad & 0x3ff,
2254 0xa9 & 0x3ff,
2255 0xa6 & 0x3ff,
2256 0xa3 & 0x3ff,
2257 0xa0 & 0x3ff,
2258 0x9d & 0x3ff,
2259 0x9a & 0x3ff,
2260 0x97 & 0x3ff,
2261 0x94 & 0x3ff,
2262 0x91 & 0x3ff,
2263 0x8e & 0x3ff,
2264 0x8b & 0x3ff,
2265 0x88 & 0x3ff,
2266 0x85 & 0x3ff,
2267 0x82 & 0x3ff,
2268 0x7f & 0x3ff,
2269 0x7d & 0x3ff,
2270 0x7a & 0x3ff,
2271 0x77 & 0x3ff,
2272 0x74 & 0x3ff,
2273 0x71 & 0x3ff,
2274 0x6f & 0x3ff,
2275 0x6c & 0x3ff,
2276 0x69 & 0x3ff,
2277 0x67 & 0x3ff,
2278 0x64 & 0x3ff,
2279 0x61 & 0x3ff,
2280 0x5f & 0x3ff,
2281 0x5c & 0x3ff,
2282 0x5a & 0x3ff,
2283 0x57 & 0x3ff,
2284 0x54 & 0x3ff,
2285 0x52 & 0x3ff,
2286 0x4f & 0x3ff,
2287 0x4d & 0x3ff,
2288 0x4a & 0x3ff,
2289 0x48 & 0x3ff,
2290 0x45 & 0x3ff,
2291 0x43 & 0x3ff,
2292 0x41 & 0x3ff,
2293 0x3e & 0x3ff,
2294 0x3c & 0x3ff,
2295 0x3a & 0x3ff,
2296 0x37 & 0x3ff,
2297 0x35 & 0x3ff,
2298 0x33 & 0x3ff,
2299 0x30 & 0x3ff,
2300 0x2e & 0x3ff,
2301 0x2c & 0x3ff,
2302 0x29 & 0x3ff,
2303 0x27 & 0x3ff,
2304 0x25 & 0x3ff,
2305 0x23 & 0x3ff,
2306 0x20 & 0x3ff,
2307 0x1e & 0x3ff,
2308 0x1c & 0x3ff,
2309 0x1a & 0x3ff,
2310 0x18 & 0x3ff,
2311 0x16 & 0x3ff,
2312 0x14 & 0x3ff,
2313 0x11 & 0x3ff,
2314 0xf & 0x3ff,
2315 0xd & 0x3ff,
2316 0xb & 0x3ff,
2317 0x9 & 0x3ff,
2318 0x7 & 0x3ff,
2319 0x5 & 0x3ff,
2320 0x3 & 0x3ff,
2321 0x1 & 0x3ff,
2322 0x3fc & 0x3ff,
2323 0x3f4 & 0x3ff,
2324 0x3ec & 0x3ff,
2325 0x3e5 & 0x3ff,
2326 0x3dd & 0x3ff,
2327 0x3d5 & 0x3ff,
2328 0x3ce & 0x3ff,
2329 0x3c7 & 0x3ff,
2330 0x3bf & 0x3ff,
2331 0x3b8 & 0x3ff,
2332 0x3b1 & 0x3ff,
2333 0x3aa & 0x3ff,
2334 0x3a3 & 0x3ff,
2335 0x39c & 0x3ff,
2336 0x395 & 0x3ff,
2337 0x38e & 0x3ff,
2338 0x388 & 0x3ff,
2339 0x381 & 0x3ff,
2340 0x37a & 0x3ff,
2341 0x374 & 0x3ff,
2342 0x36d & 0x3ff,
2343 0x367 & 0x3ff,
2344 0x361 & 0x3ff,
2345 0x35a & 0x3ff,
2346 0x354 & 0x3ff,
2347 0x34e & 0x3ff,
2348 0x348 & 0x3ff,
2349 0x342 & 0x3ff,
2350 0x33c & 0x3ff,
2351 0x336 & 0x3ff,
2352 0x330 & 0x3ff,
2353 0x32b & 0x3ff,
2354 0x325 & 0x3ff,
2355 0x31f & 0x3ff,
2356 0x31a & 0x3ff,
2357 0x314 & 0x3ff,
2358 0x30f & 0x3ff,
2359 0x309 & 0x3ff,
2360 0x304 & 0x3ff,
2361 0x2fe & 0x3ff,
2362 0x2f9 & 0x3ff,
2363 0x2f4 & 0x3ff,
2364 0x2ee & 0x3ff,
2365 0x2e9 & 0x3ff,
2366 0x2e4 & 0x3ff,
2367 0x2df & 0x3ff,
2368 0x2da & 0x3ff,
2369 0x2d5 & 0x3ff,
2370 0x2d0 & 0x3ff,
2371 0x2cb & 0x3ff,
2372 0x2c6 & 0x3ff,
2373 0x2c1 & 0x3ff,
2374 0x2bd & 0x3ff,
2375 0x2b8 & 0x3ff,
2376 0x2b3 & 0x3ff,
2377 0x2ae & 0x3ff,
2378 0x2aa & 0x3ff,
2379 0x2a5 & 0x3ff,
2380 0x2a1 & 0x3ff,
2381 0x29c & 0x3ff,
2382 0x298 & 0x3ff,
2383 0x293 & 0x3ff,
2384 0x28f & 0x3ff,
2385 0x28a & 0x3ff,
2386 0x286 & 0x3ff,
2387 0x282 & 0x3ff,
2388 0x27d & 0x3ff,
2389 0x279 & 0x3ff,
2390 0x275 & 0x3ff,
2391 0x271 & 0x3ff,
2392 0x26d & 0x3ff,
2393 0x268 & 0x3ff,
2394 0x264 & 0x3ff,
2395 0x260 & 0x3ff,
2396 0x25c & 0x3ff,
2397 0x258 & 0x3ff,
2398 0x254 & 0x3ff,
2399 0x250 & 0x3ff,
2400 0x24c & 0x3ff,
2401 0x249 & 0x3ff,
2402 0x245 & 0x3ff,
2403 0x241 & 0x3ff,
2404 0x23d & 0x3ff,
2405 0x239 & 0x3ff,
2406 0x235 & 0x3ff,
2407 0x232 & 0x3ff,
2408 0x22e & 0x3ff,
2409 0x22a & 0x3ff,
2410 0x227 & 0x3ff,
2411 0x223 & 0x3ff,
2412 0x220 & 0x3ff,
2413 0x21c & 0x3ff,
2414 0x218 & 0x3ff,
2415 0x215 & 0x3ff,
2416 0x211 & 0x3ff,
2417 0x20e & 0x3ff,
2418 0x20a & 0x3ff,
2419 0x207 & 0x3ff,
2420 0x204 & 0x3ff,
2421 0x200 & 0x3ff,
2422 0x1fd & 0x3ff,
2423 0x1f9 & 0x3ff,
2424 0x1f6 & 0x3ff,
2425 0x1f3 & 0x3ff,
2426 0x1f0 & 0x3ff,
2427 0x1ec & 0x3ff,
2428 0x1e9 & 0x3ff,
2429 0x1e6 & 0x3ff,
2430 0x1e3 & 0x3ff,
2431 0x1df & 0x3ff,
2432 0x1dc & 0x3ff,
2433 0x1d9 & 0x3ff,
2434 0x1d6 & 0x3ff,
2435 0x1d3 & 0x3ff,
2436 0x1d0 & 0x3ff,
2437 0x1cd & 0x3ff,
2438 0x1ca & 0x3ff,
2439 0x1c7 & 0x3ff,
2440 0x1c4 & 0x3ff,
2441 0x1c1 & 0x3ff,
2442 0x1be & 0x3ff,
2443 0x1bb & 0x3ff,
2444 0x1b8 & 0x3ff,
2445 0x1b5 & 0x3ff,
2446 0x1b2 & 0x3ff,
2447 0x1af & 0x3ff,
2448 0x1ac & 0x3ff,
2449 0x1aa & 0x3ff,
2450 0
2455 0x3fc & 0x3ff,
2456 0x3f4 & 0x3ff,
2457 0x3ec & 0x3ff,
2458 0x3e4 & 0x3ff,
2459 0x3dd & 0x3ff,
2460 0x3d5 & 0x3ff,
2461 0x3cd & 0x3ff,
2462 0x3c6 & 0x3ff,
2463 0x3be & 0x3ff,
2464 0x3b7 & 0x3ff,
2465 0x3af & 0x3ff,
2466 0x3a8 & 0x3ff,
2467 0x3a1 & 0x3ff,
2468 0x399 & 0x3ff,
2469 0x392 & 0x3ff,
2470 0x38b & 0x3ff,
2471 0x384 & 0x3ff,
2472 0x37d & 0x3ff,
2473 0x376 & 0x3ff,
2474 0x36f & 0x3ff,
2475 0x368 & 0x3ff,
2476 0x361 & 0x3ff,
2477 0x35b & 0x3ff,
2478 0x354 & 0x3ff,
2479 0x34d & 0x3ff,
2480 0x346 & 0x3ff,
2481 0x340 & 0x3ff,
2482 0x339 & 0x3ff,
2483 0x333 & 0x3ff,
2484 0x32c & 0x3ff,
2485 0x326 & 0x3ff,
2486 0x320 & 0x3ff,
2487 0x319 & 0x3ff,
2488 0x313 & 0x3ff,
2489 0x30d & 0x3ff,
2490 0x307 & 0x3ff,
2491 0x300 & 0x3ff,
2492 0x2fa & 0x3ff,
2493 0x2f4 & 0x3ff,
2494 0x2ee & 0x3ff,
2495 0x2e8 & 0x3ff,
2496 0x2e2 & 0x3ff,
2497 0x2dc & 0x3ff,
2498 0x2d7 & 0x3ff,
2499 0x2d1 & 0x3ff,
2500 0x2cb & 0x3ff,
2501 0x2c5 & 0x3ff,
2502 0x2bf & 0x3ff,
2503 0x2ba & 0x3ff,
2504 0x2b4 & 0x3ff,
2505 0x2af & 0x3ff,
2506 0x2a9 & 0x3ff,
2507 0x2a3 & 0x3ff,
2508 0x29e & 0x3ff,
2509 0x299 & 0x3ff,
2510 0x293 & 0x3ff,
2511 0x28e & 0x3ff,
2512 0x288 & 0x3ff,
2513 0x283 & 0x3ff,
2514 0x27e & 0x3ff,
2515 0x279 & 0x3ff,
2516 0x273 & 0x3ff,
2517 0x26e & 0x3ff,
2518 0x269 & 0x3ff,
2519 0x264 & 0x3ff,
2520 0x25f & 0x3ff,
2521 0x25a & 0x3ff,
2522 0x255 & 0x3ff,
2523 0x250 & 0x3ff,
2524 0x24b & 0x3ff,
2525 0x246 & 0x3ff,
2526 0x241 & 0x3ff,
2527 0x23c & 0x3ff,
2528 0x237 & 0x3ff,
2529 0x232 & 0x3ff,
2530 0x22e & 0x3ff,
2531 0x229 & 0x3ff,
2532 0x224 & 0x3ff,
2533 0x21f & 0x3ff,
2534 0x21b & 0x3ff,
2535 0x216 & 0x3ff,
2536 0x211 & 0x3ff,
2537 0x20d & 0x3ff,
2538 0x208 & 0x3ff,
2539 0x204 & 0x3ff,
2540 0x1ff & 0x3ff,
2541 0x1fb & 0x3ff,
2542 0x1f6 & 0x3ff,
2543 0x1f2 & 0x3ff,
2544 0x1ed & 0x3ff,
2545 0x1e9 & 0x3ff,
2546 0x1e5 & 0x3ff,
2547 0x1e0 & 0x3ff,
2548 0x1dc & 0x3ff,
2549 0x1d8 & 0x3ff,
2550 0x1d4 & 0x3ff,
2551 0x1cf & 0x3ff,
2552 0x1cb & 0x3ff,
2553 0x1c7 & 0x3ff,
2554 0x1c3 & 0x3ff,
2555 0x1bf & 0x3ff,
2556 0x1bb & 0x3ff,
2557 0x1b6 & 0x3ff,
2558 0x1b2 & 0x3ff,
2559 0x1ae & 0x3ff,
2560 0x1aa & 0x3ff,
2561 0x1a6 & 0x3ff,
2562 0x1a2 & 0x3ff,
2563 0x19e & 0x3ff,
2564 0x19a & 0x3ff,
2565 0x197 & 0x3ff,
2566 0x193 & 0x3ff,
2567 0x18f & 0x3ff,
2568 0x18b & 0x3ff,
2569 0x187 & 0x3ff,
2570 0x183 & 0x3ff,
2571 0x17f & 0x3ff,
2572 0x17c & 0x3ff,
2573 0x178 & 0x3ff,
2574 0x174 & 0x3ff,
2575 0x171 & 0x3ff,
2576 0x16d & 0x3ff,
2577 0x169 & 0x3ff,
2578 0x166 & 0x3ff,
2579 0x162 & 0x3ff,
2580 0x15e & 0x3ff,
2581 0x15b & 0x3ff,
2582 0x157 & 0x3ff,
2583 0x154 & 0x3ff,
2584 0x150 & 0x3ff,
2585 0x14d & 0x3ff,
2586 0x149 & 0x3ff,
2587 0x146 & 0x3ff,
2588 0x142 & 0x3ff,
2589 0x13f & 0x3ff,
2590 0x13b & 0x3ff,
2591 0x138 & 0x3ff,
2592 0x134 & 0x3ff,
2593 0x131 & 0x3ff,
2594 0x12e & 0x3ff,
2595 0x12a & 0x3ff,
2596 0x127 & 0x3ff,
2597 0x124 & 0x3ff,
2598 0x120 & 0x3ff,
2599 0x11d & 0x3ff,
2600 0x11a & 0x3ff,
2601 0x117 & 0x3ff,
2602 0x113 & 0x3ff,
2603 0x110 & 0x3ff,
2604 0x10d & 0x3ff,
2605 0x10a & 0x3ff,
2606 0x107 & 0x3ff,
2607 0x103 & 0x3ff,
2608 0x100 & 0x3ff,
2609 0xfd & 0x3ff,
2610 0xfa & 0x3ff,
2611 0xf7 & 0x3ff,
2612 0xf4 & 0x3ff,
2613 0xf1 & 0x3ff,
2614 0xee & 0x3ff,
2615 0xeb & 0x3ff,
2616 0xe8 & 0x3ff,
2617 0xe5 & 0x3ff,
2618 0xe2 & 0x3ff,
2619 0xdf & 0x3ff,
2620 0xdc & 0x3ff,
2621 0xd9 & 0x3ff,
2622 0xd6 & 0x3ff,
2623 0xd3 & 0x3ff,
2624 0xd0 & 0x3ff,
2625 0xcd & 0x3ff,
2626 0xca & 0x3ff,
2627 0xc8 & 0x3ff,
2628 0xc5 & 0x3ff,
2629 0xc2 & 0x3ff,
2630 0xbf & 0x3ff,
2631 0xbc & 0x3ff,
2632 0xb9 & 0x3ff,
2633 0xb7 & 0x3ff,
2634 0xb4 & 0x3ff,
2635 0xb1 & 0x3ff,
2636 0xae & 0x3ff,
2637 0xac & 0x3ff,
2638 0xa9 & 0x3ff,
2639 0xa6 & 0x3ff,
2640 0xa4 & 0x3ff,
2641 0xa1 & 0x3ff,
2642 0x9e & 0x3ff,
2643 0x9c & 0x3ff,
2644 0x99 & 0x3ff,
2645 0x96 & 0x3ff,
2646 0x94 & 0x3ff,
2647 0x91 & 0x3ff,
2648 0x8e & 0x3ff,
2649 0x8c & 0x3ff,
2650 0x89 & 0x3ff,
2651 0x87 & 0x3ff,
2652 0x84 & 0x3ff,
2653 0x82 & 0x3ff,
2654 0x7f & 0x3ff,
2655 0x7c & 0x3ff,
2656 0x7a & 0x3ff,
2657 0x77 & 0x3ff,
2658 0x75 & 0x3ff,
2659 0x73 & 0x3ff,
2660 0x70 & 0x3ff,
2661 0x6e & 0x3ff,
2662 0x6b & 0x3ff,
2663 0x69 & 0x3ff,
2664 0x66 & 0x3ff,
2665 0x64 & 0x3ff,
2666 0x61 & 0x3ff,
2667 0x5f & 0x3ff,
2668 0x5d & 0x3ff,
2669 0x5a & 0x3ff,
2670 0x58 & 0x3ff,
2671 0x56 & 0x3ff,
2672 0x53 & 0x3ff,
2673 0x51 & 0x3ff,
2674 0x4f & 0x3ff,
2675 0x4c & 0x3ff,
2676 0x4a & 0x3ff,
2677 0x48 & 0x3ff,
2678 0x45 & 0x3ff,
2679 0x43 & 0x3ff,
2680 0x41 & 0x3ff,
2681 0x3f & 0x3ff,
2682 0x3c & 0x3ff,
2683 0x3a & 0x3ff,
2684 0x38 & 0x3ff,
2685 0x36 & 0x3ff,
2686 0x33 & 0x3ff,
2687 0x31 & 0x3ff,
2688 0x2f & 0x3ff,
2689 0x2d & 0x3ff,
2690 0x2b & 0x3ff,
2691 0x29 & 0x3ff,
2692 0x26 & 0x3ff,
2693 0x24 & 0x3ff,
2694 0x22 & 0x3ff,
2695 0x20 & 0x3ff,
2696 0x1e & 0x3ff,
2697 0x1c & 0x3ff,
2698 0x1a & 0x3ff,
2699 0x18 & 0x3ff,
2700 0x15 & 0x3ff,
2701 0x13 & 0x3ff,
2702 0x11 & 0x3ff,
2703 0xf & 0x3ff,
2704 0xd & 0x3ff,
2705 0xb & 0x3ff,
2706 0x9 & 0x3ff,
2707 0x7 & 0x3ff,
2708 0x5 & 0x3ff,
2709 0x3 & 0x3ff,
2710 0x1 & 0x3ff,
2711 0
2721 return 0;
2728 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2738 soffsetx4_in_0 = *valp & 0x3ffff;
2739 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
2741 return 0;
2750 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
2752 return 0;
2760 immr_in_0 = *valp & 0xf;
2763 return 0;
2772 immr_in_0 = (immr_out_0 & 0xf);
2774 return 0;
2782 uimm12x8_in_0 = *valp & 0xfff;
2785 return 0;
2794 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
2796 return 0;
2804 simm4_in_0 = *valp & 0xf;
2807 return 0;
2816 simm4_in_0 = (simm4_out_0 & 0xf);
2818 return 0;
2824 return 0;
2838 return 0;
2852 return 0;
2866 return 0;
2880 return 0;
2894 return 0;
2910 immrx4_in_0 = *valp & 0xf;
2911 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
2913 return 0;
2922 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
2924 return 0;
2932 lsi4x4_in_0 = *valp & 0xf;
2935 return 0;
2944 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
2946 return 0;
2954 simm7_in_0 = *valp & 0x7f;
2955 …simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | …
2957 return 0;
2966 simm7_in_0 = (simm7_out_0 & 0x7f);
2968 return 0;
2976 uimm6_in_0 = *valp & 0x3f;
2977 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
2979 return 0;
2988 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
2990 return 0;
2998 ai4const_in_0 = *valp & 0xf;
2999 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
3001 return 0;
3012 case 0xffffffff: ai4const_in_0 = 0; break;
3013 case 0x1: ai4const_in_0 = 0x1; break;
3014 case 0x2: ai4const_in_0 = 0x2; break;
3015 case 0x3: ai4const_in_0 = 0x3; break;
3016 case 0x4: ai4const_in_0 = 0x4; break;
3017 case 0x5: ai4const_in_0 = 0x5; break;
3018 case 0x6: ai4const_in_0 = 0x6; break;
3019 case 0x7: ai4const_in_0 = 0x7; break;
3020 case 0x8: ai4const_in_0 = 0x8; break;
3021 case 0x9: ai4const_in_0 = 0x9; break;
3022 case 0xa: ai4const_in_0 = 0xa; break;
3023 case 0xb: ai4const_in_0 = 0xb; break;
3024 case 0xc: ai4const_in_0 = 0xc; break;
3025 case 0xd: ai4const_in_0 = 0xd; break;
3026 case 0xe: ai4const_in_0 = 0xe; break;
3027 default: ai4const_in_0 = 0xf; break;
3030 return 0;
3038 b4const_in_0 = *valp & 0xf;
3039 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
3041 return 0;
3052 case 0xffffffff: b4const_in_0 = 0; break;
3053 case 0x1: b4const_in_0 = 0x1; break;
3054 case 0x2: b4const_in_0 = 0x2; break;
3055 case 0x3: b4const_in_0 = 0x3; break;
3056 case 0x4: b4const_in_0 = 0x4; break;
3057 case 0x5: b4const_in_0 = 0x5; break;
3058 case 0x6: b4const_in_0 = 0x6; break;
3059 case 0x7: b4const_in_0 = 0x7; break;
3060 case 0x8: b4const_in_0 = 0x8; break;
3061 case 0xa: b4const_in_0 = 0x9; break;
3062 case 0xc: b4const_in_0 = 0xa; break;
3063 case 0x10: b4const_in_0 = 0xb; break;
3064 case 0x20: b4const_in_0 = 0xc; break;
3065 case 0x40: b4const_in_0 = 0xd; break;
3066 case 0x80: b4const_in_0 = 0xe; break;
3067 default: b4const_in_0 = 0xf; break;
3070 return 0;
3078 b4constu_in_0 = *valp & 0xf;
3079 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
3081 return 0;
3092 case 0x8000: b4constu_in_0 = 0; break;
3093 case 0x10000: b4constu_in_0 = 0x1; break;
3094 case 0x2: b4constu_in_0 = 0x2; break;
3095 case 0x3: b4constu_in_0 = 0x3; break;
3096 case 0x4: b4constu_in_0 = 0x4; break;
3097 case 0x5: b4constu_in_0 = 0x5; break;
3098 case 0x6: b4constu_in_0 = 0x6; break;
3099 case 0x7: b4constu_in_0 = 0x7; break;
3100 case 0x8: b4constu_in_0 = 0x8; break;
3101 case 0xa: b4constu_in_0 = 0x9; break;
3102 case 0xc: b4constu_in_0 = 0xa; break;
3103 case 0x10: b4constu_in_0 = 0xb; break;
3104 case 0x20: b4constu_in_0 = 0xc; break;
3105 case 0x40: b4constu_in_0 = 0xd; break;
3106 case 0x80: b4constu_in_0 = 0xe; break;
3107 default: b4constu_in_0 = 0xf; break;
3110 return 0;
3118 immt_in_0 = *valp & 0xf;
3121 return 0;
3130 immt_in_0 = immt_out_0 & 0xf;
3132 return 0;
3140 uimms8_in_0 = *valp & 0x7;
3143 return 0;
3152 uimms8_in_0 = uimms8_out_0 & 0x7;
3154 return 0;
3162 uimm8_in_0 = *valp & 0xff;
3165 return 0;
3174 uimm8_in_0 = (uimm8_out_0 & 0xff);
3176 return 0;
3184 uimm8x2_in_0 = *valp & 0xff;
3187 return 0;
3196 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
3198 return 0;
3206 uimm8x4_in_0 = *valp & 0xff;
3209 return 0;
3218 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
3220 return 0;
3228 uimm4x16_in_0 = *valp & 0xf;
3231 return 0;
3240 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
3242 return 0;
3250 uimmrx4_in_0 = *valp & 0xf;
3253 return 0;
3262 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
3264 return 0;
3272 simm8_in_0 = *valp & 0xff;
3275 return 0;
3284 simm8_in_0 = (simm8_out_0 & 0xff);
3286 return 0;
3294 simm8x256_in_0 = *valp & 0xff;
3297 return 0;
3306 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
3308 return 0;
3316 simm12b_in_0 = *valp & 0xfff;
3319 return 0;
3328 simm12b_in_0 = (simm12b_out_0 & 0xfff);
3330 return 0;
3338 msalp32_in_0 = *valp & 0x1f;
3339 msalp32_out_0 = 0x20 - msalp32_in_0;
3341 return 0;
3350 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
3352 return 0;
3360 op2p1_in_0 = *valp & 0xf;
3361 op2p1_out_0 = op2p1_in_0 + 0x1;
3363 return 0;
3372 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
3374 return 0;
3382 label8_in_0 = *valp & 0xff;
3383 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
3385 return 0;
3394 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
3396 return 0;
3404 ulabel8_in_0 = *valp & 0xff;
3405 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
3407 return 0;
3416 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
3418 return 0;
3426 label12_in_0 = *valp & 0xfff;
3427 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
3429 return 0;
3438 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
3440 return 0;
3448 soffset_in_0 = *valp & 0x3ffff;
3449 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
3451 return 0;
3460 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
3462 return 0;
3470 uimm16x4_in_0 = *valp & 0xffff;
3471 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
3473 return 0;
3482 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
3484 return 0;
3490 return 0;
3504 return 0;
3518 return 0;
3532 return 0;
3546 return 0;
3560 return 0;
3576 imms_in_0 = *valp & 0xf;
3579 return 0;
3588 imms_in_0 = imms_out_0 & 0xf;
3590 return 0;
3596 return 0;
3611 return 0;
3618 error = (*valp >= 16) || ((*valp & 1) != 0);
3627 return 0;
3634 error = (*valp >= 16) || ((*valp & 3) != 0);
3643 return 0;
3650 error = (*valp >= 16) || ((*valp & 7) != 0);
3659 return 0;
3666 error = (*valp >= 16) || ((*valp & 15) != 0);
3676 tp7_in_0 = *valp & 0xf;
3677 tp7_out_0 = tp7_in_0 + 0x7;
3679 return 0;
3688 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
3690 return 0;
3698 xt_wbr15_label_in_0 = *valp & 0x7fff;
3699 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
3701 return 0;
3710 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
3712 return 0;
3720 xt_wbr18_label_in_0 = *valp & 0x3ffff;
3721 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
3723 return 0;
3732 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
3734 return 0;
3740 return 0;
3756 imm_t_in_0 = *valp & 0xf;
3757 imm_t_out_0 = (0 << 4) | imm_t_in_0;
3759 return 0;
3768 imm_t_in_0 = (imm_t_out_0 & 0xf);
3770 return 0;
3778 imm8x4_in_0 = *valp & 0xff;
3779 imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0;
3781 return 0;
3790 imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff);
3792 return 0;
3800 imm8x8_in_0 = *valp & 0xff;
3801 imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0;
3803 return 0;
3812 imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff);
3814 return 0;
3822 bbi_in_0 = *valp & 0x1f;
3823 bbi_out_0 = (0 << 5) | bbi_in_0;
3825 return 0;
3834 bbi_in_0 = (bbi_out_0 & 0x1f);
3836 return 0;
3844 s_in_0 = *valp & 0xf;
3845 s_out_0 = (0 << 4) | s_in_0;
3847 return 0;
3856 s_in_0 = (s_out_0 & 0xf);
3858 return 0;
3866 bitindex_in_0 = *valp & 0x1f;
3867 bitindex_out_0 = (0 << 5) | bitindex_in_0;
3869 return 0;
3878 bitindex_in_0 = (bitindex_out_0 & 0x1f);
3880 return 0;
3886 *valp -= (pc & ~0x3);
3887 return 0;
3893 *valp += (pc & ~0x3);
3894 return 0;
3901 return 0;
3908 return 0;
3915 return 0;
3922 return 0;
3929 return 0;
3936 return 0;
3943 return 0;
3950 return 0;
3957 return 0;
3964 return 0;
3970 *valp -= ((pc + 3) & ~0x3);
3971 return 0;
3977 *valp += ((pc + 3) & ~0x3);
3978 return 0;
3985 return 0;
3992 return 0;
3999 return 0;
4006 return 0;
4010 { "soffsetx4", FIELD_offset, -1, 0,
4014 { "immr", FIELD_r, -1, 0,
4015 0,
4017 0, 0 },
4018 { "uimm12x8", FIELD_imm12, -1, 0,
4019 0,
4021 0, 0 },
4022 { "simm4", FIELD_mn, -1, 0,
4023 0,
4025 0, 0 },
4029 0, 0 },
4033 0, 0 },
4037 0, 0 },
4041 0, 0 },
4045 0, 0 },
4049 0, 0 },
4053 0, 0 },
4057 0, 0 },
4061 0, 0 },
4062 { "immrx4", FIELD_r, -1, 0,
4063 0,
4065 0, 0 },
4066 { "lsi4x4", FIELD_r, -1, 0,
4067 0,
4069 0, 0 },
4070 { "simm7", FIELD_imm7, -1, 0,
4071 0,
4073 0, 0 },
4074 { "uimm6", FIELD_imm6, -1, 0,
4078 { "ai4const", FIELD_t, -1, 0,
4079 0,
4081 0, 0 },
4082 { "b4const", FIELD_r, -1, 0,
4083 0,
4085 0, 0 },
4086 { "b4constu", FIELD_r, -1, 0,
4087 0,
4089 0, 0 },
4090 { "immt", FIELD_t, -1, 0,
4091 0,
4093 0, 0 },
4094 { "uimms8", FIELD_imms8, -1, 0,
4095 0,
4097 0, 0 },
4098 { "uimm8", FIELD_imm8, -1, 0,
4099 0,
4101 0, 0 },
4102 { "uimm8x2", FIELD_imm8, -1, 0,
4103 0,
4105 0, 0 },
4106 { "uimm8x4", FIELD_imm8, -1, 0,
4107 0,
4109 0, 0 },
4110 { "uimm4x16", FIELD_op2, -1, 0,
4111 0,
4113 0, 0 },
4114 { "uimmrx4", FIELD_r, -1, 0,
4115 0,
4117 0, 0 },
4118 { "simm8", FIELD_imm8, -1, 0,
4119 0,
4121 0, 0 },
4122 { "simm8x256", FIELD_imm8, -1, 0,
4123 0,
4125 0, 0 },
4126 { "simm12b", FIELD_imm12b, -1, 0,
4127 0,
4129 0, 0 },
4130 { "msalp32", FIELD_sal, -1, 0,
4131 0,
4133 0, 0 },
4134 { "op2p1", FIELD_op2, -1, 0,
4135 0,
4137 0, 0 },
4138 { "label8", FIELD_imm8, -1, 0,
4142 { "ulabel8", FIELD_imm8, -1, 0,
4146 { "label12", FIELD_imm12, -1, 0,
4150 { "soffset", FIELD_offset, -1, 0,
4154 { "uimm16x4", FIELD_imm16, -1, 0,
4161 0, 0 },
4165 0, 0 },
4169 0, 0 },
4173 0, 0 },
4177 0, 0 },
4181 0, 0 },
4185 0, 0 },
4186 { "imms", FIELD_s, -1, 0,
4187 0,
4189 0, 0 },
4190 { "imms1", FIELD_s, -1, 0,
4191 0,
4193 0, 0 },
4197 0, 0 },
4201 0, 0 },
4205 0, 0 },
4209 0, 0 },
4213 0, 0 },
4217 0, 0 },
4221 0, 0 },
4225 0, 0 },
4229 0, 0 },
4233 0, 0 },
4237 0, 0 },
4241 0, 0 },
4245 0, 0 },
4249 0, 0 },
4253 0, 0 },
4257 0, 0 },
4258 { "tp7", FIELD_t, -1, 0,
4259 0,
4261 0, 0 },
4262 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
4266 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
4273 0, 0 },
4277 0, 0 },
4281 0, 0 },
4282 { "imm_t", FIELD_t, -1, 0,
4283 0,
4285 0, 0 },
4286 { "imm_s", FIELD_s, -1, 0,
4287 0,
4289 0, 0 },
4290 { "imm8x4", FIELD_imm8, -1, 0,
4291 0,
4293 0, 0 },
4294 { "imm8x8", FIELD_imm8, -1, 0,
4295 0,
4297 0, 0 },
4298 { "bbi", FIELD_bbi, -1, 0,
4299 0,
4301 0, 0 },
4302 { "sae", FIELD_sae, -1, 0,
4303 0,
4305 0, 0 },
4306 { "sas", FIELD_sas, -1, 0,
4307 0,
4309 0, 0 },
4310 { "sargt", FIELD_sargt, -1, 0,
4311 0,
4313 0, 0 },
4314 { "s", FIELD_s, -1, 0,
4315 0,
4317 0, 0 },
4318 { "bitindex", FIELD_bitindex, -1, 0,
4319 0,
4321 0, 0 },
4322 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
4323 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
4324 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
4325 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
4326 { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
4327 { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 },
4328 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
4329 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
4330 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
4331 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
4332 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
4333 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
4334 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
4335 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
4336 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
4337 { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 },
4338 { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 },
4339 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
4340 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
4341 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
4342 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
4343 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
4344 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
4345 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
4346 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
4347 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
4348 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
4349 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
4350 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
4351 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
4352 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
4353 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
4354 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
4355 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
4356 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
4357 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
4358 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
4359 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
4360 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
4361 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
4362 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
4363 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
4364 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
4365 { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
4366 { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
4367 { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
4368 { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
4369 { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
4370 { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
4371 { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
4372 { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
4373 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
4374 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
4375 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
8634 { 0, 0 /* xt_iclass_excw */,
8635 0, 0, 0, 0 },
8636 { 0, 0 /* xt_iclass_rfe */,
8637 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
8638 { 0, 0 /* xt_iclass_rfde */,
8639 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
8640 { 0, 0 /* xt_iclass_syscall */,
8641 0, 0, 0, 0 },
8643 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
8645 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
8647 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
8649 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
8651 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
8653 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
8655 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
8657 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
8659 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
8661 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
8662 { 0, 0 /* xt_iclass_rfwou */,
8663 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
8665 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
8667 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
8669 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
8671 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
8673 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
8675 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
8677 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
8679 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
8681 0, 0, 0, 0 },
8683 0, 0, 0, 0 },
8685 0, 0, 0, 0 },
8686 { 0, 0 /* xt_iclass_ill_n */,
8687 0, 0, 0, 0 },
8689 0, 0, 0, 0 },
8691 0, 0, 0, 0 },
8693 0, 0, 0, 0 },
8694 { 0, 0 /* xt_iclass_nopn */,
8695 0, 0, 0, 0 },
8697 0, 0, 0, 0 },
8699 0, 0, 0, 0 },
8701 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
8703 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
8705 0, 0, 0, 0 },
8707 0, 0, 0, 0 },
8709 0, 0, 0, 0 },
8711 0, 0, 0, 0 },
8713 0, 0, 0, 0 },
8715 0, 0, 0, 0 },
8717 0, 0, 0, 0 },
8719 0, 0, 0, 0 },
8721 0, 0, 0, 0 },
8723 0, 0, 0, 0 },
8725 0, 0, 0, 0 },
8727 0, 0, 0, 0 },
8728 { 0, 0 /* xt_iclass_ill */,
8729 0, 0, 0, 0 },
8731 0, 0, 0, 0 },
8733 0, 0, 0, 0 },
8735 0, 0, 0, 0 },
8737 0, 0, 0, 0 },
8739 0, 0, 0, 0 },
8741 0, 0, 0, 0 },
8743 0, 0, 0, 0 },
8745 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
8747 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
8749 0, 0, 0, 0 },
8751 0, 0, 0, 0 },
8753 0, 0, 0, 0 },
8754 { 0, 0 /* xt_iclass_nop */,
8755 0, 0, 0, 0 },
8757 0, 0, 0, 0 },
8759 0, 0, 0, 0 },
8761 0, 0, 0, 0 },
8763 0, 0, 0, 0 },
8765 0, 0, 0, 0 },
8767 0, 0, 0, 0 },
8769 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
8771 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
8773 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
8775 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
8777 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
8779 0, 0, 0, 0 },
8781 0, 0, 0, 0 },
8783 0, 0, 0, 0 },
8784 { 0, 0 /* xt_iclass_memw */,
8785 0, 0, 0, 0 },
8786 { 0, 0 /* xt_iclass_extw */,
8787 0, 0, 0, 0 },
8788 { 0, 0 /* xt_iclass_isync */,
8789 0, 0, 0, 0 },
8790 { 0, 0 /* xt_iclass_sync */,
8791 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
8793 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
8795 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
8797 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
8799 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
8801 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
8803 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
8805 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
8807 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
8809 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
8811 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
8813 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
8815 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
8817 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
8819 0, 0, 0, 0 },
8821 0, 0, 0, 0 },
8823 0, 0, 0, 0 },
8825 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
8827 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
8829 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
8831 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
8833 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
8835 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
8837 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
8839 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
8841 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
8843 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
8845 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
8847 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
8849 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
8851 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
8853 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
8855 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
8857 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
8859 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
8861 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
8863 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
8865 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
8867 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
8869 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
8871 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
8873 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
8875 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
8877 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
8879 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
8881 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
8883 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
8885 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
8887 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
8889 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
8891 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
8893 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
8895 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
8897 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
8899 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
8901 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
8903 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
8905 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
8907 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
8909 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
8911 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
8913 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
8915 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
8917 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
8919 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
8921 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
8923 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
8925 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
8927 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
8929 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
8931 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
8933 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
8935 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
8937 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
8939 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
8941 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
8943 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
8945 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
8947 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
8949 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
8951 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
8953 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
8955 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
8957 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
8959 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
8961 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
8963 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
8965 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
8967 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
8969 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
8971 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
8973 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
8975 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
8977 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
8979 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
8981 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
8983 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
8985 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
8987 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
8989 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
8991 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
8993 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
8995 0, 0, 0, 0 },
8997 0, 0, 0, 0 },
8999 0, 0, 0, 0 },
9001 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
9003 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
9005 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
9007 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
9009 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
9011 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
9013 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
9015 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
9017 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
9019 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
9021 0, 0, 0, 0 },
9023 0, 0, 0, 0 },
9025 0, 0, 0, 0 },
9027 0, 0, 0, 0 },
9029 0, 0, 0, 0 },
9031 0, 0, 0, 0 },
9033 0, 0, 0, 0 },
9035 0, 0, 0, 0 },
9037 0, 0, 0, 0 },
9039 0, 0, 0, 0 },
9041 0, 0, 0, 0 },
9043 0, 0, 0, 0 },
9045 0, 0, 0, 0 },
9047 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
9049 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
9051 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
9053 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
9055 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
9057 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
9059 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
9061 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
9063 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
9065 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
9067 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
9069 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
9071 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
9073 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
9075 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
9077 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
9079 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
9081 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
9083 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
9085 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
9087 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
9089 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
9091 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
9093 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
9095 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
9097 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
9099 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
9101 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
9103 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
9105 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
9107 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
9109 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
9111 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
9113 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
9115 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
9117 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
9119 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
9121 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
9123 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
9125 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
9127 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
9129 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
9131 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
9133 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
9135 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
9137 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
9139 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
9141 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
9143 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
9145 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
9147 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
9149 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
9150 { 0, 0 /* xt_iclass_rfdd */,
9151 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
9153 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
9155 0, 0, 0, 0 },
9157 0, 0, 0, 0 },
9159 0, 0, 0, 0 },
9161 0, 0, 0, 0 },
9163 0, 0, 0, 0 },
9165 0, 0, 0, 0 },
9167 0, 0, 0, 0 },
9169 0, 0, 0, 0 },
9171 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
9173 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
9175 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
9177 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
9179 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
9181 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
9183 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
9185 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
9187 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
9189 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
9191 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
9193 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
9195 0, 0, 0, 0 },
9197 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
9199 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
9201 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
9203 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
9205 0, 0, 0, 0 },
9207 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 },
9209 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
9211 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
9213 0, 0, 0, 0 },
9215 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
9217 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
9219 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
9221 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 },
9223 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 },
9225 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
9227 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
9229 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
9231 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
9233 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
9235 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
9237 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
9239 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
9241 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
9243 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
9245 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
9247 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
9249 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
9251 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
9253 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
9255 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
9257 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
9259 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
9260 { 0, 0 /* xt_iclass_ldpte */,
9261 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
9262 { 0, 0 /* xt_iclass_hwwitlba */,
9263 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
9264 { 0, 0 /* xt_iclass_hwwdtlba */,
9265 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
9267 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
9269 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
9271 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
9273 0, 0, 0, 0 },
9275 0, 0, 0, 0 },
9277 0, 0, 0, 0 },
9279 0, 0, 0, 0 },
9281 0, 0, 0, 0 },
9283 0, 0, 0, 0 },
9285 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
9287 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
9289 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
9291 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
9293 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
9295 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
9297 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
9299 0, 0, 0, 0 },
9301 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 },
9303 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 },
9305 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 },
9307 3, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
9309 3, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
9311 9, Iclass_rur_fcr_stateArgs, 0, 0 },
9313 9, Iclass_wur_fcr_stateArgs, 0, 0 },
9315 8, Iclass_rur_fsr_stateArgs, 0, 0 },
9317 8, Iclass_wur_fsr_stateArgs, 0, 0 },
9321 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
9323 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
9325 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 },
9327 2, Iclass_rur_expstate_stateArgs, 0, 0 },
9329 2, Iclass_wur_expstate_stateArgs, 0, 0 },
9331 1, Iclass_LSI_stateArgs, 0, 0 },
9333 1, Iclass_LSIP_stateArgs, 0, 0 },
9335 1, Iclass_LSX_stateArgs, 0, 0 },
9337 1, Iclass_LSXP_stateArgs, 0, 0 },
9339 1, Iclass_SSI_stateArgs, 0, 0 },
9341 1, Iclass_SSIP_stateArgs, 0, 0 },
9343 1, Iclass_SSX_stateArgs, 0, 0 },
9345 1, Iclass_SSXP_stateArgs, 0, 0 },
9347 1, Iclass_LDI_stateArgs, 0, 0 },
9349 1, Iclass_LDIP_stateArgs, 0, 0 },
9351 1, Iclass_LDX_stateArgs, 0, 0 },
9353 1, Iclass_LDXP_stateArgs, 0, 0 },
9355 1, Iclass_SDI_stateArgs, 0, 0 },
9357 1, Iclass_SDIP_stateArgs, 0, 0 },
9359 1, Iclass_SDX_stateArgs, 0, 0 },
9361 1, Iclass_SDXP_stateArgs, 0, 0 },
9363 1, Iclass_ABS_S_stateArgs, 0, 0 },
9365 1, Iclass_NEG_S_stateArgs, 0, 0 },
9367 1, Iclass_ABS_D_stateArgs, 0, 0 },
9369 1, Iclass_NEG_D_stateArgs, 0, 0 },
9371 1, Iclass_MOV_S_stateArgs, 0, 0 },
9373 1, Iclass_MOV_D_stateArgs, 0, 0 },
9375 1, Iclass_MOVEQZ_S_stateArgs, 0, 0 },
9377 1, Iclass_MOVNEZ_S_stateArgs, 0, 0 },
9379 1, Iclass_MOVLTZ_S_stateArgs, 0, 0 },
9381 1, Iclass_MOVGEZ_S_stateArgs, 0, 0 },
9383 1, Iclass_MOVF_S_stateArgs, 0, 0 },
9385 1, Iclass_MOVT_S_stateArgs, 0, 0 },
9387 1, Iclass_WFR_stateArgs, 0, 0 },
9389 1, Iclass_RFR_stateArgs, 0, 0 },
9391 1, Iclass_RFRD_stateArgs, 0, 0 },
9393 1, Iclass_WFRD_stateArgs, 0, 0 },
9395 3, Iclass_ROUND_S_stateArgs, 0, 0 },
9397 3, Iclass_ROUND_D_stateArgs, 0, 0 },
9399 3, Iclass_CEIL_S_stateArgs, 0, 0 },
9401 3, Iclass_CEIL_D_stateArgs, 0, 0 },
9403 3, Iclass_FLOOR_S_stateArgs, 0, 0 },
9405 3, Iclass_FLOOR_D_stateArgs, 0, 0 },
9407 3, Iclass_TRUNC_S_stateArgs, 0, 0 },
9409 3, Iclass_TRUNC_D_stateArgs, 0, 0 },
9411 3, Iclass_UTRUNC_S_stateArgs, 0, 0 },
9413 3, Iclass_UTRUNC_D_stateArgs, 0, 0 },
9415 3, Iclass_FLOAT_S_stateArgs, 0, 0 },
9417 2, Iclass_FLOAT_D_stateArgs, 0, 0 },
9419 3, Iclass_UFLOAT_S_stateArgs, 0, 0 },
9421 2, Iclass_UFLOAT_D_stateArgs, 0, 0 },
9423 2, Iclass_CVTD_S_stateArgs, 0, 0 },
9425 6, Iclass_CVTS_D_stateArgs, 0, 0 },
9427 2, Iclass_UN_S_stateArgs, 0, 0 },
9429 2, Iclass_UN_D_stateArgs, 0, 0 },
9431 2, Iclass_ULT_S_stateArgs, 0, 0 },
9433 2, Iclass_ULT_D_stateArgs, 0, 0 },
9435 2, Iclass_ULE_S_stateArgs, 0, 0 },
9437 2, Iclass_ULE_D_stateArgs, 0, 0 },
9439 2, Iclass_UEQ_S_stateArgs, 0, 0 },
9441 2, Iclass_UEQ_D_stateArgs, 0, 0 },
9443 2, Iclass_OLT_S_stateArgs, 0, 0 },
9445 2, Iclass_OLT_D_stateArgs, 0, 0 },
9447 2, Iclass_OLE_S_stateArgs, 0, 0 },
9449 2, Iclass_OLE_D_stateArgs, 0, 0 },
9451 2, Iclass_OEQ_S_stateArgs, 0, 0 },
9453 2, Iclass_OEQ_D_stateArgs, 0, 0 },
9455 6, Iclass_ADD_S_stateArgs, 0, 0 },
9457 6, Iclass_ADD_D_stateArgs, 0, 0 },
9459 6, Iclass_SUB_S_stateArgs, 0, 0 },
9461 6, Iclass_SUB_D_stateArgs, 0, 0 },
9463 6, Iclass_MUL_S_stateArgs, 0, 0 },
9465 6, Iclass_MUL_D_stateArgs, 0, 0 },
9467 6, Iclass_MADD_S_stateArgs, 0, 0 },
9469 6, Iclass_MADD_D_stateArgs, 0, 0 },
9471 6, Iclass_MSUB_S_stateArgs, 0, 0 },
9473 6, Iclass_MSUB_D_stateArgs, 0, 0 },
9475 1, Iclass_SQRT0_S_stateArgs, 0, 0 },
9477 1, Iclass_SQRT0_D_stateArgs, 0, 0 },
9479 1, Iclass_DIV0_S_stateArgs, 0, 0 },
9481 1, Iclass_DIV0_D_stateArgs, 0, 0 },
9483 3, Iclass_RECIP0_S_stateArgs, 0, 0 },
9485 3, Iclass_RECIP0_D_stateArgs, 0, 0 },
9487 3, Iclass_RSQRT0_S_stateArgs, 0, 0 },
9489 3, Iclass_RSQRT0_D_stateArgs, 0, 0 },
9491 1, Iclass_MADDN_S_stateArgs, 0, 0 },
9493 1, Iclass_MADDN_D_stateArgs, 0, 0 },
9495 5, Iclass_DIVN_S_stateArgs, 0, 0 },
9497 5, Iclass_DIVN_D_stateArgs, 0, 0 },
9499 1, Iclass_CONST_S_stateArgs, 0, 0 },
9501 1, Iclass_CONST_D_stateArgs, 0, 0 },
9503 1, Iclass_NEXP01_S_stateArgs, 0, 0 },
9505 1, Iclass_NEXP01_D_stateArgs, 0, 0 },
9507 1, Iclass_ADDEXP_S_stateArgs, 0, 0 },
9509 1, Iclass_ADDEXP_D_stateArgs, 0, 0 },
9511 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 },
9513 1, Iclass_ADDEXPM_D_stateArgs, 0, 0 },
9515 3, Iclass_MKDADJ_S_stateArgs, 0, 0 },
9517 3, Iclass_MKDADJ_D_stateArgs, 0, 0 },
9519 2, Iclass_MKSADJ_S_stateArgs, 0, 0 },
9521 2, Iclass_MKSADJ_D_stateArgs, 0, 0 }
9977 slotbuf[0] = 0x2080;
9983 slotbuf[0] = 0x3000;
9989 slotbuf[0] = 0x3200;
9995 slotbuf[0] = 0x5000;
10001 slotbuf[0] = 0x35;
10007 slotbuf[0] = 0x25;
10013 slotbuf[0] = 0x15;
10019 slotbuf[0] = 0xf0;
10025 slotbuf[0] = 0xe0;
10031 slotbuf[0] = 0xd0;
10037 slotbuf[0] = 0x36;
10043 slotbuf[0] = 0x1000;
10049 slotbuf[0] = 0x408000;
10055 slotbuf[0] = 0x90;
10061 slotbuf[0] = 0xf01d;
10067 slotbuf[0] = 0x3400;
10073 slotbuf[0] = 0x3500;
10079 slotbuf[0] = 0x90000;
10085 slotbuf[0] = 0x490000;
10091 slotbuf[0] = 0x34800;
10097 slotbuf[0] = 0x134800;
10103 slotbuf[0] = 0x614800;
10109 slotbuf[0] = 0x34900;
10115 slotbuf[0] = 0x134900;
10121 slotbuf[0] = 0x614900;
10127 slotbuf[0] = 0xa;
10133 slotbuf[0] = 0xb;
10139 slotbuf[0] = 0x8c;
10145 slotbuf[0] = 0xcc;
10151 slotbuf[0] = 0xf06d;
10157 slotbuf[0] = 0x8;
10163 slotbuf[0] = 0xd;
10169 slotbuf[0] = 0xc;
10175 slotbuf[0] = 0xf03d;
10181 slotbuf[0] = 0xf00d;
10187 slotbuf[0] = 0x9;
10193 slotbuf[0] = 0xe30e70;
10199 slotbuf[0] = 0xf3e700;
10205 slotbuf[0] = 0xc002;
10211 slotbuf[0] = 0xd002;
10217 slotbuf[0] = 0x800000;
10223 slotbuf[0] = 0x900000;
10229 slotbuf[0] = 0xa00000;
10235 slotbuf[0] = 0xb00000;
10241 slotbuf[0] = 0xc00000;
10247 slotbuf[0] = 0xd00000;
10253 slotbuf[0] = 0xe00000;
10259 slotbuf[0] = 0xf00000;
10265 slotbuf[0] = 0x100000;
10271 slotbuf[0] = 0x200000;
10277 slotbuf[0] = 0x300000;
10283 slotbuf[0] = 0x26;
10289 slotbuf[0] = 0xe6;
10295 slotbuf[0] = 0xa6;
10301 slotbuf[0] = 0x66;
10307 slotbuf[0] = 0x6007;
10313 slotbuf[0] = 0xe007;
10319 slotbuf[0] = 0xf6;
10325 slotbuf[0] = 0xb6;
10331 slotbuf[0] = 0x4007;
10337 slotbuf[0] = 0x8007;
10343 slotbuf[0] = 0x5007;
10349 slotbuf[0] = 0xd007;
10355 slotbuf[0] = 0x1007;
10361 slotbuf[0] = 0xa007;
10367 slotbuf[0] = 0xb007;
10373 slotbuf[0] = 0x2007;
10379 slotbuf[0] = 0x3007;
10385 slotbuf[0] = 0xc007;
10391 slotbuf[0] = 0x9007;
10397 slotbuf[0] = 0x7;
10403 slotbuf[0] = 0x16;
10409 slotbuf[0] = 0xd6;
10415 slotbuf[0] = 0x96;
10421 slotbuf[0] = 0x56;
10427 slotbuf[0] = 0x5;
10433 slotbuf[0] = 0xc0;
10439 slotbuf[0] = 0x40000;
10445 slotbuf[0] = 0;
10451 slotbuf[0] = 0x6;
10457 slotbuf[0] = 0xa0;
10463 slotbuf[0] = 0x1002;
10469 slotbuf[0] = 0x9002;
10475 slotbuf[0] = 0x2002;
10481 slotbuf[0] = 0x1;
10487 slotbuf[0] = 0x2;
10493 slotbuf[0] = 0x8076;
10499 slotbuf[0] = 0xa076;
10505 slotbuf[0] = 0x9076;
10511 slotbuf[0] = 0xa002;
10517 slotbuf[0] = 0x830000;
10523 slotbuf[0] = 0xb30000;
10529 slotbuf[0] = 0xa30000;
10535 slotbuf[0] = 0x930000;
10541 slotbuf[0] = 0x600100;
10547 slotbuf[0] = 0x600000;
10553 slotbuf[0] = 0x20f0;
10559 slotbuf[0] = 0x80;
10565 slotbuf[0] = 0x5100;
10571 slotbuf[0] = 0x5002;
10577 slotbuf[0] = 0x6002;
10583 slotbuf[0] = 0x590000;
10589 slotbuf[0] = 0x4002;
10595 slotbuf[0] = 0x403000;
10601 slotbuf[0] = 0x402000;
10607 slotbuf[0] = 0x401000;
10613 slotbuf[0] = 0x400000;
10619 slotbuf[0] = 0x404000;
10625 slotbuf[0] = 0xa10000;
10631 slotbuf[0] = 0x810000;
10637 slotbuf[0] = 0xb10000;
10643 slotbuf[0] = 0x910000;
10649 slotbuf[0] = 0x10000;
10655 slotbuf[0] = 0x210000;
10661 slotbuf[0] = 0x410000;
10667 slotbuf[0] = 0x20c0;
10673 slotbuf[0] = 0x20d0;
10679 slotbuf[0] = 0x2000;
10685 slotbuf[0] = 0x2030;
10691 slotbuf[0] = 0x2020;
10697 slotbuf[0] = 0x2010;
10703 slotbuf[0] = 0x6000;
10709 slotbuf[0] = 0x30100;
10715 slotbuf[0] = 0x130100;
10721 slotbuf[0] = 0x610100;
10727 slotbuf[0] = 0x30200;
10733 slotbuf[0] = 0x130200;
10739 slotbuf[0] = 0x610200;
10745 slotbuf[0] = 0x30000;
10751 slotbuf[0] = 0x130000;
10757 slotbuf[0] = 0x610000;
10763 slotbuf[0] = 0x30300;
10769 slotbuf[0] = 0x130300;
10775 slotbuf[0] = 0x610300;
10781 slotbuf[0] = 0x36100;
10787 slotbuf[0] = 0x136100;
10793 slotbuf[0] = 0x616100;
10799 slotbuf[0] = 0x3b000;
10805 slotbuf[0] = 0x13b000;
10811 slotbuf[0] = 0x3d000;
10817 slotbuf[0] = 0x3e600;
10823 slotbuf[0] = 0x13e600;
10829 slotbuf[0] = 0x61e600;
10835 slotbuf[0] = 0x3b100;
10841 slotbuf[0] = 0x13b100;
10847 slotbuf[0] = 0x61b100;
10853 slotbuf[0] = 0x3d100;
10859 slotbuf[0] = 0x13d100;
10865 slotbuf[0] = 0x61d100;
10871 slotbuf[0] = 0x3b200;
10877 slotbuf[0] = 0x13b200;
10883 slotbuf[0] = 0x61b200;
10889 slotbuf[0] = 0x3d200;
10895 slotbuf[0] = 0x13d200;
10901 slotbuf[0] = 0x61d200;
10907 slotbuf[0] = 0x3b300;
10913 slotbuf[0] = 0x13b300;
10919 slotbuf[0] = 0x61b300;
10925 slotbuf[0] = 0x3d300;
10931 slotbuf[0] = 0x13d300;
10937 slotbuf[0] = 0x61d300;
10943 slotbuf[0] = 0x3b400;
10949 slotbuf[0] = 0x13b400;
10955 slotbuf[0] = 0x61b400;
10961 slotbuf[0] = 0x3d400;
10967 slotbuf[0] = 0x13d400;
10973 slotbuf[0] = 0x61d400;
10979 slotbuf[0] = 0x3b500;
10985 slotbuf[0] = 0x13b500;
10991 slotbuf[0] = 0x61b500;
10997 slotbuf[0] = 0x3d500;
11003 slotbuf[0] = 0x13d500;
11009 slotbuf[0] = 0x61d500;
11015 slotbuf[0] = 0x3b600;
11021 slotbuf[0] = 0x13b600;
11027 slotbuf[0] = 0x61b600;
11033 slotbuf[0] = 0x3d600;
11039 slotbuf[0] = 0x13d600;
11045 slotbuf[0] = 0x61d600;
11051 slotbuf[0] = 0x3b700;
11057 slotbuf[0] = 0x13b700;
11063 slotbuf[0] = 0x61b700;
11069 slotbuf[0] = 0x3d700;
11075 slotbuf[0] = 0x13d700;
11081 slotbuf[0] = 0x61d700;
11087 slotbuf[0] = 0x3c200;
11093 slotbuf[0] = 0x13c200;
11099 slotbuf[0] = 0x61c200;
11105 slotbuf[0] = 0x3c300;
11111 slotbuf[0] = 0x13c300;
11117 slotbuf[0] = 0x61c300;
11123 slotbuf[0] = 0x3c400;
11129 slotbuf[0] = 0x13c400;
11135 slotbuf[0] = 0x61c400;
11141 slotbuf[0] = 0x3c500;
11147 slotbuf[0] = 0x13c500;
11153 slotbuf[0] = 0x61c500;
11159 slotbuf[0] = 0x3c600;
11165 slotbuf[0] = 0x13c600;
11171 slotbuf[0] = 0x61c600;
11177 slotbuf[0] = 0x3c700;
11183 slotbuf[0] = 0x13c700;
11189 slotbuf[0] = 0x61c700;
11195 slotbuf[0] = 0x3ee00;
11201 slotbuf[0] = 0x13ee00;
11207 slotbuf[0] = 0x61ee00;
11213 slotbuf[0] = 0x3c000;
11219 slotbuf[0] = 0x13c000;
11225 slotbuf[0] = 0x61c000;
11231 slotbuf[0] = 0x3e800;
11237 slotbuf[0] = 0x13e800;
11243 slotbuf[0] = 0x61e800;
11249 slotbuf[0] = 0x3f400;
11255 slotbuf[0] = 0x13f400;
11261 slotbuf[0] = 0x61f400;
11267 slotbuf[0] = 0x3f500;
11273 slotbuf[0] = 0x13f500;
11279 slotbuf[0] = 0x61f500;
11285 slotbuf[0] = 0x3eb00;
11291 slotbuf[0] = 0x3e700;
11297 slotbuf[0] = 0x13e700;
11303 slotbuf[0] = 0x61e700;
11309 slotbuf[0] = 0x720000;
11315 slotbuf[0] = 0x620000;
11321 slotbuf[0] = 0xd10000;
11327 slotbuf[0] = 0xc10000;
11333 slotbuf[0] = 0x820000;
11339 slotbuf[0] = 0x770004;
11345 slotbuf[0] = 0x750004;
11351 slotbuf[0] = 0x760004;
11357 slotbuf[0] = 0x740004;
11363 slotbuf[0] = 0x730004;
11369 slotbuf[0] = 0x710004;
11375 slotbuf[0] = 0x720004;
11381 slotbuf[0] = 0x700004;
11387 slotbuf[0] = 0x370004;
11393 slotbuf[0] = 0x350004;
11399 slotbuf[0] = 0x360004;
11405 slotbuf[0] = 0x340004;
11411 slotbuf[0] = 0x670004;
11417 slotbuf[0] = 0x650004;
11423 slotbuf[0] = 0x660004;
11429 slotbuf[0] = 0x640004;
11435 slotbuf[0] = 0x270004;
11441 slotbuf[0] = 0x250004;
11447 slotbuf[0] = 0x260004;
11453 slotbuf[0] = 0x240004;
11459 slotbuf[0] = 0x7b0004;
11465 slotbuf[0] = 0x790004;
11471 slotbuf[0] = 0x7a0004;
11477 slotbuf[0] = 0x780004;
11483 slotbuf[0] = 0x7f0004;
11489 slotbuf[0] = 0x7d0004;
11495 slotbuf[0] = 0x7e0004;
11501 slotbuf[0] = 0x7c0004;
11507 slotbuf[0] = 0x3b0004;
11513 slotbuf[0] = 0x390004;
11519 slotbuf[0] = 0x3a0004;
11525 slotbuf[0] = 0x380004;
11531 slotbuf[0] = 0x3f0004;
11537 slotbuf[0] = 0x3d0004;
11543 slotbuf[0] = 0x3e0004;
11549 slotbuf[0] = 0x3c0004;
11555 slotbuf[0] = 0x6b0004;
11561 slotbuf[0] = 0x690004;
11567 slotbuf[0] = 0x6a0004;
11573 slotbuf[0] = 0x680004;
11579 slotbuf[0] = 0x6f0004;
11585 slotbuf[0] = 0x6d0004;
11591 slotbuf[0] = 0x6e0004;
11597 slotbuf[0] = 0x6c0004;
11603 slotbuf[0] = 0x2b0004;
11609 slotbuf[0] = 0x290004;
11615 slotbuf[0] = 0x2a0004;
11621 slotbuf[0] = 0x280004;
11627 slotbuf[0] = 0x2f0004;
11633 slotbuf[0] = 0x2d0004;
11639 slotbuf[0] = 0x2e0004;
11645 slotbuf[0] = 0x2c0004;
11651 slotbuf[0] = 0x5b0004;
11657 slotbuf[0] = 0x4b0004;
11663 slotbuf[0] = 0x590004;
11669 slotbuf[0] = 0x490004;
11675 slotbuf[0] = 0x5a0004;
11681 slotbuf[0] = 0x4a0004;
11687 slotbuf[0] = 0x580004;
11693 slotbuf[0] = 0x480004;
11699 slotbuf[0] = 0x1b0004;
11705 slotbuf[0] = 0xb0004;
11711 slotbuf[0] = 0x190004;
11717 slotbuf[0] = 0x90004;
11723 slotbuf[0] = 0x1a0004;
11729 slotbuf[0] = 0xa0004;
11735 slotbuf[0] = 0x180004;
11741 slotbuf[0] = 0x80004;
11747 slotbuf[0] = 0x900004;
11753 slotbuf[0] = 0x800004;
11759 slotbuf[0] = 0x32000;
11765 slotbuf[0] = 0x132000;
11771 slotbuf[0] = 0x612000;
11777 slotbuf[0] = 0x32100;
11783 slotbuf[0] = 0x132100;
11789 slotbuf[0] = 0x612100;
11795 slotbuf[0] = 0x32200;
11801 slotbuf[0] = 0x132200;
11807 slotbuf[0] = 0x612200;
11813 slotbuf[0] = 0x32300;
11819 slotbuf[0] = 0x132300;
11825 slotbuf[0] = 0x612300;
11831 slotbuf[0] = 0x31000;
11837 slotbuf[0] = 0x131000;
11843 slotbuf[0] = 0x611000;
11849 slotbuf[0] = 0x31100;
11855 slotbuf[0] = 0x131100;
11861 slotbuf[0] = 0x611100;
11867 slotbuf[0] = 0x3010;
11873 slotbuf[0] = 0x7000;
11879 slotbuf[0] = 0x3e200;
11885 slotbuf[0] = 0x13e200;
11891 slotbuf[0] = 0x13e300;
11897 slotbuf[0] = 0x3e400;
11903 slotbuf[0] = 0x13e400;
11909 slotbuf[0] = 0x61e400;
11915 slotbuf[0] = 0x4000;
11921 slotbuf[0] = 0xf02d;
11927 slotbuf[0] = 0x39000;
11933 slotbuf[0] = 0x139000;
11939 slotbuf[0] = 0x619000;
11945 slotbuf[0] = 0x3a000;
11951 slotbuf[0] = 0x13a000;
11957 slotbuf[0] = 0x61a000;
11963 slotbuf[0] = 0x39100;
11969 slotbuf[0] = 0x139100;
11975 slotbuf[0] = 0x619100;
11981 slotbuf[0] = 0x3a100;
11987 slotbuf[0] = 0x13a100;
11993 slotbuf[0] = 0x61a100;
11999 slotbuf[0] = 0x38000;
12005 slotbuf[0] = 0x138000;
12011 slotbuf[0] = 0x618000;
12017 slotbuf[0] = 0x38100;
12023 slotbuf[0] = 0x138100;
12029 slotbuf[0] = 0x618100;
12035 slotbuf[0] = 0x36000;
12041 slotbuf[0] = 0x136000;
12047 slotbuf[0] = 0x616000;
12053 slotbuf[0] = 0x3e900;
12059 slotbuf[0] = 0x13e900;
12065 slotbuf[0] = 0x61e900;
12071 slotbuf[0] = 0x3ec00;
12077 slotbuf[0] = 0x13ec00;
12083 slotbuf[0] = 0x61ec00;
12089 slotbuf[0] = 0x3ed00;
12095 slotbuf[0] = 0x13ed00;
12101 slotbuf[0] = 0x61ed00;
12107 slotbuf[0] = 0x36800;
12113 slotbuf[0] = 0x136800;
12119 slotbuf[0] = 0x616800;
12125 slotbuf[0] = 0x70e0;
12131 slotbuf[0] = 0x70f0;
12137 slotbuf[0] = 0xf1e000;
12143 slotbuf[0] = 0xf1e010;
12149 slotbuf[0] = 0x135900;
12155 slotbuf[0] = 0x20000;
12161 slotbuf[0] = 0x120000;
12167 slotbuf[0] = 0x220000;
12173 slotbuf[0] = 0x320000;
12179 slotbuf[0] = 0x420000;
12185 slotbuf[0] = 0x9000;
12191 slotbuf[0] = 0x8000;
12197 slotbuf[0] = 0xb000;
12203 slotbuf[0] = 0xa000;
12209 slotbuf[0] = 0x76;
12215 slotbuf[0] = 0x1076;
12221 slotbuf[0] = 0xc30000;
12227 slotbuf[0] = 0xd30000;
12233 slotbuf[0] = 0x30400;
12239 slotbuf[0] = 0x130400;
12245 slotbuf[0] = 0x610400;
12251 slotbuf[0] = 0x3ea00;
12257 slotbuf[0] = 0x13ea00;
12263 slotbuf[0] = 0x61ea00;
12269 slotbuf[0] = 0x3f000;
12275 slotbuf[0] = 0x13f000;
12281 slotbuf[0] = 0x61f000;
12287 slotbuf[0] = 0x3f100;
12293 slotbuf[0] = 0x13f100;
12299 slotbuf[0] = 0x61f100;
12305 slotbuf[0] = 0x3f200;
12311 slotbuf[0] = 0x13f200;
12317 slotbuf[0] = 0x61f200;
12323 slotbuf[0] = 0x70e2;
12329 slotbuf[0] = 0x70c2;
12335 slotbuf[0] = 0x270d2;
12341 slotbuf[0] = 0x370d2;
12347 slotbuf[0] = 0x70d2;
12353 slotbuf[0] = 0x70f2;
12359 slotbuf[0] = 0xf10000;
12365 slotbuf[0] = 0xf12000;
12371 slotbuf[0] = 0xf11000;
12377 slotbuf[0] = 0xf13000;
12383 slotbuf[0] = 0x7042;
12389 slotbuf[0] = 0x7052;
12395 slotbuf[0] = 0xf7082;
12401 slotbuf[0] = 0x47082;
12407 slotbuf[0] = 0x57082;
12413 slotbuf[0] = 0x7062;
12419 slotbuf[0] = 0x7072;
12425 slotbuf[0] = 0x7002;
12431 slotbuf[0] = 0x7022;
12437 slotbuf[0] = 0x7012;
12443 slotbuf[0] = 0x7032;
12449 slotbuf[0] = 0x27082;
12455 slotbuf[0] = 0x37082;
12461 slotbuf[0] = 0x7082;
12467 slotbuf[0] = 0xf19000;
12473 slotbuf[0] = 0xf18000;
12479 slotbuf[0] = 0xf1b000;
12485 slotbuf[0] = 0xf1a000;
12491 slotbuf[0] = 0x135300;
12497 slotbuf[0] = 0x35300;
12503 slotbuf[0] = 0x615300;
12509 slotbuf[0] = 0x35a00;
12515 slotbuf[0] = 0x135a00;
12521 slotbuf[0] = 0x615a00;
12527 slotbuf[0] = 0x35b00;
12533 slotbuf[0] = 0x135b00;
12539 slotbuf[0] = 0x615b00;
12545 slotbuf[0] = 0x35c00;
12551 slotbuf[0] = 0x135c00;
12557 slotbuf[0] = 0x615c00;
12563 slotbuf[0] = 0x50c000;
12569 slotbuf[0] = 0x50d000;
12575 slotbuf[0] = 0x50b000;
12581 slotbuf[0] = 0x50f000;
12587 slotbuf[0] = 0x50e000;
12593 slotbuf[0] = 0x504000;
12599 slotbuf[0] = 0x505000;
12605 slotbuf[0] = 0x503000;
12611 slotbuf[0] = 0x507000;
12617 slotbuf[0] = 0x506000;
12623 slotbuf[0] = 0xf1f000;
12629 slotbuf[0] = 0x501000;
12635 slotbuf[0] = 0x509000;
12641 slotbuf[0] = 0x3e000;
12647 slotbuf[0] = 0x13e000;
12653 slotbuf[0] = 0x61e000;
12659 slotbuf[0] = 0x330000;
12665 slotbuf[0] = 0x530000;
12671 slotbuf[0] = 0x730000;
12677 slotbuf[0] = 0x430000;
12683 slotbuf[0] = 0x630000;
12689 slotbuf[0] = 0x40e000;
12695 slotbuf[0] = 0x40f000;
12701 slotbuf[0] = 0x230000;
12707 slotbuf[0] = 0xb002;
12713 slotbuf[0] = 0xf002;
12719 slotbuf[0] = 0xe002;
12725 slotbuf[0] = 0x30c00;
12731 slotbuf[0] = 0x130c00;
12737 slotbuf[0] = 0x610c00;
12743 slotbuf[0] = 0x36300;
12749 slotbuf[0] = 0x136300;
12755 slotbuf[0] = 0x616300;
12761 slotbuf[0] = 0xd20000;
12767 slotbuf[0] = 0xc20000;
12773 slotbuf[0] = 0xf20000;
12779 slotbuf[0] = 0xe20000;
12785 slotbuf[0] = 0x35f00;
12791 slotbuf[0] = 0x135f00;
12797 slotbuf[0] = 0x615f00;
12803 slotbuf[0] = 0x406000;
12809 slotbuf[0] = 0x407000;
12815 slotbuf[0] = 0xe30e80;
12821 slotbuf[0] = 0xf3e800;
12827 slotbuf[0] = 0xe30e90;
12833 slotbuf[0] = 0xf3e900;
12839 slotbuf[0] = 0xe0000;
12845 slotbuf[0] = 0xe1000;
12851 slotbuf[0] = 0xe1200;
12857 slotbuf[0] = 0xe2000;
12863 slotbuf[0] = 0xe30e60;
12869 slotbuf[0] = 0xf3e600;
12875 slotbuf[0] = 0x3;
12881 slotbuf[0] = 0x8003;
12887 slotbuf[0] = 0x80000;
12893 slotbuf[0] = 0x180000;
12899 slotbuf[0] = 0x4003;
12905 slotbuf[0] = 0xc003;
12911 slotbuf[0] = 0x480000;
12917 slotbuf[0] = 0x580000;
12923 slotbuf[0] = 0x1003;
12929 slotbuf[0] = 0x9003;
12935 slotbuf[0] = 0x280000;
12941 slotbuf[0] = 0x380000;
12947 slotbuf[0] = 0x5003;
12953 slotbuf[0] = 0xd003;
12959 slotbuf[0] = 0x680000;
12965 slotbuf[0] = 0x780000;
12971 slotbuf[0] = 0xfa0010;
12977 slotbuf[0] = 0xfa0060;
12983 slotbuf[0] = 0xff0010;
12989 slotbuf[0] = 0xff0060;
12995 slotbuf[0] = 0xfa0000;
13001 slotbuf[0] = 0xff0000;
13007 slotbuf[0] = 0x8b0000;
13013 slotbuf[0] = 0x9b0000;
13019 slotbuf[0] = 0xab0000;
13025 slotbuf[0] = 0xbb0000;
13031 slotbuf[0] = 0xcb0000;
13037 slotbuf[0] = 0xdb0000;
13043 slotbuf[0] = 0xfa0050;
13049 slotbuf[0] = 0xfa0040;
13055 slotbuf[0] = 0xff0040;
13061 slotbuf[0] = 0x8e0000;
13067 slotbuf[0] = 0x8a0000;
13073 slotbuf[0] = 0x8f0000;
13079 slotbuf[0] = 0xba0000;
13085 slotbuf[0] = 0xbf0000;
13091 slotbuf[0] = 0xaa0000;
13097 slotbuf[0] = 0xaf0000;
13103 slotbuf[0] = 0x9a0000;
13109 slotbuf[0] = 0x9f0000;
13115 slotbuf[0] = 0xea0000;
13121 slotbuf[0] = 0xef0000;
13127 slotbuf[0] = 0xca0000;
13133 slotbuf[0] = 0xcf0000;
13139 slotbuf[0] = 0xda0000;
13145 slotbuf[0] = 0xdf0000;
13151 slotbuf[0] = 0xfa0020;
13157 slotbuf[0] = 0xff0020;
13163 slotbuf[0] = 0x1b0000;
13169 slotbuf[0] = 0x1e0000;
13175 slotbuf[0] = 0x5b0000;
13181 slotbuf[0] = 0x5e0000;
13187 slotbuf[0] = 0x7b0000;
13193 slotbuf[0] = 0x7e0000;
13199 slotbuf[0] = 0x3b0000;
13205 slotbuf[0] = 0x3e0000;
13211 slotbuf[0] = 0x4b0000;
13217 slotbuf[0] = 0x4e0000;
13223 slotbuf[0] = 0x6b0000;
13229 slotbuf[0] = 0x6e0000;
13235 slotbuf[0] = 0x2b0000;
13241 slotbuf[0] = 0x2e0000;
13247 slotbuf[0] = 0xa0000;
13253 slotbuf[0] = 0xf0000;
13259 slotbuf[0] = 0x1a0000;
13265 slotbuf[0] = 0x1f0000;
13271 slotbuf[0] = 0x2a0000;
13277 slotbuf[0] = 0x2f0000;
13283 slotbuf[0] = 0x4a0000;
13289 slotbuf[0] = 0x4f0000;
13295 slotbuf[0] = 0x5a0000;
13301 slotbuf[0] = 0x5f0000;
13307 slotbuf[0] = 0xfa0090;
13313 slotbuf[0] = 0xff0090;
13319 slotbuf[0] = 0xfa0070;
13325 slotbuf[0] = 0xff0070;
13331 slotbuf[0] = 0xfa0080;
13337 slotbuf[0] = 0xff0080;
13343 slotbuf[0] = 0xfa00a0;
13349 slotbuf[0] = 0xff00a0;
13355 slotbuf[0] = 0x6a0000;
13361 slotbuf[0] = 0x6f0000;
13367 slotbuf[0] = 0x7a0000;
13373 slotbuf[0] = 0x7f0000;
13379 slotbuf[0] = 0xfa0030;
13385 slotbuf[0] = 0xff0030;
13391 slotbuf[0] = 0xfa00b0;
13397 slotbuf[0] = 0xff00b0;
13403 slotbuf[0] = 0xfa00e0;
13409 slotbuf[0] = 0xff00e0;
13415 slotbuf[0] = 0xfa00f0;
13421 slotbuf[0] = 0xff00f0;
13427 slotbuf[0] = 0xfa00d0;
13433 slotbuf[0] = 0xff00d0;
13439 slotbuf[0] = 0xfa00c0;
13445 slotbuf[0] = 0xff00c0;
13449 Opcode_excw_Slot_inst_encode, 0, 0
13453 Opcode_rfe_Slot_inst_encode, 0, 0
13457 Opcode_rfde_Slot_inst_encode, 0, 0
13461 Opcode_syscall_Slot_inst_encode, 0, 0
13465 Opcode_call12_Slot_inst_encode, 0, 0
13469 Opcode_call8_Slot_inst_encode, 0, 0
13473 Opcode_call4_Slot_inst_encode, 0, 0
13477 Opcode_callx12_Slot_inst_encode, 0, 0
13481 Opcode_callx8_Slot_inst_encode, 0, 0
13485 Opcode_callx4_Slot_inst_encode, 0, 0
13489 Opcode_entry_Slot_inst_encode, 0, 0
13493 Opcode_movsp_Slot_inst_encode, 0, 0
13497 Opcode_rotw_Slot_inst_encode, 0, 0
13501 Opcode_retw_Slot_inst_encode, 0, 0
13505 0, 0, Opcode_retw_n_Slot_inst16b_encode
13509 Opcode_rfwo_Slot_inst_encode, 0, 0
13513 Opcode_rfwu_Slot_inst_encode, 0, 0
13517 Opcode_l32e_Slot_inst_encode, 0, 0
13521 Opcode_s32e_Slot_inst_encode, 0, 0
13525 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
13529 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
13533 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
13537 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
13541 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
13545 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
13549 0, Opcode_add_n_Slot_inst16a_encode, 0
13553 0, Opcode_addi_n_Slot_inst16a_encode, 0
13557 0, 0, Opcode_beqz_n_Slot_inst16b_encode
13561 0, 0, Opcode_bnez_n_Slot_inst16b_encode
13565 0, 0, Opcode_ill_n_Slot_inst16b_encode
13569 0, Opcode_l32i_n_Slot_inst16a_encode, 0
13573 0, 0, Opcode_mov_n_Slot_inst16b_encode
13577 0, 0, Opcode_movi_n_Slot_inst16b_encode
13581 0, 0, Opcode_nop_n_Slot_inst16b_encode
13585 0, 0, Opcode_ret_n_Slot_inst16b_encode
13589 0, Opcode_s32i_n_Slot_inst16a_encode, 0
13593 Opcode_rur_threadptr_Slot_inst_encode, 0, 0
13597 Opcode_wur_threadptr_Slot_inst_encode, 0, 0
13601 Opcode_addi_Slot_inst_encode, 0, 0
13605 Opcode_addmi_Slot_inst_encode, 0, 0
13609 Opcode_add_Slot_inst_encode, 0, 0
13613 Opcode_addx2_Slot_inst_encode, 0, 0
13617 Opcode_addx4_Slot_inst_encode, 0, 0
13621 Opcode_addx8_Slot_inst_encode, 0, 0
13625 Opcode_sub_Slot_inst_encode, 0, 0
13629 Opcode_subx2_Slot_inst_encode, 0, 0
13633 Opcode_subx4_Slot_inst_encode, 0, 0
13637 Opcode_subx8_Slot_inst_encode, 0, 0
13641 Opcode_and_Slot_inst_encode, 0, 0
13645 Opcode_or_Slot_inst_encode, 0, 0
13649 Opcode_xor_Slot_inst_encode, 0, 0
13653 Opcode_beqi_Slot_inst_encode, 0, 0
13657 Opcode_bgei_Slot_inst_encode, 0, 0
13661 Opcode_blti_Slot_inst_encode, 0, 0
13665 Opcode_bnei_Slot_inst_encode, 0, 0
13669 Opcode_bbci_Slot_inst_encode, 0, 0
13673 Opcode_bbsi_Slot_inst_encode, 0, 0
13677 Opcode_bgeui_Slot_inst_encode, 0, 0
13681 Opcode_bltui_Slot_inst_encode, 0, 0
13685 Opcode_ball_Slot_inst_encode, 0, 0
13689 Opcode_bany_Slot_inst_encode, 0, 0
13693 Opcode_bbc_Slot_inst_encode, 0, 0
13697 Opcode_bbs_Slot_inst_encode, 0, 0
13701 Opcode_beq_Slot_inst_encode, 0, 0
13705 Opcode_bge_Slot_inst_encode, 0, 0
13709 Opcode_bgeu_Slot_inst_encode, 0, 0
13713 Opcode_blt_Slot_inst_encode, 0, 0
13717 Opcode_bltu_Slot_inst_encode, 0, 0
13721 Opcode_bnall_Slot_inst_encode, 0, 0
13725 Opcode_bne_Slot_inst_encode, 0, 0
13729 Opcode_bnone_Slot_inst_encode, 0, 0
13733 Opcode_beqz_Slot_inst_encode, 0, 0
13737 Opcode_bgez_Slot_inst_encode, 0, 0
13741 Opcode_bltz_Slot_inst_encode, 0, 0
13745 Opcode_bnez_Slot_inst_encode, 0, 0
13749 Opcode_call0_Slot_inst_encode, 0, 0
13753 Opcode_callx0_Slot_inst_encode, 0, 0
13757 Opcode_extui_Slot_inst_encode, 0, 0
13761 Opcode_ill_Slot_inst_encode, 0, 0
13765 Opcode_j_Slot_inst_encode, 0, 0
13769 Opcode_jx_Slot_inst_encode, 0, 0
13773 Opcode_l16ui_Slot_inst_encode, 0, 0
13777 Opcode_l16si_Slot_inst_encode, 0, 0
13781 Opcode_l32i_Slot_inst_encode, 0, 0
13785 Opcode_l32r_Slot_inst_encode, 0, 0
13789 Opcode_l8ui_Slot_inst_encode, 0, 0
13793 Opcode_loop_Slot_inst_encode, 0, 0
13797 Opcode_loopgtz_Slot_inst_encode, 0, 0
13801 Opcode_loopnez_Slot_inst_encode, 0, 0
13805 Opcode_movi_Slot_inst_encode, 0, 0
13809 Opcode_moveqz_Slot_inst_encode, 0, 0
13813 Opcode_movgez_Slot_inst_encode, 0, 0
13817 Opcode_movltz_Slot_inst_encode, 0, 0
13821 Opcode_movnez_Slot_inst_encode, 0, 0
13825 Opcode_abs_Slot_inst_encode, 0, 0
13829 Opcode_neg_Slot_inst_encode, 0, 0
13833 Opcode_nop_Slot_inst_encode, 0, 0
13837 Opcode_ret_Slot_inst_encode, 0, 0
13841 Opcode_simcall_Slot_inst_encode, 0, 0
13845 Opcode_s16i_Slot_inst_encode, 0, 0
13849 Opcode_s32i_Slot_inst_encode, 0, 0
13853 Opcode_s32nb_Slot_inst_encode, 0, 0
13857 Opcode_s8i_Slot_inst_encode, 0, 0
13861 Opcode_ssa8b_Slot_inst_encode, 0, 0
13865 Opcode_ssa8l_Slot_inst_encode, 0, 0
13869 Opcode_ssl_Slot_inst_encode, 0, 0
13873 Opcode_ssr_Slot_inst_encode, 0, 0
13877 Opcode_ssai_Slot_inst_encode, 0, 0
13881 Opcode_sll_Slot_inst_encode, 0, 0
13885 Opcode_src_Slot_inst_encode, 0, 0
13889 Opcode_sra_Slot_inst_encode, 0, 0
13893 Opcode_srl_Slot_inst_encode, 0, 0
13897 Opcode_slli_Slot_inst_encode, 0, 0
13901 Opcode_srai_Slot_inst_encode, 0, 0
13905 Opcode_srli_Slot_inst_encode, 0, 0
13909 Opcode_memw_Slot_inst_encode, 0, 0
13913 Opcode_extw_Slot_inst_encode, 0, 0
13917 Opcode_isync_Slot_inst_encode, 0, 0
13921 Opcode_dsync_Slot_inst_encode, 0, 0
13925 Opcode_esync_Slot_inst_encode, 0, 0
13929 Opcode_rsync_Slot_inst_encode, 0, 0
13933 Opcode_rsil_Slot_inst_encode, 0, 0
13937 Opcode_rsr_lend_Slot_inst_encode, 0, 0
13941 Opcode_wsr_lend_Slot_inst_encode, 0, 0
13945 Opcode_xsr_lend_Slot_inst_encode, 0, 0
13949 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
13953 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
13957 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
13961 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
13965 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
13969 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
13973 Opcode_rsr_sar_Slot_inst_encode, 0, 0
13977 Opcode_wsr_sar_Slot_inst_encode, 0, 0
13981 Opcode_xsr_sar_Slot_inst_encode, 0, 0
13985 Opcode_rsr_memctl_Slot_inst_encode, 0, 0
13989 Opcode_wsr_memctl_Slot_inst_encode, 0, 0
13993 Opcode_xsr_memctl_Slot_inst_encode, 0, 0
13997 Opcode_rsr_configid0_Slot_inst_encode, 0, 0
14001 Opcode_wsr_configid0_Slot_inst_encode, 0, 0
14005 Opcode_rsr_configid1_Slot_inst_encode, 0, 0
14009 Opcode_rsr_ps_Slot_inst_encode, 0, 0
14013 Opcode_wsr_ps_Slot_inst_encode, 0, 0
14017 Opcode_xsr_ps_Slot_inst_encode, 0, 0
14021 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
14025 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
14029 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
14033 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
14037 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
14041 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
14045 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
14049 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
14053 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
14057 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
14061 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
14065 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
14069 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
14073 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
14077 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
14081 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
14085 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
14089 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
14093 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
14097 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
14101 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
14105 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
14109 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
14113 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
14117 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
14121 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
14125 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
14129 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
14133 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
14137 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
14141 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
14145 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
14149 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
14153 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
14157 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
14161 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
14165 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
14169 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
14173 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
14177 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
14181 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
14185 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
14189 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
14193 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
14197 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
14201 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
14205 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
14209 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
14213 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
14217 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
14221 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
14225 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
14229 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
14233 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
14237 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
14241 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
14245 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
14249 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
14253 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
14257 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
14261 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
14265 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
14269 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
14273 Opcode_rsr_depc_Slot_inst_encode, 0, 0
14277 Opcode_wsr_depc_Slot_inst_encode, 0, 0
14281 Opcode_xsr_depc_Slot_inst_encode, 0, 0
14285 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
14289 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
14293 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
14297 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
14301 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
14305 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
14309 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
14313 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
14317 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
14321 Opcode_rsr_prid_Slot_inst_encode, 0, 0
14325 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
14329 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
14333 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
14337 Opcode_salt_Slot_inst_encode, 0, 0
14341 Opcode_saltu_Slot_inst_encode, 0, 0
14345 Opcode_mul16s_Slot_inst_encode, 0, 0
14349 Opcode_mul16u_Slot_inst_encode, 0, 0
14353 Opcode_mull_Slot_inst_encode, 0, 0
14357 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
14361 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
14365 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
14369 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
14373 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
14377 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
14381 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
14385 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
14389 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
14393 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
14397 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
14401 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
14405 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
14409 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
14413 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
14417 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
14421 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
14425 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
14429 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
14433 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
14437 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
14441 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
14445 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
14449 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
14453 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
14457 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
14461 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
14465 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
14469 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
14473 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
14477 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
14481 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
14485 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
14489 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
14493 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
14497 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
14501 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
14505 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
14509 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
14513 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
14517 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
14521 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
14525 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
14529 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
14533 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
14537 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
14541 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
14545 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
14549 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
14553 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
14557 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
14561 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
14565 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
14569 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
14573 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
14577 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
14581 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
14585 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
14589 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
14593 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
14597 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
14601 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
14605 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
14609 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
14613 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
14617 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
14621 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
14625 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
14629 Opcode_lddec_Slot_inst_encode, 0, 0
14633 Opcode_ldinc_Slot_inst_encode, 0, 0
14637 Opcode_rsr_m0_Slot_inst_encode, 0, 0
14641 Opcode_wsr_m0_Slot_inst_encode, 0, 0
14645 Opcode_xsr_m0_Slot_inst_encode, 0, 0
14649 Opcode_rsr_m1_Slot_inst_encode, 0, 0
14653 Opcode_wsr_m1_Slot_inst_encode, 0, 0
14657 Opcode_xsr_m1_Slot_inst_encode, 0, 0
14661 Opcode_rsr_m2_Slot_inst_encode, 0, 0
14665 Opcode_wsr_m2_Slot_inst_encode, 0, 0
14669 Opcode_xsr_m2_Slot_inst_encode, 0, 0
14673 Opcode_rsr_m3_Slot_inst_encode, 0, 0
14677 Opcode_wsr_m3_Slot_inst_encode, 0, 0
14681 Opcode_xsr_m3_Slot_inst_encode, 0, 0
14685 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
14689 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
14693 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
14697 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
14701 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
14705 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
14709 Opcode_rfi_Slot_inst_encode, 0, 0
14713 Opcode_waiti_Slot_inst_encode, 0, 0
14717 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
14721 Opcode_wsr_intset_Slot_inst_encode, 0, 0
14725 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
14729 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
14733 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
14737 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
14741 Opcode_break_Slot_inst_encode, 0, 0
14745 0, 0, Opcode_break_n_Slot_inst16b_encode
14749 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
14753 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
14757 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
14761 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
14765 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
14769 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
14773 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
14777 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
14781 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
14785 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
14789 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
14793 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
14797 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
14801 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
14805 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
14809 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
14813 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
14817 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
14821 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
14825 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
14829 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
14833 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
14837 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
14841 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
14845 Opcode_rsr_icount_Slot_inst_encode, 0, 0
14849 Opcode_wsr_icount_Slot_inst_encode, 0, 0
14853 Opcode_xsr_icount_Slot_inst_encode, 0, 0
14857 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
14861 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
14865 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
14869 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
14873 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
14877 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
14881 Opcode_lddr32_p_Slot_inst_encode, 0, 0
14885 Opcode_sddr32_p_Slot_inst_encode, 0, 0
14889 Opcode_rfdo_Slot_inst_encode, 0, 0
14893 Opcode_rfdd_Slot_inst_encode, 0, 0
14897 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
14901 Opcode_andb_Slot_inst_encode, 0, 0
14905 Opcode_andbc_Slot_inst_encode, 0, 0
14909 Opcode_orb_Slot_inst_encode, 0, 0
14913 Opcode_orbc_Slot_inst_encode, 0, 0
14917 Opcode_xorb_Slot_inst_encode, 0, 0
14921 Opcode_all4_Slot_inst_encode, 0, 0
14925 Opcode_any4_Slot_inst_encode, 0, 0
14929 Opcode_all8_Slot_inst_encode, 0, 0
14933 Opcode_any8_Slot_inst_encode, 0, 0
14937 Opcode_bf_Slot_inst_encode, 0, 0
14941 Opcode_bt_Slot_inst_encode, 0, 0
14945 Opcode_movf_Slot_inst_encode, 0, 0
14949 Opcode_movt_Slot_inst_encode, 0, 0
14953 Opcode_rsr_br_Slot_inst_encode, 0, 0
14957 Opcode_wsr_br_Slot_inst_encode, 0, 0
14961 Opcode_xsr_br_Slot_inst_encode, 0, 0
14965 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
14969 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
14973 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
14977 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
14981 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
14985 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
14989 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
14993 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
14997 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
15001 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
15005 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
15009 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
15013 Opcode_ihi_Slot_inst_encode, 0, 0
15017 Opcode_ipf_Slot_inst_encode, 0, 0
15021 Opcode_ihu_Slot_inst_encode, 0, 0
15025 Opcode_iiu_Slot_inst_encode, 0, 0
15029 Opcode_ipfl_Slot_inst_encode, 0, 0
15033 Opcode_iii_Slot_inst_encode, 0, 0
15037 Opcode_lict_Slot_inst_encode, 0, 0
15041 Opcode_licw_Slot_inst_encode, 0, 0
15045 Opcode_sict_Slot_inst_encode, 0, 0
15049 Opcode_sicw_Slot_inst_encode, 0, 0
15053 Opcode_dhwb_Slot_inst_encode, 0, 0
15057 Opcode_dhwbi_Slot_inst_encode, 0, 0
15061 Opcode_diwbui_p_Slot_inst_encode, 0, 0
15065 Opcode_diwb_Slot_inst_encode, 0, 0
15069 Opcode_diwbi_Slot_inst_encode, 0, 0
15073 Opcode_dhi_Slot_inst_encode, 0, 0
15077 Opcode_dii_Slot_inst_encode, 0, 0
15081 Opcode_dpfr_Slot_inst_encode, 0, 0
15085 Opcode_dpfro_Slot_inst_encode, 0, 0
15089 Opcode_dpfw_Slot_inst_encode, 0, 0
15093 Opcode_dpfwo_Slot_inst_encode, 0, 0
15097 Opcode_dhu_Slot_inst_encode, 0, 0
15101 Opcode_diu_Slot_inst_encode, 0, 0
15105 Opcode_dpfl_Slot_inst_encode, 0, 0
15109 Opcode_sdct_Slot_inst_encode, 0, 0
15113 Opcode_ldct_Slot_inst_encode, 0, 0
15117 Opcode_sdcw_Slot_inst_encode, 0, 0
15121 Opcode_ldcw_Slot_inst_encode, 0, 0
15125 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
15129 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
15133 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
15137 Opcode_rsr_rasid_Slot_inst_encode, 0, 0
15141 Opcode_wsr_rasid_Slot_inst_encode, 0, 0
15145 Opcode_xsr_rasid_Slot_inst_encode, 0, 0
15149 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
15153 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
15157 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
15161 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
15165 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
15169 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
15173 Opcode_idtlb_Slot_inst_encode, 0, 0
15177 Opcode_pdtlb_Slot_inst_encode, 0, 0
15181 Opcode_rdtlb0_Slot_inst_encode, 0, 0
15185 Opcode_rdtlb1_Slot_inst_encode, 0, 0
15189 Opcode_wdtlb_Slot_inst_encode, 0, 0
15193 Opcode_iitlb_Slot_inst_encode, 0, 0
15197 Opcode_pitlb_Slot_inst_encode, 0, 0
15201 Opcode_ritlb0_Slot_inst_encode, 0, 0
15205 Opcode_ritlb1_Slot_inst_encode, 0, 0
15209 Opcode_witlb_Slot_inst_encode, 0, 0
15213 Opcode_ldpte_Slot_inst_encode, 0, 0
15217 Opcode_hwwitlba_Slot_inst_encode, 0, 0
15221 Opcode_hwwdtlba_Slot_inst_encode, 0, 0
15225 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
15229 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
15233 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
15237 Opcode_clamps_Slot_inst_encode, 0, 0
15241 Opcode_max_Slot_inst_encode, 0, 0
15245 Opcode_maxu_Slot_inst_encode, 0, 0
15249 Opcode_min_Slot_inst_encode, 0, 0
15253 Opcode_minu_Slot_inst_encode, 0, 0
15257 Opcode_nsa_Slot_inst_encode, 0, 0
15261 Opcode_nsau_Slot_inst_encode, 0, 0
15265 Opcode_sext_Slot_inst_encode, 0, 0
15269 Opcode_l32ai_Slot_inst_encode, 0, 0
15273 Opcode_s32ri_Slot_inst_encode, 0, 0
15277 Opcode_s32c1i_Slot_inst_encode, 0, 0
15281 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
15285 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
15289 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
15293 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
15297 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
15301 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
15305 Opcode_quos_Slot_inst_encode, 0, 0
15309 Opcode_quou_Slot_inst_encode, 0, 0
15313 Opcode_rems_Slot_inst_encode, 0, 0
15317 Opcode_remu_Slot_inst_encode, 0, 0
15321 Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
15325 Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
15329 Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
15333 Opcode_rer_Slot_inst_encode, 0, 0
15337 Opcode_wer_Slot_inst_encode, 0, 0
15341 Opcode_rur_fcr_Slot_inst_encode, 0, 0
15345 Opcode_wur_fcr_Slot_inst_encode, 0, 0
15349 Opcode_rur_fsr_Slot_inst_encode, 0, 0
15353 Opcode_wur_fsr_Slot_inst_encode, 0, 0
15357 Opcode_read_impwire_Slot_inst_encode, 0, 0
15361 Opcode_setb_expstate_Slot_inst_encode, 0, 0
15365 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
15369 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
15373 Opcode_rur_expstate_Slot_inst_encode, 0, 0
15377 Opcode_wur_expstate_Slot_inst_encode, 0, 0
15381 Opcode_lsi_Slot_inst_encode, 0, 0
15385 Opcode_lsip_Slot_inst_encode, 0, 0
15389 Opcode_lsx_Slot_inst_encode, 0, 0
15393 Opcode_lsxp_Slot_inst_encode, 0, 0
15397 Opcode_ssi_Slot_inst_encode, 0, 0
15401 Opcode_ssip_Slot_inst_encode, 0, 0
15405 Opcode_ssx_Slot_inst_encode, 0, 0
15409 Opcode_ssxp_Slot_inst_encode, 0, 0
15413 Opcode_ldi_Slot_inst_encode, 0, 0
15417 Opcode_ldip_Slot_inst_encode, 0, 0
15421 Opcode_ldx_Slot_inst_encode, 0, 0
15425 Opcode_ldxp_Slot_inst_encode, 0, 0
15429 Opcode_sdi_Slot_inst_encode, 0, 0
15433 Opcode_sdip_Slot_inst_encode, 0, 0
15437 Opcode_sdx_Slot_inst_encode, 0, 0
15441 Opcode_sdxp_Slot_inst_encode, 0, 0
15445 Opcode_abs_s_Slot_inst_encode, 0, 0
15449 Opcode_neg_s_Slot_inst_encode, 0, 0
15453 Opcode_abs_d_Slot_inst_encode, 0, 0
15457 Opcode_neg_d_Slot_inst_encode, 0, 0
15461 Opcode_mov_s_Slot_inst_encode, 0, 0
15465 Opcode_mov_d_Slot_inst_encode, 0, 0
15469 Opcode_moveqz_s_Slot_inst_encode, 0, 0
15473 Opcode_movnez_s_Slot_inst_encode, 0, 0
15477 Opcode_movltz_s_Slot_inst_encode, 0, 0
15481 Opcode_movgez_s_Slot_inst_encode, 0, 0
15485 Opcode_movf_s_Slot_inst_encode, 0, 0
15489 Opcode_movt_s_Slot_inst_encode, 0, 0
15493 Opcode_wfr_Slot_inst_encode, 0, 0
15497 Opcode_rfr_Slot_inst_encode, 0, 0
15501 Opcode_rfrd_Slot_inst_encode, 0, 0
15505 Opcode_wfrd_Slot_inst_encode, 0, 0
15509 Opcode_round_s_Slot_inst_encode, 0, 0
15513 Opcode_round_d_Slot_inst_encode, 0, 0
15517 Opcode_ceil_s_Slot_inst_encode, 0, 0
15521 Opcode_ceil_d_Slot_inst_encode, 0, 0
15525 Opcode_floor_s_Slot_inst_encode, 0, 0
15529 Opcode_floor_d_Slot_inst_encode, 0, 0
15533 Opcode_trunc_s_Slot_inst_encode, 0, 0
15537 Opcode_trunc_d_Slot_inst_encode, 0, 0
15541 Opcode_utrunc_s_Slot_inst_encode, 0, 0
15545 Opcode_utrunc_d_Slot_inst_encode, 0, 0
15549 Opcode_float_s_Slot_inst_encode, 0, 0
15553 Opcode_float_d_Slot_inst_encode, 0, 0
15557 Opcode_ufloat_s_Slot_inst_encode, 0, 0
15561 Opcode_ufloat_d_Slot_inst_encode, 0, 0
15565 Opcode_cvtd_s_Slot_inst_encode, 0, 0
15569 Opcode_cvts_d_Slot_inst_encode, 0, 0
15573 Opcode_un_s_Slot_inst_encode, 0, 0
15577 Opcode_un_d_Slot_inst_encode, 0, 0
15581 Opcode_ult_s_Slot_inst_encode, 0, 0
15585 Opcode_ult_d_Slot_inst_encode, 0, 0
15589 Opcode_ule_s_Slot_inst_encode, 0, 0
15593 Opcode_ule_d_Slot_inst_encode, 0, 0
15597 Opcode_ueq_s_Slot_inst_encode, 0, 0
15601 Opcode_ueq_d_Slot_inst_encode, 0, 0
15605 Opcode_olt_s_Slot_inst_encode, 0, 0
15609 Opcode_olt_d_Slot_inst_encode, 0, 0
15613 Opcode_ole_s_Slot_inst_encode, 0, 0
15617 Opcode_ole_d_Slot_inst_encode, 0, 0
15621 Opcode_oeq_s_Slot_inst_encode, 0, 0
15625 Opcode_oeq_d_Slot_inst_encode, 0, 0
15629 Opcode_add_s_Slot_inst_encode, 0, 0
15633 Opcode_add_d_Slot_inst_encode, 0, 0
15637 Opcode_sub_s_Slot_inst_encode, 0, 0
15641 Opcode_sub_d_Slot_inst_encode, 0, 0
15645 Opcode_mul_s_Slot_inst_encode, 0, 0
15649 Opcode_mul_d_Slot_inst_encode, 0, 0
15653 Opcode_madd_s_Slot_inst_encode, 0, 0
15657 Opcode_madd_d_Slot_inst_encode, 0, 0
15661 Opcode_msub_s_Slot_inst_encode, 0, 0
15665 Opcode_msub_d_Slot_inst_encode, 0, 0
15669 Opcode_sqrt0_s_Slot_inst_encode, 0, 0
15673 Opcode_sqrt0_d_Slot_inst_encode, 0, 0
15677 Opcode_div0_s_Slot_inst_encode, 0, 0
15681 Opcode_div0_d_Slot_inst_encode, 0, 0
15685 Opcode_recip0_s_Slot_inst_encode, 0, 0
15689 Opcode_recip0_d_Slot_inst_encode, 0, 0
15693 Opcode_rsqrt0_s_Slot_inst_encode, 0, 0
15697 Opcode_rsqrt0_d_Slot_inst_encode, 0, 0
15701 Opcode_maddn_s_Slot_inst_encode, 0, 0
15705 Opcode_maddn_d_Slot_inst_encode, 0, 0
15709 Opcode_divn_s_Slot_inst_encode, 0, 0
15713 Opcode_divn_d_Slot_inst_encode, 0, 0
15717 Opcode_const_s_Slot_inst_encode, 0, 0
15721 Opcode_const_d_Slot_inst_encode, 0, 0
15725 Opcode_nexp01_s_Slot_inst_encode, 0, 0
15729 Opcode_nexp01_d_Slot_inst_encode, 0, 0
15733 Opcode_addexp_s_Slot_inst_encode, 0, 0
15737 Opcode_addexp_d_Slot_inst_encode, 0, 0
15741 Opcode_addexpm_s_Slot_inst_encode, 0, 0
15745 Opcode_addexpm_d_Slot_inst_encode, 0, 0
15749 Opcode_mkdadj_s_Slot_inst_encode, 0, 0
15753 Opcode_mkdadj_d_Slot_inst_encode, 0, 0
15757 Opcode_mksadj_s_Slot_inst_encode, 0, 0
15761 Opcode_mksadj_d_Slot_inst_encode, 0, 0
15771 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15775 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15779 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15783 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15787 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15791 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15795 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15799 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15803 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15807 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15811 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15815 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15819 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15823 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15827 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15831 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15835 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15839 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15843 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15847 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15851 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15855 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15859 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15863 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15867 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15871 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15875 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15879 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15883 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15887 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15891 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15895 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15899 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15903 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15907 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15911 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15915 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15919 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15923 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15927 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15931 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15935 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15939 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15943 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15947 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15951 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15955 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15959 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15963 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15967 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15971 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15975 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15979 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15983 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15987 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15991 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15995 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
15999 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
16003 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
16007 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
16011 { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
16016 0,
16017 Opcode_excw_encode_fns, 0, 0 },
16020 Opcode_rfe_encode_fns, 0, 0 },
16023 Opcode_rfde_encode_fns, 0, 0 },
16025 0,
16026 Opcode_syscall_encode_fns, 0, 0 },
16029 Opcode_call12_encode_fns, 0, 0 },
16032 Opcode_call8_encode_fns, 0, 0 },
16035 Opcode_call4_encode_fns, 0, 0 },
16038 Opcode_callx12_encode_fns, 0, 0 },
16041 Opcode_callx8_encode_fns, 0, 0 },
16044 Opcode_callx4_encode_fns, 0, 0 },
16046 0,
16047 Opcode_entry_encode_fns, 0, 0 },
16049 0,
16050 Opcode_movsp_encode_fns, 0, 0 },
16052 0,
16053 Opcode_rotw_encode_fns, 0, 0 },
16056 Opcode_retw_encode_fns, 0, 0 },
16059 Opcode_retw_n_encode_fns, 0, 0 },
16062 Opcode_rfwo_encode_fns, 0, 0 },
16065 Opcode_rfwu_encode_fns, 0, 0 },
16067 0,
16070 0,
16073 0,
16074 Opcode_rsr_windowbase_encode_fns, 0, 0 },
16076 0,
16077 Opcode_wsr_windowbase_encode_fns, 0, 0 },
16079 0,
16080 Opcode_xsr_windowbase_encode_fns, 0, 0 },
16082 0,
16083 Opcode_rsr_windowstart_encode_fns, 0, 0 },
16085 0,
16086 Opcode_wsr_windowstart_encode_fns, 0, 0 },
16088 0,
16089 Opcode_xsr_windowstart_encode_fns, 0, 0 },
16091 0,
16092 Opcode_add_n_encode_fns, 0, 0 },
16094 0,
16095 Opcode_addi_n_encode_fns, 0, 0 },
16098 Opcode_beqz_n_encode_fns, 0, 0 },
16101 Opcode_bnez_n_encode_fns, 0, 0 },
16103 0,
16104 Opcode_ill_n_encode_fns, 0, 0 },
16106 0,
16109 0,
16110 Opcode_mov_n_encode_fns, 0, 0 },
16112 0,
16113 Opcode_movi_n_encode_fns, 0, 0 },
16115 0,
16116 Opcode_nop_n_encode_fns, 0, 0 },
16119 Opcode_ret_n_encode_fns, 0, 0 },
16121 0,
16124 0,
16125 Opcode_rur_threadptr_encode_fns, 0, 0 },
16127 0,
16128 Opcode_wur_threadptr_encode_fns, 0, 0 },
16130 0,
16131 Opcode_addi_encode_fns, 0, 0 },
16133 0,
16134 Opcode_addmi_encode_fns, 0, 0 },
16136 0,
16137 Opcode_add_encode_fns, 0, 0 },
16139 0,
16140 Opcode_addx2_encode_fns, 0, 0 },
16142 0,
16143 Opcode_addx4_encode_fns, 0, 0 },
16145 0,
16146 Opcode_addx8_encode_fns, 0, 0 },
16148 0,
16149 Opcode_sub_encode_fns, 0, 0 },
16151 0,
16152 Opcode_subx2_encode_fns, 0, 0 },
16154 0,
16155 Opcode_subx4_encode_fns, 0, 0 },
16157 0,
16158 Opcode_subx8_encode_fns, 0, 0 },
16160 0,
16161 Opcode_and_encode_fns, 0, 0 },
16163 0,
16164 Opcode_or_encode_fns, 0, 0 },
16166 0,
16167 Opcode_xor_encode_fns, 0, 0 },
16170 Opcode_beqi_encode_fns, 0, 0 },
16173 Opcode_bgei_encode_fns, 0, 0 },
16176 Opcode_blti_encode_fns, 0, 0 },
16179 Opcode_bnei_encode_fns, 0, 0 },
16182 Opcode_bbci_encode_fns, 0, 0 },
16185 Opcode_bbsi_encode_fns, 0, 0 },
16188 Opcode_bgeui_encode_fns, 0, 0 },
16191 Opcode_bltui_encode_fns, 0, 0 },
16194 Opcode_ball_encode_fns, 0, 0 },
16197 Opcode_bany_encode_fns, 0, 0 },
16200 Opcode_bbc_encode_fns, 0, 0 },
16203 Opcode_bbs_encode_fns, 0, 0 },
16206 Opcode_beq_encode_fns, 0, 0 },
16209 Opcode_bge_encode_fns, 0, 0 },
16212 Opcode_bgeu_encode_fns, 0, 0 },
16215 Opcode_blt_encode_fns, 0, 0 },
16218 Opcode_bltu_encode_fns, 0, 0 },
16221 Opcode_bnall_encode_fns, 0, 0 },
16224 Opcode_bne_encode_fns, 0, 0 },
16227 Opcode_bnone_encode_fns, 0, 0 },
16230 Opcode_beqz_encode_fns, 0, 0 },
16233 Opcode_bgez_encode_fns, 0, 0 },
16236 Opcode_bltz_encode_fns, 0, 0 },
16239 Opcode_bnez_encode_fns, 0, 0 },
16242 Opcode_call0_encode_fns, 0, 0 },
16245 Opcode_callx0_encode_fns, 0, 0 },
16247 0,
16248 Opcode_extui_encode_fns, 0, 0 },
16250 0,
16251 Opcode_ill_encode_fns, 0, 0 },
16254 Opcode_j_encode_fns, 0, 0 },
16257 Opcode_jx_encode_fns, 0, 0 },
16259 0,
16262 0,
16265 0,
16268 0,
16271 0,
16275 Opcode_loop_encode_fns, 0, 0 },
16278 Opcode_loopgtz_encode_fns, 0, 0 },
16281 Opcode_loopnez_encode_fns, 0, 0 },
16283 0,
16284 Opcode_movi_encode_fns, 0, 0 },
16286 0,
16287 Opcode_moveqz_encode_fns, 0, 0 },
16289 0,
16290 Opcode_movgez_encode_fns, 0, 0 },
16292 0,
16293 Opcode_movltz_encode_fns, 0, 0 },
16295 0,
16296 Opcode_movnez_encode_fns, 0, 0 },
16298 0,
16299 Opcode_abs_encode_fns, 0, 0 },
16301 0,
16302 Opcode_neg_encode_fns, 0, 0 },
16304 0,
16305 Opcode_nop_encode_fns, 0, 0 },
16308 Opcode_ret_encode_fns, 0, 0 },
16310 0,
16311 Opcode_simcall_encode_fns, 0, 0 },
16313 0,
16316 0,
16319 0,
16322 0,
16325 0,
16326 Opcode_ssa8b_encode_fns, 0, 0 },
16328 0,
16329 Opcode_ssa8l_encode_fns, 0, 0 },
16331 0,
16332 Opcode_ssl_encode_fns, 0, 0 },
16334 0,
16335 Opcode_ssr_encode_fns, 0, 0 },
16337 0,
16338 Opcode_ssai_encode_fns, 0, 0 },
16340 0,
16341 Opcode_sll_encode_fns, 0, 0 },
16343 0,
16344 Opcode_src_encode_fns, 0, 0 },
16346 0,
16347 Opcode_sra_encode_fns, 0, 0 },
16349 0,
16350 Opcode_srl_encode_fns, 0, 0 },
16352 0,
16353 Opcode_slli_encode_fns, 0, 0 },
16355 0,
16356 Opcode_srai_encode_fns, 0, 0 },
16358 0,
16359 Opcode_srli_encode_fns, 0, 0 },
16361 0,
16362 Opcode_memw_encode_fns, 0, 0 },
16364 0,
16365 Opcode_extw_encode_fns, 0, 0 },
16367 0,
16368 Opcode_isync_encode_fns, 0, 0 },
16370 0,
16371 Opcode_dsync_encode_fns, 0, 0 },
16373 0,
16374 Opcode_esync_encode_fns, 0, 0 },
16376 0,
16377 Opcode_rsync_encode_fns, 0, 0 },
16379 0,
16380 Opcode_rsil_encode_fns, 0, 0 },
16382 0,
16383 Opcode_rsr_lend_encode_fns, 0, 0 },
16385 0,
16386 Opcode_wsr_lend_encode_fns, 0, 0 },
16388 0,
16389 Opcode_xsr_lend_encode_fns, 0, 0 },
16391 0,
16392 Opcode_rsr_lcount_encode_fns, 0, 0 },
16394 0,
16395 Opcode_wsr_lcount_encode_fns, 0, 0 },
16397 0,
16398 Opcode_xsr_lcount_encode_fns, 0, 0 },
16400 0,
16401 Opcode_rsr_lbeg_encode_fns, 0, 0 },
16403 0,
16404 Opcode_wsr_lbeg_encode_fns, 0, 0 },
16406 0,
16407 Opcode_xsr_lbeg_encode_fns, 0, 0 },
16409 0,
16410 Opcode_rsr_sar_encode_fns, 0, 0 },
16412 0,
16413 Opcode_wsr_sar_encode_fns, 0, 0 },
16415 0,
16416 Opcode_xsr_sar_encode_fns, 0, 0 },
16418 0,
16419 Opcode_rsr_memctl_encode_fns, 0, 0 },
16421 0,
16422 Opcode_wsr_memctl_encode_fns, 0, 0 },
16424 0,
16425 Opcode_xsr_memctl_encode_fns, 0, 0 },
16427 0,
16428 Opcode_rsr_configid0_encode_fns, 0, 0 },
16430 0,
16431 Opcode_wsr_configid0_encode_fns, 0, 0 },
16433 0,
16434 Opcode_rsr_configid1_encode_fns, 0, 0 },
16436 0,
16437 Opcode_rsr_ps_encode_fns, 0, 0 },
16439 0,
16440 Opcode_wsr_ps_encode_fns, 0, 0 },
16442 0,
16443 Opcode_xsr_ps_encode_fns, 0, 0 },
16445 0,
16446 Opcode_rsr_epc1_encode_fns, 0, 0 },
16448 0,
16449 Opcode_wsr_epc1_encode_fns, 0, 0 },
16451 0,
16452 Opcode_xsr_epc1_encode_fns, 0, 0 },
16454 0,
16455 Opcode_rsr_excsave1_encode_fns, 0, 0 },
16457 0,
16458 Opcode_wsr_excsave1_encode_fns, 0, 0 },
16460 0,
16461 Opcode_xsr_excsave1_encode_fns, 0, 0 },
16463 0,
16464 Opcode_rsr_epc2_encode_fns, 0, 0 },
16466 0,
16467 Opcode_wsr_epc2_encode_fns, 0, 0 },
16469 0,
16470 Opcode_xsr_epc2_encode_fns, 0, 0 },
16472 0,
16473 Opcode_rsr_excsave2_encode_fns, 0, 0 },
16475 0,
16476 Opcode_wsr_excsave2_encode_fns, 0, 0 },
16478 0,
16479 Opcode_xsr_excsave2_encode_fns, 0, 0 },
16481 0,
16482 Opcode_rsr_epc3_encode_fns, 0, 0 },
16484 0,
16485 Opcode_wsr_epc3_encode_fns, 0, 0 },
16487 0,
16488 Opcode_xsr_epc3_encode_fns, 0, 0 },
16490 0,
16491 Opcode_rsr_excsave3_encode_fns, 0, 0 },
16493 0,
16494 Opcode_wsr_excsave3_encode_fns, 0, 0 },
16496 0,
16497 Opcode_xsr_excsave3_encode_fns, 0, 0 },
16499 0,
16500 Opcode_rsr_epc4_encode_fns, 0, 0 },
16502 0,
16503 Opcode_wsr_epc4_encode_fns, 0, 0 },
16505 0,
16506 Opcode_xsr_epc4_encode_fns, 0, 0 },
16508 0,
16509 Opcode_rsr_excsave4_encode_fns, 0, 0 },
16511 0,
16512 Opcode_wsr_excsave4_encode_fns, 0, 0 },
16514 0,
16515 Opcode_xsr_excsave4_encode_fns, 0, 0 },
16517 0,
16518 Opcode_rsr_epc5_encode_fns, 0, 0 },
16520 0,
16521 Opcode_wsr_epc5_encode_fns, 0, 0 },
16523 0,
16524 Opcode_xsr_epc5_encode_fns, 0, 0 },
16526 0,
16527 Opcode_rsr_excsave5_encode_fns, 0, 0 },
16529 0,
16530 Opcode_wsr_excsave5_encode_fns, 0, 0 },
16532 0,
16533 Opcode_xsr_excsave5_encode_fns, 0, 0 },
16535 0,
16536 Opcode_rsr_epc6_encode_fns, 0, 0 },
16538 0,
16539 Opcode_wsr_epc6_encode_fns, 0, 0 },
16541 0,
16542 Opcode_xsr_epc6_encode_fns, 0, 0 },
16544 0,
16545 Opcode_rsr_excsave6_encode_fns, 0, 0 },
16547 0,
16548 Opcode_wsr_excsave6_encode_fns, 0, 0 },
16550 0,
16551 Opcode_xsr_excsave6_encode_fns, 0, 0 },
16553 0,
16554 Opcode_rsr_epc7_encode_fns, 0, 0 },
16556 0,
16557 Opcode_wsr_epc7_encode_fns, 0, 0 },
16559 0,
16560 Opcode_xsr_epc7_encode_fns, 0, 0 },
16562 0,
16563 Opcode_rsr_excsave7_encode_fns, 0, 0 },
16565 0,
16566 Opcode_wsr_excsave7_encode_fns, 0, 0 },
16568 0,
16569 Opcode_xsr_excsave7_encode_fns, 0, 0 },
16571 0,
16572 Opcode_rsr_eps2_encode_fns, 0, 0 },
16574 0,
16575 Opcode_wsr_eps2_encode_fns, 0, 0 },
16577 0,
16578 Opcode_xsr_eps2_encode_fns, 0, 0 },
16580 0,
16581 Opcode_rsr_eps3_encode_fns, 0, 0 },
16583 0,
16584 Opcode_wsr_eps3_encode_fns, 0, 0 },
16586 0,
16587 Opcode_xsr_eps3_encode_fns, 0, 0 },
16589 0,
16590 Opcode_rsr_eps4_encode_fns, 0, 0 },
16592 0,
16593 Opcode_wsr_eps4_encode_fns, 0, 0 },
16595 0,
16596 Opcode_xsr_eps4_encode_fns, 0, 0 },
16598 0,
16599 Opcode_rsr_eps5_encode_fns, 0, 0 },
16601 0,
16602 Opcode_wsr_eps5_encode_fns, 0, 0 },
16604 0,
16605 Opcode_xsr_eps5_encode_fns, 0, 0 },
16607 0,
16608 Opcode_rsr_eps6_encode_fns, 0, 0 },
16610 0,
16611 Opcode_wsr_eps6_encode_fns, 0, 0 },
16613 0,
16614 Opcode_xsr_eps6_encode_fns, 0, 0 },
16616 0,
16617 Opcode_rsr_eps7_encode_fns, 0, 0 },
16619 0,
16620 Opcode_wsr_eps7_encode_fns, 0, 0 },
16622 0,
16623 Opcode_xsr_eps7_encode_fns, 0, 0 },
16625 0,
16626 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
16628 0,
16629 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
16631 0,
16632 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
16634 0,
16635 Opcode_rsr_depc_encode_fns, 0, 0 },
16637 0,
16638 Opcode_wsr_depc_encode_fns, 0, 0 },
16640 0,
16641 Opcode_xsr_depc_encode_fns, 0, 0 },
16643 0,
16644 Opcode_rsr_exccause_encode_fns, 0, 0 },
16646 0,
16647 Opcode_wsr_exccause_encode_fns, 0, 0 },
16649 0,
16650 Opcode_xsr_exccause_encode_fns, 0, 0 },
16652 0,
16653 Opcode_rsr_misc0_encode_fns, 0, 0 },
16655 0,
16656 Opcode_wsr_misc0_encode_fns, 0, 0 },
16658 0,
16659 Opcode_xsr_misc0_encode_fns, 0, 0 },
16661 0,
16662 Opcode_rsr_misc1_encode_fns, 0, 0 },
16664 0,
16665 Opcode_wsr_misc1_encode_fns, 0, 0 },
16667 0,
16668 Opcode_xsr_misc1_encode_fns, 0, 0 },
16670 0,
16671 Opcode_rsr_prid_encode_fns, 0, 0 },
16673 0,
16674 Opcode_rsr_vecbase_encode_fns, 0, 0 },
16676 0,
16677 Opcode_wsr_vecbase_encode_fns, 0, 0 },
16679 0,
16680 Opcode_xsr_vecbase_encode_fns, 0, 0 },
16682 0,
16683 Opcode_salt_encode_fns, 0, 0 },
16685 0,
16686 Opcode_saltu_encode_fns, 0, 0 },
16688 0,
16689 Opcode_mul16s_encode_fns, 0, 0 },
16691 0,
16692 Opcode_mul16u_encode_fns, 0, 0 },
16694 0,
16695 Opcode_mull_encode_fns, 0, 0 },
16697 0,
16698 Opcode_mul_aa_hh_encode_fns, 0, 0 },
16700 0,
16701 Opcode_mul_aa_hl_encode_fns, 0, 0 },
16703 0,
16704 Opcode_mul_aa_lh_encode_fns, 0, 0 },
16706 0,
16707 Opcode_mul_aa_ll_encode_fns, 0, 0 },
16709 0,
16710 Opcode_umul_aa_hh_encode_fns, 0, 0 },
16712 0,
16713 Opcode_umul_aa_hl_encode_fns, 0, 0 },
16715 0,
16716 Opcode_umul_aa_lh_encode_fns, 0, 0 },
16718 0,
16719 Opcode_umul_aa_ll_encode_fns, 0, 0 },
16721 0,
16722 Opcode_mul_ad_hh_encode_fns, 0, 0 },
16724 0,
16725 Opcode_mul_ad_hl_encode_fns, 0, 0 },
16727 0,
16728 Opcode_mul_ad_lh_encode_fns, 0, 0 },
16730 0,
16731 Opcode_mul_ad_ll_encode_fns, 0, 0 },
16733 0,
16734 Opcode_mul_da_hh_encode_fns, 0, 0 },
16736 0,
16737 Opcode_mul_da_hl_encode_fns, 0, 0 },
16739 0,
16740 Opcode_mul_da_lh_encode_fns, 0, 0 },
16742 0,
16743 Opcode_mul_da_ll_encode_fns, 0, 0 },
16745 0,
16746 Opcode_mul_dd_hh_encode_fns, 0, 0 },
16748 0,
16749 Opcode_mul_dd_hl_encode_fns, 0, 0 },
16751 0,
16752 Opcode_mul_dd_lh_encode_fns, 0, 0 },
16754 0,
16755 Opcode_mul_dd_ll_encode_fns, 0, 0 },
16757 0,
16758 Opcode_mula_aa_hh_encode_fns, 0, 0 },
16760 0,
16761 Opcode_mula_aa_hl_encode_fns, 0, 0 },
16763 0,
16764 Opcode_mula_aa_lh_encode_fns, 0, 0 },
16766 0,
16767 Opcode_mula_aa_ll_encode_fns, 0, 0 },
16769 0,
16770 Opcode_muls_aa_hh_encode_fns, 0, 0 },
16772 0,
16773 Opcode_muls_aa_hl_encode_fns, 0, 0 },
16775 0,
16776 Opcode_muls_aa_lh_encode_fns, 0, 0 },
16778 0,
16779 Opcode_muls_aa_ll_encode_fns, 0, 0 },
16781 0,
16782 Opcode_mula_ad_hh_encode_fns, 0, 0 },
16784 0,
16785 Opcode_mula_ad_hl_encode_fns, 0, 0 },
16787 0,
16788 Opcode_mula_ad_lh_encode_fns, 0, 0 },
16790 0,
16791 Opcode_mula_ad_ll_encode_fns, 0, 0 },
16793 0,
16794 Opcode_muls_ad_hh_encode_fns, 0, 0 },
16796 0,
16797 Opcode_muls_ad_hl_encode_fns, 0, 0 },
16799 0,
16800 Opcode_muls_ad_lh_encode_fns, 0, 0 },
16802 0,
16803 Opcode_muls_ad_ll_encode_fns, 0, 0 },
16805 0,
16806 Opcode_mula_da_hh_encode_fns, 0, 0 },
16808 0,
16809 Opcode_mula_da_hl_encode_fns, 0, 0 },
16811 0,
16812 Opcode_mula_da_lh_encode_fns, 0, 0 },
16814 0,
16815 Opcode_mula_da_ll_encode_fns, 0, 0 },
16817 0,
16818 Opcode_muls_da_hh_encode_fns, 0, 0 },
16820 0,
16821 Opcode_muls_da_hl_encode_fns, 0, 0 },
16823 0,
16824 Opcode_muls_da_lh_encode_fns, 0, 0 },
16826 0,
16827 Opcode_muls_da_ll_encode_fns, 0, 0 },
16829 0,
16830 Opcode_mula_dd_hh_encode_fns, 0, 0 },
16832 0,
16833 Opcode_mula_dd_hl_encode_fns, 0, 0 },
16835 0,
16836 Opcode_mula_dd_lh_encode_fns, 0, 0 },
16838 0,
16839 Opcode_mula_dd_ll_encode_fns, 0, 0 },
16841 0,
16842 Opcode_muls_dd_hh_encode_fns, 0, 0 },
16844 0,
16845 Opcode_muls_dd_hl_encode_fns, 0, 0 },
16847 0,
16848 Opcode_muls_dd_lh_encode_fns, 0, 0 },
16850 0,
16851 Opcode_muls_dd_ll_encode_fns, 0, 0 },
16853 0,
16856 0,
16859 0,
16862 0,
16865 0,
16868 0,
16871 0,
16874 0,
16877 0,
16880 0,
16883 0,
16886 0,
16889 0,
16892 0,
16895 0,
16898 0,
16901 0,
16904 0,
16907 0,
16908 Opcode_rsr_m0_encode_fns, 0, 0 },
16910 0,
16911 Opcode_wsr_m0_encode_fns, 0, 0 },
16913 0,
16914 Opcode_xsr_m0_encode_fns, 0, 0 },
16916 0,
16917 Opcode_rsr_m1_encode_fns, 0, 0 },
16919 0,
16920 Opcode_wsr_m1_encode_fns, 0, 0 },
16922 0,
16923 Opcode_xsr_m1_encode_fns, 0, 0 },
16925 0,
16926 Opcode_rsr_m2_encode_fns, 0, 0 },
16928 0,
16929 Opcode_wsr_m2_encode_fns, 0, 0 },
16931 0,
16932 Opcode_xsr_m2_encode_fns, 0, 0 },
16934 0,
16935 Opcode_rsr_m3_encode_fns, 0, 0 },
16937 0,
16938 Opcode_wsr_m3_encode_fns, 0, 0 },
16940 0,
16941 Opcode_xsr_m3_encode_fns, 0, 0 },
16943 0,
16944 Opcode_rsr_acclo_encode_fns, 0, 0 },
16946 0,
16947 Opcode_wsr_acclo_encode_fns, 0, 0 },
16949 0,
16950 Opcode_xsr_acclo_encode_fns, 0, 0 },
16952 0,
16953 Opcode_rsr_acchi_encode_fns, 0, 0 },
16955 0,
16956 Opcode_wsr_acchi_encode_fns, 0, 0 },
16958 0,
16959 Opcode_xsr_acchi_encode_fns, 0, 0 },
16962 Opcode_rfi_encode_fns, 0, 0 },
16964 0,
16965 Opcode_waiti_encode_fns, 0, 0 },
16967 0,
16968 Opcode_rsr_interrupt_encode_fns, 0, 0 },
16970 0,
16971 Opcode_wsr_intset_encode_fns, 0, 0 },
16973 0,
16974 Opcode_wsr_intclear_encode_fns, 0, 0 },
16976 0,
16977 Opcode_rsr_intenable_encode_fns, 0, 0 },
16979 0,
16980 Opcode_wsr_intenable_encode_fns, 0, 0 },
16982 0,
16983 Opcode_xsr_intenable_encode_fns, 0, 0 },
16985 0,
16986 Opcode_break_encode_fns, 0, 0 },
16988 0,
16989 Opcode_break_n_encode_fns, 0, 0 },
16991 0,
16992 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
16994 0,
16995 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
16997 0,
16998 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
17000 0,
17001 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
17003 0,
17004 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
17006 0,
17007 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
17009 0,
17010 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
17012 0,
17013 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
17015 0,
17016 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
17018 0,
17019 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
17021 0,
17022 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
17024 0,
17025 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
17027 0,
17028 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
17030 0,
17031 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
17033 0,
17034 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
17036 0,
17037 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
17039 0,
17040 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
17042 0,
17043 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
17045 0,
17046 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
17048 0,
17049 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
17051 0,
17052 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
17054 0,
17055 Opcode_rsr_debugcause_encode_fns, 0, 0 },
17057 0,
17058 Opcode_wsr_debugcause_encode_fns, 0, 0 },
17060 0,
17061 Opcode_xsr_debugcause_encode_fns, 0, 0 },
17063 0,
17064 Opcode_rsr_icount_encode_fns, 0, 0 },
17066 0,
17067 Opcode_wsr_icount_encode_fns, 0, 0 },
17069 0,
17070 Opcode_xsr_icount_encode_fns, 0, 0 },
17072 0,
17073 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
17075 0,
17076 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
17078 0,
17079 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
17081 0,
17082 Opcode_rsr_ddr_encode_fns, 0, 0 },
17084 0,
17085 Opcode_wsr_ddr_encode_fns, 0, 0 },
17087 0,
17088 Opcode_xsr_ddr_encode_fns, 0, 0 },
17090 0,
17093 0,
17097 Opcode_rfdo_encode_fns, 0, 0 },
17100 Opcode_rfdd_encode_fns, 0, 0 },
17102 0,
17103 Opcode_wsr_mmid_encode_fns, 0, 0 },
17105 0,
17106 Opcode_andb_encode_fns, 0, 0 },
17108 0,
17109 Opcode_andbc_encode_fns, 0, 0 },
17111 0,
17112 Opcode_orb_encode_fns, 0, 0 },
17114 0,
17115 Opcode_orbc_encode_fns, 0, 0 },
17117 0,
17118 Opcode_xorb_encode_fns, 0, 0 },
17120 0,
17121 Opcode_all4_encode_fns, 0, 0 },
17123 0,
17124 Opcode_any4_encode_fns, 0, 0 },
17126 0,
17127 Opcode_all8_encode_fns, 0, 0 },
17129 0,
17130 Opcode_any8_encode_fns, 0, 0 },
17133 Opcode_bf_encode_fns, 0, 0 },
17136 Opcode_bt_encode_fns, 0, 0 },
17138 0,
17139 Opcode_movf_encode_fns, 0, 0 },
17141 0,
17142 Opcode_movt_encode_fns, 0, 0 },
17144 0,
17145 Opcode_rsr_br_encode_fns, 0, 0 },
17147 0,
17148 Opcode_wsr_br_encode_fns, 0, 0 },
17150 0,
17151 Opcode_xsr_br_encode_fns, 0, 0 },
17153 0,
17154 Opcode_rsr_ccount_encode_fns, 0, 0 },
17156 0,
17157 Opcode_wsr_ccount_encode_fns, 0, 0 },
17159 0,
17160 Opcode_xsr_ccount_encode_fns, 0, 0 },
17162 0,
17163 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
17165 0,
17166 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
17168 0,
17169 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
17171 0,
17172 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
17174 0,
17175 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
17177 0,
17178 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
17180 0,
17181 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
17183 0,
17184 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
17186 0,
17187 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
17189 0,
17190 Opcode_ihi_encode_fns, 0, 0 },
17192 0,
17193 Opcode_ipf_encode_fns, 0, 0 },
17195 0,
17196 Opcode_ihu_encode_fns, 0, 0 },
17198 0,
17199 Opcode_iiu_encode_fns, 0, 0 },
17201 0,
17202 Opcode_ipfl_encode_fns, 0, 0 },
17204 0,
17205 Opcode_iii_encode_fns, 0, 0 },
17207 0,
17210 0,
17213 0,
17216 0,
17219 0,
17220 Opcode_dhwb_encode_fns, 0, 0 },
17222 0,
17223 Opcode_dhwbi_encode_fns, 0, 0 },
17225 0,
17226 Opcode_diwbui_p_encode_fns, 0, 0 },
17228 0,
17229 Opcode_diwb_encode_fns, 0, 0 },
17231 0,
17232 Opcode_diwbi_encode_fns, 0, 0 },
17234 0,
17235 Opcode_dhi_encode_fns, 0, 0 },
17237 0,
17238 Opcode_dii_encode_fns, 0, 0 },
17240 0,
17241 Opcode_dpfr_encode_fns, 0, 0 },
17243 0,
17244 Opcode_dpfro_encode_fns, 0, 0 },
17246 0,
17247 Opcode_dpfw_encode_fns, 0, 0 },
17249 0,
17250 Opcode_dpfwo_encode_fns, 0, 0 },
17252 0,
17253 Opcode_dhu_encode_fns, 0, 0 },
17255 0,
17256 Opcode_diu_encode_fns, 0, 0 },
17258 0,
17259 Opcode_dpfl_encode_fns, 0, 0 },
17261 0,
17264 0,
17267 0,
17270 0,
17273 0,
17274 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
17276 0,
17277 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
17279 0,
17280 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
17282 0,
17283 Opcode_rsr_rasid_encode_fns, 0, 0 },
17285 0,
17286 Opcode_wsr_rasid_encode_fns, 0, 0 },
17288 0,
17289 Opcode_xsr_rasid_encode_fns, 0, 0 },
17291 0,
17292 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
17294 0,
17295 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
17297 0,
17298 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
17300 0,
17301 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
17303 0,
17304 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
17306 0,
17307 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
17309 0,
17310 Opcode_idtlb_encode_fns, 0, 0 },
17312 0,
17313 Opcode_pdtlb_encode_fns, 0, 0 },
17315 0,
17316 Opcode_rdtlb0_encode_fns, 0, 0 },
17318 0,
17319 Opcode_rdtlb1_encode_fns, 0, 0 },
17321 0,
17322 Opcode_wdtlb_encode_fns, 0, 0 },
17324 0,
17325 Opcode_iitlb_encode_fns, 0, 0 },
17327 0,
17328 Opcode_pitlb_encode_fns, 0, 0 },
17330 0,
17331 Opcode_ritlb0_encode_fns, 0, 0 },
17333 0,
17334 Opcode_ritlb1_encode_fns, 0, 0 },
17336 0,
17337 Opcode_witlb_encode_fns, 0, 0 },
17339 0,
17343 Opcode_hwwitlba_encode_fns, 0, 0 },
17345 0,
17346 Opcode_hwwdtlba_encode_fns, 0, 0 },
17348 0,
17349 Opcode_rsr_cpenable_encode_fns, 0, 0 },
17351 0,
17352 Opcode_wsr_cpenable_encode_fns, 0, 0 },
17354 0,
17355 Opcode_xsr_cpenable_encode_fns, 0, 0 },
17357 0,
17358 Opcode_clamps_encode_fns, 0, 0 },
17360 0,
17361 Opcode_max_encode_fns, 0, 0 },
17363 0,
17364 Opcode_maxu_encode_fns, 0, 0 },
17366 0,
17367 Opcode_min_encode_fns, 0, 0 },
17369 0,
17370 Opcode_minu_encode_fns, 0, 0 },
17372 0,
17373 Opcode_nsa_encode_fns, 0, 0 },
17375 0,
17376 Opcode_nsau_encode_fns, 0, 0 },
17378 0,
17379 Opcode_sext_encode_fns, 0, 0 },
17381 0,
17384 0,
17387 0,
17390 0,
17391 Opcode_rsr_scompare1_encode_fns, 0, 0 },
17393 0,
17394 Opcode_wsr_scompare1_encode_fns, 0, 0 },
17396 0,
17397 Opcode_xsr_scompare1_encode_fns, 0, 0 },
17399 0,
17400 Opcode_rsr_atomctl_encode_fns, 0, 0 },
17402 0,
17403 Opcode_wsr_atomctl_encode_fns, 0, 0 },
17405 0,
17406 Opcode_xsr_atomctl_encode_fns, 0, 0 },
17408 0,
17409 Opcode_quos_encode_fns, 0, 0 },
17411 0,
17412 Opcode_quou_encode_fns, 0, 0 },
17414 0,
17415 Opcode_rems_encode_fns, 0, 0 },
17417 0,
17418 Opcode_remu_encode_fns, 0, 0 },
17420 0,
17421 Opcode_rsr_eraccess_encode_fns, 0, 0 },
17423 0,
17424 Opcode_wsr_eraccess_encode_fns, 0, 0 },
17426 0,
17427 Opcode_xsr_eraccess_encode_fns, 0, 0 },
17429 0,
17430 Opcode_rer_encode_fns, 0, 0 },
17432 0,
17433 Opcode_wer_encode_fns, 0, 0 },
17435 0,
17436 Opcode_rur_fcr_encode_fns, 0, 0 },
17438 0,
17439 Opcode_wur_fcr_encode_fns, 0, 0 },
17441 0,
17442 Opcode_rur_fsr_encode_fns, 0, 0 },
17444 0,
17445 Opcode_wur_fsr_encode_fns, 0, 0 },
17447 0,
17448 Opcode_read_impwire_encode_fns, 0, 0 },
17450 0,
17451 Opcode_setb_expstate_encode_fns, 0, 0 },
17453 0,
17454 Opcode_clrb_expstate_encode_fns, 0, 0 },
17456 0,
17457 Opcode_wrmsk_expstate_encode_fns, 0, 0 },
17459 0,
17460 Opcode_rur_expstate_encode_fns, 0, 0 },
17462 0,
17463 Opcode_wur_expstate_encode_fns, 0, 0 },
17465 0,
17468 0,
17471 0,
17474 0,
17477 0,
17480 0,
17483 0,
17486 0,
17489 0,
17492 0,
17495 0,
17498 0,
17501 0,
17504 0,
17507 0,
17510 0,
17513 0,
17514 Opcode_abs_s_encode_fns, 0, 0 },
17516 0,
17517 Opcode_neg_s_encode_fns, 0, 0 },
17519 0,
17520 Opcode_abs_d_encode_fns, 0, 0 },
17522 0,
17523 Opcode_neg_d_encode_fns, 0, 0 },
17525 0,
17526 Opcode_mov_s_encode_fns, 0, 0 },
17528 0,
17529 Opcode_mov_d_encode_fns, 0, 0 },
17531 0,
17532 Opcode_moveqz_s_encode_fns, 0, 0 },
17534 0,
17535 Opcode_movnez_s_encode_fns, 0, 0 },
17537 0,
17538 Opcode_movltz_s_encode_fns, 0, 0 },
17540 0,
17541 Opcode_movgez_s_encode_fns, 0, 0 },
17543 0,
17544 Opcode_movf_s_encode_fns, 0, 0 },
17546 0,
17547 Opcode_movt_s_encode_fns, 0, 0 },
17549 0,
17550 Opcode_wfr_encode_fns, 0, 0 },
17552 0,
17553 Opcode_rfr_encode_fns, 0, 0 },
17555 0,
17556 Opcode_rfrd_encode_fns, 0, 0 },
17558 0,
17559 Opcode_wfrd_encode_fns, 0, 0 },
17561 0,
17562 Opcode_round_s_encode_fns, 0, 0 },
17564 0,
17565 Opcode_round_d_encode_fns, 0, 0 },
17567 0,
17568 Opcode_ceil_s_encode_fns, 0, 0 },
17570 0,
17571 Opcode_ceil_d_encode_fns, 0, 0 },
17573 0,
17574 Opcode_floor_s_encode_fns, 0, 0 },
17576 0,
17577 Opcode_floor_d_encode_fns, 0, 0 },
17579 0,
17580 Opcode_trunc_s_encode_fns, 0, 0 },
17582 0,
17583 Opcode_trunc_d_encode_fns, 0, 0 },
17585 0,
17586 Opcode_utrunc_s_encode_fns, 0, 0 },
17588 0,
17589 Opcode_utrunc_d_encode_fns, 0, 0 },
17591 0,
17592 Opcode_float_s_encode_fns, 0, 0 },
17594 0,
17595 Opcode_float_d_encode_fns, 0, 0 },
17597 0,
17598 Opcode_ufloat_s_encode_fns, 0, 0 },
17600 0,
17601 Opcode_ufloat_d_encode_fns, 0, 0 },
17603 0,
17604 Opcode_cvtd_s_encode_fns, 0, 0 },
17606 0,
17607 Opcode_cvts_d_encode_fns, 0, 0 },
17609 0,
17610 Opcode_un_s_encode_fns, 0, 0 },
17612 0,
17613 Opcode_un_d_encode_fns, 0, 0 },
17615 0,
17616 Opcode_ult_s_encode_fns, 0, 0 },
17618 0,
17619 Opcode_ult_d_encode_fns, 0, 0 },
17621 0,
17622 Opcode_ule_s_encode_fns, 0, 0 },
17624 0,
17625 Opcode_ule_d_encode_fns, 0, 0 },
17627 0,
17628 Opcode_ueq_s_encode_fns, 0, 0 },
17630 0,
17631 Opcode_ueq_d_encode_fns, 0, 0 },
17633 0,
17634 Opcode_olt_s_encode_fns, 0, 0 },
17636 0,
17637 Opcode_olt_d_encode_fns, 0, 0 },
17639 0,
17640 Opcode_ole_s_encode_fns, 0, 0 },
17642 0,
17643 Opcode_ole_d_encode_fns, 0, 0 },
17645 0,
17646 Opcode_oeq_s_encode_fns, 0, 0 },
17648 0,
17649 Opcode_oeq_d_encode_fns, 0, 0 },
17651 0,
17652 Opcode_add_s_encode_fns, 0, 0 },
17654 0,
17655 Opcode_add_d_encode_fns, 0, 0 },
17657 0,
17658 Opcode_sub_s_encode_fns, 0, 0 },
17660 0,
17661 Opcode_sub_d_encode_fns, 0, 0 },
17663 0,
17664 Opcode_mul_s_encode_fns, 0, 0 },
17666 0,
17667 Opcode_mul_d_encode_fns, 0, 0 },
17669 0,
17670 Opcode_madd_s_encode_fns, 0, 0 },
17672 0,
17673 Opcode_madd_d_encode_fns, 0, 0 },
17675 0,
17676 Opcode_msub_s_encode_fns, 0, 0 },
17678 0,
17679 Opcode_msub_d_encode_fns, 0, 0 },
17681 0,
17682 Opcode_sqrt0_s_encode_fns, 0, 0 },
17684 0,
17685 Opcode_sqrt0_d_encode_fns, 0, 0 },
17687 0,
17688 Opcode_div0_s_encode_fns, 0, 0 },
17690 0,
17691 Opcode_div0_d_encode_fns, 0, 0 },
17693 0,
17694 Opcode_recip0_s_encode_fns, 0, 0 },
17696 0,
17697 Opcode_recip0_d_encode_fns, 0, 0 },
17699 0,
17700 Opcode_rsqrt0_s_encode_fns, 0, 0 },
17702 0,
17703 Opcode_rsqrt0_d_encode_fns, 0, 0 },
17705 0,
17706 Opcode_maddn_s_encode_fns, 0, 0 },
17708 0,
17709 Opcode_maddn_d_encode_fns, 0, 0 },
17711 0,
17712 Opcode_divn_s_encode_fns, 0, 0 },
17714 0,
17715 Opcode_divn_d_encode_fns, 0, 0 },
17717 0,
17718 Opcode_const_s_encode_fns, 0, 0 },
17720 0,
17721 Opcode_const_d_encode_fns, 0, 0 },
17723 0,
17724 Opcode_nexp01_s_encode_fns, 0, 0 },
17726 0,
17727 Opcode_nexp01_d_encode_fns, 0, 0 },
17729 0,
17730 Opcode_addexp_s_encode_fns, 0, 0 },
17732 0,
17733 Opcode_addexp_d_encode_fns, 0, 0 },
17735 0,
17736 Opcode_addexpm_s_encode_fns, 0, 0 },
17738 0,
17739 Opcode_addexpm_d_encode_fns, 0, 0 },
17741 0,
17742 Opcode_mkdadj_s_encode_fns, 0, 0 },
17744 0,
17745 Opcode_mkdadj_d_encode_fns, 0, 0 },
17747 0,
17748 Opcode_mksadj_s_encode_fns, 0, 0 },
17750 0,
17751 Opcode_mksadj_d_encode_fns, 0, 0 }
18342 if (Field_op0_Slot_inst_get (insn) == 0)
18344 if (Field_op1_Slot_inst_get (insn) == 0)
18346 if (Field_op2_Slot_inst_get (insn) == 0)
18348 if (Field_r_Slot_inst_get (insn) == 0)
18350 if (Field_m_Slot_inst_get (insn) == 0 &&
18351 Field_s_Slot_inst_get (insn) == 0 &&
18352 Field_n_Slot_inst_get (insn) == 0)
18356 if (Field_n_Slot_inst_get (insn) == 0)
18365 if (Field_n_Slot_inst_get (insn) == 0)
18379 if (Field_s_Slot_inst_get (insn) == 0)
18381 if (Field_t_Slot_inst_get (insn) == 0)
18401 if (Field_t_Slot_inst_get (insn) == 0)
18403 if (Field_s_Slot_inst_get (insn) == 0)
18419 if (Field_s_Slot_inst_get (insn) == 0 &&
18420 Field_t_Slot_inst_get (insn) == 0)
18428 Field_t_Slot_inst_get (insn) == 0)
18454 if (Field_r_Slot_inst_get (insn) == 0 &&
18455 Field_t_Slot_inst_get (insn) == 0)
18458 Field_t_Slot_inst_get (insn) == 0)
18461 Field_t_Slot_inst_get (insn) == 0)
18464 Field_t_Slot_inst_get (insn) == 0)
18467 Field_thi3_Slot_inst_get (insn) == 0)
18474 Field_s_Slot_inst_get (insn) == 0)
18488 Field_t_Slot_inst_get (insn) == 0)
18501 Field_t_Slot_inst_get (insn) == 0)
18512 if (Field_s_Slot_inst_get (insn) == 0)
18536 if ((Field_op2_Slot_inst_get (insn) == 0 ||
18546 if (Field_sr_Slot_inst_get (insn) == 0)
18680 Field_s_Slot_inst_get (insn) == 0)
18683 Field_t_Slot_inst_get (insn) == 0)
18686 Field_s_Slot_inst_get (insn) == 0)
18694 if (Field_r_Slot_inst_get (insn) == 0)
18711 Field_t_Slot_inst_get (insn) == 0)
18722 if (Field_op2_Slot_inst_get (insn) == 0)
18749 if (Field_op2_Slot_inst_get (insn) == 0)
18751 if (Field_sr_Slot_inst_get (insn) == 0)
18892 if (Field_sr_Slot_inst_get (insn) == 0)
19083 if (Field_op2_Slot_inst_get (insn) == 0)
19102 if (Field_op2_Slot_inst_get (insn) == 0)
19111 if (Field_op2_Slot_inst_get (insn) == 0)
19141 if (Field_t_Slot_inst_get (insn) == 0)
19225 if (Field_op2_Slot_inst_get (insn) == 0)
19255 if (Field_t_Slot_inst_get (insn) == 0)
19287 if (Field_r_Slot_inst_get (insn) == 0 &&
19288 Field_s_Slot_inst_get (insn) == 0 &&
19289 Field_op2_Slot_inst_get (insn) == 0 &&
19293 Field_s3to1_Slot_inst_get (insn) == 0 &&
19294 Field_op2_Slot_inst_get (insn) == 0 &&
19299 Field_op2_Slot_inst_get (insn) == 0 &&
19303 Field_op2_Slot_inst_get (insn) == 0 &&
19311 if (Field_r_Slot_inst_get (insn) == 0)
19325 if (Field_t_Slot_inst_get (insn) == 0)
19343 if (Field_op1_Slot_inst_get (insn) == 0)
19354 Field_op2_Slot_inst_get (insn) == 0)
19361 if (Field_op1_Slot_inst_get (insn) == 0)
19390 if (Field_r_Slot_inst_get (insn) == 0)
19409 if (Field_op2_Slot_inst_get (insn) == 0)
19412 Field_t3_Slot_inst_get (insn) == 0 &&
19413 Field_tlo_Slot_inst_get (insn) == 0 &&
19414 Field_r3_Slot_inst_get (insn) == 0)
19417 Field_t3_Slot_inst_get (insn) == 0 &&
19418 Field_tlo_Slot_inst_get (insn) == 0 &&
19419 Field_r3_Slot_inst_get (insn) == 0)
19422 Field_t3_Slot_inst_get (insn) == 0 &&
19423 Field_tlo_Slot_inst_get (insn) == 0 &&
19424 Field_r3_Slot_inst_get (insn) == 0)
19427 Field_t3_Slot_inst_get (insn) == 0 &&
19428 Field_tlo_Slot_inst_get (insn) == 0 &&
19429 Field_r3_Slot_inst_get (insn) == 0)
19435 Field_t3_Slot_inst_get (insn) == 0 &&
19436 Field_tlo_Slot_inst_get (insn) == 0 &&
19437 Field_r3_Slot_inst_get (insn) == 0)
19440 Field_t3_Slot_inst_get (insn) == 0 &&
19441 Field_tlo_Slot_inst_get (insn) == 0 &&
19442 Field_r3_Slot_inst_get (insn) == 0)
19445 Field_t3_Slot_inst_get (insn) == 0 &&
19446 Field_tlo_Slot_inst_get (insn) == 0 &&
19447 Field_r3_Slot_inst_get (insn) == 0)
19450 Field_t3_Slot_inst_get (insn) == 0 &&
19451 Field_tlo_Slot_inst_get (insn) == 0 &&
19452 Field_r3_Slot_inst_get (insn) == 0)
19458 Field_s_Slot_inst_get (insn) == 0 &&
19459 Field_w_Slot_inst_get (insn) == 0 &&
19460 Field_r3_Slot_inst_get (insn) == 0 &&
19461 Field_t3_Slot_inst_get (insn) == 0 &&
19462 Field_tlo_Slot_inst_get (insn) == 0)
19465 Field_s_Slot_inst_get (insn) == 0 &&
19466 Field_w_Slot_inst_get (insn) == 0 &&
19467 Field_r3_Slot_inst_get (insn) == 0 &&
19468 Field_t3_Slot_inst_get (insn) == 0 &&
19469 Field_tlo_Slot_inst_get (insn) == 0)
19472 Field_s_Slot_inst_get (insn) == 0 &&
19473 Field_w_Slot_inst_get (insn) == 0 &&
19474 Field_r3_Slot_inst_get (insn) == 0 &&
19475 Field_t3_Slot_inst_get (insn) == 0 &&
19476 Field_tlo_Slot_inst_get (insn) == 0)
19479 Field_s_Slot_inst_get (insn) == 0 &&
19480 Field_w_Slot_inst_get (insn) == 0 &&
19481 Field_r3_Slot_inst_get (insn) == 0 &&
19482 Field_t3_Slot_inst_get (insn) == 0 &&
19483 Field_tlo_Slot_inst_get (insn) == 0)
19486 Field_s_Slot_inst_get (insn) == 0 &&
19487 Field_w_Slot_inst_get (insn) == 0 &&
19488 Field_r3_Slot_inst_get (insn) == 0 &&
19489 Field_t3_Slot_inst_get (insn) == 0 &&
19490 Field_tlo_Slot_inst_get (insn) == 0)
19493 Field_s_Slot_inst_get (insn) == 0 &&
19494 Field_w_Slot_inst_get (insn) == 0 &&
19495 Field_r3_Slot_inst_get (insn) == 0 &&
19496 Field_t3_Slot_inst_get (insn) == 0 &&
19497 Field_tlo_Slot_inst_get (insn) == 0)
19500 Field_s_Slot_inst_get (insn) == 0 &&
19501 Field_w_Slot_inst_get (insn) == 0 &&
19502 Field_r3_Slot_inst_get (insn) == 0 &&
19503 Field_t3_Slot_inst_get (insn) == 0 &&
19504 Field_tlo_Slot_inst_get (insn) == 0)
19507 Field_s_Slot_inst_get (insn) == 0 &&
19508 Field_w_Slot_inst_get (insn) == 0 &&
19509 Field_r3_Slot_inst_get (insn) == 0 &&
19510 Field_t3_Slot_inst_get (insn) == 0 &&
19511 Field_tlo_Slot_inst_get (insn) == 0)
19514 Field_s_Slot_inst_get (insn) == 0 &&
19515 Field_w_Slot_inst_get (insn) == 0 &&
19516 Field_r3_Slot_inst_get (insn) == 0 &&
19517 Field_t3_Slot_inst_get (insn) == 0 &&
19518 Field_tlo_Slot_inst_get (insn) == 0)
19521 Field_s_Slot_inst_get (insn) == 0 &&
19522 Field_w_Slot_inst_get (insn) == 0 &&
19523 Field_r3_Slot_inst_get (insn) == 0 &&
19524 Field_t3_Slot_inst_get (insn) == 0 &&
19525 Field_tlo_Slot_inst_get (insn) == 0)
19528 Field_s_Slot_inst_get (insn) == 0 &&
19529 Field_w_Slot_inst_get (insn) == 0 &&
19530 Field_r3_Slot_inst_get (insn) == 0 &&
19531 Field_t3_Slot_inst_get (insn) == 0 &&
19532 Field_tlo_Slot_inst_get (insn) == 0)
19535 Field_s_Slot_inst_get (insn) == 0 &&
19536 Field_w_Slot_inst_get (insn) == 0 &&
19537 Field_r3_Slot_inst_get (insn) == 0 &&
19538 Field_t3_Slot_inst_get (insn) == 0 &&
19539 Field_tlo_Slot_inst_get (insn) == 0)
19545 Field_r_Slot_inst_get (insn) == 0 &&
19546 Field_t3_Slot_inst_get (insn) == 0 &&
19547 Field_tlo_Slot_inst_get (insn) == 0)
19550 Field_r_Slot_inst_get (insn) == 0 &&
19551 Field_t3_Slot_inst_get (insn) == 0 &&
19552 Field_tlo_Slot_inst_get (insn) == 0)
19555 Field_r_Slot_inst_get (insn) == 0 &&
19556 Field_t3_Slot_inst_get (insn) == 0 &&
19557 Field_tlo_Slot_inst_get (insn) == 0)
19560 Field_r_Slot_inst_get (insn) == 0 &&
19561 Field_t3_Slot_inst_get (insn) == 0 &&
19562 Field_tlo_Slot_inst_get (insn) == 0)
19565 Field_r_Slot_inst_get (insn) == 0 &&
19566 Field_t3_Slot_inst_get (insn) == 0 &&
19567 Field_tlo_Slot_inst_get (insn) == 0)
19570 Field_r_Slot_inst_get (insn) == 0 &&
19571 Field_t3_Slot_inst_get (insn) == 0 &&
19572 Field_tlo_Slot_inst_get (insn) == 0)
19575 Field_r_Slot_inst_get (insn) == 0 &&
19576 Field_t3_Slot_inst_get (insn) == 0 &&
19577 Field_tlo_Slot_inst_get (insn) == 0)
19580 Field_r_Slot_inst_get (insn) == 0 &&
19581 Field_t3_Slot_inst_get (insn) == 0 &&
19582 Field_tlo_Slot_inst_get (insn) == 0)
19585 Field_r_Slot_inst_get (insn) == 0 &&
19586 Field_t3_Slot_inst_get (insn) == 0 &&
19587 Field_tlo_Slot_inst_get (insn) == 0)
19590 Field_r_Slot_inst_get (insn) == 0 &&
19591 Field_t3_Slot_inst_get (insn) == 0 &&
19592 Field_tlo_Slot_inst_get (insn) == 0)
19595 Field_r_Slot_inst_get (insn) == 0 &&
19596 Field_t3_Slot_inst_get (insn) == 0 &&
19597 Field_tlo_Slot_inst_get (insn) == 0)
19600 Field_r_Slot_inst_get (insn) == 0 &&
19601 Field_t3_Slot_inst_get (insn) == 0 &&
19602 Field_tlo_Slot_inst_get (insn) == 0)
19608 Field_r3_Slot_inst_get (insn) == 0)
19611 Field_r3_Slot_inst_get (insn) == 0)
19614 Field_r3_Slot_inst_get (insn) == 0)
19617 Field_r3_Slot_inst_get (insn) == 0)
19623 Field_r3_Slot_inst_get (insn) == 0)
19626 Field_r3_Slot_inst_get (insn) == 0)
19629 Field_r3_Slot_inst_get (insn) == 0)
19632 Field_r3_Slot_inst_get (insn) == 0)
19638 Field_s_Slot_inst_get (insn) == 0 &&
19639 Field_w_Slot_inst_get (insn) == 0 &&
19640 Field_r3_Slot_inst_get (insn) == 0)
19643 Field_s_Slot_inst_get (insn) == 0 &&
19644 Field_w_Slot_inst_get (insn) == 0 &&
19645 Field_r3_Slot_inst_get (insn) == 0)
19648 Field_s_Slot_inst_get (insn) == 0 &&
19649 Field_w_Slot_inst_get (insn) == 0 &&
19650 Field_r3_Slot_inst_get (insn) == 0)
19653 Field_s_Slot_inst_get (insn) == 0 &&
19654 Field_w_Slot_inst_get (insn) == 0 &&
19655 Field_r3_Slot_inst_get (insn) == 0)
19658 Field_s_Slot_inst_get (insn) == 0 &&
19659 Field_w_Slot_inst_get (insn) == 0 &&
19660 Field_r3_Slot_inst_get (insn) == 0)
19663 Field_s_Slot_inst_get (insn) == 0 &&
19664 Field_w_Slot_inst_get (insn) == 0 &&
19665 Field_r3_Slot_inst_get (insn) == 0)
19668 Field_s_Slot_inst_get (insn) == 0 &&
19669 Field_w_Slot_inst_get (insn) == 0 &&
19670 Field_r3_Slot_inst_get (insn) == 0)
19673 Field_s_Slot_inst_get (insn) == 0 &&
19674 Field_w_Slot_inst_get (insn) == 0 &&
19675 Field_r3_Slot_inst_get (insn) == 0)
19678 Field_s_Slot_inst_get (insn) == 0 &&
19679 Field_w_Slot_inst_get (insn) == 0 &&
19680 Field_r3_Slot_inst_get (insn) == 0)
19683 Field_s_Slot_inst_get (insn) == 0 &&
19684 Field_w_Slot_inst_get (insn) == 0 &&
19685 Field_r3_Slot_inst_get (insn) == 0)
19688 Field_s_Slot_inst_get (insn) == 0 &&
19689 Field_w_Slot_inst_get (insn) == 0 &&
19690 Field_r3_Slot_inst_get (insn) == 0)
19693 Field_s_Slot_inst_get (insn) == 0 &&
19694 Field_w_Slot_inst_get (insn) == 0 &&
19695 Field_r3_Slot_inst_get (insn) == 0)
19700 if (Field_op1_Slot_inst_get (insn) == 0 &&
19701 Field_r_Slot_inst_get (insn) == 0)
19704 Field_r_Slot_inst_get (insn) == 0)
19707 Field_r_Slot_inst_get (insn) == 0)
19710 Field_r_Slot_inst_get (insn) == 0)
19713 Field_r_Slot_inst_get (insn) == 0)
19716 Field_r_Slot_inst_get (insn) == 0)
19719 Field_r_Slot_inst_get (insn) == 0)
19722 Field_r_Slot_inst_get (insn) == 0)
19725 Field_r_Slot_inst_get (insn) == 0)
19728 Field_r_Slot_inst_get (insn) == 0)
19731 Field_r_Slot_inst_get (insn) == 0)
19734 Field_r_Slot_inst_get (insn) == 0)
19737 Field_r_Slot_inst_get (insn) == 0)
19740 Field_r_Slot_inst_get (insn) == 0)
19743 Field_r_Slot_inst_get (insn) == 0)
19746 Field_r_Slot_inst_get (insn) == 0)
19751 if (Field_op1_Slot_inst_get (insn) == 0 &&
19752 Field_t_Slot_inst_get (insn) == 0 &&
19753 Field_rhi_Slot_inst_get (insn) == 0)
19758 if (Field_op1_Slot_inst_get (insn) == 0 &&
19759 Field_t_Slot_inst_get (insn) == 0 &&
19760 Field_rhi_Slot_inst_get (insn) == 0)
19766 if (Field_n_Slot_inst_get (insn) == 0)
19777 if (Field_n_Slot_inst_get (insn) == 0)
19781 if (Field_m_Slot_inst_get (insn) == 0)
19792 if (Field_m_Slot_inst_get (insn) == 0)
19803 if (Field_m_Slot_inst_get (insn) == 0)
19807 if (Field_r_Slot_inst_get (insn) == 0)
19826 if (Field_r_Slot_inst_get (insn) == 0)
19865 if (Field_i_Slot_inst16b_get (insn) == 0)
19869 if (Field_z_Slot_inst16b_get (insn) == 0)
19877 if (Field_r_Slot_inst16b_get (insn) == 0)
19881 if (Field_t_Slot_inst16b_get (insn) == 0)
19888 Field_s_Slot_inst16b_get (insn) == 0)
19891 Field_s_Slot_inst16b_get (insn) == 0)
19919 slotbuf[0] = (insn[0] & 0xffffff);
19926 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
19933 slotbuf[0] = (insn[0] & 0xffff);
19940 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19947 slotbuf[0] = (insn[0] & 0xffff);
19954 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19990 0,
19991 0,
19992 0,
19993 0,
19994 0,
19995 0,
19996 0,
19997 0,
20066 0,
20067 0,
20068 0,
20069 0,
20070 0,
20071 0,
20072 0,
20073 0,
20112 0,
20113 0,
20114 0,
20115 0,
20117 0,
20118 0,
20119 0,
20120 0,
20121 0,
20122 0,
20123 0,
20125 0,
20126 0,
20128 0,
20129 0,
20130 0,
20131 0,
20132 0,
20133 0,
20134 0,
20135 0,
20136 0,
20137 0,
20138 0,
20139 0,
20140 0,
20141 0,
20148 0,
20149 0,
20150 0,
20151 0,
20152 0,
20153 0,
20154 0,
20155 0,
20156 0,
20157 0,
20158 0,
20159 0,
20160 0,
20161 0,
20162 0,
20163 0,
20164 0,
20165 0,
20166 0,
20167 0,
20168 0,
20169 0,
20170 0,
20188 0,
20189 0,
20190 0,
20191 0,
20193 0,
20194 0,
20195 0,
20196 0,
20197 0,
20198 0,
20199 0,
20201 0,
20202 0,
20204 0,
20205 0,
20206 0,
20207 0,
20208 0,
20209 0,
20210 0,
20211 0,
20212 0,
20213 0,
20214 0,
20215 0,
20216 0,
20217 0,
20224 0,
20225 0,
20226 0,
20227 0,
20228 0,
20229 0,
20230 0,
20231 0,
20232 0,
20233 0,
20234 0,
20235 0,
20236 0,
20237 0,
20238 0,
20239 0,
20240 0,
20241 0,
20242 0,
20243 0,
20244 0,
20245 0,
20246 0,
20264 0,
20265 0,
20266 0,
20267 0,
20269 0,
20270 0,
20271 0,
20272 0,
20273 0,
20274 0,
20275 0,
20277 0,
20278 0,
20280 0,
20281 0,
20282 0,
20283 0,
20284 0,
20285 0,
20286 0,
20287 0,
20288 0,
20289 0,
20290 0,
20291 0,
20292 0,
20293 0,
20302 0,
20303 0,
20304 0,
20305 0,
20306 0,
20307 0,
20308 0,
20309 0,
20310 0,
20311 0,
20312 0,
20313 0,
20314 0,
20315 0,
20316 0,
20317 0,
20318 0,
20319 0,
20320 0,
20321 0,
20322 0,
20340 0,
20341 0,
20342 0,
20343 0,
20345 0,
20346 0,
20347 0,
20348 0,
20349 0,
20350 0,
20351 0,
20353 0,
20354 0,
20356 0,
20357 0,
20358 0,
20359 0,
20360 0,
20361 0,
20362 0,
20363 0,
20364 0,
20365 0,
20366 0,
20367 0,
20368 0,
20369 0,
20378 0,
20379 0,
20380 0,
20381 0,
20382 0,
20383 0,
20384 0,
20385 0,
20386 0,
20387 0,
20388 0,
20389 0,
20390 0,
20391 0,
20392 0,
20393 0,
20394 0,
20395 0,
20396 0,
20397 0,
20398 0,
20414 { "Inst", "x24", 0,
20418 { "Inst16a", "x16a", 0,
20422 { "Inst16b", "x16b", 0,
20434 insn[0] = 0;
20440 insn[0] = 0x8;
20446 insn[0] = 0xc;
20449 static int Format_x24_slots[] = { 0 };
20465 if ((insn[0] & 0x8) == 0)
20466 return 0; /* x24 */
20467 if ((insn[0] & 0xc) == 0x8)
20469 if ((insn[0] & 0xe) == 0xc)
20736 int l = insn[0];
20744 0 /* little-endian */,
20745 3 /* insn_size */, 0,
20751 579, opcodes, 0,
20753 NUM_STATES, states, 0,
20754 NUM_SYSREGS, sysregs, 0,
20755 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
20756 1, interfaces, 0,
20757 1, funcUnits, 0