Lines Matching +full:0 +full:xd00000
32 { "LBEG", 0, 0 },
33 { "LEND", 1, 0 },
34 { "LCOUNT", 2, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
41 { "MMID", 89, 0 },
42 { "DDR", 104, 0 },
43 { "CONFIGID0", 176, 0 },
44 { "CONFIGID1", 208, 0 },
45 { "INTERRUPT", 226, 0 },
46 { "INTCLEAR", 227, 0 },
47 { "CCOUNT", 234, 0 },
48 { "PRID", 235, 0 },
49 { "ICOUNT", 236, 0 },
50 { "CCOMPARE0", 240, 0 },
51 { "CCOMPARE1", 241, 0 },
52 { "CCOMPARE2", 242, 0 },
53 { "VECBASE", 231, 0 },
54 { "EPC1", 177, 0 },
55 { "EPC2", 178, 0 },
56 { "EPC3", 179, 0 },
57 { "EPC4", 180, 0 },
58 { "EPC5", 181, 0 },
59 { "EPC6", 182, 0 },
60 { "EPC7", 183, 0 },
61 { "EXCSAVE1", 209, 0 },
62 { "EXCSAVE2", 210, 0 },
63 { "EXCSAVE3", 211, 0 },
64 { "EXCSAVE4", 212, 0 },
65 { "EXCSAVE5", 213, 0 },
66 { "EXCSAVE6", 214, 0 },
67 { "EXCSAVE7", 215, 0 },
68 { "EPS2", 194, 0 },
69 { "EPS3", 195, 0 },
70 { "EPS4", 196, 0 },
71 { "EPS5", 197, 0 },
72 { "EPS6", 198, 0 },
73 { "EPS7", 199, 0 },
74 { "EXCCAUSE", 232, 0 },
75 { "DEPC", 192, 0 },
76 { "EXCVADDR", 238, 0 },
77 { "WINDOWBASE", 72, 0 },
78 { "WINDOWSTART", 73, 0 },
79 { "SAR", 3, 0 },
80 { "PS", 230, 0 },
81 { "MISC0", 244, 0 },
82 { "MISC1", 245, 0 },
83 { "INTENABLE", 228, 0 },
84 { "DBREAKA0", 144, 0 },
85 { "DBREAKC0", 160, 0 },
86 { "DBREAKA1", 145, 0 },
87 { "DBREAKC1", 161, 0 },
88 { "IBREAKA0", 128, 0 },
89 { "IBREAKA1", 129, 0 },
90 { "IBREAKENABLE", 96, 0 },
91 { "ICOUNTLEVEL", 237, 0 },
92 { "DEBUGCAUSE", 233, 0 },
93 { "SCOMPARE1", 12, 0 },
94 { "ATOMCTL", 99, 0 },
106 { "LCOUNT", 32, 0 },
107 { "PC", 32, 0 },
108 { "ICOUNT", 32, 0 },
109 { "DDR", 32, 0 },
110 { "INTERRUPT", 22, 0 },
111 { "CCOUNT", 32, 0 },
112 { "XTSYNC", 1, 0 },
113 { "VECBASE", 22, 0 },
114 { "EPC1", 32, 0 },
115 { "EPC2", 32, 0 },
116 { "EPC3", 32, 0 },
117 { "EPC4", 32, 0 },
118 { "EPC5", 32, 0 },
119 { "EPC6", 32, 0 },
120 { "EPC7", 32, 0 },
121 { "EXCSAVE1", 32, 0 },
122 { "EXCSAVE2", 32, 0 },
123 { "EXCSAVE3", 32, 0 },
124 { "EXCSAVE4", 32, 0 },
125 { "EXCSAVE5", 32, 0 },
126 { "EXCSAVE6", 32, 0 },
127 { "EXCSAVE7", 32, 0 },
128 { "EPS2", 13, 0 },
129 { "EPS3", 13, 0 },
130 { "EPS4", 13, 0 },
131 { "EPS5", 13, 0 },
132 { "EPS6", 13, 0 },
133 { "EPS7", 13, 0 },
134 { "EXCCAUSE", 6, 0 },
135 { "PSINTLEVEL", 4, 0 },
136 { "PSUM", 1, 0 },
137 { "PSWOE", 1, 0 },
138 { "PSEXCM", 1, 0 },
139 { "DEPC", 32, 0 },
140 { "EXCVADDR", 32, 0 },
141 { "WindowBase", 3, 0 },
142 { "WindowStart", 8, 0 },
143 { "PSCALLINC", 2, 0 },
144 { "PSOWB", 4, 0 },
145 { "LBEG", 32, 0 },
146 { "LEND", 32, 0 },
147 { "SAR", 6, 0 },
148 { "MISC0", 32, 0 },
149 { "MISC1", 32, 0 },
150 { "ACC", 40, 0 },
151 { "InOCDMode", 1, 0 },
152 { "INTENABLE", 22, 0 },
153 { "DBREAKA0", 32, 0 },
154 { "DBREAKC0", 8, 0 },
155 { "DBREAKA1", 32, 0 },
156 { "DBREAKC1", 8, 0 },
157 { "IBREAKA0", 32, 0 },
158 { "IBREAKA1", 32, 0 },
159 { "IBREAKENABLE", 2, 0 },
160 { "ICOUNTLEVEL", 4, 0 },
161 { "DEBUGCAUSE", 6, 0 },
162 { "DBNUM", 4, 0 },
163 { "CCOMPARE0", 32, 0 },
164 { "CCOMPARE1", 32, 0 },
165 { "CCOMPARE2", 32, 0 },
166 { "SCOMPARE1", 32, 0 },
167 { "ATOMCTL", 6, 0 },
168 { "ERI_RAW_INTERLOCK", 1, 0 },
247 unsigned tie_t = 0;
248 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
257 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
263 unsigned tie_t = 0;
264 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
273 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
279 unsigned tie_t = 0;
280 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
289 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
295 unsigned tie_t = 0;
296 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
305 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
311 unsigned tie_t = 0;
312 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
321 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
327 unsigned tie_t = 0;
328 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
337 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
343 unsigned tie_t = 0;
344 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
353 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
359 unsigned tie_t = 0;
360 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
369 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
375 unsigned tie_t = 0;
376 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
377 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
386 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
388 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
394 unsigned tie_t = 0;
395 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
404 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
410 unsigned tie_t = 0;
411 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
420 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
426 unsigned tie_t = 0;
427 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
436 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
442 unsigned tie_t = 0;
443 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
452 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
458 unsigned tie_t = 0;
459 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
468 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
474 unsigned tie_t = 0;
475 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
484 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
490 unsigned tie_t = 0;
491 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
492 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
501 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
503 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
509 unsigned tie_t = 0;
510 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
519 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
525 unsigned tie_t = 0;
526 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
535 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
541 unsigned tie_t = 0;
542 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
551 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
557 unsigned tie_t = 0;
558 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
567 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
573 unsigned tie_t = 0;
574 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
583 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
589 unsigned tie_t = 0;
590 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
599 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
605 unsigned tie_t = 0;
606 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
615 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
621 unsigned tie_t = 0;
622 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
631 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
637 unsigned tie_t = 0;
638 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
647 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
653 unsigned tie_t = 0;
654 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
663 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
669 unsigned tie_t = 0;
670 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
671 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
680 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
682 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
688 unsigned tie_t = 0;
689 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
698 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
704 unsigned tie_t = 0;
705 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
714 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
720 unsigned tie_t = 0;
721 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
730 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
736 unsigned tie_t = 0;
737 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
738 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
747 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
749 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
755 unsigned tie_t = 0;
756 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
765 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
771 unsigned tie_t = 0;
772 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
781 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
787 unsigned tie_t = 0;
788 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
797 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
803 unsigned tie_t = 0;
804 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
813 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
819 unsigned tie_t = 0;
820 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
829 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
835 unsigned tie_t = 0;
836 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
837 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
846 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
848 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
854 unsigned tie_t = 0;
855 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
856 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
865 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
867 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
873 unsigned tie_t = 0;
874 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
875 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
884 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
886 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
892 unsigned tie_t = 0;
893 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
902 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
908 unsigned tie_t = 0;
909 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
910 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
919 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
921 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
927 unsigned tie_t = 0;
928 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
929 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
938 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
940 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
946 unsigned tie_t = 0;
947 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
948 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
957 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
959 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
965 unsigned tie_t = 0;
966 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
967 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
976 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
978 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
984 unsigned tie_t = 0;
985 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
986 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
995 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
997 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1003 unsigned tie_t = 0;
1004 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1013 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1019 unsigned tie_t = 0;
1020 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1029 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1035 unsigned tie_t = 0;
1036 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1045 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1051 unsigned tie_t = 0;
1052 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1053 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1062 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1064 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1070 unsigned tie_t = 0;
1071 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1080 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1086 unsigned tie_t = 0;
1087 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1096 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1102 unsigned tie_t = 0;
1103 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1112 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1118 unsigned tie_t = 0;
1119 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1128 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1134 unsigned tie_t = 0;
1135 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1144 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1150 unsigned tie_t = 0;
1151 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1160 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1166 unsigned tie_t = 0;
1167 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1176 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1182 unsigned tie_t = 0;
1183 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1192 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1198 unsigned tie_t = 0;
1199 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1208 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1214 unsigned tie_t = 0;
1215 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1224 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1230 unsigned tie_t = 0;
1231 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1232 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1241 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1243 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1249 unsigned tie_t = 0;
1250 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1251 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1260 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1262 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1268 unsigned tie_t = 0;
1269 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1270 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1279 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1281 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1287 unsigned tie_t = 0;
1288 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1289 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1298 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1300 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1306 unsigned tie_t = 0;
1307 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1316 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1322 unsigned tie_t = 0;
1323 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1332 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1338 unsigned tie_t = 0;
1339 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1348 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1354 unsigned tie_t = 0;
1355 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1364 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1370 unsigned tie_t = 0;
1371 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1380 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1386 unsigned tie_t = 0;
1387 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1396 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1402 unsigned tie_t = 0;
1403 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1404 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1413 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1415 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1421 unsigned tie_t = 0;
1422 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1423 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1432 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1434 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1440 unsigned tie_t = 0;
1441 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1442 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1451 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1453 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1459 unsigned tie_t = 0;
1460 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1469 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1475 unsigned tie_t = 0;
1476 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1485 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1498 return 0;
1522 return 0;
1605 #define funcUnits 0
1624 { "ERI_RD_Out", 14, 0, 0, 'o' },
1625 { "ERI_RD_In", 32, 0, 1, 'i' },
1626 { "ERI_RD_Rdy", 1, 0, 0, 'i' },
1627 { "ERI_WR_Out", 46, 0, 2, 'o' },
1628 { "ERI_WR_In", 1, 0, 3, 'i' },
1629 { "IMPWIRE", 32, 0, 4, 'i' }
1646 0xffffffff,
1647 0x1,
1648 0x2,
1649 0x3,
1650 0x4,
1651 0x5,
1652 0x6,
1653 0x7,
1654 0x8,
1655 0x9,
1656 0xa,
1657 0xb,
1658 0xc,
1659 0xd,
1660 0xe,
1661 0xf,
1662 0
1667 0xffffffff,
1668 0x1,
1669 0x2,
1670 0x3,
1671 0x4,
1672 0x5,
1673 0x6,
1674 0x7,
1675 0x8,
1676 0xa,
1677 0xc,
1678 0x10,
1679 0x20,
1680 0x40,
1681 0x80,
1682 0x100,
1683 0
1688 0x8000,
1689 0x10000,
1690 0x2,
1691 0x3,
1692 0x4,
1693 0x5,
1694 0x6,
1695 0x7,
1696 0x8,
1697 0xa,
1698 0xc,
1699 0x10,
1700 0x20,
1701 0x40,
1702 0x80,
1703 0x100,
1704 0
1714 return 0;
1721 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
1731 soffsetx4_in_0 = *valp & 0x3ffff;
1732 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1734 return 0;
1743 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1745 return 0;
1753 uimm12x8_in_0 = *valp & 0xfff;
1756 return 0;
1765 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1767 return 0;
1775 simm4_in_0 = *valp & 0xf;
1778 return 0;
1787 simm4_in_0 = (simm4_out_0 & 0xf);
1789 return 0;
1795 return 0;
1807 return 0;
1819 return 0;
1831 return 0;
1843 return 0;
1855 return 0;
1869 immrx4_in_0 = *valp & 0xf;
1870 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1872 return 0;
1881 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1883 return 0;
1891 lsi4x4_in_0 = *valp & 0xf;
1894 return 0;
1903 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1905 return 0;
1913 simm7_in_0 = *valp & 0x7f;
1914 …simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | …
1916 return 0;
1925 simm7_in_0 = (simm7_out_0 & 0x7f);
1927 return 0;
1935 uimm6_in_0 = *valp & 0x3f;
1936 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1938 return 0;
1947 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1949 return 0;
1957 ai4const_in_0 = *valp & 0xf;
1958 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1960 return 0;
1971 case 0xffffffff: ai4const_in_0 = 0; break;
1972 case 0x1: ai4const_in_0 = 0x1; break;
1973 case 0x2: ai4const_in_0 = 0x2; break;
1974 case 0x3: ai4const_in_0 = 0x3; break;
1975 case 0x4: ai4const_in_0 = 0x4; break;
1976 case 0x5: ai4const_in_0 = 0x5; break;
1977 case 0x6: ai4const_in_0 = 0x6; break;
1978 case 0x7: ai4const_in_0 = 0x7; break;
1979 case 0x8: ai4const_in_0 = 0x8; break;
1980 case 0x9: ai4const_in_0 = 0x9; break;
1981 case 0xa: ai4const_in_0 = 0xa; break;
1982 case 0xb: ai4const_in_0 = 0xb; break;
1983 case 0xc: ai4const_in_0 = 0xc; break;
1984 case 0xd: ai4const_in_0 = 0xd; break;
1985 case 0xe: ai4const_in_0 = 0xe; break;
1986 default: ai4const_in_0 = 0xf; break;
1989 return 0;
1997 b4const_in_0 = *valp & 0xf;
1998 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
2000 return 0;
2011 case 0xffffffff: b4const_in_0 = 0; break;
2012 case 0x1: b4const_in_0 = 0x1; break;
2013 case 0x2: b4const_in_0 = 0x2; break;
2014 case 0x3: b4const_in_0 = 0x3; break;
2015 case 0x4: b4const_in_0 = 0x4; break;
2016 case 0x5: b4const_in_0 = 0x5; break;
2017 case 0x6: b4const_in_0 = 0x6; break;
2018 case 0x7: b4const_in_0 = 0x7; break;
2019 case 0x8: b4const_in_0 = 0x8; break;
2020 case 0xa: b4const_in_0 = 0x9; break;
2021 case 0xc: b4const_in_0 = 0xa; break;
2022 case 0x10: b4const_in_0 = 0xb; break;
2023 case 0x20: b4const_in_0 = 0xc; break;
2024 case 0x40: b4const_in_0 = 0xd; break;
2025 case 0x80: b4const_in_0 = 0xe; break;
2026 default: b4const_in_0 = 0xf; break;
2029 return 0;
2037 b4constu_in_0 = *valp & 0xf;
2038 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
2040 return 0;
2051 case 0x8000: b4constu_in_0 = 0; break;
2052 case 0x10000: b4constu_in_0 = 0x1; break;
2053 case 0x2: b4constu_in_0 = 0x2; break;
2054 case 0x3: b4constu_in_0 = 0x3; break;
2055 case 0x4: b4constu_in_0 = 0x4; break;
2056 case 0x5: b4constu_in_0 = 0x5; break;
2057 case 0x6: b4constu_in_0 = 0x6; break;
2058 case 0x7: b4constu_in_0 = 0x7; break;
2059 case 0x8: b4constu_in_0 = 0x8; break;
2060 case 0xa: b4constu_in_0 = 0x9; break;
2061 case 0xc: b4constu_in_0 = 0xa; break;
2062 case 0x10: b4constu_in_0 = 0xb; break;
2063 case 0x20: b4constu_in_0 = 0xc; break;
2064 case 0x40: b4constu_in_0 = 0xd; break;
2065 case 0x80: b4constu_in_0 = 0xe; break;
2066 default: b4constu_in_0 = 0xf; break;
2069 return 0;
2077 uimm8_in_0 = *valp & 0xff;
2080 return 0;
2089 uimm8_in_0 = (uimm8_out_0 & 0xff);
2091 return 0;
2099 uimm8x2_in_0 = *valp & 0xff;
2102 return 0;
2111 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
2113 return 0;
2121 uimm8x4_in_0 = *valp & 0xff;
2124 return 0;
2133 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
2135 return 0;
2143 uimm4x16_in_0 = *valp & 0xf;
2146 return 0;
2155 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
2157 return 0;
2165 uimmrx4_in_0 = *valp & 0xf;
2168 return 0;
2177 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
2179 return 0;
2187 simm8_in_0 = *valp & 0xff;
2190 return 0;
2199 simm8_in_0 = (simm8_out_0 & 0xff);
2201 return 0;
2209 simm8x256_in_0 = *valp & 0xff;
2212 return 0;
2221 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
2223 return 0;
2231 simm12b_in_0 = *valp & 0xfff;
2234 return 0;
2243 simm12b_in_0 = (simm12b_out_0 & 0xfff);
2245 return 0;
2253 msalp32_in_0 = *valp & 0x1f;
2254 msalp32_out_0 = 0x20 - msalp32_in_0;
2256 return 0;
2265 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2267 return 0;
2275 op2p1_in_0 = *valp & 0xf;
2276 op2p1_out_0 = op2p1_in_0 + 0x1;
2278 return 0;
2287 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2289 return 0;
2297 label8_in_0 = *valp & 0xff;
2298 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2300 return 0;
2309 label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2311 return 0;
2319 ulabel8_in_0 = *valp & 0xff;
2320 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
2322 return 0;
2331 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
2333 return 0;
2341 label12_in_0 = *valp & 0xfff;
2342 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2344 return 0;
2353 label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2355 return 0;
2363 soffset_in_0 = *valp & 0x3ffff;
2364 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2366 return 0;
2375 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2377 return 0;
2385 uimm16x4_in_0 = *valp & 0xffff;
2386 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2388 return 0;
2397 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2399 return 0;
2407 bbi_in_0 = *valp & 0x1f;
2408 bbi_out_0 = (0 << 5) | bbi_in_0;
2410 return 0;
2419 bbi_in_0 = (bbi_out_0 & 0x1f);
2421 return 0;
2429 s_in_0 = *valp & 0xf;
2430 s_out_0 = (0 << 4) | s_in_0;
2432 return 0;
2441 s_in_0 = (s_out_0 & 0xf);
2443 return 0;
2449 return 0;
2461 return 0;
2473 return 0;
2485 return 0;
2497 return 0;
2509 return 0;
2523 immt_in_0 = *valp & 0xf;
2526 return 0;
2535 immt_in_0 = immt_out_0 & 0xf;
2537 return 0;
2545 tp7_in_0 = *valp & 0xf;
2546 tp7_out_0 = tp7_in_0 + 0x7;
2548 return 0;
2557 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2559 return 0;
2567 xt_wbr15_label_in_0 = *valp & 0x7fff;
2568 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2570 return 0;
2579 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2581 return 0;
2589 xt_wbr18_label_in_0 = *valp & 0x3ffff;
2590 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2592 return 0;
2601 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2603 return 0;
2611 bitindex_in_0 = *valp & 0x1f;
2612 bitindex_out_0 = (0 << 5) | bitindex_in_0;
2614 return 0;
2623 bitindex_in_0 = (bitindex_out_0 & 0x1f);
2625 return 0;
2631 *valp -= (pc & ~0x3);
2632 return 0;
2638 *valp += (pc & ~0x3);
2639 return 0;
2646 return 0;
2653 return 0;
2660 return 0;
2667 return 0;
2674 return 0;
2681 return 0;
2688 return 0;
2695 return 0;
2702 return 0;
2709 return 0;
2715 *valp -= ((pc + 3) & ~0x3);
2716 return 0;
2722 *valp += ((pc + 3) & ~0x3);
2723 return 0;
2730 return 0;
2737 return 0;
2744 return 0;
2751 return 0;
2755 { "soffsetx4", FIELD_offset, -1, 0,
2759 { "uimm12x8", FIELD_imm12, -1, 0,
2760 0,
2762 0, 0 },
2763 { "simm4", FIELD_mn, -1, 0,
2764 0,
2766 0, 0 },
2770 0, 0 },
2774 0, 0 },
2778 0, 0 },
2782 0, 0 },
2786 0, 0 },
2790 0, 0 },
2794 0, 0 },
2798 0, 0 },
2802 0, 0 },
2803 { "immrx4", FIELD_r, -1, 0,
2804 0,
2806 0, 0 },
2807 { "lsi4x4", FIELD_r, -1, 0,
2808 0,
2810 0, 0 },
2811 { "simm7", FIELD_imm7, -1, 0,
2812 0,
2814 0, 0 },
2815 { "uimm6", FIELD_imm6, -1, 0,
2819 { "ai4const", FIELD_t, -1, 0,
2820 0,
2822 0, 0 },
2823 { "b4const", FIELD_r, -1, 0,
2824 0,
2826 0, 0 },
2827 { "b4constu", FIELD_r, -1, 0,
2828 0,
2830 0, 0 },
2831 { "uimm8", FIELD_imm8, -1, 0,
2832 0,
2834 0, 0 },
2835 { "uimm8x2", FIELD_imm8, -1, 0,
2836 0,
2838 0, 0 },
2839 { "uimm8x4", FIELD_imm8, -1, 0,
2840 0,
2842 0, 0 },
2843 { "uimm4x16", FIELD_op2, -1, 0,
2844 0,
2846 0, 0 },
2847 { "uimmrx4", FIELD_r, -1, 0,
2848 0,
2850 0, 0 },
2851 { "simm8", FIELD_imm8, -1, 0,
2852 0,
2854 0, 0 },
2855 { "simm8x256", FIELD_imm8, -1, 0,
2856 0,
2858 0, 0 },
2859 { "simm12b", FIELD_imm12b, -1, 0,
2860 0,
2862 0, 0 },
2863 { "msalp32", FIELD_sal, -1, 0,
2864 0,
2866 0, 0 },
2867 { "op2p1", FIELD_op2, -1, 0,
2868 0,
2870 0, 0 },
2871 { "label8", FIELD_imm8, -1, 0,
2875 { "ulabel8", FIELD_imm8, -1, 0,
2879 { "label12", FIELD_imm12, -1, 0,
2883 { "soffset", FIELD_offset, -1, 0,
2887 { "uimm16x4", FIELD_imm16, -1, 0,
2891 { "bbi", FIELD_bbi, -1, 0,
2892 0,
2894 0, 0 },
2895 { "sae", FIELD_sae, -1, 0,
2896 0,
2898 0, 0 },
2899 { "sas", FIELD_sas, -1, 0,
2900 0,
2902 0, 0 },
2903 { "sargt", FIELD_sargt, -1, 0,
2904 0,
2906 0, 0 },
2907 { "s", FIELD_s, -1, 0,
2908 0,
2910 0, 0 },
2914 0, 0 },
2918 0, 0 },
2922 0, 0 },
2926 0, 0 },
2930 0, 0 },
2934 0, 0 },
2938 0, 0 },
2939 { "immt", FIELD_t, -1, 0,
2940 0,
2942 0, 0 },
2943 { "imms", FIELD_s, -1, 0,
2944 0,
2946 0, 0 },
2947 { "tp7", FIELD_t, -1, 0,
2948 0,
2950 0, 0 },
2951 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2955 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2959 { "bitindex", FIELD_bitindex, -1, 0,
2960 0,
2962 0, 0 },
2963 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2964 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2965 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2966 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2967 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2968 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2969 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2970 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2971 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2972 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2973 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2974 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2975 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
2976 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
2977 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
2978 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
2979 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
2980 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
2981 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
2982 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
2983 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
2984 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
2985 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
2986 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
2987 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
2988 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
2989 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
2990 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
2991 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
2992 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
2993 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
2994 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
2995 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
2996 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
2997 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
2998 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
2999 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
3000 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
3001 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
3002 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
3003 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
3004 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
5415 { 0, 0 /* xt_iclass_excw */,
5416 0, 0, 0, 0 },
5417 { 0, 0 /* xt_iclass_rfe */,
5418 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5419 { 0, 0 /* xt_iclass_rfde */,
5420 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5421 { 0, 0 /* xt_iclass_syscall */,
5422 0, 0, 0, 0 },
5424 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5426 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5428 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5430 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5432 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5434 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5436 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5438 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5440 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5442 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5443 { 0, 0 /* xt_iclass_rfwou */,
5444 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5446 0, 0, 0, 0 },
5448 0, 0, 0, 0 },
5450 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5452 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5454 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5456 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5458 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5460 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5462 0, 0, 0, 0 },
5464 0, 0, 0, 0 },
5466 0, 0, 0, 0 },
5467 { 0, 0 /* xt_iclass_ill_n */,
5468 0, 0, 0, 0 },
5470 0, 0, 0, 0 },
5472 0, 0, 0, 0 },
5474 0, 0, 0, 0 },
5475 { 0, 0 /* xt_iclass_nopn */,
5476 0, 0, 0, 0 },
5478 0, 0, 0, 0 },
5480 0, 0, 0, 0 },
5482 0, 0, 0, 0 },
5484 0, 0, 0, 0 },
5486 0, 0, 0, 0 },
5488 0, 0, 0, 0 },
5490 0, 0, 0, 0 },
5492 0, 0, 0, 0 },
5494 0, 0, 0, 0 },
5496 0, 0, 0, 0 },
5498 0, 0, 0, 0 },
5500 0, 0, 0, 0 },
5502 0, 0, 0, 0 },
5504 0, 0, 0, 0 },
5505 { 0, 0 /* xt_iclass_ill */,
5506 0, 0, 0, 0 },
5508 0, 0, 0, 0 },
5510 0, 0, 0, 0 },
5512 0, 0, 0, 0 },
5514 0, 0, 0, 0 },
5516 0, 0, 0, 0 },
5518 0, 0, 0, 0 },
5520 0, 0, 0, 0 },
5522 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5524 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5526 0, 0, 0, 0 },
5528 0, 0, 0, 0 },
5530 0, 0, 0, 0 },
5531 { 0, 0 /* xt_iclass_nop */,
5532 0, 0, 0, 0 },
5534 0, 0, 0, 0 },
5535 { 0, 0 /* xt_iclass_simcall */,
5536 0, 0, 0, 0 },
5538 0, 0, 0, 0 },
5540 0, 0, 0, 0 },
5542 0, 0, 0, 0 },
5544 0, 0, 0, 0 },
5546 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5548 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5550 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5552 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5554 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5556 0, 0, 0, 0 },
5558 0, 0, 0, 0 },
5560 0, 0, 0, 0 },
5561 { 0, 0 /* xt_iclass_memw */,
5562 0, 0, 0, 0 },
5563 { 0, 0 /* xt_iclass_extw */,
5564 0, 0, 0, 0 },
5565 { 0, 0 /* xt_iclass_isync */,
5566 0, 0, 0, 0 },
5567 { 0, 0 /* xt_iclass_sync */,
5568 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5570 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5572 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5574 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5576 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5578 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5580 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5582 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5584 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5586 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5588 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5590 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5592 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5594 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5596 0, 0, 0, 0 },
5598 0, 0, 0, 0 },
5600 0, 0, 0, 0 },
5602 0, 0, 0, 0 },
5604 0, 0, 0, 0 },
5606 0, 0, 0, 0 },
5608 0, 0, 0, 0 },
5610 0, 0, 0, 0 },
5612 0, 0, 0, 0 },
5614 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5616 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5618 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5620 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5622 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5624 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5626 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5628 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5630 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5632 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5634 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5636 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5638 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5640 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5642 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5644 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5646 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5648 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5650 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5652 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5654 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5656 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5658 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5660 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5662 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5664 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5666 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5668 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5670 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5672 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5674 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5676 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5678 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5680 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5682 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5684 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5686 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5688 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5690 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5692 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5694 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5696 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5698 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5700 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5702 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5704 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5706 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5708 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5710 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5712 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5714 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5716 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5718 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5720 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5722 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5724 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5726 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5728 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5730 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5732 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5734 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5736 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5738 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5740 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5742 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5744 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5746 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5748 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5750 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5752 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5754 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5756 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5758 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5760 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5762 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5764 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5766 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5768 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5770 0, 0, 0, 0 },
5772 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5774 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5776 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
5778 0, 0, 0, 0 },
5780 0, 0, 0, 0 },
5782 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
5784 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
5786 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
5788 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
5790 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
5792 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
5794 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
5796 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
5798 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
5800 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
5802 0, 0, 0, 0 },
5804 0, 0, 0, 0 },
5806 0, 0, 0, 0 },
5808 0, 0, 0, 0 },
5810 0, 0, 0, 0 },
5812 0, 0, 0, 0 },
5814 0, 0, 0, 0 },
5816 0, 0, 0, 0 },
5818 0, 0, 0, 0 },
5820 0, 0, 0, 0 },
5822 0, 0, 0, 0 },
5824 0, 0, 0, 0 },
5826 0, 0, 0, 0 },
5828 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
5830 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
5832 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
5834 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
5836 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
5838 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
5840 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
5842 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
5844 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5846 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5848 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5850 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5852 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5854 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5856 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5858 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5860 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5862 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5864 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5866 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5868 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5870 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5872 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5874 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5876 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5878 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5880 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5882 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5884 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5886 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5888 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5890 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5892 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5894 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5896 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5898 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5900 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5902 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5904 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5906 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5908 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5910 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5912 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5914 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5916 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5918 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5920 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5922 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5924 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5926 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
5928 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
5930 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5931 { 0, 0 /* xt_iclass_rfdd */,
5932 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5934 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5936 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5938 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5940 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5942 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5944 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5946 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5948 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5950 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5952 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5954 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5956 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5958 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5960 0, 0, 0, 0 },
5962 0, 0, 0, 0 },
5964 0, 0, 0, 0 },
5966 0, 0, 0, 0 },
5968 0, 0, 0, 0 },
5970 0, 0, 0, 0 },
5972 0, 0, 0, 0 },
5974 0, 0, 0, 0 },
5976 0, 0, 0, 0 },
5978 0, 0, 0, 0 },
5980 0, 0, 0, 0 },
5982 0, 0, 0, 0 },
5984 0, 0, 0, 0 },
5986 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
5988 0, 0, 0, 0 },
5990 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
5992 0, 0, 0, 0 },
5994 0, 0, 0, 0 },
5996 0, 0, 0, 0 },
5998 0, 0, 0, 0 },
6000 0, 0, 0, 0 },
6002 0, 0, 0, 0 },
6004 0, 0, 0, 0 },
6006 0, 0, 0, 0 },
6008 0, 0, 0, 0 },
6010 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6012 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6014 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6016 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6018 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
6020 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
6022 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
6024 0, 0, 0, 0 },
6030 1, Iclass_rur_expstate_stateArgs, 0, 0 },
6032 1, Iclass_wur_expstate_stateArgs, 0, 0 },
6034 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
6036 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6038 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6040 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6365 slotbuf[0] = 0x2080;
6371 slotbuf[0] = 0x3000;
6377 slotbuf[0] = 0x3200;
6383 slotbuf[0] = 0x5000;
6389 slotbuf[0] = 0x35;
6395 slotbuf[0] = 0x25;
6401 slotbuf[0] = 0x15;
6407 slotbuf[0] = 0xf0;
6413 slotbuf[0] = 0xe0;
6419 slotbuf[0] = 0xd0;
6425 slotbuf[0] = 0x36;
6431 slotbuf[0] = 0x1000;
6437 slotbuf[0] = 0x408000;
6443 slotbuf[0] = 0x90;
6449 slotbuf[0] = 0xf01d;
6455 slotbuf[0] = 0x3400;
6461 slotbuf[0] = 0x3500;
6467 slotbuf[0] = 0x90000;
6473 slotbuf[0] = 0x490000;
6479 slotbuf[0] = 0x34800;
6485 slotbuf[0] = 0x134800;
6491 slotbuf[0] = 0x614800;
6497 slotbuf[0] = 0x34900;
6503 slotbuf[0] = 0x134900;
6509 slotbuf[0] = 0x614900;
6515 slotbuf[0] = 0xa;
6521 slotbuf[0] = 0xb;
6527 slotbuf[0] = 0x8c;
6533 slotbuf[0] = 0xcc;
6539 slotbuf[0] = 0xf06d;
6545 slotbuf[0] = 0x8;
6551 slotbuf[0] = 0xd;
6557 slotbuf[0] = 0xc;
6563 slotbuf[0] = 0xf03d;
6569 slotbuf[0] = 0xf00d;
6575 slotbuf[0] = 0x9;
6581 slotbuf[0] = 0xc002;
6587 slotbuf[0] = 0xd002;
6593 slotbuf[0] = 0x800000;
6599 slotbuf[0] = 0xc00000;
6605 slotbuf[0] = 0x900000;
6611 slotbuf[0] = 0xa00000;
6617 slotbuf[0] = 0xb00000;
6623 slotbuf[0] = 0xd00000;
6629 slotbuf[0] = 0xe00000;
6635 slotbuf[0] = 0xf00000;
6641 slotbuf[0] = 0x100000;
6647 slotbuf[0] = 0x200000;
6653 slotbuf[0] = 0x300000;
6659 slotbuf[0] = 0x26;
6665 slotbuf[0] = 0x66;
6671 slotbuf[0] = 0xe6;
6677 slotbuf[0] = 0xa6;
6683 slotbuf[0] = 0x6007;
6689 slotbuf[0] = 0xe007;
6695 slotbuf[0] = 0xf6;
6701 slotbuf[0] = 0xb6;
6707 slotbuf[0] = 0x1007;
6713 slotbuf[0] = 0x9007;
6719 slotbuf[0] = 0xa007;
6725 slotbuf[0] = 0x2007;
6731 slotbuf[0] = 0xb007;
6737 slotbuf[0] = 0x3007;
6743 slotbuf[0] = 0x8007;
6749 slotbuf[0] = 0x7;
6755 slotbuf[0] = 0x4007;
6761 slotbuf[0] = 0xc007;
6767 slotbuf[0] = 0x5007;
6773 slotbuf[0] = 0xd007;
6779 slotbuf[0] = 0x16;
6785 slotbuf[0] = 0x56;
6791 slotbuf[0] = 0xd6;
6797 slotbuf[0] = 0x96;
6803 slotbuf[0] = 0x5;
6809 slotbuf[0] = 0xc0;
6815 slotbuf[0] = 0x40000;
6821 slotbuf[0] = 0;
6827 slotbuf[0] = 0x6;
6833 slotbuf[0] = 0xa0;
6839 slotbuf[0] = 0x1002;
6845 slotbuf[0] = 0x9002;
6851 slotbuf[0] = 0x2002;
6857 slotbuf[0] = 0x1;
6863 slotbuf[0] = 0x2;
6869 slotbuf[0] = 0x8076;
6875 slotbuf[0] = 0x9076;
6881 slotbuf[0] = 0xa076;
6887 slotbuf[0] = 0xa002;
6893 slotbuf[0] = 0x830000;
6899 slotbuf[0] = 0x930000;
6905 slotbuf[0] = 0xa30000;
6911 slotbuf[0] = 0xb30000;
6917 slotbuf[0] = 0x600000;
6923 slotbuf[0] = 0x600100;
6929 slotbuf[0] = 0x20f0;
6935 slotbuf[0] = 0x80;
6941 slotbuf[0] = 0x5100;
6947 slotbuf[0] = 0x5002;
6953 slotbuf[0] = 0x6002;
6959 slotbuf[0] = 0x590000;
6965 slotbuf[0] = 0x4002;
6971 slotbuf[0] = 0x400000;
6977 slotbuf[0] = 0x401000;
6983 slotbuf[0] = 0x402000;
6989 slotbuf[0] = 0x403000;
6995 slotbuf[0] = 0x404000;
7001 slotbuf[0] = 0xa10000;
7007 slotbuf[0] = 0x810000;
7013 slotbuf[0] = 0x910000;
7019 slotbuf[0] = 0xb10000;
7025 slotbuf[0] = 0x10000;
7031 slotbuf[0] = 0x210000;
7037 slotbuf[0] = 0x410000;
7043 slotbuf[0] = 0x20c0;
7049 slotbuf[0] = 0x20d0;
7055 slotbuf[0] = 0x2000;
7061 slotbuf[0] = 0x2010;
7067 slotbuf[0] = 0x2020;
7073 slotbuf[0] = 0x2030;
7079 slotbuf[0] = 0x6000;
7085 slotbuf[0] = 0x30100;
7091 slotbuf[0] = 0x130100;
7097 slotbuf[0] = 0x610100;
7103 slotbuf[0] = 0x30200;
7109 slotbuf[0] = 0x130200;
7115 slotbuf[0] = 0x610200;
7121 slotbuf[0] = 0x30000;
7127 slotbuf[0] = 0x130000;
7133 slotbuf[0] = 0x610000;
7139 slotbuf[0] = 0x30300;
7145 slotbuf[0] = 0x130300;
7151 slotbuf[0] = 0x610300;
7157 slotbuf[0] = 0x36100;
7163 slotbuf[0] = 0x136100;
7169 slotbuf[0] = 0x616100;
7175 slotbuf[0] = 0x30500;
7181 slotbuf[0] = 0x130500;
7187 slotbuf[0] = 0x610500;
7193 slotbuf[0] = 0x3b000;
7199 slotbuf[0] = 0x13b000;
7205 slotbuf[0] = 0x3d000;
7211 slotbuf[0] = 0x3e600;
7217 slotbuf[0] = 0x13e600;
7223 slotbuf[0] = 0x61e600;
7229 slotbuf[0] = 0x3b100;
7235 slotbuf[0] = 0x13b100;
7241 slotbuf[0] = 0x61b100;
7247 slotbuf[0] = 0x3d100;
7253 slotbuf[0] = 0x13d100;
7259 slotbuf[0] = 0x61d100;
7265 slotbuf[0] = 0x3b200;
7271 slotbuf[0] = 0x13b200;
7277 slotbuf[0] = 0x61b200;
7283 slotbuf[0] = 0x3d200;
7289 slotbuf[0] = 0x13d200;
7295 slotbuf[0] = 0x61d200;
7301 slotbuf[0] = 0x3b300;
7307 slotbuf[0] = 0x13b300;
7313 slotbuf[0] = 0x61b300;
7319 slotbuf[0] = 0x3d300;
7325 slotbuf[0] = 0x13d300;
7331 slotbuf[0] = 0x61d300;
7337 slotbuf[0] = 0x3b400;
7343 slotbuf[0] = 0x13b400;
7349 slotbuf[0] = 0x61b400;
7355 slotbuf[0] = 0x3d400;
7361 slotbuf[0] = 0x13d400;
7367 slotbuf[0] = 0x61d400;
7373 slotbuf[0] = 0x3b500;
7379 slotbuf[0] = 0x13b500;
7385 slotbuf[0] = 0x61b500;
7391 slotbuf[0] = 0x3d500;
7397 slotbuf[0] = 0x13d500;
7403 slotbuf[0] = 0x61d500;
7409 slotbuf[0] = 0x3b600;
7415 slotbuf[0] = 0x13b600;
7421 slotbuf[0] = 0x61b600;
7427 slotbuf[0] = 0x3d600;
7433 slotbuf[0] = 0x13d600;
7439 slotbuf[0] = 0x61d600;
7445 slotbuf[0] = 0x3b700;
7451 slotbuf[0] = 0x13b700;
7457 slotbuf[0] = 0x61b700;
7463 slotbuf[0] = 0x3d700;
7469 slotbuf[0] = 0x13d700;
7475 slotbuf[0] = 0x61d700;
7481 slotbuf[0] = 0x3c200;
7487 slotbuf[0] = 0x13c200;
7493 slotbuf[0] = 0x61c200;
7499 slotbuf[0] = 0x3c300;
7505 slotbuf[0] = 0x13c300;
7511 slotbuf[0] = 0x61c300;
7517 slotbuf[0] = 0x3c400;
7523 slotbuf[0] = 0x13c400;
7529 slotbuf[0] = 0x61c400;
7535 slotbuf[0] = 0x3c500;
7541 slotbuf[0] = 0x13c500;
7547 slotbuf[0] = 0x61c500;
7553 slotbuf[0] = 0x3c600;
7559 slotbuf[0] = 0x13c600;
7565 slotbuf[0] = 0x61c600;
7571 slotbuf[0] = 0x3c700;
7577 slotbuf[0] = 0x13c700;
7583 slotbuf[0] = 0x61c700;
7589 slotbuf[0] = 0x3ee00;
7595 slotbuf[0] = 0x13ee00;
7601 slotbuf[0] = 0x61ee00;
7607 slotbuf[0] = 0x3c000;
7613 slotbuf[0] = 0x13c000;
7619 slotbuf[0] = 0x61c000;
7625 slotbuf[0] = 0x3e800;
7631 slotbuf[0] = 0x13e800;
7637 slotbuf[0] = 0x61e800;
7643 slotbuf[0] = 0x3f400;
7649 slotbuf[0] = 0x13f400;
7655 slotbuf[0] = 0x61f400;
7661 slotbuf[0] = 0x3f500;
7667 slotbuf[0] = 0x13f500;
7673 slotbuf[0] = 0x61f500;
7679 slotbuf[0] = 0x3eb00;
7685 slotbuf[0] = 0x3e700;
7691 slotbuf[0] = 0x13e700;
7697 slotbuf[0] = 0x61e700;
7703 slotbuf[0] = 0xc10000;
7709 slotbuf[0] = 0xd10000;
7715 slotbuf[0] = 0x820000;
7721 slotbuf[0] = 0x740004;
7727 slotbuf[0] = 0x750004;
7733 slotbuf[0] = 0x760004;
7739 slotbuf[0] = 0x770004;
7745 slotbuf[0] = 0x700004;
7751 slotbuf[0] = 0x710004;
7757 slotbuf[0] = 0x720004;
7763 slotbuf[0] = 0x730004;
7769 slotbuf[0] = 0x340004;
7775 slotbuf[0] = 0x350004;
7781 slotbuf[0] = 0x360004;
7787 slotbuf[0] = 0x370004;
7793 slotbuf[0] = 0x640004;
7799 slotbuf[0] = 0x650004;
7805 slotbuf[0] = 0x660004;
7811 slotbuf[0] = 0x670004;
7817 slotbuf[0] = 0x240004;
7823 slotbuf[0] = 0x250004;
7829 slotbuf[0] = 0x260004;
7835 slotbuf[0] = 0x270004;
7841 slotbuf[0] = 0x780004;
7847 slotbuf[0] = 0x790004;
7853 slotbuf[0] = 0x7a0004;
7859 slotbuf[0] = 0x7b0004;
7865 slotbuf[0] = 0x7c0004;
7871 slotbuf[0] = 0x7d0004;
7877 slotbuf[0] = 0x7e0004;
7883 slotbuf[0] = 0x7f0004;
7889 slotbuf[0] = 0x380004;
7895 slotbuf[0] = 0x390004;
7901 slotbuf[0] = 0x3a0004;
7907 slotbuf[0] = 0x3b0004;
7913 slotbuf[0] = 0x3c0004;
7919 slotbuf[0] = 0x3d0004;
7925 slotbuf[0] = 0x3e0004;
7931 slotbuf[0] = 0x3f0004;
7937 slotbuf[0] = 0x680004;
7943 slotbuf[0] = 0x690004;
7949 slotbuf[0] = 0x6a0004;
7955 slotbuf[0] = 0x6b0004;
7961 slotbuf[0] = 0x6c0004;
7967 slotbuf[0] = 0x6d0004;
7973 slotbuf[0] = 0x6e0004;
7979 slotbuf[0] = 0x6f0004;
7985 slotbuf[0] = 0x280004;
7991 slotbuf[0] = 0x290004;
7997 slotbuf[0] = 0x2a0004;
8003 slotbuf[0] = 0x2b0004;
8009 slotbuf[0] = 0x2c0004;
8015 slotbuf[0] = 0x2d0004;
8021 slotbuf[0] = 0x2e0004;
8027 slotbuf[0] = 0x2f0004;
8033 slotbuf[0] = 0x580004;
8039 slotbuf[0] = 0x480004;
8045 slotbuf[0] = 0x590004;
8051 slotbuf[0] = 0x490004;
8057 slotbuf[0] = 0x5a0004;
8063 slotbuf[0] = 0x4a0004;
8069 slotbuf[0] = 0x5b0004;
8075 slotbuf[0] = 0x4b0004;
8081 slotbuf[0] = 0x180004;
8087 slotbuf[0] = 0x80004;
8093 slotbuf[0] = 0x190004;
8099 slotbuf[0] = 0x90004;
8105 slotbuf[0] = 0x1a0004;
8111 slotbuf[0] = 0xa0004;
8117 slotbuf[0] = 0x1b0004;
8123 slotbuf[0] = 0xb0004;
8129 slotbuf[0] = 0x900004;
8135 slotbuf[0] = 0x800004;
8141 slotbuf[0] = 0x32000;
8147 slotbuf[0] = 0x132000;
8153 slotbuf[0] = 0x612000;
8159 slotbuf[0] = 0x32100;
8165 slotbuf[0] = 0x132100;
8171 slotbuf[0] = 0x612100;
8177 slotbuf[0] = 0x32200;
8183 slotbuf[0] = 0x132200;
8189 slotbuf[0] = 0x612200;
8195 slotbuf[0] = 0x32300;
8201 slotbuf[0] = 0x132300;
8207 slotbuf[0] = 0x612300;
8213 slotbuf[0] = 0x31000;
8219 slotbuf[0] = 0x131000;
8225 slotbuf[0] = 0x611000;
8231 slotbuf[0] = 0x31100;
8237 slotbuf[0] = 0x131100;
8243 slotbuf[0] = 0x611100;
8249 slotbuf[0] = 0x3010;
8255 slotbuf[0] = 0x7000;
8261 slotbuf[0] = 0x3e200;
8267 slotbuf[0] = 0x13e200;
8273 slotbuf[0] = 0x13e300;
8279 slotbuf[0] = 0x3e400;
8285 slotbuf[0] = 0x13e400;
8291 slotbuf[0] = 0x61e400;
8297 slotbuf[0] = 0x4000;
8303 slotbuf[0] = 0xf02d;
8309 slotbuf[0] = 0x39000;
8315 slotbuf[0] = 0x139000;
8321 slotbuf[0] = 0x619000;
8327 slotbuf[0] = 0x3a000;
8333 slotbuf[0] = 0x13a000;
8339 slotbuf[0] = 0x61a000;
8345 slotbuf[0] = 0x39100;
8351 slotbuf[0] = 0x139100;
8357 slotbuf[0] = 0x619100;
8363 slotbuf[0] = 0x3a100;
8369 slotbuf[0] = 0x13a100;
8375 slotbuf[0] = 0x61a100;
8381 slotbuf[0] = 0x38000;
8387 slotbuf[0] = 0x138000;
8393 slotbuf[0] = 0x618000;
8399 slotbuf[0] = 0x38100;
8405 slotbuf[0] = 0x138100;
8411 slotbuf[0] = 0x618100;
8417 slotbuf[0] = 0x36000;
8423 slotbuf[0] = 0x136000;
8429 slotbuf[0] = 0x616000;
8435 slotbuf[0] = 0x3e900;
8441 slotbuf[0] = 0x13e900;
8447 slotbuf[0] = 0x61e900;
8453 slotbuf[0] = 0x3ec00;
8459 slotbuf[0] = 0x13ec00;
8465 slotbuf[0] = 0x61ec00;
8471 slotbuf[0] = 0x3ed00;
8477 slotbuf[0] = 0x13ed00;
8483 slotbuf[0] = 0x61ed00;
8489 slotbuf[0] = 0x36800;
8495 slotbuf[0] = 0x136800;
8501 slotbuf[0] = 0x616800;
8507 slotbuf[0] = 0x70e0;
8513 slotbuf[0] = 0x70f0;
8519 slotbuf[0] = 0xf1e000;
8525 slotbuf[0] = 0xf1e010;
8531 slotbuf[0] = 0x135900;
8537 slotbuf[0] = 0x3ea00;
8543 slotbuf[0] = 0x13ea00;
8549 slotbuf[0] = 0x61ea00;
8555 slotbuf[0] = 0x3f000;
8561 slotbuf[0] = 0x13f000;
8567 slotbuf[0] = 0x61f000;
8573 slotbuf[0] = 0x3f100;
8579 slotbuf[0] = 0x13f100;
8585 slotbuf[0] = 0x61f100;
8591 slotbuf[0] = 0x3f200;
8597 slotbuf[0] = 0x13f200;
8603 slotbuf[0] = 0x61f200;
8609 slotbuf[0] = 0x70c2;
8615 slotbuf[0] = 0x70e2;
8621 slotbuf[0] = 0x70d2;
8627 slotbuf[0] = 0x270d2;
8633 slotbuf[0] = 0x370d2;
8639 slotbuf[0] = 0x70f2;
8645 slotbuf[0] = 0xf10000;
8651 slotbuf[0] = 0xf12000;
8657 slotbuf[0] = 0xf11000;
8663 slotbuf[0] = 0xf13000;
8669 slotbuf[0] = 0x7042;
8675 slotbuf[0] = 0x7052;
8681 slotbuf[0] = 0xf7082;
8687 slotbuf[0] = 0x47082;
8693 slotbuf[0] = 0x57082;
8699 slotbuf[0] = 0x7062;
8705 slotbuf[0] = 0x7072;
8711 slotbuf[0] = 0x7002;
8717 slotbuf[0] = 0x7012;
8723 slotbuf[0] = 0x7022;
8729 slotbuf[0] = 0x7032;
8735 slotbuf[0] = 0x7082;
8741 slotbuf[0] = 0x27082;
8747 slotbuf[0] = 0x37082;
8753 slotbuf[0] = 0xf19000;
8759 slotbuf[0] = 0xf18000;
8765 slotbuf[0] = 0x50c000;
8771 slotbuf[0] = 0x50d000;
8777 slotbuf[0] = 0x50b000;
8783 slotbuf[0] = 0x50f000;
8789 slotbuf[0] = 0x50e000;
8795 slotbuf[0] = 0x504000;
8801 slotbuf[0] = 0x505000;
8807 slotbuf[0] = 0x503000;
8813 slotbuf[0] = 0x507000;
8819 slotbuf[0] = 0x506000;
8825 slotbuf[0] = 0x330000;
8831 slotbuf[0] = 0x430000;
8837 slotbuf[0] = 0x530000;
8843 slotbuf[0] = 0x630000;
8849 slotbuf[0] = 0x730000;
8855 slotbuf[0] = 0x40e000;
8861 slotbuf[0] = 0x40f000;
8867 slotbuf[0] = 0x230000;
8873 slotbuf[0] = 0xb002;
8879 slotbuf[0] = 0xf002;
8885 slotbuf[0] = 0xe002;
8891 slotbuf[0] = 0x30c00;
8897 slotbuf[0] = 0x130c00;
8903 slotbuf[0] = 0x610c00;
8909 slotbuf[0] = 0x36300;
8915 slotbuf[0] = 0x136300;
8921 slotbuf[0] = 0x616300;
8927 slotbuf[0] = 0xc20000;
8933 slotbuf[0] = 0xd20000;
8939 slotbuf[0] = 0xe20000;
8945 slotbuf[0] = 0xf20000;
8951 slotbuf[0] = 0x406000;
8957 slotbuf[0] = 0x407000;
8963 slotbuf[0] = 0xe30e60;
8969 slotbuf[0] = 0xf3e600;
8975 slotbuf[0] = 0xe0000;
8981 slotbuf[0] = 0xe1000;
8987 slotbuf[0] = 0xe1200;
8993 slotbuf[0] = 0xe2000;
8997 Opcode_excw_Slot_inst_encode, 0, 0
9001 Opcode_rfe_Slot_inst_encode, 0, 0
9005 Opcode_rfde_Slot_inst_encode, 0, 0
9009 Opcode_syscall_Slot_inst_encode, 0, 0
9013 Opcode_call12_Slot_inst_encode, 0, 0
9017 Opcode_call8_Slot_inst_encode, 0, 0
9021 Opcode_call4_Slot_inst_encode, 0, 0
9025 Opcode_callx12_Slot_inst_encode, 0, 0
9029 Opcode_callx8_Slot_inst_encode, 0, 0
9033 Opcode_callx4_Slot_inst_encode, 0, 0
9037 Opcode_entry_Slot_inst_encode, 0, 0
9041 Opcode_movsp_Slot_inst_encode, 0, 0
9045 Opcode_rotw_Slot_inst_encode, 0, 0
9049 Opcode_retw_Slot_inst_encode, 0, 0
9053 0, 0, Opcode_retw_n_Slot_inst16b_encode
9057 Opcode_rfwo_Slot_inst_encode, 0, 0
9061 Opcode_rfwu_Slot_inst_encode, 0, 0
9065 Opcode_l32e_Slot_inst_encode, 0, 0
9069 Opcode_s32e_Slot_inst_encode, 0, 0
9073 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9077 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9081 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9085 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9089 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9093 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9097 0, Opcode_add_n_Slot_inst16a_encode, 0
9101 0, Opcode_addi_n_Slot_inst16a_encode, 0
9105 0, 0, Opcode_beqz_n_Slot_inst16b_encode
9109 0, 0, Opcode_bnez_n_Slot_inst16b_encode
9113 0, 0, Opcode_ill_n_Slot_inst16b_encode
9117 0, Opcode_l32i_n_Slot_inst16a_encode, 0
9121 0, 0, Opcode_mov_n_Slot_inst16b_encode
9125 0, 0, Opcode_movi_n_Slot_inst16b_encode
9129 0, 0, Opcode_nop_n_Slot_inst16b_encode
9133 0, 0, Opcode_ret_n_Slot_inst16b_encode
9137 0, Opcode_s32i_n_Slot_inst16a_encode, 0
9141 Opcode_addi_Slot_inst_encode, 0, 0
9145 Opcode_addmi_Slot_inst_encode, 0, 0
9149 Opcode_add_Slot_inst_encode, 0, 0
9153 Opcode_sub_Slot_inst_encode, 0, 0
9157 Opcode_addx2_Slot_inst_encode, 0, 0
9161 Opcode_addx4_Slot_inst_encode, 0, 0
9165 Opcode_addx8_Slot_inst_encode, 0, 0
9169 Opcode_subx2_Slot_inst_encode, 0, 0
9173 Opcode_subx4_Slot_inst_encode, 0, 0
9177 Opcode_subx8_Slot_inst_encode, 0, 0
9181 Opcode_and_Slot_inst_encode, 0, 0
9185 Opcode_or_Slot_inst_encode, 0, 0
9189 Opcode_xor_Slot_inst_encode, 0, 0
9193 Opcode_beqi_Slot_inst_encode, 0, 0
9197 Opcode_bnei_Slot_inst_encode, 0, 0
9201 Opcode_bgei_Slot_inst_encode, 0, 0
9205 Opcode_blti_Slot_inst_encode, 0, 0
9209 Opcode_bbci_Slot_inst_encode, 0, 0
9213 Opcode_bbsi_Slot_inst_encode, 0, 0
9217 Opcode_bgeui_Slot_inst_encode, 0, 0
9221 Opcode_bltui_Slot_inst_encode, 0, 0
9225 Opcode_beq_Slot_inst_encode, 0, 0
9229 Opcode_bne_Slot_inst_encode, 0, 0
9233 Opcode_bge_Slot_inst_encode, 0, 0
9237 Opcode_blt_Slot_inst_encode, 0, 0
9241 Opcode_bgeu_Slot_inst_encode, 0, 0
9245 Opcode_bltu_Slot_inst_encode, 0, 0
9249 Opcode_bany_Slot_inst_encode, 0, 0
9253 Opcode_bnone_Slot_inst_encode, 0, 0
9257 Opcode_ball_Slot_inst_encode, 0, 0
9261 Opcode_bnall_Slot_inst_encode, 0, 0
9265 Opcode_bbc_Slot_inst_encode, 0, 0
9269 Opcode_bbs_Slot_inst_encode, 0, 0
9273 Opcode_beqz_Slot_inst_encode, 0, 0
9277 Opcode_bnez_Slot_inst_encode, 0, 0
9281 Opcode_bgez_Slot_inst_encode, 0, 0
9285 Opcode_bltz_Slot_inst_encode, 0, 0
9289 Opcode_call0_Slot_inst_encode, 0, 0
9293 Opcode_callx0_Slot_inst_encode, 0, 0
9297 Opcode_extui_Slot_inst_encode, 0, 0
9301 Opcode_ill_Slot_inst_encode, 0, 0
9305 Opcode_j_Slot_inst_encode, 0, 0
9309 Opcode_jx_Slot_inst_encode, 0, 0
9313 Opcode_l16ui_Slot_inst_encode, 0, 0
9317 Opcode_l16si_Slot_inst_encode, 0, 0
9321 Opcode_l32i_Slot_inst_encode, 0, 0
9325 Opcode_l32r_Slot_inst_encode, 0, 0
9329 Opcode_l8ui_Slot_inst_encode, 0, 0
9333 Opcode_loop_Slot_inst_encode, 0, 0
9337 Opcode_loopnez_Slot_inst_encode, 0, 0
9341 Opcode_loopgtz_Slot_inst_encode, 0, 0
9345 Opcode_movi_Slot_inst_encode, 0, 0
9349 Opcode_moveqz_Slot_inst_encode, 0, 0
9353 Opcode_movnez_Slot_inst_encode, 0, 0
9357 Opcode_movltz_Slot_inst_encode, 0, 0
9361 Opcode_movgez_Slot_inst_encode, 0, 0
9365 Opcode_neg_Slot_inst_encode, 0, 0
9369 Opcode_abs_Slot_inst_encode, 0, 0
9373 Opcode_nop_Slot_inst_encode, 0, 0
9377 Opcode_ret_Slot_inst_encode, 0, 0
9381 Opcode_simcall_Slot_inst_encode, 0, 0
9385 Opcode_s16i_Slot_inst_encode, 0, 0
9389 Opcode_s32i_Slot_inst_encode, 0, 0
9393 Opcode_s32nb_Slot_inst_encode, 0, 0
9397 Opcode_s8i_Slot_inst_encode, 0, 0
9401 Opcode_ssr_Slot_inst_encode, 0, 0
9405 Opcode_ssl_Slot_inst_encode, 0, 0
9409 Opcode_ssa8l_Slot_inst_encode, 0, 0
9413 Opcode_ssa8b_Slot_inst_encode, 0, 0
9417 Opcode_ssai_Slot_inst_encode, 0, 0
9421 Opcode_sll_Slot_inst_encode, 0, 0
9425 Opcode_src_Slot_inst_encode, 0, 0
9429 Opcode_srl_Slot_inst_encode, 0, 0
9433 Opcode_sra_Slot_inst_encode, 0, 0
9437 Opcode_slli_Slot_inst_encode, 0, 0
9441 Opcode_srai_Slot_inst_encode, 0, 0
9445 Opcode_srli_Slot_inst_encode, 0, 0
9449 Opcode_memw_Slot_inst_encode, 0, 0
9453 Opcode_extw_Slot_inst_encode, 0, 0
9457 Opcode_isync_Slot_inst_encode, 0, 0
9461 Opcode_rsync_Slot_inst_encode, 0, 0
9465 Opcode_esync_Slot_inst_encode, 0, 0
9469 Opcode_dsync_Slot_inst_encode, 0, 0
9473 Opcode_rsil_Slot_inst_encode, 0, 0
9477 Opcode_rsr_lend_Slot_inst_encode, 0, 0
9481 Opcode_wsr_lend_Slot_inst_encode, 0, 0
9485 Opcode_xsr_lend_Slot_inst_encode, 0, 0
9489 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
9493 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
9497 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
9501 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
9505 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
9509 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
9513 Opcode_rsr_sar_Slot_inst_encode, 0, 0
9517 Opcode_wsr_sar_Slot_inst_encode, 0, 0
9521 Opcode_xsr_sar_Slot_inst_encode, 0, 0
9525 Opcode_rsr_memctl_Slot_inst_encode, 0, 0
9529 Opcode_wsr_memctl_Slot_inst_encode, 0, 0
9533 Opcode_xsr_memctl_Slot_inst_encode, 0, 0
9537 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
9541 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
9545 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
9549 Opcode_rsr_configid0_Slot_inst_encode, 0, 0
9553 Opcode_wsr_configid0_Slot_inst_encode, 0, 0
9557 Opcode_rsr_configid1_Slot_inst_encode, 0, 0
9561 Opcode_rsr_ps_Slot_inst_encode, 0, 0
9565 Opcode_wsr_ps_Slot_inst_encode, 0, 0
9569 Opcode_xsr_ps_Slot_inst_encode, 0, 0
9573 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
9577 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
9581 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
9585 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
9589 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
9593 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
9597 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
9601 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
9605 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
9609 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
9613 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
9617 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
9621 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
9625 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
9629 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
9633 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
9637 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
9641 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
9645 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
9649 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
9653 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
9657 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
9661 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
9665 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
9669 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
9673 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
9677 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
9681 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
9685 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
9689 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
9693 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
9697 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
9701 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
9705 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
9709 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
9713 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
9717 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
9721 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
9725 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
9729 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
9733 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
9737 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
9741 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
9745 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
9749 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
9753 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
9757 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
9761 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
9765 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
9769 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
9773 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
9777 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
9781 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
9785 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
9789 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
9793 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
9797 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
9801 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
9805 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
9809 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
9813 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
9817 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
9821 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
9825 Opcode_rsr_depc_Slot_inst_encode, 0, 0
9829 Opcode_wsr_depc_Slot_inst_encode, 0, 0
9833 Opcode_xsr_depc_Slot_inst_encode, 0, 0
9837 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
9841 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
9845 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
9849 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
9853 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
9857 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
9861 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
9865 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
9869 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
9873 Opcode_rsr_prid_Slot_inst_encode, 0, 0
9877 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
9881 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
9885 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
9889 Opcode_mul16u_Slot_inst_encode, 0, 0
9893 Opcode_mul16s_Slot_inst_encode, 0, 0
9897 Opcode_mull_Slot_inst_encode, 0, 0
9901 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
9905 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
9909 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
9913 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
9917 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
9921 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
9925 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
9929 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
9933 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
9937 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
9941 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
9945 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
9949 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
9953 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
9957 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
9961 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
9965 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
9969 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
9973 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
9977 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
9981 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
9985 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
9989 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
9993 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
9997 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
10001 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
10005 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
10009 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
10013 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
10017 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
10021 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
10025 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
10029 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
10033 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
10037 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
10041 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
10045 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
10049 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
10053 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10057 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10061 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10065 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10069 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10073 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10077 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10081 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10085 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10089 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10093 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10097 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10101 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10105 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10109 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10113 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10117 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10121 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10125 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10129 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10133 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10137 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10141 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10145 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10149 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10153 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10157 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10161 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10165 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10169 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10173 Opcode_lddec_Slot_inst_encode, 0, 0
10177 Opcode_ldinc_Slot_inst_encode, 0, 0
10181 Opcode_rsr_m0_Slot_inst_encode, 0, 0
10185 Opcode_wsr_m0_Slot_inst_encode, 0, 0
10189 Opcode_xsr_m0_Slot_inst_encode, 0, 0
10193 Opcode_rsr_m1_Slot_inst_encode, 0, 0
10197 Opcode_wsr_m1_Slot_inst_encode, 0, 0
10201 Opcode_xsr_m1_Slot_inst_encode, 0, 0
10205 Opcode_rsr_m2_Slot_inst_encode, 0, 0
10209 Opcode_wsr_m2_Slot_inst_encode, 0, 0
10213 Opcode_xsr_m2_Slot_inst_encode, 0, 0
10217 Opcode_rsr_m3_Slot_inst_encode, 0, 0
10221 Opcode_wsr_m3_Slot_inst_encode, 0, 0
10225 Opcode_xsr_m3_Slot_inst_encode, 0, 0
10229 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10233 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10237 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10241 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10245 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10249 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10253 Opcode_rfi_Slot_inst_encode, 0, 0
10257 Opcode_waiti_Slot_inst_encode, 0, 0
10261 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10265 Opcode_wsr_intset_Slot_inst_encode, 0, 0
10269 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10273 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10277 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10281 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10285 Opcode_break_Slot_inst_encode, 0, 0
10289 0, 0, Opcode_break_n_Slot_inst16b_encode
10293 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10297 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10301 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10305 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10309 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10313 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10317 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10321 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10325 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10329 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10333 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10337 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10341 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10345 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10349 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10353 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10357 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10361 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10365 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10369 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10373 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10377 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10381 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10385 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10389 Opcode_rsr_icount_Slot_inst_encode, 0, 0
10393 Opcode_wsr_icount_Slot_inst_encode, 0, 0
10397 Opcode_xsr_icount_Slot_inst_encode, 0, 0
10401 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10405 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10409 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10413 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10417 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
10421 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
10425 Opcode_lddr32_p_Slot_inst_encode, 0, 0
10429 Opcode_sddr32_p_Slot_inst_encode, 0, 0
10433 Opcode_rfdo_Slot_inst_encode, 0, 0
10437 Opcode_rfdd_Slot_inst_encode, 0, 0
10441 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
10445 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
10449 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
10453 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
10457 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
10461 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
10465 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
10469 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
10473 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
10477 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
10481 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
10485 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
10489 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
10493 Opcode_ipf_Slot_inst_encode, 0, 0
10497 Opcode_ihi_Slot_inst_encode, 0, 0
10501 Opcode_ipfl_Slot_inst_encode, 0, 0
10505 Opcode_ihu_Slot_inst_encode, 0, 0
10509 Opcode_iiu_Slot_inst_encode, 0, 0
10513 Opcode_iii_Slot_inst_encode, 0, 0
10517 Opcode_lict_Slot_inst_encode, 0, 0
10521 Opcode_licw_Slot_inst_encode, 0, 0
10525 Opcode_sict_Slot_inst_encode, 0, 0
10529 Opcode_sicw_Slot_inst_encode, 0, 0
10533 Opcode_dhwb_Slot_inst_encode, 0, 0
10537 Opcode_dhwbi_Slot_inst_encode, 0, 0
10541 Opcode_diwbui_p_Slot_inst_encode, 0, 0
10545 Opcode_diwb_Slot_inst_encode, 0, 0
10549 Opcode_diwbi_Slot_inst_encode, 0, 0
10553 Opcode_dhi_Slot_inst_encode, 0, 0
10557 Opcode_dii_Slot_inst_encode, 0, 0
10561 Opcode_dpfr_Slot_inst_encode, 0, 0
10565 Opcode_dpfw_Slot_inst_encode, 0, 0
10569 Opcode_dpfro_Slot_inst_encode, 0, 0
10573 Opcode_dpfwo_Slot_inst_encode, 0, 0
10577 Opcode_dpfl_Slot_inst_encode, 0, 0
10581 Opcode_dhu_Slot_inst_encode, 0, 0
10585 Opcode_diu_Slot_inst_encode, 0, 0
10589 Opcode_sdct_Slot_inst_encode, 0, 0
10593 Opcode_ldct_Slot_inst_encode, 0, 0
10597 Opcode_idtlb_Slot_inst_encode, 0, 0
10601 Opcode_pdtlb_Slot_inst_encode, 0, 0
10605 Opcode_rdtlb0_Slot_inst_encode, 0, 0
10609 Opcode_rdtlb1_Slot_inst_encode, 0, 0
10613 Opcode_wdtlb_Slot_inst_encode, 0, 0
10617 Opcode_iitlb_Slot_inst_encode, 0, 0
10621 Opcode_pitlb_Slot_inst_encode, 0, 0
10625 Opcode_ritlb0_Slot_inst_encode, 0, 0
10629 Opcode_ritlb1_Slot_inst_encode, 0, 0
10633 Opcode_witlb_Slot_inst_encode, 0, 0
10637 Opcode_clamps_Slot_inst_encode, 0, 0
10641 Opcode_min_Slot_inst_encode, 0, 0
10645 Opcode_max_Slot_inst_encode, 0, 0
10649 Opcode_minu_Slot_inst_encode, 0, 0
10653 Opcode_maxu_Slot_inst_encode, 0, 0
10657 Opcode_nsa_Slot_inst_encode, 0, 0
10661 Opcode_nsau_Slot_inst_encode, 0, 0
10665 Opcode_sext_Slot_inst_encode, 0, 0
10669 Opcode_l32ai_Slot_inst_encode, 0, 0
10673 Opcode_s32ri_Slot_inst_encode, 0, 0
10677 Opcode_s32c1i_Slot_inst_encode, 0, 0
10681 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
10685 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
10689 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
10693 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
10697 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
10701 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
10705 Opcode_quou_Slot_inst_encode, 0, 0
10709 Opcode_quos_Slot_inst_encode, 0, 0
10713 Opcode_remu_Slot_inst_encode, 0, 0
10717 Opcode_rems_Slot_inst_encode, 0, 0
10721 Opcode_rer_Slot_inst_encode, 0, 0
10725 Opcode_wer_Slot_inst_encode, 0, 0
10729 Opcode_rur_expstate_Slot_inst_encode, 0, 0
10733 Opcode_wur_expstate_Slot_inst_encode, 0, 0
10737 Opcode_read_impwire_Slot_inst_encode, 0, 0
10741 Opcode_setb_expstate_Slot_inst_encode, 0, 0
10745 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
10749 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
10760 0,
10761 Opcode_excw_encode_fns, 0, 0 },
10764 Opcode_rfe_encode_fns, 0, 0 },
10767 Opcode_rfde_encode_fns, 0, 0 },
10769 0,
10770 Opcode_syscall_encode_fns, 0, 0 },
10773 Opcode_call12_encode_fns, 0, 0 },
10776 Opcode_call8_encode_fns, 0, 0 },
10779 Opcode_call4_encode_fns, 0, 0 },
10782 Opcode_callx12_encode_fns, 0, 0 },
10785 Opcode_callx8_encode_fns, 0, 0 },
10788 Opcode_callx4_encode_fns, 0, 0 },
10790 0,
10791 Opcode_entry_encode_fns, 0, 0 },
10793 0,
10794 Opcode_movsp_encode_fns, 0, 0 },
10796 0,
10797 Opcode_rotw_encode_fns, 0, 0 },
10800 Opcode_retw_encode_fns, 0, 0 },
10803 Opcode_retw_n_encode_fns, 0, 0 },
10806 Opcode_rfwo_encode_fns, 0, 0 },
10809 Opcode_rfwu_encode_fns, 0, 0 },
10811 0,
10812 Opcode_l32e_encode_fns, 0, 0 },
10814 0,
10815 Opcode_s32e_encode_fns, 0, 0 },
10817 0,
10818 Opcode_rsr_windowbase_encode_fns, 0, 0 },
10820 0,
10821 Opcode_wsr_windowbase_encode_fns, 0, 0 },
10823 0,
10824 Opcode_xsr_windowbase_encode_fns, 0, 0 },
10826 0,
10827 Opcode_rsr_windowstart_encode_fns, 0, 0 },
10829 0,
10830 Opcode_wsr_windowstart_encode_fns, 0, 0 },
10832 0,
10833 Opcode_xsr_windowstart_encode_fns, 0, 0 },
10835 0,
10836 Opcode_add_n_encode_fns, 0, 0 },
10838 0,
10839 Opcode_addi_n_encode_fns, 0, 0 },
10842 Opcode_beqz_n_encode_fns, 0, 0 },
10845 Opcode_bnez_n_encode_fns, 0, 0 },
10847 0,
10848 Opcode_ill_n_encode_fns, 0, 0 },
10850 0,
10851 Opcode_l32i_n_encode_fns, 0, 0 },
10853 0,
10854 Opcode_mov_n_encode_fns, 0, 0 },
10856 0,
10857 Opcode_movi_n_encode_fns, 0, 0 },
10859 0,
10860 Opcode_nop_n_encode_fns, 0, 0 },
10863 Opcode_ret_n_encode_fns, 0, 0 },
10865 0,
10866 Opcode_s32i_n_encode_fns, 0, 0 },
10868 0,
10869 Opcode_addi_encode_fns, 0, 0 },
10871 0,
10872 Opcode_addmi_encode_fns, 0, 0 },
10874 0,
10875 Opcode_add_encode_fns, 0, 0 },
10877 0,
10878 Opcode_sub_encode_fns, 0, 0 },
10880 0,
10881 Opcode_addx2_encode_fns, 0, 0 },
10883 0,
10884 Opcode_addx4_encode_fns, 0, 0 },
10886 0,
10887 Opcode_addx8_encode_fns, 0, 0 },
10889 0,
10890 Opcode_subx2_encode_fns, 0, 0 },
10892 0,
10893 Opcode_subx4_encode_fns, 0, 0 },
10895 0,
10896 Opcode_subx8_encode_fns, 0, 0 },
10898 0,
10899 Opcode_and_encode_fns, 0, 0 },
10901 0,
10902 Opcode_or_encode_fns, 0, 0 },
10904 0,
10905 Opcode_xor_encode_fns, 0, 0 },
10908 Opcode_beqi_encode_fns, 0, 0 },
10911 Opcode_bnei_encode_fns, 0, 0 },
10914 Opcode_bgei_encode_fns, 0, 0 },
10917 Opcode_blti_encode_fns, 0, 0 },
10920 Opcode_bbci_encode_fns, 0, 0 },
10923 Opcode_bbsi_encode_fns, 0, 0 },
10926 Opcode_bgeui_encode_fns, 0, 0 },
10929 Opcode_bltui_encode_fns, 0, 0 },
10932 Opcode_beq_encode_fns, 0, 0 },
10935 Opcode_bne_encode_fns, 0, 0 },
10938 Opcode_bge_encode_fns, 0, 0 },
10941 Opcode_blt_encode_fns, 0, 0 },
10944 Opcode_bgeu_encode_fns, 0, 0 },
10947 Opcode_bltu_encode_fns, 0, 0 },
10950 Opcode_bany_encode_fns, 0, 0 },
10953 Opcode_bnone_encode_fns, 0, 0 },
10956 Opcode_ball_encode_fns, 0, 0 },
10959 Opcode_bnall_encode_fns, 0, 0 },
10962 Opcode_bbc_encode_fns, 0, 0 },
10965 Opcode_bbs_encode_fns, 0, 0 },
10968 Opcode_beqz_encode_fns, 0, 0 },
10971 Opcode_bnez_encode_fns, 0, 0 },
10974 Opcode_bgez_encode_fns, 0, 0 },
10977 Opcode_bltz_encode_fns, 0, 0 },
10980 Opcode_call0_encode_fns, 0, 0 },
10983 Opcode_callx0_encode_fns, 0, 0 },
10985 0,
10986 Opcode_extui_encode_fns, 0, 0 },
10988 0,
10989 Opcode_ill_encode_fns, 0, 0 },
10992 Opcode_j_encode_fns, 0, 0 },
10995 Opcode_jx_encode_fns, 0, 0 },
10997 0,
10998 Opcode_l16ui_encode_fns, 0, 0 },
11000 0,
11001 Opcode_l16si_encode_fns, 0, 0 },
11003 0,
11004 Opcode_l32i_encode_fns, 0, 0 },
11006 0,
11007 Opcode_l32r_encode_fns, 0, 0 },
11009 0,
11010 Opcode_l8ui_encode_fns, 0, 0 },
11013 Opcode_loop_encode_fns, 0, 0 },
11016 Opcode_loopnez_encode_fns, 0, 0 },
11019 Opcode_loopgtz_encode_fns, 0, 0 },
11021 0,
11022 Opcode_movi_encode_fns, 0, 0 },
11024 0,
11025 Opcode_moveqz_encode_fns, 0, 0 },
11027 0,
11028 Opcode_movnez_encode_fns, 0, 0 },
11030 0,
11031 Opcode_movltz_encode_fns, 0, 0 },
11033 0,
11034 Opcode_movgez_encode_fns, 0, 0 },
11036 0,
11037 Opcode_neg_encode_fns, 0, 0 },
11039 0,
11040 Opcode_abs_encode_fns, 0, 0 },
11042 0,
11043 Opcode_nop_encode_fns, 0, 0 },
11046 Opcode_ret_encode_fns, 0, 0 },
11048 0,
11049 Opcode_simcall_encode_fns, 0, 0 },
11051 0,
11052 Opcode_s16i_encode_fns, 0, 0 },
11054 0,
11055 Opcode_s32i_encode_fns, 0, 0 },
11057 0,
11058 Opcode_s32nb_encode_fns, 0, 0 },
11060 0,
11061 Opcode_s8i_encode_fns, 0, 0 },
11063 0,
11064 Opcode_ssr_encode_fns, 0, 0 },
11066 0,
11067 Opcode_ssl_encode_fns, 0, 0 },
11069 0,
11070 Opcode_ssa8l_encode_fns, 0, 0 },
11072 0,
11073 Opcode_ssa8b_encode_fns, 0, 0 },
11075 0,
11076 Opcode_ssai_encode_fns, 0, 0 },
11078 0,
11079 Opcode_sll_encode_fns, 0, 0 },
11081 0,
11082 Opcode_src_encode_fns, 0, 0 },
11084 0,
11085 Opcode_srl_encode_fns, 0, 0 },
11087 0,
11088 Opcode_sra_encode_fns, 0, 0 },
11090 0,
11091 Opcode_slli_encode_fns, 0, 0 },
11093 0,
11094 Opcode_srai_encode_fns, 0, 0 },
11096 0,
11097 Opcode_srli_encode_fns, 0, 0 },
11099 0,
11100 Opcode_memw_encode_fns, 0, 0 },
11102 0,
11103 Opcode_extw_encode_fns, 0, 0 },
11105 0,
11106 Opcode_isync_encode_fns, 0, 0 },
11108 0,
11109 Opcode_rsync_encode_fns, 0, 0 },
11111 0,
11112 Opcode_esync_encode_fns, 0, 0 },
11114 0,
11115 Opcode_dsync_encode_fns, 0, 0 },
11117 0,
11118 Opcode_rsil_encode_fns, 0, 0 },
11120 0,
11121 Opcode_rsr_lend_encode_fns, 0, 0 },
11123 0,
11124 Opcode_wsr_lend_encode_fns, 0, 0 },
11126 0,
11127 Opcode_xsr_lend_encode_fns, 0, 0 },
11129 0,
11130 Opcode_rsr_lcount_encode_fns, 0, 0 },
11132 0,
11133 Opcode_wsr_lcount_encode_fns, 0, 0 },
11135 0,
11136 Opcode_xsr_lcount_encode_fns, 0, 0 },
11138 0,
11139 Opcode_rsr_lbeg_encode_fns, 0, 0 },
11141 0,
11142 Opcode_wsr_lbeg_encode_fns, 0, 0 },
11144 0,
11145 Opcode_xsr_lbeg_encode_fns, 0, 0 },
11147 0,
11148 Opcode_rsr_sar_encode_fns, 0, 0 },
11150 0,
11151 Opcode_wsr_sar_encode_fns, 0, 0 },
11153 0,
11154 Opcode_xsr_sar_encode_fns, 0, 0 },
11156 0,
11157 Opcode_rsr_memctl_encode_fns, 0, 0 },
11159 0,
11160 Opcode_wsr_memctl_encode_fns, 0, 0 },
11162 0,
11163 Opcode_xsr_memctl_encode_fns, 0, 0 },
11165 0,
11166 Opcode_rsr_litbase_encode_fns, 0, 0 },
11168 0,
11169 Opcode_wsr_litbase_encode_fns, 0, 0 },
11171 0,
11172 Opcode_xsr_litbase_encode_fns, 0, 0 },
11174 0,
11175 Opcode_rsr_configid0_encode_fns, 0, 0 },
11177 0,
11178 Opcode_wsr_configid0_encode_fns, 0, 0 },
11180 0,
11181 Opcode_rsr_configid1_encode_fns, 0, 0 },
11183 0,
11184 Opcode_rsr_ps_encode_fns, 0, 0 },
11186 0,
11187 Opcode_wsr_ps_encode_fns, 0, 0 },
11189 0,
11190 Opcode_xsr_ps_encode_fns, 0, 0 },
11192 0,
11193 Opcode_rsr_epc1_encode_fns, 0, 0 },
11195 0,
11196 Opcode_wsr_epc1_encode_fns, 0, 0 },
11198 0,
11199 Opcode_xsr_epc1_encode_fns, 0, 0 },
11201 0,
11202 Opcode_rsr_excsave1_encode_fns, 0, 0 },
11204 0,
11205 Opcode_wsr_excsave1_encode_fns, 0, 0 },
11207 0,
11208 Opcode_xsr_excsave1_encode_fns, 0, 0 },
11210 0,
11211 Opcode_rsr_epc2_encode_fns, 0, 0 },
11213 0,
11214 Opcode_wsr_epc2_encode_fns, 0, 0 },
11216 0,
11217 Opcode_xsr_epc2_encode_fns, 0, 0 },
11219 0,
11220 Opcode_rsr_excsave2_encode_fns, 0, 0 },
11222 0,
11223 Opcode_wsr_excsave2_encode_fns, 0, 0 },
11225 0,
11226 Opcode_xsr_excsave2_encode_fns, 0, 0 },
11228 0,
11229 Opcode_rsr_epc3_encode_fns, 0, 0 },
11231 0,
11232 Opcode_wsr_epc3_encode_fns, 0, 0 },
11234 0,
11235 Opcode_xsr_epc3_encode_fns, 0, 0 },
11237 0,
11238 Opcode_rsr_excsave3_encode_fns, 0, 0 },
11240 0,
11241 Opcode_wsr_excsave3_encode_fns, 0, 0 },
11243 0,
11244 Opcode_xsr_excsave3_encode_fns, 0, 0 },
11246 0,
11247 Opcode_rsr_epc4_encode_fns, 0, 0 },
11249 0,
11250 Opcode_wsr_epc4_encode_fns, 0, 0 },
11252 0,
11253 Opcode_xsr_epc4_encode_fns, 0, 0 },
11255 0,
11256 Opcode_rsr_excsave4_encode_fns, 0, 0 },
11258 0,
11259 Opcode_wsr_excsave4_encode_fns, 0, 0 },
11261 0,
11262 Opcode_xsr_excsave4_encode_fns, 0, 0 },
11264 0,
11265 Opcode_rsr_epc5_encode_fns, 0, 0 },
11267 0,
11268 Opcode_wsr_epc5_encode_fns, 0, 0 },
11270 0,
11271 Opcode_xsr_epc5_encode_fns, 0, 0 },
11273 0,
11274 Opcode_rsr_excsave5_encode_fns, 0, 0 },
11276 0,
11277 Opcode_wsr_excsave5_encode_fns, 0, 0 },
11279 0,
11280 Opcode_xsr_excsave5_encode_fns, 0, 0 },
11282 0,
11283 Opcode_rsr_epc6_encode_fns, 0, 0 },
11285 0,
11286 Opcode_wsr_epc6_encode_fns, 0, 0 },
11288 0,
11289 Opcode_xsr_epc6_encode_fns, 0, 0 },
11291 0,
11292 Opcode_rsr_excsave6_encode_fns, 0, 0 },
11294 0,
11295 Opcode_wsr_excsave6_encode_fns, 0, 0 },
11297 0,
11298 Opcode_xsr_excsave6_encode_fns, 0, 0 },
11300 0,
11301 Opcode_rsr_epc7_encode_fns, 0, 0 },
11303 0,
11304 Opcode_wsr_epc7_encode_fns, 0, 0 },
11306 0,
11307 Opcode_xsr_epc7_encode_fns, 0, 0 },
11309 0,
11310 Opcode_rsr_excsave7_encode_fns, 0, 0 },
11312 0,
11313 Opcode_wsr_excsave7_encode_fns, 0, 0 },
11315 0,
11316 Opcode_xsr_excsave7_encode_fns, 0, 0 },
11318 0,
11319 Opcode_rsr_eps2_encode_fns, 0, 0 },
11321 0,
11322 Opcode_wsr_eps2_encode_fns, 0, 0 },
11324 0,
11325 Opcode_xsr_eps2_encode_fns, 0, 0 },
11327 0,
11328 Opcode_rsr_eps3_encode_fns, 0, 0 },
11330 0,
11331 Opcode_wsr_eps3_encode_fns, 0, 0 },
11333 0,
11334 Opcode_xsr_eps3_encode_fns, 0, 0 },
11336 0,
11337 Opcode_rsr_eps4_encode_fns, 0, 0 },
11339 0,
11340 Opcode_wsr_eps4_encode_fns, 0, 0 },
11342 0,
11343 Opcode_xsr_eps4_encode_fns, 0, 0 },
11345 0,
11346 Opcode_rsr_eps5_encode_fns, 0, 0 },
11348 0,
11349 Opcode_wsr_eps5_encode_fns, 0, 0 },
11351 0,
11352 Opcode_xsr_eps5_encode_fns, 0, 0 },
11354 0,
11355 Opcode_rsr_eps6_encode_fns, 0, 0 },
11357 0,
11358 Opcode_wsr_eps6_encode_fns, 0, 0 },
11360 0,
11361 Opcode_xsr_eps6_encode_fns, 0, 0 },
11363 0,
11364 Opcode_rsr_eps7_encode_fns, 0, 0 },
11366 0,
11367 Opcode_wsr_eps7_encode_fns, 0, 0 },
11369 0,
11370 Opcode_xsr_eps7_encode_fns, 0, 0 },
11372 0,
11373 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
11375 0,
11376 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
11378 0,
11379 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
11381 0,
11382 Opcode_rsr_depc_encode_fns, 0, 0 },
11384 0,
11385 Opcode_wsr_depc_encode_fns, 0, 0 },
11387 0,
11388 Opcode_xsr_depc_encode_fns, 0, 0 },
11390 0,
11391 Opcode_rsr_exccause_encode_fns, 0, 0 },
11393 0,
11394 Opcode_wsr_exccause_encode_fns, 0, 0 },
11396 0,
11397 Opcode_xsr_exccause_encode_fns, 0, 0 },
11399 0,
11400 Opcode_rsr_misc0_encode_fns, 0, 0 },
11402 0,
11403 Opcode_wsr_misc0_encode_fns, 0, 0 },
11405 0,
11406 Opcode_xsr_misc0_encode_fns, 0, 0 },
11408 0,
11409 Opcode_rsr_misc1_encode_fns, 0, 0 },
11411 0,
11412 Opcode_wsr_misc1_encode_fns, 0, 0 },
11414 0,
11415 Opcode_xsr_misc1_encode_fns, 0, 0 },
11417 0,
11418 Opcode_rsr_prid_encode_fns, 0, 0 },
11420 0,
11421 Opcode_rsr_vecbase_encode_fns, 0, 0 },
11423 0,
11424 Opcode_wsr_vecbase_encode_fns, 0, 0 },
11426 0,
11427 Opcode_xsr_vecbase_encode_fns, 0, 0 },
11429 0,
11430 Opcode_mul16u_encode_fns, 0, 0 },
11432 0,
11433 Opcode_mul16s_encode_fns, 0, 0 },
11435 0,
11436 Opcode_mull_encode_fns, 0, 0 },
11438 0,
11439 Opcode_mul_aa_ll_encode_fns, 0, 0 },
11441 0,
11442 Opcode_mul_aa_hl_encode_fns, 0, 0 },
11444 0,
11445 Opcode_mul_aa_lh_encode_fns, 0, 0 },
11447 0,
11448 Opcode_mul_aa_hh_encode_fns, 0, 0 },
11450 0,
11451 Opcode_umul_aa_ll_encode_fns, 0, 0 },
11453 0,
11454 Opcode_umul_aa_hl_encode_fns, 0, 0 },
11456 0,
11457 Opcode_umul_aa_lh_encode_fns, 0, 0 },
11459 0,
11460 Opcode_umul_aa_hh_encode_fns, 0, 0 },
11462 0,
11463 Opcode_mul_ad_ll_encode_fns, 0, 0 },
11465 0,
11466 Opcode_mul_ad_hl_encode_fns, 0, 0 },
11468 0,
11469 Opcode_mul_ad_lh_encode_fns, 0, 0 },
11471 0,
11472 Opcode_mul_ad_hh_encode_fns, 0, 0 },
11474 0,
11475 Opcode_mul_da_ll_encode_fns, 0, 0 },
11477 0,
11478 Opcode_mul_da_hl_encode_fns, 0, 0 },
11480 0,
11481 Opcode_mul_da_lh_encode_fns, 0, 0 },
11483 0,
11484 Opcode_mul_da_hh_encode_fns, 0, 0 },
11486 0,
11487 Opcode_mul_dd_ll_encode_fns, 0, 0 },
11489 0,
11490 Opcode_mul_dd_hl_encode_fns, 0, 0 },
11492 0,
11493 Opcode_mul_dd_lh_encode_fns, 0, 0 },
11495 0,
11496 Opcode_mul_dd_hh_encode_fns, 0, 0 },
11498 0,
11499 Opcode_mula_aa_ll_encode_fns, 0, 0 },
11501 0,
11502 Opcode_mula_aa_hl_encode_fns, 0, 0 },
11504 0,
11505 Opcode_mula_aa_lh_encode_fns, 0, 0 },
11507 0,
11508 Opcode_mula_aa_hh_encode_fns, 0, 0 },
11510 0,
11511 Opcode_muls_aa_ll_encode_fns, 0, 0 },
11513 0,
11514 Opcode_muls_aa_hl_encode_fns, 0, 0 },
11516 0,
11517 Opcode_muls_aa_lh_encode_fns, 0, 0 },
11519 0,
11520 Opcode_muls_aa_hh_encode_fns, 0, 0 },
11522 0,
11523 Opcode_mula_ad_ll_encode_fns, 0, 0 },
11525 0,
11526 Opcode_mula_ad_hl_encode_fns, 0, 0 },
11528 0,
11529 Opcode_mula_ad_lh_encode_fns, 0, 0 },
11531 0,
11532 Opcode_mula_ad_hh_encode_fns, 0, 0 },
11534 0,
11535 Opcode_muls_ad_ll_encode_fns, 0, 0 },
11537 0,
11538 Opcode_muls_ad_hl_encode_fns, 0, 0 },
11540 0,
11541 Opcode_muls_ad_lh_encode_fns, 0, 0 },
11543 0,
11544 Opcode_muls_ad_hh_encode_fns, 0, 0 },
11546 0,
11547 Opcode_mula_da_ll_encode_fns, 0, 0 },
11549 0,
11550 Opcode_mula_da_hl_encode_fns, 0, 0 },
11552 0,
11553 Opcode_mula_da_lh_encode_fns, 0, 0 },
11555 0,
11556 Opcode_mula_da_hh_encode_fns, 0, 0 },
11558 0,
11559 Opcode_muls_da_ll_encode_fns, 0, 0 },
11561 0,
11562 Opcode_muls_da_hl_encode_fns, 0, 0 },
11564 0,
11565 Opcode_muls_da_lh_encode_fns, 0, 0 },
11567 0,
11568 Opcode_muls_da_hh_encode_fns, 0, 0 },
11570 0,
11571 Opcode_mula_dd_ll_encode_fns, 0, 0 },
11573 0,
11574 Opcode_mula_dd_hl_encode_fns, 0, 0 },
11576 0,
11577 Opcode_mula_dd_lh_encode_fns, 0, 0 },
11579 0,
11580 Opcode_mula_dd_hh_encode_fns, 0, 0 },
11582 0,
11583 Opcode_muls_dd_ll_encode_fns, 0, 0 },
11585 0,
11586 Opcode_muls_dd_hl_encode_fns, 0, 0 },
11588 0,
11589 Opcode_muls_dd_lh_encode_fns, 0, 0 },
11591 0,
11592 Opcode_muls_dd_hh_encode_fns, 0, 0 },
11594 0,
11595 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
11597 0,
11598 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
11600 0,
11601 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
11603 0,
11604 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
11606 0,
11607 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
11609 0,
11610 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
11612 0,
11613 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
11615 0,
11616 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
11618 0,
11619 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
11621 0,
11622 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
11624 0,
11625 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
11627 0,
11628 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
11630 0,
11631 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
11633 0,
11634 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
11636 0,
11637 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
11639 0,
11640 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
11642 0,
11643 Opcode_lddec_encode_fns, 0, 0 },
11645 0,
11646 Opcode_ldinc_encode_fns, 0, 0 },
11648 0,
11649 Opcode_rsr_m0_encode_fns, 0, 0 },
11651 0,
11652 Opcode_wsr_m0_encode_fns, 0, 0 },
11654 0,
11655 Opcode_xsr_m0_encode_fns, 0, 0 },
11657 0,
11658 Opcode_rsr_m1_encode_fns, 0, 0 },
11660 0,
11661 Opcode_wsr_m1_encode_fns, 0, 0 },
11663 0,
11664 Opcode_xsr_m1_encode_fns, 0, 0 },
11666 0,
11667 Opcode_rsr_m2_encode_fns, 0, 0 },
11669 0,
11670 Opcode_wsr_m2_encode_fns, 0, 0 },
11672 0,
11673 Opcode_xsr_m2_encode_fns, 0, 0 },
11675 0,
11676 Opcode_rsr_m3_encode_fns, 0, 0 },
11678 0,
11679 Opcode_wsr_m3_encode_fns, 0, 0 },
11681 0,
11682 Opcode_xsr_m3_encode_fns, 0, 0 },
11684 0,
11685 Opcode_rsr_acclo_encode_fns, 0, 0 },
11687 0,
11688 Opcode_wsr_acclo_encode_fns, 0, 0 },
11690 0,
11691 Opcode_xsr_acclo_encode_fns, 0, 0 },
11693 0,
11694 Opcode_rsr_acchi_encode_fns, 0, 0 },
11696 0,
11697 Opcode_wsr_acchi_encode_fns, 0, 0 },
11699 0,
11700 Opcode_xsr_acchi_encode_fns, 0, 0 },
11703 Opcode_rfi_encode_fns, 0, 0 },
11705 0,
11706 Opcode_waiti_encode_fns, 0, 0 },
11708 0,
11709 Opcode_rsr_interrupt_encode_fns, 0, 0 },
11711 0,
11712 Opcode_wsr_intset_encode_fns, 0, 0 },
11714 0,
11715 Opcode_wsr_intclear_encode_fns, 0, 0 },
11717 0,
11718 Opcode_rsr_intenable_encode_fns, 0, 0 },
11720 0,
11721 Opcode_wsr_intenable_encode_fns, 0, 0 },
11723 0,
11724 Opcode_xsr_intenable_encode_fns, 0, 0 },
11726 0,
11727 Opcode_break_encode_fns, 0, 0 },
11729 0,
11730 Opcode_break_n_encode_fns, 0, 0 },
11732 0,
11733 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
11735 0,
11736 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
11738 0,
11739 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
11741 0,
11742 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
11744 0,
11745 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
11747 0,
11748 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
11750 0,
11751 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
11753 0,
11754 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
11756 0,
11757 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
11759 0,
11760 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
11762 0,
11763 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
11765 0,
11766 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
11768 0,
11769 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
11771 0,
11772 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
11774 0,
11775 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
11777 0,
11778 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
11780 0,
11781 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
11783 0,
11784 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
11786 0,
11787 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
11789 0,
11790 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
11792 0,
11793 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
11795 0,
11796 Opcode_rsr_debugcause_encode_fns, 0, 0 },
11798 0,
11799 Opcode_wsr_debugcause_encode_fns, 0, 0 },
11801 0,
11802 Opcode_xsr_debugcause_encode_fns, 0, 0 },
11804 0,
11805 Opcode_rsr_icount_encode_fns, 0, 0 },
11807 0,
11808 Opcode_wsr_icount_encode_fns, 0, 0 },
11810 0,
11811 Opcode_xsr_icount_encode_fns, 0, 0 },
11813 0,
11814 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
11816 0,
11817 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
11819 0,
11820 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
11822 0,
11823 Opcode_rsr_ddr_encode_fns, 0, 0 },
11825 0,
11826 Opcode_wsr_ddr_encode_fns, 0, 0 },
11828 0,
11829 Opcode_xsr_ddr_encode_fns, 0, 0 },
11831 0,
11832 Opcode_lddr32_p_encode_fns, 0, 0 },
11834 0,
11835 Opcode_sddr32_p_encode_fns, 0, 0 },
11838 Opcode_rfdo_encode_fns, 0, 0 },
11841 Opcode_rfdd_encode_fns, 0, 0 },
11843 0,
11844 Opcode_wsr_mmid_encode_fns, 0, 0 },
11846 0,
11847 Opcode_rsr_ccount_encode_fns, 0, 0 },
11849 0,
11850 Opcode_wsr_ccount_encode_fns, 0, 0 },
11852 0,
11853 Opcode_xsr_ccount_encode_fns, 0, 0 },
11855 0,
11856 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
11858 0,
11859 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
11861 0,
11862 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
11864 0,
11865 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
11867 0,
11868 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
11870 0,
11871 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
11873 0,
11874 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
11876 0,
11877 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
11879 0,
11880 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
11882 0,
11883 Opcode_ipf_encode_fns, 0, 0 },
11885 0,
11886 Opcode_ihi_encode_fns, 0, 0 },
11888 0,
11889 Opcode_ipfl_encode_fns, 0, 0 },
11891 0,
11892 Opcode_ihu_encode_fns, 0, 0 },
11894 0,
11895 Opcode_iiu_encode_fns, 0, 0 },
11897 0,
11898 Opcode_iii_encode_fns, 0, 0 },
11900 0,
11901 Opcode_lict_encode_fns, 0, 0 },
11903 0,
11904 Opcode_licw_encode_fns, 0, 0 },
11906 0,
11907 Opcode_sict_encode_fns, 0, 0 },
11909 0,
11910 Opcode_sicw_encode_fns, 0, 0 },
11912 0,
11913 Opcode_dhwb_encode_fns, 0, 0 },
11915 0,
11916 Opcode_dhwbi_encode_fns, 0, 0 },
11918 0,
11919 Opcode_diwbui_p_encode_fns, 0, 0 },
11921 0,
11922 Opcode_diwb_encode_fns, 0, 0 },
11924 0,
11925 Opcode_diwbi_encode_fns, 0, 0 },
11927 0,
11928 Opcode_dhi_encode_fns, 0, 0 },
11930 0,
11931 Opcode_dii_encode_fns, 0, 0 },
11933 0,
11934 Opcode_dpfr_encode_fns, 0, 0 },
11936 0,
11937 Opcode_dpfw_encode_fns, 0, 0 },
11939 0,
11940 Opcode_dpfro_encode_fns, 0, 0 },
11942 0,
11943 Opcode_dpfwo_encode_fns, 0, 0 },
11945 0,
11946 Opcode_dpfl_encode_fns, 0, 0 },
11948 0,
11949 Opcode_dhu_encode_fns, 0, 0 },
11951 0,
11952 Opcode_diu_encode_fns, 0, 0 },
11954 0,
11955 Opcode_sdct_encode_fns, 0, 0 },
11957 0,
11958 Opcode_ldct_encode_fns, 0, 0 },
11960 0,
11961 Opcode_idtlb_encode_fns, 0, 0 },
11963 0,
11964 Opcode_pdtlb_encode_fns, 0, 0 },
11966 0,
11967 Opcode_rdtlb0_encode_fns, 0, 0 },
11969 0,
11970 Opcode_rdtlb1_encode_fns, 0, 0 },
11972 0,
11973 Opcode_wdtlb_encode_fns, 0, 0 },
11975 0,
11976 Opcode_iitlb_encode_fns, 0, 0 },
11978 0,
11979 Opcode_pitlb_encode_fns, 0, 0 },
11981 0,
11982 Opcode_ritlb0_encode_fns, 0, 0 },
11984 0,
11985 Opcode_ritlb1_encode_fns, 0, 0 },
11987 0,
11988 Opcode_witlb_encode_fns, 0, 0 },
11990 0,
11991 Opcode_clamps_encode_fns, 0, 0 },
11993 0,
11994 Opcode_min_encode_fns, 0, 0 },
11996 0,
11997 Opcode_max_encode_fns, 0, 0 },
11999 0,
12000 Opcode_minu_encode_fns, 0, 0 },
12002 0,
12003 Opcode_maxu_encode_fns, 0, 0 },
12005 0,
12006 Opcode_nsa_encode_fns, 0, 0 },
12008 0,
12009 Opcode_nsau_encode_fns, 0, 0 },
12011 0,
12012 Opcode_sext_encode_fns, 0, 0 },
12014 0,
12015 Opcode_l32ai_encode_fns, 0, 0 },
12017 0,
12018 Opcode_s32ri_encode_fns, 0, 0 },
12020 0,
12021 Opcode_s32c1i_encode_fns, 0, 0 },
12023 0,
12024 Opcode_rsr_scompare1_encode_fns, 0, 0 },
12026 0,
12027 Opcode_wsr_scompare1_encode_fns, 0, 0 },
12029 0,
12030 Opcode_xsr_scompare1_encode_fns, 0, 0 },
12032 0,
12033 Opcode_rsr_atomctl_encode_fns, 0, 0 },
12035 0,
12036 Opcode_wsr_atomctl_encode_fns, 0, 0 },
12038 0,
12039 Opcode_xsr_atomctl_encode_fns, 0, 0 },
12041 0,
12042 Opcode_quou_encode_fns, 0, 0 },
12044 0,
12045 Opcode_quos_encode_fns, 0, 0 },
12047 0,
12048 Opcode_remu_encode_fns, 0, 0 },
12050 0,
12051 Opcode_rems_encode_fns, 0, 0 },
12053 0,
12054 Opcode_rer_encode_fns, 0, 0 },
12056 0,
12057 Opcode_wer_encode_fns, 0, 0 },
12059 0,
12060 Opcode_rur_expstate_encode_fns, 0, 0 },
12062 0,
12063 Opcode_wur_expstate_encode_fns, 0, 0 },
12065 0,
12066 Opcode_read_impwire_encode_fns, 0, 0 },
12068 0,
12069 Opcode_setb_expstate_encode_fns, 0, 0 },
12071 0,
12072 Opcode_clrb_expstate_encode_fns, 0, 0 },
12074 0,
12075 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
12526 if (Field_op0_Slot_inst_get (insn) == 0)
12528 if (Field_op1_Slot_inst_get (insn) == 0)
12530 if (Field_op2_Slot_inst_get (insn) == 0)
12532 if (Field_r_Slot_inst_get (insn) == 0)
12534 if (Field_m_Slot_inst_get (insn) == 0 &&
12535 Field_s_Slot_inst_get (insn) == 0 &&
12536 Field_n_Slot_inst_get (insn) == 0)
12540 if (Field_n_Slot_inst_get (insn) == 0)
12549 if (Field_n_Slot_inst_get (insn) == 0)
12563 if (Field_s_Slot_inst_get (insn) == 0)
12565 if (Field_t_Slot_inst_get (insn) == 0)
12585 if (Field_t_Slot_inst_get (insn) == 0)
12587 if (Field_s_Slot_inst_get (insn) == 0)
12603 if (Field_s_Slot_inst_get (insn) == 0 &&
12604 Field_t_Slot_inst_get (insn) == 0)
12607 Field_t_Slot_inst_get (insn) == 0)
12613 Field_t_Slot_inst_get (insn) == 0)
12631 if (Field_r_Slot_inst_get (insn) == 0 &&
12632 Field_t_Slot_inst_get (insn) == 0)
12635 Field_t_Slot_inst_get (insn) == 0)
12638 Field_t_Slot_inst_get (insn) == 0)
12641 Field_t_Slot_inst_get (insn) == 0)
12644 Field_thi3_Slot_inst_get (insn) == 0)
12651 Field_s_Slot_inst_get (insn) == 0)
12663 Field_t_Slot_inst_get (insn) == 0)
12674 Field_t_Slot_inst_get (insn) == 0)
12685 if (Field_s_Slot_inst_get (insn) == 0)
12709 if ((Field_op2_Slot_inst_get (insn) == 0 ||
12719 if (Field_sr_Slot_inst_get (insn) == 0)
12841 Field_s_Slot_inst_get (insn) == 0)
12844 Field_t_Slot_inst_get (insn) == 0)
12847 Field_s_Slot_inst_get (insn) == 0)
12855 if (Field_r_Slot_inst_get (insn) == 0)
12868 Field_t_Slot_inst_get (insn) == 0)
12890 if (Field_op2_Slot_inst_get (insn) == 0)
12892 if (Field_sr_Slot_inst_get (insn) == 0)
13021 if (Field_sr_Slot_inst_get (insn) == 0)
13184 if (Field_op2_Slot_inst_get (insn) == 0)
13191 if (Field_r_Slot_inst_get (insn) == 0 &&
13192 Field_s_Slot_inst_get (insn) == 0 &&
13193 Field_op2_Slot_inst_get (insn) == 0 &&
13197 Field_s3to1_Slot_inst_get (insn) == 0 &&
13198 Field_op2_Slot_inst_get (insn) == 0 &&
13203 Field_op2_Slot_inst_get (insn) == 0 &&
13207 Field_op2_Slot_inst_get (insn) == 0 &&
13215 if (Field_r_Slot_inst_get (insn) == 0)
13229 if (Field_t_Slot_inst_get (insn) == 0)
13247 if (Field_op1_Slot_inst_get (insn) == 0)
13258 Field_op2_Slot_inst_get (insn) == 0)
13265 if (Field_op1_Slot_inst_get (insn) == 0)
13294 if (Field_op2_Slot_inst_get (insn) == 0)
13297 Field_t3_Slot_inst_get (insn) == 0 &&
13298 Field_tlo_Slot_inst_get (insn) == 0 &&
13299 Field_r3_Slot_inst_get (insn) == 0)
13302 Field_t3_Slot_inst_get (insn) == 0 &&
13303 Field_tlo_Slot_inst_get (insn) == 0 &&
13304 Field_r3_Slot_inst_get (insn) == 0)
13307 Field_t3_Slot_inst_get (insn) == 0 &&
13308 Field_tlo_Slot_inst_get (insn) == 0 &&
13309 Field_r3_Slot_inst_get (insn) == 0)
13312 Field_t3_Slot_inst_get (insn) == 0 &&
13313 Field_tlo_Slot_inst_get (insn) == 0 &&
13314 Field_r3_Slot_inst_get (insn) == 0)
13320 Field_t3_Slot_inst_get (insn) == 0 &&
13321 Field_tlo_Slot_inst_get (insn) == 0 &&
13322 Field_r3_Slot_inst_get (insn) == 0)
13325 Field_t3_Slot_inst_get (insn) == 0 &&
13326 Field_tlo_Slot_inst_get (insn) == 0 &&
13327 Field_r3_Slot_inst_get (insn) == 0)
13330 Field_t3_Slot_inst_get (insn) == 0 &&
13331 Field_tlo_Slot_inst_get (insn) == 0 &&
13332 Field_r3_Slot_inst_get (insn) == 0)
13335 Field_t3_Slot_inst_get (insn) == 0 &&
13336 Field_tlo_Slot_inst_get (insn) == 0 &&
13337 Field_r3_Slot_inst_get (insn) == 0)
13343 Field_s_Slot_inst_get (insn) == 0 &&
13344 Field_w_Slot_inst_get (insn) == 0 &&
13345 Field_r3_Slot_inst_get (insn) == 0 &&
13346 Field_t3_Slot_inst_get (insn) == 0 &&
13347 Field_tlo_Slot_inst_get (insn) == 0)
13350 Field_s_Slot_inst_get (insn) == 0 &&
13351 Field_w_Slot_inst_get (insn) == 0 &&
13352 Field_r3_Slot_inst_get (insn) == 0 &&
13353 Field_t3_Slot_inst_get (insn) == 0 &&
13354 Field_tlo_Slot_inst_get (insn) == 0)
13357 Field_s_Slot_inst_get (insn) == 0 &&
13358 Field_w_Slot_inst_get (insn) == 0 &&
13359 Field_r3_Slot_inst_get (insn) == 0 &&
13360 Field_t3_Slot_inst_get (insn) == 0 &&
13361 Field_tlo_Slot_inst_get (insn) == 0)
13364 Field_s_Slot_inst_get (insn) == 0 &&
13365 Field_w_Slot_inst_get (insn) == 0 &&
13366 Field_r3_Slot_inst_get (insn) == 0 &&
13367 Field_t3_Slot_inst_get (insn) == 0 &&
13368 Field_tlo_Slot_inst_get (insn) == 0)
13371 Field_s_Slot_inst_get (insn) == 0 &&
13372 Field_w_Slot_inst_get (insn) == 0 &&
13373 Field_r3_Slot_inst_get (insn) == 0 &&
13374 Field_t3_Slot_inst_get (insn) == 0 &&
13375 Field_tlo_Slot_inst_get (insn) == 0)
13378 Field_s_Slot_inst_get (insn) == 0 &&
13379 Field_w_Slot_inst_get (insn) == 0 &&
13380 Field_r3_Slot_inst_get (insn) == 0 &&
13381 Field_t3_Slot_inst_get (insn) == 0 &&
13382 Field_tlo_Slot_inst_get (insn) == 0)
13385 Field_s_Slot_inst_get (insn) == 0 &&
13386 Field_w_Slot_inst_get (insn) == 0 &&
13387 Field_r3_Slot_inst_get (insn) == 0 &&
13388 Field_t3_Slot_inst_get (insn) == 0 &&
13389 Field_tlo_Slot_inst_get (insn) == 0)
13392 Field_s_Slot_inst_get (insn) == 0 &&
13393 Field_w_Slot_inst_get (insn) == 0 &&
13394 Field_r3_Slot_inst_get (insn) == 0 &&
13395 Field_t3_Slot_inst_get (insn) == 0 &&
13396 Field_tlo_Slot_inst_get (insn) == 0)
13399 Field_s_Slot_inst_get (insn) == 0 &&
13400 Field_w_Slot_inst_get (insn) == 0 &&
13401 Field_r3_Slot_inst_get (insn) == 0 &&
13402 Field_t3_Slot_inst_get (insn) == 0 &&
13403 Field_tlo_Slot_inst_get (insn) == 0)
13406 Field_s_Slot_inst_get (insn) == 0 &&
13407 Field_w_Slot_inst_get (insn) == 0 &&
13408 Field_r3_Slot_inst_get (insn) == 0 &&
13409 Field_t3_Slot_inst_get (insn) == 0 &&
13410 Field_tlo_Slot_inst_get (insn) == 0)
13413 Field_s_Slot_inst_get (insn) == 0 &&
13414 Field_w_Slot_inst_get (insn) == 0 &&
13415 Field_r3_Slot_inst_get (insn) == 0 &&
13416 Field_t3_Slot_inst_get (insn) == 0 &&
13417 Field_tlo_Slot_inst_get (insn) == 0)
13420 Field_s_Slot_inst_get (insn) == 0 &&
13421 Field_w_Slot_inst_get (insn) == 0 &&
13422 Field_r3_Slot_inst_get (insn) == 0 &&
13423 Field_t3_Slot_inst_get (insn) == 0 &&
13424 Field_tlo_Slot_inst_get (insn) == 0)
13430 Field_r_Slot_inst_get (insn) == 0 &&
13431 Field_t3_Slot_inst_get (insn) == 0 &&
13432 Field_tlo_Slot_inst_get (insn) == 0)
13435 Field_r_Slot_inst_get (insn) == 0 &&
13436 Field_t3_Slot_inst_get (insn) == 0 &&
13437 Field_tlo_Slot_inst_get (insn) == 0)
13440 Field_r_Slot_inst_get (insn) == 0 &&
13441 Field_t3_Slot_inst_get (insn) == 0 &&
13442 Field_tlo_Slot_inst_get (insn) == 0)
13445 Field_r_Slot_inst_get (insn) == 0 &&
13446 Field_t3_Slot_inst_get (insn) == 0 &&
13447 Field_tlo_Slot_inst_get (insn) == 0)
13450 Field_r_Slot_inst_get (insn) == 0 &&
13451 Field_t3_Slot_inst_get (insn) == 0 &&
13452 Field_tlo_Slot_inst_get (insn) == 0)
13455 Field_r_Slot_inst_get (insn) == 0 &&
13456 Field_t3_Slot_inst_get (insn) == 0 &&
13457 Field_tlo_Slot_inst_get (insn) == 0)
13460 Field_r_Slot_inst_get (insn) == 0 &&
13461 Field_t3_Slot_inst_get (insn) == 0 &&
13462 Field_tlo_Slot_inst_get (insn) == 0)
13465 Field_r_Slot_inst_get (insn) == 0 &&
13466 Field_t3_Slot_inst_get (insn) == 0 &&
13467 Field_tlo_Slot_inst_get (insn) == 0)
13470 Field_r_Slot_inst_get (insn) == 0 &&
13471 Field_t3_Slot_inst_get (insn) == 0 &&
13472 Field_tlo_Slot_inst_get (insn) == 0)
13475 Field_r_Slot_inst_get (insn) == 0 &&
13476 Field_t3_Slot_inst_get (insn) == 0 &&
13477 Field_tlo_Slot_inst_get (insn) == 0)
13480 Field_r_Slot_inst_get (insn) == 0 &&
13481 Field_t3_Slot_inst_get (insn) == 0 &&
13482 Field_tlo_Slot_inst_get (insn) == 0)
13485 Field_r_Slot_inst_get (insn) == 0 &&
13486 Field_t3_Slot_inst_get (insn) == 0 &&
13487 Field_tlo_Slot_inst_get (insn) == 0)
13493 Field_r3_Slot_inst_get (insn) == 0)
13496 Field_r3_Slot_inst_get (insn) == 0)
13499 Field_r3_Slot_inst_get (insn) == 0)
13502 Field_r3_Slot_inst_get (insn) == 0)
13508 Field_r3_Slot_inst_get (insn) == 0)
13511 Field_r3_Slot_inst_get (insn) == 0)
13514 Field_r3_Slot_inst_get (insn) == 0)
13517 Field_r3_Slot_inst_get (insn) == 0)
13523 Field_s_Slot_inst_get (insn) == 0 &&
13524 Field_w_Slot_inst_get (insn) == 0 &&
13525 Field_r3_Slot_inst_get (insn) == 0)
13528 Field_s_Slot_inst_get (insn) == 0 &&
13529 Field_w_Slot_inst_get (insn) == 0 &&
13530 Field_r3_Slot_inst_get (insn) == 0)
13533 Field_s_Slot_inst_get (insn) == 0 &&
13534 Field_w_Slot_inst_get (insn) == 0 &&
13535 Field_r3_Slot_inst_get (insn) == 0)
13538 Field_s_Slot_inst_get (insn) == 0 &&
13539 Field_w_Slot_inst_get (insn) == 0 &&
13540 Field_r3_Slot_inst_get (insn) == 0)
13543 Field_s_Slot_inst_get (insn) == 0 &&
13544 Field_w_Slot_inst_get (insn) == 0 &&
13545 Field_r3_Slot_inst_get (insn) == 0)
13548 Field_s_Slot_inst_get (insn) == 0 &&
13549 Field_w_Slot_inst_get (insn) == 0 &&
13550 Field_r3_Slot_inst_get (insn) == 0)
13553 Field_s_Slot_inst_get (insn) == 0 &&
13554 Field_w_Slot_inst_get (insn) == 0 &&
13555 Field_r3_Slot_inst_get (insn) == 0)
13558 Field_s_Slot_inst_get (insn) == 0 &&
13559 Field_w_Slot_inst_get (insn) == 0 &&
13560 Field_r3_Slot_inst_get (insn) == 0)
13563 Field_s_Slot_inst_get (insn) == 0 &&
13564 Field_w_Slot_inst_get (insn) == 0 &&
13565 Field_r3_Slot_inst_get (insn) == 0)
13568 Field_s_Slot_inst_get (insn) == 0 &&
13569 Field_w_Slot_inst_get (insn) == 0 &&
13570 Field_r3_Slot_inst_get (insn) == 0)
13573 Field_s_Slot_inst_get (insn) == 0 &&
13574 Field_w_Slot_inst_get (insn) == 0 &&
13575 Field_r3_Slot_inst_get (insn) == 0)
13578 Field_s_Slot_inst_get (insn) == 0 &&
13579 Field_w_Slot_inst_get (insn) == 0 &&
13580 Field_r3_Slot_inst_get (insn) == 0)
13585 if (Field_op1_Slot_inst_get (insn) == 0 &&
13586 Field_r_Slot_inst_get (insn) == 0)
13589 Field_r_Slot_inst_get (insn) == 0)
13592 Field_r_Slot_inst_get (insn) == 0)
13595 Field_r_Slot_inst_get (insn) == 0)
13598 Field_r_Slot_inst_get (insn) == 0)
13601 Field_r_Slot_inst_get (insn) == 0)
13604 Field_r_Slot_inst_get (insn) == 0)
13607 Field_r_Slot_inst_get (insn) == 0)
13610 Field_r_Slot_inst_get (insn) == 0)
13613 Field_r_Slot_inst_get (insn) == 0)
13616 Field_r_Slot_inst_get (insn) == 0)
13619 Field_r_Slot_inst_get (insn) == 0)
13622 Field_r_Slot_inst_get (insn) == 0)
13625 Field_r_Slot_inst_get (insn) == 0)
13628 Field_r_Slot_inst_get (insn) == 0)
13631 Field_r_Slot_inst_get (insn) == 0)
13636 if (Field_op1_Slot_inst_get (insn) == 0 &&
13637 Field_t_Slot_inst_get (insn) == 0 &&
13638 Field_rhi_Slot_inst_get (insn) == 0)
13643 if (Field_op1_Slot_inst_get (insn) == 0 &&
13644 Field_t_Slot_inst_get (insn) == 0 &&
13645 Field_rhi_Slot_inst_get (insn) == 0)
13651 if (Field_n_Slot_inst_get (insn) == 0)
13662 if (Field_n_Slot_inst_get (insn) == 0)
13666 if (Field_m_Slot_inst_get (insn) == 0)
13677 if (Field_m_Slot_inst_get (insn) == 0)
13688 if (Field_m_Slot_inst_get (insn) == 0)
13707 if (Field_r_Slot_inst_get (insn) == 0)
13746 if (Field_i_Slot_inst16b_get (insn) == 0)
13750 if (Field_z_Slot_inst16b_get (insn) == 0)
13758 if (Field_r_Slot_inst16b_get (insn) == 0)
13762 if (Field_t_Slot_inst16b_get (insn) == 0)
13769 Field_s_Slot_inst16b_get (insn) == 0)
13772 Field_s_Slot_inst16b_get (insn) == 0)
13800 slotbuf[0] = (insn[0] & 0xffffff);
13807 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
13814 slotbuf[0] = (insn[0] & 0xffff);
13821 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13828 slotbuf[0] = (insn[0] & 0xffff);
13835 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13867 0,
13868 0,
13869 0,
13870 0,
13871 0,
13872 0,
13873 0,
13874 0,
13927 0,
13928 0,
13929 0,
13930 0,
13931 0,
13932 0,
13933 0,
13934 0,
13961 0,
13962 0,
13963 0,
13964 0,
13966 0,
13967 0,
13968 0,
13969 0,
13970 0,
13972 0,
13973 0,
13975 0,
13976 0,
13977 0,
13978 0,
13979 0,
13980 0,
13981 0,
13984 0,
13986 0,
13995 0,
13996 0,
13997 0,
13998 0,
13999 0,
14000 0,
14001 0,
14002 0,
14003 0,
14004 0,
14005 0,
14021 0,
14022 0,
14023 0,
14024 0,
14026 0,
14027 0,
14028 0,
14029 0,
14030 0,
14032 0,
14033 0,
14035 0,
14036 0,
14037 0,
14038 0,
14039 0,
14040 0,
14041 0,
14044 0,
14046 0,
14055 0,
14056 0,
14057 0,
14058 0,
14059 0,
14060 0,
14061 0,
14062 0,
14063 0,
14064 0,
14065 0,
14081 0,
14082 0,
14083 0,
14084 0,
14086 0,
14087 0,
14088 0,
14089 0,
14090 0,
14092 0,
14093 0,
14095 0,
14096 0,
14097 0,
14098 0,
14099 0,
14100 0,
14101 0,
14104 0,
14106 0,
14115 0,
14116 0,
14117 0,
14118 0,
14119 0,
14120 0,
14121 0,
14122 0,
14123 0,
14124 0,
14125 0,
14141 0,
14142 0,
14143 0,
14144 0,
14146 0,
14147 0,
14148 0,
14149 0,
14150 0,
14152 0,
14153 0,
14155 0,
14156 0,
14157 0,
14158 0,
14159 0,
14160 0,
14161 0,
14164 0,
14166 0,
14175 0,
14176 0,
14177 0,
14178 0,
14179 0,
14180 0,
14181 0,
14182 0,
14183 0,
14184 0,
14185 0,
14199 { "Inst", "x24", 0,
14203 { "Inst16a", "x16a", 0,
14207 { "Inst16b", "x16b", 0,
14219 insn[0] = 0;
14225 insn[0] = 0x8;
14231 insn[0] = 0xc;
14234 static int Format_x24_slots[] = { 0 };
14250 if ((insn[0] & 0x8) == 0)
14251 return 0; /* x24 */
14252 if ((insn[0] & 0xc) == 0x8)
14254 if ((insn[0] & 0xe) == 0xc)
14521 int l = insn[0];
14529 0 /* little-endian */,
14530 3 /* insn_size */, 0,
14536 439, opcodes, 0,
14538 NUM_STATES, states, 0,
14539 NUM_SYSREGS, sysregs, 0,
14540 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
14541 6, interfaces, 0,
14542 0, funcUnits, 0