Lines Matching +full:0 +full:xd00000
29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
32 { "ACCLO", 16, 0 },
33 { "ACCHI", 17, 0 },
34 { "M0", 32, 0 },
35 { "M1", 33, 0 },
36 { "M2", 34, 0 },
37 { "M3", 35, 0 },
38 { "PTEVADDR", 83, 0 },
39 { "MMID", 89, 0 },
40 { "DDR", 104, 0 },
41 { "176", 176, 0 },
42 { "208", 208, 0 },
43 { "INTERRUPT", 226, 0 },
44 { "INTCLEAR", 227, 0 },
45 { "CCOUNT", 234, 0 },
46 { "PRID", 235, 0 },
47 { "ICOUNT", 236, 0 },
48 { "CCOMPARE0", 240, 0 },
49 { "CCOMPARE1", 241, 0 },
50 { "CCOMPARE2", 242, 0 },
51 { "VECBASE", 231, 0 },
52 { "EPC1", 177, 0 },
53 { "EPC2", 178, 0 },
54 { "EPC3", 179, 0 },
55 { "EPC4", 180, 0 },
56 { "EPC5", 181, 0 },
57 { "EPC6", 182, 0 },
58 { "EPC7", 183, 0 },
59 { "EXCSAVE1", 209, 0 },
60 { "EXCSAVE2", 210, 0 },
61 { "EXCSAVE3", 211, 0 },
62 { "EXCSAVE4", 212, 0 },
63 { "EXCSAVE5", 213, 0 },
64 { "EXCSAVE6", 214, 0 },
65 { "EXCSAVE7", 215, 0 },
66 { "EPS2", 194, 0 },
67 { "EPS3", 195, 0 },
68 { "EPS4", 196, 0 },
69 { "EPS5", 197, 0 },
70 { "EPS6", 198, 0 },
71 { "EPS7", 199, 0 },
72 { "EXCCAUSE", 232, 0 },
73 { "DEPC", 192, 0 },
74 { "EXCVADDR", 238, 0 },
75 { "WINDOWBASE", 72, 0 },
76 { "WINDOWSTART", 73, 0 },
77 { "SAR", 3, 0 },
78 { "LITBASE", 5, 0 },
79 { "PS", 230, 0 },
80 { "MISC0", 244, 0 },
81 { "MISC1", 245, 0 },
82 { "INTENABLE", 228, 0 },
83 { "DBREAKA0", 144, 0 },
84 { "DBREAKC0", 160, 0 },
85 { "DBREAKA1", 145, 0 },
86 { "DBREAKC1", 161, 0 },
87 { "IBREAKA0", 128, 0 },
88 { "IBREAKA1", 129, 0 },
89 { "IBREAKENABLE", 96, 0 },
90 { "ICOUNTLEVEL", 237, 0 },
91 { "DEBUGCAUSE", 233, 0 },
92 { "RASID", 90, 0 },
93 { "ITLBCFG", 91, 0 },
94 { "DTLBCFG", 92, 0 },
95 { "CPENABLE", 224, 0 },
96 { "SCOMPARE1", 12, 0 },
109 { "LCOUNT", 32, 0 },
110 { "PC", 32, 0 },
111 { "ICOUNT", 32, 0 },
112 { "DDR", 32, 0 },
113 { "INTERRUPT", 22, 0 },
114 { "CCOUNT", 32, 0 },
115 { "XTSYNC", 1, 0 },
116 { "VECBASE", 22, 0 },
117 { "EPC1", 32, 0 },
118 { "EPC2", 32, 0 },
119 { "EPC3", 32, 0 },
120 { "EPC4", 32, 0 },
121 { "EPC5", 32, 0 },
122 { "EPC6", 32, 0 },
123 { "EPC7", 32, 0 },
124 { "EXCSAVE1", 32, 0 },
125 { "EXCSAVE2", 32, 0 },
126 { "EXCSAVE3", 32, 0 },
127 { "EXCSAVE4", 32, 0 },
128 { "EXCSAVE5", 32, 0 },
129 { "EXCSAVE6", 32, 0 },
130 { "EXCSAVE7", 32, 0 },
131 { "EPS2", 15, 0 },
132 { "EPS3", 15, 0 },
133 { "EPS4", 15, 0 },
134 { "EPS5", 15, 0 },
135 { "EPS6", 15, 0 },
136 { "EPS7", 15, 0 },
137 { "EXCCAUSE", 6, 0 },
138 { "PSINTLEVEL", 4, 0 },
139 { "PSUM", 1, 0 },
140 { "PSWOE", 1, 0 },
141 { "PSRING", 2, 0 },
142 { "PSEXCM", 1, 0 },
143 { "DEPC", 32, 0 },
144 { "EXCVADDR", 32, 0 },
145 { "WindowBase", 3, 0 },
146 { "WindowStart", 8, 0 },
147 { "PSCALLINC", 2, 0 },
148 { "PSOWB", 4, 0 },
149 { "LBEG", 32, 0 },
150 { "LEND", 32, 0 },
151 { "SAR", 6, 0 },
152 { "THREADPTR", 32, 0 },
153 { "LITBADDR", 20, 0 },
154 { "LITBEN", 1, 0 },
155 { "MISC0", 32, 0 },
156 { "MISC1", 32, 0 },
157 { "ACC", 40, 0 },
158 { "InOCDMode", 1, 0 },
159 { "INTENABLE", 22, 0 },
160 { "DBREAKA0", 32, 0 },
161 { "DBREAKC0", 8, 0 },
162 { "DBREAKA1", 32, 0 },
163 { "DBREAKC1", 8, 0 },
164 { "IBREAKA0", 32, 0 },
165 { "IBREAKA1", 32, 0 },
166 { "IBREAKENABLE", 2, 0 },
167 { "ICOUNTLEVEL", 4, 0 },
168 { "DEBUGCAUSE", 6, 0 },
169 { "DBNUM", 4, 0 },
170 { "CCOMPARE0", 32, 0 },
171 { "CCOMPARE1", 32, 0 },
172 { "CCOMPARE2", 32, 0 },
173 { "ASID3", 8, 0 },
174 { "ASID2", 8, 0 },
175 { "ASID1", 8, 0 },
176 { "INSTPGSZID4", 2, 0 },
177 { "DATAPGSZID4", 2, 0 },
178 { "PTBASE", 10, 0 },
179 { "CPENABLE", 8, 0 },
180 { "SCOMPARE1", 32, 0 },
189 #define STATE_LCOUNT 0
269 unsigned tie_t = 0;
270 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
279 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
285 unsigned tie_t = 0;
286 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
295 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
301 unsigned tie_t = 0;
302 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
311 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
317 unsigned tie_t = 0;
318 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
327 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
333 unsigned tie_t = 0;
334 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
335 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
344 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
346 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
352 unsigned tie_t = 0;
353 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
362 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
368 unsigned tie_t = 0;
369 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
378 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
384 unsigned tie_t = 0;
385 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
394 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
400 unsigned tie_t = 0;
401 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
410 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
416 unsigned tie_t = 0;
417 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
426 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
432 unsigned tie_t = 0;
433 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
434 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
443 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
445 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
451 unsigned tie_t = 0;
452 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
461 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
467 unsigned tie_t = 0;
468 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
477 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
483 unsigned tie_t = 0;
484 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
493 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
499 unsigned tie_t = 0;
500 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
509 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
515 unsigned tie_t = 0;
516 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
525 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
531 unsigned tie_t = 0;
532 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
541 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
547 unsigned tie_t = 0;
548 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
557 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
563 unsigned tie_t = 0;
564 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
573 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
579 unsigned tie_t = 0;
580 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
589 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
595 unsigned tie_t = 0;
596 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
605 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
611 unsigned tie_t = 0;
612 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
621 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
627 unsigned tie_t = 0;
628 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
637 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
643 unsigned tie_t = 0;
644 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
653 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
659 unsigned tie_t = 0;
660 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
669 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
675 unsigned tie_t = 0;
676 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
677 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
686 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
688 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
694 unsigned tie_t = 0;
695 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
696 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
705 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
707 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
713 unsigned tie_t = 0;
714 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
715 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
724 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
726 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
732 unsigned tie_t = 0;
733 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
742 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
748 unsigned tie_t = 0;
749 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
750 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
759 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
761 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
767 unsigned tie_t = 0;
768 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
769 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
778 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
780 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
786 unsigned tie_t = 0;
787 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
788 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
797 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
799 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
805 unsigned tie_t = 0;
806 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
807 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
816 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
818 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
824 unsigned tie_t = 0;
825 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
826 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
835 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
837 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
843 unsigned tie_t = 0;
844 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
845 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
854 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
856 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
862 unsigned tie_t = 0;
863 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
864 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
873 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
875 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
881 unsigned tie_t = 0;
882 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
891 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
897 unsigned tie_t = 0;
898 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
907 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
913 unsigned tie_t = 0;
914 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
923 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
929 unsigned tie_t = 0;
930 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
939 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
945 unsigned tie_t = 0;
946 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
947 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
956 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
958 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
964 unsigned tie_t = 0;
965 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
974 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
980 unsigned tie_t = 0;
981 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
990 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
996 unsigned tie_t = 0;
997 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1006 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1012 unsigned tie_t = 0;
1013 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1022 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1028 unsigned tie_t = 0;
1029 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1038 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1044 unsigned tie_t = 0;
1045 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1054 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1060 unsigned tie_t = 0;
1061 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1070 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1076 unsigned tie_t = 0;
1077 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1086 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1092 unsigned tie_t = 0;
1093 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1102 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1108 unsigned tie_t = 0;
1109 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1118 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1124 unsigned tie_t = 0;
1125 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1134 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1140 unsigned tie_t = 0;
1141 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1150 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1156 unsigned tie_t = 0;
1157 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1158 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1167 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1169 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1175 unsigned tie_t = 0;
1176 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1177 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1186 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1188 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1194 unsigned tie_t = 0;
1195 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1196 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1205 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1207 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1213 unsigned tie_t = 0;
1214 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1215 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1224 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1226 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1232 unsigned tie_t = 0;
1233 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1242 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1248 unsigned tie_t = 0;
1249 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1258 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1264 unsigned tie_t = 0;
1265 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1274 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1280 unsigned tie_t = 0;
1281 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1290 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1296 unsigned tie_t = 0;
1297 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1306 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1312 unsigned tie_t = 0;
1313 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1322 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1328 unsigned tie_t = 0;
1329 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1338 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1344 unsigned tie_t = 0;
1345 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1354 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1360 unsigned tie_t = 0;
1361 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1370 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1376 unsigned tie_t = 0;
1377 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1386 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1392 unsigned tie_t = 0;
1393 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1402 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1408 unsigned tie_t = 0;
1409 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1410 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1419 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1421 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1427 unsigned tie_t = 0;
1428 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1429 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1438 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1440 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1446 unsigned tie_t = 0;
1447 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1448 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1457 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1459 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1465 unsigned tie_t = 0;
1466 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1475 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1481 unsigned tie_t = 0;
1482 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1491 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1497 unsigned tie_t = 0;
1498 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1507 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1520 return 0;
1544 return 0;
1576 { "AR", "a", 0, 32, 32 },
1584 { "IMPWIRE", 32, 0, 0, 'i' }
1592 0xffffffff,
1593 0x1,
1594 0x2,
1595 0x3,
1596 0x4,
1597 0x5,
1598 0x6,
1599 0x7,
1600 0x8,
1601 0x9,
1602 0xa,
1603 0xb,
1604 0xc,
1605 0xd,
1606 0xe,
1607 0xf,
1608 0
1613 0xffffffff,
1614 0x1,
1615 0x2,
1616 0x3,
1617 0x4,
1618 0x5,
1619 0x6,
1620 0x7,
1621 0x8,
1622 0xa,
1623 0xc,
1624 0x10,
1625 0x20,
1626 0x40,
1627 0x80,
1628 0x100,
1629 0
1634 0x8000,
1635 0x10000,
1636 0x2,
1637 0x3,
1638 0x4,
1639 0x5,
1640 0x6,
1641 0x7,
1642 0x8,
1643 0xa,
1644 0xc,
1645 0x10,
1646 0x20,
1647 0x40,
1648 0x80,
1649 0x100,
1650 0
1660 offset_0 = *valp & 0x3ffff;
1661 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1663 return 0;
1671 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1673 return 0;
1679 *valp -= (pc & ~0x3);
1680 return 0;
1686 *valp += (pc & ~0x3);
1687 return 0;
1694 imm12_0 = *valp & 0xfff;
1697 return 0;
1705 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1707 return 0;
1714 mn_0 = *valp & 0xf;
1717 return 0;
1725 mn_0 = (simm4_0 & 0xf);
1727 return 0;
1733 return 0;
1739 return (*valp & ~0xf) != 0;
1745 return 0;
1751 return (*valp & ~0xf) != 0;
1757 return 0;
1763 return (*valp & ~0xf) != 0;
1769 return 0;
1775 return (*valp & ~0x1f) != 0;
1781 return 0;
1787 return (*valp & ~0x1f) != 0;
1793 return 0;
1799 return (*valp & ~0x1f) != 0;
1805 return 0;
1811 return (*valp & ~0x1f) != 0;
1817 return 0;
1823 return (*valp & ~0x1f) != 0;
1830 r_0 = *valp & 0xf;
1831 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
1833 return 0;
1841 r_0 = ((immrx4_0 >> 2) & 0xf);
1843 return 0;
1850 r_0 = *valp & 0xf;
1853 return 0;
1861 r_0 = ((lsi4x4_0 >> 2) & 0xf);
1863 return 0;
1870 imm7_0 = *valp & 0x7f;
1871 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
1873 return 0;
1881 imm7_0 = (simm7_0 & 0x7f);
1883 return 0;
1890 imm6_0 = *valp & 0x3f;
1891 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
1893 return 0;
1901 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
1903 return 0;
1910 return 0;
1917 return 0;
1924 t_0 = *valp & 0xf;
1925 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
1927 return 0;
1937 case 0xffffffff: t_0 = 0; break;
1938 case 0x1: t_0 = 0x1; break;
1939 case 0x2: t_0 = 0x2; break;
1940 case 0x3: t_0 = 0x3; break;
1941 case 0x4: t_0 = 0x4; break;
1942 case 0x5: t_0 = 0x5; break;
1943 case 0x6: t_0 = 0x6; break;
1944 case 0x7: t_0 = 0x7; break;
1945 case 0x8: t_0 = 0x8; break;
1946 case 0x9: t_0 = 0x9; break;
1947 case 0xa: t_0 = 0xa; break;
1948 case 0xb: t_0 = 0xb; break;
1949 case 0xc: t_0 = 0xc; break;
1950 case 0xd: t_0 = 0xd; break;
1951 case 0xe: t_0 = 0xe; break;
1952 default: t_0 = 0xf; break;
1955 return 0;
1962 r_0 = *valp & 0xf;
1963 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
1965 return 0;
1975 case 0xffffffff: r_0 = 0; break;
1976 case 0x1: r_0 = 0x1; break;
1977 case 0x2: r_0 = 0x2; break;
1978 case 0x3: r_0 = 0x3; break;
1979 case 0x4: r_0 = 0x4; break;
1980 case 0x5: r_0 = 0x5; break;
1981 case 0x6: r_0 = 0x6; break;
1982 case 0x7: r_0 = 0x7; break;
1983 case 0x8: r_0 = 0x8; break;
1984 case 0xa: r_0 = 0x9; break;
1985 case 0xc: r_0 = 0xa; break;
1986 case 0x10: r_0 = 0xb; break;
1987 case 0x20: r_0 = 0xc; break;
1988 case 0x40: r_0 = 0xd; break;
1989 case 0x80: r_0 = 0xe; break;
1990 default: r_0 = 0xf; break;
1993 return 0;
2000 r_0 = *valp & 0xf;
2001 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2003 return 0;
2013 case 0x8000: r_0 = 0; break;
2014 case 0x10000: r_0 = 0x1; break;
2015 case 0x2: r_0 = 0x2; break;
2016 case 0x3: r_0 = 0x3; break;
2017 case 0x4: r_0 = 0x4; break;
2018 case 0x5: r_0 = 0x5; break;
2019 case 0x6: r_0 = 0x6; break;
2020 case 0x7: r_0 = 0x7; break;
2021 case 0x8: r_0 = 0x8; break;
2022 case 0xa: r_0 = 0x9; break;
2023 case 0xc: r_0 = 0xa; break;
2024 case 0x10: r_0 = 0xb; break;
2025 case 0x20: r_0 = 0xc; break;
2026 case 0x40: r_0 = 0xd; break;
2027 case 0x80: r_0 = 0xe; break;
2028 default: r_0 = 0xf; break;
2031 return 0;
2038 imm8_0 = *valp & 0xff;
2041 return 0;
2049 imm8_0 = (uimm8_0 & 0xff);
2051 return 0;
2058 imm8_0 = *valp & 0xff;
2061 return 0;
2069 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2071 return 0;
2078 imm8_0 = *valp & 0xff;
2081 return 0;
2089 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2091 return 0;
2098 op2_0 = *valp & 0xf;
2101 return 0;
2109 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2111 return 0;
2118 imm8_0 = *valp & 0xff;
2121 return 0;
2129 imm8_0 = (simm8_0 & 0xff);
2131 return 0;
2138 imm8_0 = *valp & 0xff;
2141 return 0;
2149 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2151 return 0;
2158 imm12b_0 = *valp & 0xfff;
2161 return 0;
2169 imm12b_0 = (simm12b_0 & 0xfff);
2171 return 0;
2178 sal_0 = *valp & 0x1f;
2179 msalp32_0 = 0x20 - sal_0;
2181 return 0;
2189 sal_0 = (0x20 - msalp32_0) & 0x1f;
2191 return 0;
2198 op2_0 = *valp & 0xf;
2199 op2p1_0 = op2_0 + 0x1;
2201 return 0;
2209 op2_0 = (op2p1_0 - 0x1) & 0xf;
2211 return 0;
2218 imm8_0 = *valp & 0xff;
2219 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2221 return 0;
2229 imm8_0 = (label8_0 - 0x4) & 0xff;
2231 return 0;
2238 return 0;
2245 return 0;
2252 imm8_0 = *valp & 0xff;
2253 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2255 return 0;
2263 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2265 return 0;
2272 return 0;
2279 return 0;
2286 imm12_0 = *valp & 0xfff;
2287 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2289 return 0;
2297 imm12_0 = (label12_0 - 0x4) & 0xfff;
2299 return 0;
2306 return 0;
2313 return 0;
2320 offset_0 = *valp & 0x3ffff;
2321 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2323 return 0;
2331 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2333 return 0;
2340 return 0;
2347 return 0;
2354 imm16_0 = *valp & 0xffff;
2355 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2357 return 0;
2365 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2367 return 0;
2373 *valp -= ((pc + 3) & ~0x3);
2374 return 0;
2380 *valp += ((pc + 3) & ~0x3);
2381 return 0;
2387 return 0;
2393 return (*valp & ~0x3) != 0;
2400 return 0;
2407 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
2415 return 0;
2421 return (*valp & ~0x3) != 0;
2427 return 0;
2433 return (*valp & ~0x3) != 0;
2439 return 0;
2445 return (*valp & ~0x3) != 0;
2451 return 0;
2457 return (*valp & ~0x3) != 0;
2463 return 0;
2469 return (*valp & ~0x3) != 0;
2476 t_0 = *valp & 0xf;
2479 return 0;
2487 t_0 = immt_0 & 0xf;
2489 return 0;
2496 s_0 = *valp & 0xf;
2499 return 0;
2507 s_0 = imms_0 & 0xf;
2509 return 0;
2516 t_0 = *valp & 0xf;
2517 tp7_0 = t_0 + 0x7;
2519 return 0;
2527 t_0 = (tp7_0 - 0x7) & 0xf;
2529 return 0;
2536 xt_wbr15_imm_0 = *valp & 0x7fff;
2537 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
2539 return 0;
2547 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
2549 return 0;
2556 return 0;
2563 return 0;
2570 xt_wbr18_imm_0 = *valp & 0x3ffff;
2571 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
2573 return 0;
2581 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
2583 return 0;
2590 return 0;
2597 return 0;
2601 { "soffsetx4", 10, -1, 0,
2605 { "uimm12x8", 3, -1, 0,
2606 0,
2608 0, 0 },
2609 { "simm4", 26, -1, 0,
2610 0,
2612 0, 0 },
2613 { "arr", 14, 0, 1,
2616 0, 0 },
2617 { "ars", 5, 0, 1,
2620 0, 0 },
2621 { "*ars_invisible", 5, 0, 1,
2624 0, 0 },
2625 { "art", 0, 0, 1,
2628 0, 0 },
2629 { "ar0", 48, 0, 1,
2632 0, 0 },
2633 { "ar4", 49, 0, 1,
2636 0, 0 },
2637 { "ar8", 50, 0, 1,
2640 0, 0 },
2641 { "ar12", 51, 0, 1,
2644 0, 0 },
2645 { "ars_entry", 5, 0, 1,
2648 0, 0 },
2649 { "immrx4", 14, -1, 0,
2650 0,
2652 0, 0 },
2653 { "lsi4x4", 14, -1, 0,
2654 0,
2656 0, 0 },
2657 { "simm7", 34, -1, 0,
2658 0,
2660 0, 0 },
2661 { "uimm6", 33, -1, 0,
2665 { "ai4const", 0, -1, 0,
2666 0,
2668 0, 0 },
2669 { "b4const", 14, -1, 0,
2670 0,
2672 0, 0 },
2673 { "b4constu", 14, -1, 0,
2674 0,
2676 0, 0 },
2677 { "uimm8", 4, -1, 0,
2678 0,
2680 0, 0 },
2681 { "uimm8x2", 4, -1, 0,
2682 0,
2684 0, 0 },
2685 { "uimm8x4", 4, -1, 0,
2686 0,
2688 0, 0 },
2689 { "uimm4x16", 13, -1, 0,
2690 0,
2692 0, 0 },
2693 { "simm8", 4, -1, 0,
2694 0,
2696 0, 0 },
2697 { "simm8x256", 4, -1, 0,
2698 0,
2700 0, 0 },
2701 { "simm12b", 6, -1, 0,
2702 0,
2704 0, 0 },
2705 { "msalp32", 18, -1, 0,
2706 0,
2708 0, 0 },
2709 { "op2p1", 13, -1, 0,
2710 0,
2712 0, 0 },
2713 { "label8", 4, -1, 0,
2717 { "ulabel8", 4, -1, 0,
2721 { "label12", 3, -1, 0,
2725 { "soffset", 10, -1, 0,
2729 { "uimm16x4", 7, -1, 0,
2736 0, 0 },
2740 0, 0 },
2744 0, 0 },
2748 0, 0 },
2752 0, 0 },
2756 0, 0 },
2760 0, 0 },
2761 { "immt", 0, -1, 0,
2762 0,
2764 0, 0 },
2765 { "imms", 5, -1, 0,
2766 0,
2768 0, 0 },
2769 { "tp7", 0, -1, 0,
2770 0,
2772 0, 0 },
2773 { "xt_wbr15_label", 44, -1, 0,
2777 { "xt_wbr18_label", 45, -1, 0,
2781 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
2782 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
2783 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
2784 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
2785 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
2786 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
2787 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
2788 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
2789 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
2790 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
2791 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
2792 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
2793 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
2794 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
2795 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
2796 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
2797 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
2798 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
2799 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
2800 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
2801 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
2802 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
2803 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
2804 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
2805 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
2806 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
2807 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
2808 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
2809 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
2810 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
2811 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
2812 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
2813 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
2814 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
2815 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
2816 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
2817 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
2818 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
2819 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
2820 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
2821 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
2822 { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
2823 { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
2824 { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
2825 { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 },
2826 { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 },
2827 { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 },
2828 { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 }
2847 { { 0 /* soffsetx4 */ }, 'i' },
2856 { { 0 /* soffsetx4 */ }, 'i' },
2865 { { 0 /* soffsetx4 */ }, 'i' },
3149 { { 0 /* soffsetx4 */ }, 'i' },
5613 0 /* IMPWIRE */
5645 { 0, 0 /* xt_iclass_excw */,
5646 0, 0, 0, 0 },
5647 { 0, 0 /* xt_iclass_rfe */,
5648 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5649 { 0, 0 /* xt_iclass_rfde */,
5650 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5651 { 0, 0 /* xt_iclass_syscall */,
5652 0, 0, 0, 0 },
5653 { 0, 0 /* xt_iclass_simcall */,
5654 0, 0, 0, 0 },
5656 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5658 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5660 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5662 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5664 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5666 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5668 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5670 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5672 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5674 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5675 { 0, 0 /* xt_iclass_rfwou */,
5676 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5678 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
5680 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
5682 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5684 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5686 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5688 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5690 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5692 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5694 0, 0, 0, 0 },
5696 0, 0, 0, 0 },
5698 0, 0, 0, 0 },
5699 { 0, 0 /* xt_iclass_ill_n */,
5700 0, 0, 0, 0 },
5702 0, 0, 0, 0 },
5704 0, 0, 0, 0 },
5706 0, 0, 0, 0 },
5707 { 0, 0 /* xt_iclass_nopn */,
5708 0, 0, 0, 0 },
5710 0, 0, 0, 0 },
5712 0, 0, 0, 0 },
5714 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
5716 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
5718 0, 0, 0, 0 },
5720 0, 0, 0, 0 },
5722 0, 0, 0, 0 },
5724 0, 0, 0, 0 },
5726 0, 0, 0, 0 },
5728 0, 0, 0, 0 },
5730 0, 0, 0, 0 },
5732 0, 0, 0, 0 },
5734 0, 0, 0, 0 },
5736 0, 0, 0, 0 },
5738 0, 0, 0, 0 },
5740 0, 0, 0, 0 },
5741 { 0, 0 /* xt_iclass_ill */,
5742 0, 0, 0, 0 },
5744 0, 0, 0, 0 },
5746 0, 0, 0, 0 },
5748 0, 0, 0, 0 },
5750 0, 0, 0, 0 },
5752 0, 0, 0, 0 },
5754 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
5756 0, 0, 0, 0 },
5758 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5760 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5762 0, 0, 0, 0 },
5764 0, 0, 0, 0 },
5766 0, 0, 0, 0 },
5767 { 0, 0 /* xt_iclass_nop */,
5768 0, 0, 0, 0 },
5770 0, 0, 0, 0 },
5772 0, 0, 0, 0 },
5774 0, 0, 0, 0 },
5776 0, 0, 0, 0 },
5778 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5780 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5782 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5784 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5786 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5788 0, 0, 0, 0 },
5790 0, 0, 0, 0 },
5792 0, 0, 0, 0 },
5793 { 0, 0 /* xt_iclass_memw */,
5794 0, 0, 0, 0 },
5795 { 0, 0 /* xt_iclass_extw */,
5796 0, 0, 0, 0 },
5797 { 0, 0 /* xt_iclass_isync */,
5798 0, 0, 0, 0 },
5799 { 0, 0 /* xt_iclass_sync */,
5800 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5802 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5804 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5806 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5808 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5810 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5812 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5814 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5816 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5818 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5820 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5822 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5824 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5826 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5828 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
5830 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
5832 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
5834 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
5836 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
5838 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5840 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5842 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5844 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5846 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5848 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5850 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5852 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5854 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5856 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5858 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5860 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5862 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5864 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5866 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5868 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5870 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5872 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5874 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5876 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5878 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5880 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5882 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5884 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5886 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5888 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5890 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5892 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5894 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5896 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5898 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5900 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5902 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5904 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5906 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5908 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5910 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5912 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5914 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5916 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5918 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5920 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5922 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5924 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5926 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5928 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5930 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5932 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5934 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5936 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5938 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5940 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5942 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5944 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5946 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5948 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5950 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5952 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5954 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5956 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5958 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5960 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5962 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5964 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5966 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5968 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5970 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5972 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5974 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5976 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5978 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5980 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5982 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5984 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5986 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5988 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5990 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5992 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5994 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
5996 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5998 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
6000 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
6002 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
6004 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
6006 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
6008 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
6010 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
6012 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
6014 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
6016 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
6018 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
6020 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
6022 0, 0, 0, 0 },
6024 0, 0, 0, 0 },
6026 0, 0, 0, 0 },
6028 0, 0, 0, 0 },
6030 0, 0, 0, 0 },
6032 0, 0, 0, 0 },
6034 0, 0, 0, 0 },
6036 0, 0, 0, 0 },
6038 0, 0, 0, 0 },
6040 0, 0, 0, 0 },
6042 0, 0, 0, 0 },
6044 0, 0, 0, 0 },
6046 0, 0, 0, 0 },
6048 0, 0, 0, 0 },
6050 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
6052 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
6054 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
6056 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
6058 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
6060 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
6062 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
6064 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
6066 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
6068 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
6070 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
6072 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
6074 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
6076 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
6078 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
6080 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
6082 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
6084 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
6086 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
6088 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
6090 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
6092 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
6094 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
6096 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
6098 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
6100 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
6102 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
6104 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
6106 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
6108 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
6110 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
6112 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
6114 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
6116 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
6118 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
6120 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
6122 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
6124 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
6126 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
6128 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
6130 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
6132 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
6134 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
6136 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
6138 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
6140 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
6142 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
6144 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
6146 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
6148 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
6149 { 0, 0 /* xt_iclass_rfdd */,
6150 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
6152 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
6154 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
6156 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
6158 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
6160 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
6162 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
6164 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
6166 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
6168 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
6170 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
6172 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
6174 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
6176 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
6178 0, 0, 0, 0 },
6180 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
6182 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
6184 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
6186 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
6188 0, 0, 0, 0 },
6190 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
6192 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
6194 0, 0, 0, 0 },
6196 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
6198 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
6200 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
6202 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
6204 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
6206 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
6208 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
6210 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
6212 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
6214 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
6216 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
6218 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
6220 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
6222 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
6224 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
6226 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
6228 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
6230 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
6232 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
6234 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
6236 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
6237 { 0, 0 /* xt_iclass_ldpte */,
6238 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
6239 { 0, 0 /* xt_iclass_hwwitlba */,
6240 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
6241 { 0, 0 /* xt_iclass_hwwdtlba */,
6242 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
6244 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
6246 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
6248 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
6250 0, 0, 0, 0 },
6252 0, 0, 0, 0 },
6254 0, 0, 0, 0 },
6256 0, 0, 0, 0 },
6258 0, 0, 0, 0 },
6260 0, 0, 0, 0 },
6262 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6264 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6266 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6268 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6270 0, 0, 0, 0 },
6272 0, 0, 0, 0 },
6274 2, Iclass_rur_expstate_stateArgs, 0, 0 },
6276 2, Iclass_wur_expstate_stateArgs, 0, 0 },
6280 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6282 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6284 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6293 slotbuf[0] = 0x2080;
6299 slotbuf[0] = 0x3000;
6305 slotbuf[0] = 0x3200;
6311 slotbuf[0] = 0x5000;
6317 slotbuf[0] = 0x5100;
6323 slotbuf[0] = 0x35;
6329 slotbuf[0] = 0x25;
6335 slotbuf[0] = 0x15;
6341 slotbuf[0] = 0xf0;
6347 slotbuf[0] = 0xe0;
6353 slotbuf[0] = 0xd0;
6359 slotbuf[0] = 0x36;
6365 slotbuf[0] = 0x1000;
6371 slotbuf[0] = 0x408000;
6377 slotbuf[0] = 0x90;
6383 slotbuf[0] = 0xf01d;
6389 slotbuf[0] = 0x3400;
6395 slotbuf[0] = 0x3500;
6401 slotbuf[0] = 0x90000;
6407 slotbuf[0] = 0x490000;
6413 slotbuf[0] = 0x34800;
6419 slotbuf[0] = 0x134800;
6425 slotbuf[0] = 0x614800;
6431 slotbuf[0] = 0x34900;
6437 slotbuf[0] = 0x134900;
6443 slotbuf[0] = 0x614900;
6449 slotbuf[0] = 0xa;
6455 slotbuf[0] = 0xb;
6461 slotbuf[0] = 0x8c;
6467 slotbuf[0] = 0xcc;
6473 slotbuf[0] = 0xf06d;
6479 slotbuf[0] = 0x8;
6485 slotbuf[0] = 0xd;
6491 slotbuf[0] = 0xc;
6497 slotbuf[0] = 0xf03d;
6503 slotbuf[0] = 0xf00d;
6509 slotbuf[0] = 0x9;
6515 slotbuf[0] = 0xe30e70;
6521 slotbuf[0] = 0xf3e700;
6527 slotbuf[0] = 0xc002;
6533 slotbuf[0] = 0xd002;
6539 slotbuf[0] = 0x800000;
6545 slotbuf[0] = 0xc00000;
6551 slotbuf[0] = 0x900000;
6557 slotbuf[0] = 0xa00000;
6563 slotbuf[0] = 0xb00000;
6569 slotbuf[0] = 0xd00000;
6575 slotbuf[0] = 0xe00000;
6581 slotbuf[0] = 0xf00000;
6587 slotbuf[0] = 0x100000;
6593 slotbuf[0] = 0x200000;
6599 slotbuf[0] = 0x300000;
6605 slotbuf[0] = 0x26;
6611 slotbuf[0] = 0x66;
6617 slotbuf[0] = 0xe6;
6623 slotbuf[0] = 0xa6;
6629 slotbuf[0] = 0x6007;
6635 slotbuf[0] = 0xe007;
6641 slotbuf[0] = 0xf6;
6647 slotbuf[0] = 0xb6;
6653 slotbuf[0] = 0x1007;
6659 slotbuf[0] = 0x9007;
6665 slotbuf[0] = 0xa007;
6671 slotbuf[0] = 0x2007;
6677 slotbuf[0] = 0xb007;
6683 slotbuf[0] = 0x3007;
6689 slotbuf[0] = 0x8007;
6695 slotbuf[0] = 0x7;
6701 slotbuf[0] = 0x4007;
6707 slotbuf[0] = 0xc007;
6713 slotbuf[0] = 0x5007;
6719 slotbuf[0] = 0xd007;
6725 slotbuf[0] = 0x16;
6731 slotbuf[0] = 0x56;
6737 slotbuf[0] = 0xd6;
6743 slotbuf[0] = 0x96;
6749 slotbuf[0] = 0x5;
6755 slotbuf[0] = 0xc0;
6761 slotbuf[0] = 0x40000;
6767 slotbuf[0] = 0;
6773 slotbuf[0] = 0x6;
6779 slotbuf[0] = 0xa0;
6785 slotbuf[0] = 0x1002;
6791 slotbuf[0] = 0x9002;
6797 slotbuf[0] = 0x2002;
6803 slotbuf[0] = 0x1;
6809 slotbuf[0] = 0x2;
6815 slotbuf[0] = 0x8076;
6821 slotbuf[0] = 0x9076;
6827 slotbuf[0] = 0xa076;
6833 slotbuf[0] = 0xa002;
6839 slotbuf[0] = 0x830000;
6845 slotbuf[0] = 0x930000;
6851 slotbuf[0] = 0xa30000;
6857 slotbuf[0] = 0xb30000;
6863 slotbuf[0] = 0x600000;
6869 slotbuf[0] = 0x600100;
6875 slotbuf[0] = 0x20f0;
6881 slotbuf[0] = 0x80;
6887 slotbuf[0] = 0x5002;
6893 slotbuf[0] = 0x6002;
6899 slotbuf[0] = 0x4002;
6905 slotbuf[0] = 0x400000;
6911 slotbuf[0] = 0x401000;
6917 slotbuf[0] = 0x402000;
6923 slotbuf[0] = 0x403000;
6929 slotbuf[0] = 0x404000;
6935 slotbuf[0] = 0xa10000;
6941 slotbuf[0] = 0x810000;
6947 slotbuf[0] = 0x910000;
6953 slotbuf[0] = 0xb10000;
6959 slotbuf[0] = 0x10000;
6965 slotbuf[0] = 0x210000;
6971 slotbuf[0] = 0x410000;
6977 slotbuf[0] = 0x20c0;
6983 slotbuf[0] = 0x20d0;
6989 slotbuf[0] = 0x2000;
6995 slotbuf[0] = 0x2010;
7001 slotbuf[0] = 0x2020;
7007 slotbuf[0] = 0x2030;
7013 slotbuf[0] = 0x6000;
7019 slotbuf[0] = 0x30100;
7025 slotbuf[0] = 0x130100;
7031 slotbuf[0] = 0x610100;
7037 slotbuf[0] = 0x30200;
7043 slotbuf[0] = 0x130200;
7049 slotbuf[0] = 0x610200;
7055 slotbuf[0] = 0x30000;
7061 slotbuf[0] = 0x130000;
7067 slotbuf[0] = 0x610000;
7073 slotbuf[0] = 0x30300;
7079 slotbuf[0] = 0x130300;
7085 slotbuf[0] = 0x610300;
7091 slotbuf[0] = 0x30500;
7097 slotbuf[0] = 0x130500;
7103 slotbuf[0] = 0x610500;
7109 slotbuf[0] = 0x3b000;
7115 slotbuf[0] = 0x3d000;
7121 slotbuf[0] = 0x3e600;
7127 slotbuf[0] = 0x13e600;
7133 slotbuf[0] = 0x61e600;
7139 slotbuf[0] = 0x3b100;
7145 slotbuf[0] = 0x13b100;
7151 slotbuf[0] = 0x61b100;
7157 slotbuf[0] = 0x3d100;
7163 slotbuf[0] = 0x13d100;
7169 slotbuf[0] = 0x61d100;
7175 slotbuf[0] = 0x3b200;
7181 slotbuf[0] = 0x13b200;
7187 slotbuf[0] = 0x61b200;
7193 slotbuf[0] = 0x3d200;
7199 slotbuf[0] = 0x13d200;
7205 slotbuf[0] = 0x61d200;
7211 slotbuf[0] = 0x3b300;
7217 slotbuf[0] = 0x13b300;
7223 slotbuf[0] = 0x61b300;
7229 slotbuf[0] = 0x3d300;
7235 slotbuf[0] = 0x13d300;
7241 slotbuf[0] = 0x61d300;
7247 slotbuf[0] = 0x3b400;
7253 slotbuf[0] = 0x13b400;
7259 slotbuf[0] = 0x61b400;
7265 slotbuf[0] = 0x3d400;
7271 slotbuf[0] = 0x13d400;
7277 slotbuf[0] = 0x61d400;
7283 slotbuf[0] = 0x3b500;
7289 slotbuf[0] = 0x13b500;
7295 slotbuf[0] = 0x61b500;
7301 slotbuf[0] = 0x3d500;
7307 slotbuf[0] = 0x13d500;
7313 slotbuf[0] = 0x61d500;
7319 slotbuf[0] = 0x3b600;
7325 slotbuf[0] = 0x13b600;
7331 slotbuf[0] = 0x61b600;
7337 slotbuf[0] = 0x3d600;
7343 slotbuf[0] = 0x13d600;
7349 slotbuf[0] = 0x61d600;
7355 slotbuf[0] = 0x3b700;
7361 slotbuf[0] = 0x13b700;
7367 slotbuf[0] = 0x61b700;
7373 slotbuf[0] = 0x3d700;
7379 slotbuf[0] = 0x13d700;
7385 slotbuf[0] = 0x61d700;
7391 slotbuf[0] = 0x3c200;
7397 slotbuf[0] = 0x13c200;
7403 slotbuf[0] = 0x61c200;
7409 slotbuf[0] = 0x3c300;
7415 slotbuf[0] = 0x13c300;
7421 slotbuf[0] = 0x61c300;
7427 slotbuf[0] = 0x3c400;
7433 slotbuf[0] = 0x13c400;
7439 slotbuf[0] = 0x61c400;
7445 slotbuf[0] = 0x3c500;
7451 slotbuf[0] = 0x13c500;
7457 slotbuf[0] = 0x61c500;
7463 slotbuf[0] = 0x3c600;
7469 slotbuf[0] = 0x13c600;
7475 slotbuf[0] = 0x61c600;
7481 slotbuf[0] = 0x3c700;
7487 slotbuf[0] = 0x13c700;
7493 slotbuf[0] = 0x61c700;
7499 slotbuf[0] = 0x3ee00;
7505 slotbuf[0] = 0x13ee00;
7511 slotbuf[0] = 0x61ee00;
7517 slotbuf[0] = 0x3c000;
7523 slotbuf[0] = 0x13c000;
7529 slotbuf[0] = 0x61c000;
7535 slotbuf[0] = 0x3e800;
7541 slotbuf[0] = 0x13e800;
7547 slotbuf[0] = 0x61e800;
7553 slotbuf[0] = 0x3f400;
7559 slotbuf[0] = 0x13f400;
7565 slotbuf[0] = 0x61f400;
7571 slotbuf[0] = 0x3f500;
7577 slotbuf[0] = 0x13f500;
7583 slotbuf[0] = 0x61f500;
7589 slotbuf[0] = 0x3eb00;
7595 slotbuf[0] = 0x3e700;
7601 slotbuf[0] = 0x13e700;
7607 slotbuf[0] = 0x61e700;
7613 slotbuf[0] = 0x740004;
7619 slotbuf[0] = 0x750004;
7625 slotbuf[0] = 0x760004;
7631 slotbuf[0] = 0x770004;
7637 slotbuf[0] = 0x700004;
7643 slotbuf[0] = 0x710004;
7649 slotbuf[0] = 0x720004;
7655 slotbuf[0] = 0x730004;
7661 slotbuf[0] = 0x340004;
7667 slotbuf[0] = 0x350004;
7673 slotbuf[0] = 0x360004;
7679 slotbuf[0] = 0x370004;
7685 slotbuf[0] = 0x640004;
7691 slotbuf[0] = 0x650004;
7697 slotbuf[0] = 0x660004;
7703 slotbuf[0] = 0x670004;
7709 slotbuf[0] = 0x240004;
7715 slotbuf[0] = 0x250004;
7721 slotbuf[0] = 0x260004;
7727 slotbuf[0] = 0x270004;
7733 slotbuf[0] = 0x780004;
7739 slotbuf[0] = 0x790004;
7745 slotbuf[0] = 0x7a0004;
7751 slotbuf[0] = 0x7b0004;
7757 slotbuf[0] = 0x7c0004;
7763 slotbuf[0] = 0x7d0004;
7769 slotbuf[0] = 0x7e0004;
7775 slotbuf[0] = 0x7f0004;
7781 slotbuf[0] = 0x380004;
7787 slotbuf[0] = 0x390004;
7793 slotbuf[0] = 0x3a0004;
7799 slotbuf[0] = 0x3b0004;
7805 slotbuf[0] = 0x3c0004;
7811 slotbuf[0] = 0x3d0004;
7817 slotbuf[0] = 0x3e0004;
7823 slotbuf[0] = 0x3f0004;
7829 slotbuf[0] = 0x680004;
7835 slotbuf[0] = 0x690004;
7841 slotbuf[0] = 0x6a0004;
7847 slotbuf[0] = 0x6b0004;
7853 slotbuf[0] = 0x6c0004;
7859 slotbuf[0] = 0x6d0004;
7865 slotbuf[0] = 0x6e0004;
7871 slotbuf[0] = 0x6f0004;
7877 slotbuf[0] = 0x280004;
7883 slotbuf[0] = 0x290004;
7889 slotbuf[0] = 0x2a0004;
7895 slotbuf[0] = 0x2b0004;
7901 slotbuf[0] = 0x2c0004;
7907 slotbuf[0] = 0x2d0004;
7913 slotbuf[0] = 0x2e0004;
7919 slotbuf[0] = 0x2f0004;
7925 slotbuf[0] = 0x580004;
7931 slotbuf[0] = 0x480004;
7937 slotbuf[0] = 0x590004;
7943 slotbuf[0] = 0x490004;
7949 slotbuf[0] = 0x5a0004;
7955 slotbuf[0] = 0x4a0004;
7961 slotbuf[0] = 0x5b0004;
7967 slotbuf[0] = 0x4b0004;
7973 slotbuf[0] = 0x180004;
7979 slotbuf[0] = 0x80004;
7985 slotbuf[0] = 0x190004;
7991 slotbuf[0] = 0x90004;
7997 slotbuf[0] = 0x1a0004;
8003 slotbuf[0] = 0xa0004;
8009 slotbuf[0] = 0x1b0004;
8015 slotbuf[0] = 0xb0004;
8021 slotbuf[0] = 0x900004;
8027 slotbuf[0] = 0x800004;
8033 slotbuf[0] = 0xc10000;
8039 slotbuf[0] = 0xd10000;
8045 slotbuf[0] = 0x32000;
8051 slotbuf[0] = 0x132000;
8057 slotbuf[0] = 0x612000;
8063 slotbuf[0] = 0x32100;
8069 slotbuf[0] = 0x132100;
8075 slotbuf[0] = 0x612100;
8081 slotbuf[0] = 0x32200;
8087 slotbuf[0] = 0x132200;
8093 slotbuf[0] = 0x612200;
8099 slotbuf[0] = 0x32300;
8105 slotbuf[0] = 0x132300;
8111 slotbuf[0] = 0x612300;
8117 slotbuf[0] = 0x31000;
8123 slotbuf[0] = 0x131000;
8129 slotbuf[0] = 0x611000;
8135 slotbuf[0] = 0x31100;
8141 slotbuf[0] = 0x131100;
8147 slotbuf[0] = 0x611100;
8153 slotbuf[0] = 0x3010;
8159 slotbuf[0] = 0x7000;
8165 slotbuf[0] = 0x3e200;
8171 slotbuf[0] = 0x13e200;
8177 slotbuf[0] = 0x13e300;
8183 slotbuf[0] = 0x3e400;
8189 slotbuf[0] = 0x13e400;
8195 slotbuf[0] = 0x61e400;
8201 slotbuf[0] = 0x4000;
8207 slotbuf[0] = 0xf02d;
8213 slotbuf[0] = 0x39000;
8219 slotbuf[0] = 0x139000;
8225 slotbuf[0] = 0x619000;
8231 slotbuf[0] = 0x3a000;
8237 slotbuf[0] = 0x13a000;
8243 slotbuf[0] = 0x61a000;
8249 slotbuf[0] = 0x39100;
8255 slotbuf[0] = 0x139100;
8261 slotbuf[0] = 0x619100;
8267 slotbuf[0] = 0x3a100;
8273 slotbuf[0] = 0x13a100;
8279 slotbuf[0] = 0x61a100;
8285 slotbuf[0] = 0x38000;
8291 slotbuf[0] = 0x138000;
8297 slotbuf[0] = 0x618000;
8303 slotbuf[0] = 0x38100;
8309 slotbuf[0] = 0x138100;
8315 slotbuf[0] = 0x618100;
8321 slotbuf[0] = 0x36000;
8327 slotbuf[0] = 0x136000;
8333 slotbuf[0] = 0x616000;
8339 slotbuf[0] = 0x3e900;
8345 slotbuf[0] = 0x13e900;
8351 slotbuf[0] = 0x61e900;
8357 slotbuf[0] = 0x3ec00;
8363 slotbuf[0] = 0x13ec00;
8369 slotbuf[0] = 0x61ec00;
8375 slotbuf[0] = 0x3ed00;
8381 slotbuf[0] = 0x13ed00;
8387 slotbuf[0] = 0x61ed00;
8393 slotbuf[0] = 0x36800;
8399 slotbuf[0] = 0x136800;
8405 slotbuf[0] = 0x616800;
8411 slotbuf[0] = 0xf1e000;
8417 slotbuf[0] = 0xf1e010;
8423 slotbuf[0] = 0x135900;
8429 slotbuf[0] = 0x3ea00;
8435 slotbuf[0] = 0x13ea00;
8441 slotbuf[0] = 0x61ea00;
8447 slotbuf[0] = 0x3f000;
8453 slotbuf[0] = 0x13f000;
8459 slotbuf[0] = 0x61f000;
8465 slotbuf[0] = 0x3f100;
8471 slotbuf[0] = 0x13f100;
8477 slotbuf[0] = 0x61f100;
8483 slotbuf[0] = 0x3f200;
8489 slotbuf[0] = 0x13f200;
8495 slotbuf[0] = 0x61f200;
8501 slotbuf[0] = 0x70c2;
8507 slotbuf[0] = 0x70e2;
8513 slotbuf[0] = 0x70d2;
8519 slotbuf[0] = 0x270d2;
8525 slotbuf[0] = 0x370d2;
8531 slotbuf[0] = 0x70f2;
8537 slotbuf[0] = 0xf10000;
8543 slotbuf[0] = 0xf12000;
8549 slotbuf[0] = 0xf11000;
8555 slotbuf[0] = 0xf13000;
8561 slotbuf[0] = 0x7042;
8567 slotbuf[0] = 0x7052;
8573 slotbuf[0] = 0x47082;
8579 slotbuf[0] = 0x57082;
8585 slotbuf[0] = 0x7062;
8591 slotbuf[0] = 0x7072;
8597 slotbuf[0] = 0x7002;
8603 slotbuf[0] = 0x7012;
8609 slotbuf[0] = 0x7022;
8615 slotbuf[0] = 0x7032;
8621 slotbuf[0] = 0x7082;
8627 slotbuf[0] = 0x27082;
8633 slotbuf[0] = 0x37082;
8639 slotbuf[0] = 0xf19000;
8645 slotbuf[0] = 0xf18000;
8651 slotbuf[0] = 0x135300;
8657 slotbuf[0] = 0x35300;
8663 slotbuf[0] = 0x615300;
8669 slotbuf[0] = 0x35a00;
8675 slotbuf[0] = 0x135a00;
8681 slotbuf[0] = 0x615a00;
8687 slotbuf[0] = 0x35b00;
8693 slotbuf[0] = 0x135b00;
8699 slotbuf[0] = 0x615b00;
8705 slotbuf[0] = 0x35c00;
8711 slotbuf[0] = 0x135c00;
8717 slotbuf[0] = 0x615c00;
8723 slotbuf[0] = 0x50c000;
8729 slotbuf[0] = 0x50d000;
8735 slotbuf[0] = 0x50b000;
8741 slotbuf[0] = 0x50f000;
8747 slotbuf[0] = 0x50e000;
8753 slotbuf[0] = 0x504000;
8759 slotbuf[0] = 0x505000;
8765 slotbuf[0] = 0x503000;
8771 slotbuf[0] = 0x507000;
8777 slotbuf[0] = 0x506000;
8783 slotbuf[0] = 0xf1f000;
8789 slotbuf[0] = 0x501000;
8795 slotbuf[0] = 0x509000;
8801 slotbuf[0] = 0x3e000;
8807 slotbuf[0] = 0x13e000;
8813 slotbuf[0] = 0x61e000;
8819 slotbuf[0] = 0x330000;
8825 slotbuf[0] = 0x430000;
8831 slotbuf[0] = 0x530000;
8837 slotbuf[0] = 0x630000;
8843 slotbuf[0] = 0x730000;
8849 slotbuf[0] = 0x40e000;
8855 slotbuf[0] = 0x40f000;
8861 slotbuf[0] = 0x230000;
8867 slotbuf[0] = 0xb002;
8873 slotbuf[0] = 0xf002;
8879 slotbuf[0] = 0xe002;
8885 slotbuf[0] = 0x30c00;
8891 slotbuf[0] = 0x130c00;
8897 slotbuf[0] = 0x610c00;
8903 slotbuf[0] = 0xc20000;
8909 slotbuf[0] = 0xd20000;
8915 slotbuf[0] = 0xe20000;
8921 slotbuf[0] = 0xf20000;
8927 slotbuf[0] = 0x820000;
8933 slotbuf[0] = 0xe30e60;
8939 slotbuf[0] = 0xf3e600;
8945 slotbuf[0] = 0xe0000;
8951 slotbuf[0] = 0xe1000;
8957 slotbuf[0] = 0xe1200;
8963 slotbuf[0] = 0xe2000;
8967 Opcode_excw_Slot_inst_encode, 0, 0
8971 Opcode_rfe_Slot_inst_encode, 0, 0
8975 Opcode_rfde_Slot_inst_encode, 0, 0
8979 Opcode_syscall_Slot_inst_encode, 0, 0
8983 Opcode_simcall_Slot_inst_encode, 0, 0
8987 Opcode_call12_Slot_inst_encode, 0, 0
8991 Opcode_call8_Slot_inst_encode, 0, 0
8995 Opcode_call4_Slot_inst_encode, 0, 0
8999 Opcode_callx12_Slot_inst_encode, 0, 0
9003 Opcode_callx8_Slot_inst_encode, 0, 0
9007 Opcode_callx4_Slot_inst_encode, 0, 0
9011 Opcode_entry_Slot_inst_encode, 0, 0
9015 Opcode_movsp_Slot_inst_encode, 0, 0
9019 Opcode_rotw_Slot_inst_encode, 0, 0
9023 Opcode_retw_Slot_inst_encode, 0, 0
9027 0, 0, Opcode_retw_n_Slot_inst16b_encode
9031 Opcode_rfwo_Slot_inst_encode, 0, 0
9035 Opcode_rfwu_Slot_inst_encode, 0, 0
9039 Opcode_l32e_Slot_inst_encode, 0, 0
9043 Opcode_s32e_Slot_inst_encode, 0, 0
9047 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9051 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9055 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9059 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9063 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9067 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9071 0, Opcode_add_n_Slot_inst16a_encode, 0
9075 0, Opcode_addi_n_Slot_inst16a_encode, 0
9079 0, 0, Opcode_beqz_n_Slot_inst16b_encode
9083 0, 0, Opcode_bnez_n_Slot_inst16b_encode
9087 0, 0, Opcode_ill_n_Slot_inst16b_encode
9091 0, Opcode_l32i_n_Slot_inst16a_encode, 0
9095 0, 0, Opcode_mov_n_Slot_inst16b_encode
9099 0, 0, Opcode_movi_n_Slot_inst16b_encode
9103 0, 0, Opcode_nop_n_Slot_inst16b_encode
9107 0, 0, Opcode_ret_n_Slot_inst16b_encode
9111 0, Opcode_s32i_n_Slot_inst16a_encode, 0
9115 Opcode_rur_threadptr_Slot_inst_encode, 0, 0
9119 Opcode_wur_threadptr_Slot_inst_encode, 0, 0
9123 Opcode_addi_Slot_inst_encode, 0, 0
9127 Opcode_addmi_Slot_inst_encode, 0, 0
9131 Opcode_add_Slot_inst_encode, 0, 0
9135 Opcode_sub_Slot_inst_encode, 0, 0
9139 Opcode_addx2_Slot_inst_encode, 0, 0
9143 Opcode_addx4_Slot_inst_encode, 0, 0
9147 Opcode_addx8_Slot_inst_encode, 0, 0
9151 Opcode_subx2_Slot_inst_encode, 0, 0
9155 Opcode_subx4_Slot_inst_encode, 0, 0
9159 Opcode_subx8_Slot_inst_encode, 0, 0
9163 Opcode_and_Slot_inst_encode, 0, 0
9167 Opcode_or_Slot_inst_encode, 0, 0
9171 Opcode_xor_Slot_inst_encode, 0, 0
9175 Opcode_beqi_Slot_inst_encode, 0, 0
9179 Opcode_bnei_Slot_inst_encode, 0, 0
9183 Opcode_bgei_Slot_inst_encode, 0, 0
9187 Opcode_blti_Slot_inst_encode, 0, 0
9191 Opcode_bbci_Slot_inst_encode, 0, 0
9195 Opcode_bbsi_Slot_inst_encode, 0, 0
9199 Opcode_bgeui_Slot_inst_encode, 0, 0
9203 Opcode_bltui_Slot_inst_encode, 0, 0
9207 Opcode_beq_Slot_inst_encode, 0, 0
9211 Opcode_bne_Slot_inst_encode, 0, 0
9215 Opcode_bge_Slot_inst_encode, 0, 0
9219 Opcode_blt_Slot_inst_encode, 0, 0
9223 Opcode_bgeu_Slot_inst_encode, 0, 0
9227 Opcode_bltu_Slot_inst_encode, 0, 0
9231 Opcode_bany_Slot_inst_encode, 0, 0
9235 Opcode_bnone_Slot_inst_encode, 0, 0
9239 Opcode_ball_Slot_inst_encode, 0, 0
9243 Opcode_bnall_Slot_inst_encode, 0, 0
9247 Opcode_bbc_Slot_inst_encode, 0, 0
9251 Opcode_bbs_Slot_inst_encode, 0, 0
9255 Opcode_beqz_Slot_inst_encode, 0, 0
9259 Opcode_bnez_Slot_inst_encode, 0, 0
9263 Opcode_bgez_Slot_inst_encode, 0, 0
9267 Opcode_bltz_Slot_inst_encode, 0, 0
9271 Opcode_call0_Slot_inst_encode, 0, 0
9275 Opcode_callx0_Slot_inst_encode, 0, 0
9279 Opcode_extui_Slot_inst_encode, 0, 0
9283 Opcode_ill_Slot_inst_encode, 0, 0
9287 Opcode_j_Slot_inst_encode, 0, 0
9291 Opcode_jx_Slot_inst_encode, 0, 0
9295 Opcode_l16ui_Slot_inst_encode, 0, 0
9299 Opcode_l16si_Slot_inst_encode, 0, 0
9303 Opcode_l32i_Slot_inst_encode, 0, 0
9307 Opcode_l32r_Slot_inst_encode, 0, 0
9311 Opcode_l8ui_Slot_inst_encode, 0, 0
9315 Opcode_loop_Slot_inst_encode, 0, 0
9319 Opcode_loopnez_Slot_inst_encode, 0, 0
9323 Opcode_loopgtz_Slot_inst_encode, 0, 0
9327 Opcode_movi_Slot_inst_encode, 0, 0
9331 Opcode_moveqz_Slot_inst_encode, 0, 0
9335 Opcode_movnez_Slot_inst_encode, 0, 0
9339 Opcode_movltz_Slot_inst_encode, 0, 0
9343 Opcode_movgez_Slot_inst_encode, 0, 0
9347 Opcode_neg_Slot_inst_encode, 0, 0
9351 Opcode_abs_Slot_inst_encode, 0, 0
9355 Opcode_nop_Slot_inst_encode, 0, 0
9359 Opcode_ret_Slot_inst_encode, 0, 0
9363 Opcode_s16i_Slot_inst_encode, 0, 0
9367 Opcode_s32i_Slot_inst_encode, 0, 0
9371 Opcode_s8i_Slot_inst_encode, 0, 0
9375 Opcode_ssr_Slot_inst_encode, 0, 0
9379 Opcode_ssl_Slot_inst_encode, 0, 0
9383 Opcode_ssa8l_Slot_inst_encode, 0, 0
9387 Opcode_ssa8b_Slot_inst_encode, 0, 0
9391 Opcode_ssai_Slot_inst_encode, 0, 0
9395 Opcode_sll_Slot_inst_encode, 0, 0
9399 Opcode_src_Slot_inst_encode, 0, 0
9403 Opcode_srl_Slot_inst_encode, 0, 0
9407 Opcode_sra_Slot_inst_encode, 0, 0
9411 Opcode_slli_Slot_inst_encode, 0, 0
9415 Opcode_srai_Slot_inst_encode, 0, 0
9419 Opcode_srli_Slot_inst_encode, 0, 0
9423 Opcode_memw_Slot_inst_encode, 0, 0
9427 Opcode_extw_Slot_inst_encode, 0, 0
9431 Opcode_isync_Slot_inst_encode, 0, 0
9435 Opcode_rsync_Slot_inst_encode, 0, 0
9439 Opcode_esync_Slot_inst_encode, 0, 0
9443 Opcode_dsync_Slot_inst_encode, 0, 0
9447 Opcode_rsil_Slot_inst_encode, 0, 0
9451 Opcode_rsr_lend_Slot_inst_encode, 0, 0
9455 Opcode_wsr_lend_Slot_inst_encode, 0, 0
9459 Opcode_xsr_lend_Slot_inst_encode, 0, 0
9463 Opcode_rsr_lcount_Slot_inst_encode, 0, 0
9467 Opcode_wsr_lcount_Slot_inst_encode, 0, 0
9471 Opcode_xsr_lcount_Slot_inst_encode, 0, 0
9475 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
9479 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
9483 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
9487 Opcode_rsr_sar_Slot_inst_encode, 0, 0
9491 Opcode_wsr_sar_Slot_inst_encode, 0, 0
9495 Opcode_xsr_sar_Slot_inst_encode, 0, 0
9499 Opcode_rsr_litbase_Slot_inst_encode, 0, 0
9503 Opcode_wsr_litbase_Slot_inst_encode, 0, 0
9507 Opcode_xsr_litbase_Slot_inst_encode, 0, 0
9511 Opcode_rsr_176_Slot_inst_encode, 0, 0
9515 Opcode_rsr_208_Slot_inst_encode, 0, 0
9519 Opcode_rsr_ps_Slot_inst_encode, 0, 0
9523 Opcode_wsr_ps_Slot_inst_encode, 0, 0
9527 Opcode_xsr_ps_Slot_inst_encode, 0, 0
9531 Opcode_rsr_epc1_Slot_inst_encode, 0, 0
9535 Opcode_wsr_epc1_Slot_inst_encode, 0, 0
9539 Opcode_xsr_epc1_Slot_inst_encode, 0, 0
9543 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
9547 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
9551 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
9555 Opcode_rsr_epc2_Slot_inst_encode, 0, 0
9559 Opcode_wsr_epc2_Slot_inst_encode, 0, 0
9563 Opcode_xsr_epc2_Slot_inst_encode, 0, 0
9567 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
9571 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
9575 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
9579 Opcode_rsr_epc3_Slot_inst_encode, 0, 0
9583 Opcode_wsr_epc3_Slot_inst_encode, 0, 0
9587 Opcode_xsr_epc3_Slot_inst_encode, 0, 0
9591 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
9595 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
9599 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
9603 Opcode_rsr_epc4_Slot_inst_encode, 0, 0
9607 Opcode_wsr_epc4_Slot_inst_encode, 0, 0
9611 Opcode_xsr_epc4_Slot_inst_encode, 0, 0
9615 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
9619 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
9623 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
9627 Opcode_rsr_epc5_Slot_inst_encode, 0, 0
9631 Opcode_wsr_epc5_Slot_inst_encode, 0, 0
9635 Opcode_xsr_epc5_Slot_inst_encode, 0, 0
9639 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
9643 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
9647 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
9651 Opcode_rsr_epc6_Slot_inst_encode, 0, 0
9655 Opcode_wsr_epc6_Slot_inst_encode, 0, 0
9659 Opcode_xsr_epc6_Slot_inst_encode, 0, 0
9663 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
9667 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
9671 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
9675 Opcode_rsr_epc7_Slot_inst_encode, 0, 0
9679 Opcode_wsr_epc7_Slot_inst_encode, 0, 0
9683 Opcode_xsr_epc7_Slot_inst_encode, 0, 0
9687 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
9691 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
9695 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
9699 Opcode_rsr_eps2_Slot_inst_encode, 0, 0
9703 Opcode_wsr_eps2_Slot_inst_encode, 0, 0
9707 Opcode_xsr_eps2_Slot_inst_encode, 0, 0
9711 Opcode_rsr_eps3_Slot_inst_encode, 0, 0
9715 Opcode_wsr_eps3_Slot_inst_encode, 0, 0
9719 Opcode_xsr_eps3_Slot_inst_encode, 0, 0
9723 Opcode_rsr_eps4_Slot_inst_encode, 0, 0
9727 Opcode_wsr_eps4_Slot_inst_encode, 0, 0
9731 Opcode_xsr_eps4_Slot_inst_encode, 0, 0
9735 Opcode_rsr_eps5_Slot_inst_encode, 0, 0
9739 Opcode_wsr_eps5_Slot_inst_encode, 0, 0
9743 Opcode_xsr_eps5_Slot_inst_encode, 0, 0
9747 Opcode_rsr_eps6_Slot_inst_encode, 0, 0
9751 Opcode_wsr_eps6_Slot_inst_encode, 0, 0
9755 Opcode_xsr_eps6_Slot_inst_encode, 0, 0
9759 Opcode_rsr_eps7_Slot_inst_encode, 0, 0
9763 Opcode_wsr_eps7_Slot_inst_encode, 0, 0
9767 Opcode_xsr_eps7_Slot_inst_encode, 0, 0
9771 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
9775 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
9779 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
9783 Opcode_rsr_depc_Slot_inst_encode, 0, 0
9787 Opcode_wsr_depc_Slot_inst_encode, 0, 0
9791 Opcode_xsr_depc_Slot_inst_encode, 0, 0
9795 Opcode_rsr_exccause_Slot_inst_encode, 0, 0
9799 Opcode_wsr_exccause_Slot_inst_encode, 0, 0
9803 Opcode_xsr_exccause_Slot_inst_encode, 0, 0
9807 Opcode_rsr_misc0_Slot_inst_encode, 0, 0
9811 Opcode_wsr_misc0_Slot_inst_encode, 0, 0
9815 Opcode_xsr_misc0_Slot_inst_encode, 0, 0
9819 Opcode_rsr_misc1_Slot_inst_encode, 0, 0
9823 Opcode_wsr_misc1_Slot_inst_encode, 0, 0
9827 Opcode_xsr_misc1_Slot_inst_encode, 0, 0
9831 Opcode_rsr_prid_Slot_inst_encode, 0, 0
9835 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
9839 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
9843 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
9847 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
9851 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
9855 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
9859 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
9863 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
9867 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
9871 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
9875 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
9879 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
9883 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
9887 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
9891 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
9895 Opcode_mul_da_ll_Slot_inst_encode, 0, 0
9899 Opcode_mul_da_hl_Slot_inst_encode, 0, 0
9903 Opcode_mul_da_lh_Slot_inst_encode, 0, 0
9907 Opcode_mul_da_hh_Slot_inst_encode, 0, 0
9911 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
9915 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
9919 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
9923 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
9927 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
9931 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
9935 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
9939 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
9943 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
9947 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
9951 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
9955 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
9959 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
9963 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
9967 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
9971 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
9975 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
9979 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
9983 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
9987 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
9991 Opcode_mula_da_ll_Slot_inst_encode, 0, 0
9995 Opcode_mula_da_hl_Slot_inst_encode, 0, 0
9999 Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10003 Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10007 Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10011 Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10015 Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10019 Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10023 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10027 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10031 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10035 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10039 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10043 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10047 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10051 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10055 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10059 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10063 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10067 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10071 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10075 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10079 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10083 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10087 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10091 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10095 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10099 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10103 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10107 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10111 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10115 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10119 Opcode_lddec_Slot_inst_encode, 0, 0
10123 Opcode_ldinc_Slot_inst_encode, 0, 0
10127 Opcode_mul16u_Slot_inst_encode, 0, 0
10131 Opcode_mul16s_Slot_inst_encode, 0, 0
10135 Opcode_rsr_m0_Slot_inst_encode, 0, 0
10139 Opcode_wsr_m0_Slot_inst_encode, 0, 0
10143 Opcode_xsr_m0_Slot_inst_encode, 0, 0
10147 Opcode_rsr_m1_Slot_inst_encode, 0, 0
10151 Opcode_wsr_m1_Slot_inst_encode, 0, 0
10155 Opcode_xsr_m1_Slot_inst_encode, 0, 0
10159 Opcode_rsr_m2_Slot_inst_encode, 0, 0
10163 Opcode_wsr_m2_Slot_inst_encode, 0, 0
10167 Opcode_xsr_m2_Slot_inst_encode, 0, 0
10171 Opcode_rsr_m3_Slot_inst_encode, 0, 0
10175 Opcode_wsr_m3_Slot_inst_encode, 0, 0
10179 Opcode_xsr_m3_Slot_inst_encode, 0, 0
10183 Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10187 Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10191 Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10195 Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10199 Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10203 Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10207 Opcode_rfi_Slot_inst_encode, 0, 0
10211 Opcode_waiti_Slot_inst_encode, 0, 0
10215 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10219 Opcode_wsr_intset_Slot_inst_encode, 0, 0
10223 Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10227 Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10231 Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10235 Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10239 Opcode_break_Slot_inst_encode, 0, 0
10243 0, 0, Opcode_break_n_Slot_inst16b_encode
10247 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10251 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10255 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10259 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10263 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10267 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10271 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10275 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10279 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10283 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10287 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10291 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10295 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10299 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10303 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10307 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10311 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10315 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10319 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10323 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10327 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10331 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10335 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10339 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10343 Opcode_rsr_icount_Slot_inst_encode, 0, 0
10347 Opcode_wsr_icount_Slot_inst_encode, 0, 0
10351 Opcode_xsr_icount_Slot_inst_encode, 0, 0
10355 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10359 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10363 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10367 Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10371 Opcode_wsr_ddr_Slot_inst_encode, 0, 0
10375 Opcode_xsr_ddr_Slot_inst_encode, 0, 0
10379 Opcode_rfdo_Slot_inst_encode, 0, 0
10383 Opcode_rfdd_Slot_inst_encode, 0, 0
10387 Opcode_wsr_mmid_Slot_inst_encode, 0, 0
10391 Opcode_rsr_ccount_Slot_inst_encode, 0, 0
10395 Opcode_wsr_ccount_Slot_inst_encode, 0, 0
10399 Opcode_xsr_ccount_Slot_inst_encode, 0, 0
10403 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
10407 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
10411 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
10415 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
10419 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
10423 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
10427 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
10431 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
10435 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
10439 Opcode_ipf_Slot_inst_encode, 0, 0
10443 Opcode_ihi_Slot_inst_encode, 0, 0
10447 Opcode_ipfl_Slot_inst_encode, 0, 0
10451 Opcode_ihu_Slot_inst_encode, 0, 0
10455 Opcode_iiu_Slot_inst_encode, 0, 0
10459 Opcode_iii_Slot_inst_encode, 0, 0
10463 Opcode_lict_Slot_inst_encode, 0, 0
10467 Opcode_licw_Slot_inst_encode, 0, 0
10471 Opcode_sict_Slot_inst_encode, 0, 0
10475 Opcode_sicw_Slot_inst_encode, 0, 0
10479 Opcode_dhwb_Slot_inst_encode, 0, 0
10483 Opcode_dhwbi_Slot_inst_encode, 0, 0
10487 Opcode_diwb_Slot_inst_encode, 0, 0
10491 Opcode_diwbi_Slot_inst_encode, 0, 0
10495 Opcode_dhi_Slot_inst_encode, 0, 0
10499 Opcode_dii_Slot_inst_encode, 0, 0
10503 Opcode_dpfr_Slot_inst_encode, 0, 0
10507 Opcode_dpfw_Slot_inst_encode, 0, 0
10511 Opcode_dpfro_Slot_inst_encode, 0, 0
10515 Opcode_dpfwo_Slot_inst_encode, 0, 0
10519 Opcode_dpfl_Slot_inst_encode, 0, 0
10523 Opcode_dhu_Slot_inst_encode, 0, 0
10527 Opcode_diu_Slot_inst_encode, 0, 0
10531 Opcode_sdct_Slot_inst_encode, 0, 0
10535 Opcode_ldct_Slot_inst_encode, 0, 0
10539 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
10543 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
10547 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
10551 Opcode_rsr_rasid_Slot_inst_encode, 0, 0
10555 Opcode_wsr_rasid_Slot_inst_encode, 0, 0
10559 Opcode_xsr_rasid_Slot_inst_encode, 0, 0
10563 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
10567 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
10571 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
10575 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
10579 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
10583 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
10587 Opcode_idtlb_Slot_inst_encode, 0, 0
10591 Opcode_pdtlb_Slot_inst_encode, 0, 0
10595 Opcode_rdtlb0_Slot_inst_encode, 0, 0
10599 Opcode_rdtlb1_Slot_inst_encode, 0, 0
10603 Opcode_wdtlb_Slot_inst_encode, 0, 0
10607 Opcode_iitlb_Slot_inst_encode, 0, 0
10611 Opcode_pitlb_Slot_inst_encode, 0, 0
10615 Opcode_ritlb0_Slot_inst_encode, 0, 0
10619 Opcode_ritlb1_Slot_inst_encode, 0, 0
10623 Opcode_witlb_Slot_inst_encode, 0, 0
10627 Opcode_ldpte_Slot_inst_encode, 0, 0
10631 Opcode_hwwitlba_Slot_inst_encode, 0, 0
10635 Opcode_hwwdtlba_Slot_inst_encode, 0, 0
10639 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
10643 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
10647 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
10651 Opcode_clamps_Slot_inst_encode, 0, 0
10655 Opcode_min_Slot_inst_encode, 0, 0
10659 Opcode_max_Slot_inst_encode, 0, 0
10663 Opcode_minu_Slot_inst_encode, 0, 0
10667 Opcode_maxu_Slot_inst_encode, 0, 0
10671 Opcode_nsa_Slot_inst_encode, 0, 0
10675 Opcode_nsau_Slot_inst_encode, 0, 0
10679 Opcode_sext_Slot_inst_encode, 0, 0
10683 Opcode_l32ai_Slot_inst_encode, 0, 0
10687 Opcode_s32ri_Slot_inst_encode, 0, 0
10691 Opcode_s32c1i_Slot_inst_encode, 0, 0
10695 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
10699 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
10703 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
10707 Opcode_quou_Slot_inst_encode, 0, 0
10711 Opcode_quos_Slot_inst_encode, 0, 0
10715 Opcode_remu_Slot_inst_encode, 0, 0
10719 Opcode_rems_Slot_inst_encode, 0, 0
10723 Opcode_mull_Slot_inst_encode, 0, 0
10727 Opcode_rur_expstate_Slot_inst_encode, 0, 0
10731 Opcode_wur_expstate_Slot_inst_encode, 0, 0
10735 Opcode_read_impwire_Slot_inst_encode, 0, 0
10739 Opcode_setb_expstate_Slot_inst_encode, 0, 0
10743 Opcode_clrb_expstate_Slot_inst_encode, 0, 0
10747 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
10754 { "excw", 0 /* xt_iclass_excw */,
10755 0,
10756 Opcode_excw_encode_fns, 0, 0 },
10759 Opcode_rfe_encode_fns, 0, 0 },
10762 Opcode_rfde_encode_fns, 0, 0 },
10764 0,
10765 Opcode_syscall_encode_fns, 0, 0 },
10767 0,
10768 Opcode_simcall_encode_fns, 0, 0 },
10771 Opcode_call12_encode_fns, 0, 0 },
10774 Opcode_call8_encode_fns, 0, 0 },
10777 Opcode_call4_encode_fns, 0, 0 },
10780 Opcode_callx12_encode_fns, 0, 0 },
10783 Opcode_callx8_encode_fns, 0, 0 },
10786 Opcode_callx4_encode_fns, 0, 0 },
10788 0,
10789 Opcode_entry_encode_fns, 0, 0 },
10791 0,
10792 Opcode_movsp_encode_fns, 0, 0 },
10794 0,
10795 Opcode_rotw_encode_fns, 0, 0 },
10798 Opcode_retw_encode_fns, 0, 0 },
10801 Opcode_retw_n_encode_fns, 0, 0 },
10804 Opcode_rfwo_encode_fns, 0, 0 },
10807 Opcode_rfwu_encode_fns, 0, 0 },
10809 0,
10810 Opcode_l32e_encode_fns, 0, 0 },
10812 0,
10813 Opcode_s32e_encode_fns, 0, 0 },
10815 0,
10816 Opcode_rsr_windowbase_encode_fns, 0, 0 },
10818 0,
10819 Opcode_wsr_windowbase_encode_fns, 0, 0 },
10821 0,
10822 Opcode_xsr_windowbase_encode_fns, 0, 0 },
10824 0,
10825 Opcode_rsr_windowstart_encode_fns, 0, 0 },
10827 0,
10828 Opcode_wsr_windowstart_encode_fns, 0, 0 },
10830 0,
10831 Opcode_xsr_windowstart_encode_fns, 0, 0 },
10833 0,
10834 Opcode_add_n_encode_fns, 0, 0 },
10836 0,
10837 Opcode_addi_n_encode_fns, 0, 0 },
10840 Opcode_beqz_n_encode_fns, 0, 0 },
10843 Opcode_bnez_n_encode_fns, 0, 0 },
10845 0,
10846 Opcode_ill_n_encode_fns, 0, 0 },
10848 0,
10849 Opcode_l32i_n_encode_fns, 0, 0 },
10851 0,
10852 Opcode_mov_n_encode_fns, 0, 0 },
10854 0,
10855 Opcode_movi_n_encode_fns, 0, 0 },
10857 0,
10858 Opcode_nop_n_encode_fns, 0, 0 },
10861 Opcode_ret_n_encode_fns, 0, 0 },
10863 0,
10864 Opcode_s32i_n_encode_fns, 0, 0 },
10866 0,
10867 Opcode_rur_threadptr_encode_fns, 0, 0 },
10869 0,
10870 Opcode_wur_threadptr_encode_fns, 0, 0 },
10872 0,
10873 Opcode_addi_encode_fns, 0, 0 },
10875 0,
10876 Opcode_addmi_encode_fns, 0, 0 },
10878 0,
10879 Opcode_add_encode_fns, 0, 0 },
10881 0,
10882 Opcode_sub_encode_fns, 0, 0 },
10884 0,
10885 Opcode_addx2_encode_fns, 0, 0 },
10887 0,
10888 Opcode_addx4_encode_fns, 0, 0 },
10890 0,
10891 Opcode_addx8_encode_fns, 0, 0 },
10893 0,
10894 Opcode_subx2_encode_fns, 0, 0 },
10896 0,
10897 Opcode_subx4_encode_fns, 0, 0 },
10899 0,
10900 Opcode_subx8_encode_fns, 0, 0 },
10902 0,
10903 Opcode_and_encode_fns, 0, 0 },
10905 0,
10906 Opcode_or_encode_fns, 0, 0 },
10908 0,
10909 Opcode_xor_encode_fns, 0, 0 },
10912 Opcode_beqi_encode_fns, 0, 0 },
10915 Opcode_bnei_encode_fns, 0, 0 },
10918 Opcode_bgei_encode_fns, 0, 0 },
10921 Opcode_blti_encode_fns, 0, 0 },
10924 Opcode_bbci_encode_fns, 0, 0 },
10927 Opcode_bbsi_encode_fns, 0, 0 },
10930 Opcode_bgeui_encode_fns, 0, 0 },
10933 Opcode_bltui_encode_fns, 0, 0 },
10936 Opcode_beq_encode_fns, 0, 0 },
10939 Opcode_bne_encode_fns, 0, 0 },
10942 Opcode_bge_encode_fns, 0, 0 },
10945 Opcode_blt_encode_fns, 0, 0 },
10948 Opcode_bgeu_encode_fns, 0, 0 },
10951 Opcode_bltu_encode_fns, 0, 0 },
10954 Opcode_bany_encode_fns, 0, 0 },
10957 Opcode_bnone_encode_fns, 0, 0 },
10960 Opcode_ball_encode_fns, 0, 0 },
10963 Opcode_bnall_encode_fns, 0, 0 },
10966 Opcode_bbc_encode_fns, 0, 0 },
10969 Opcode_bbs_encode_fns, 0, 0 },
10972 Opcode_beqz_encode_fns, 0, 0 },
10975 Opcode_bnez_encode_fns, 0, 0 },
10978 Opcode_bgez_encode_fns, 0, 0 },
10981 Opcode_bltz_encode_fns, 0, 0 },
10984 Opcode_call0_encode_fns, 0, 0 },
10987 Opcode_callx0_encode_fns, 0, 0 },
10989 0,
10990 Opcode_extui_encode_fns, 0, 0 },
10992 0,
10993 Opcode_ill_encode_fns, 0, 0 },
10996 Opcode_j_encode_fns, 0, 0 },
10999 Opcode_jx_encode_fns, 0, 0 },
11001 0,
11002 Opcode_l16ui_encode_fns, 0, 0 },
11004 0,
11005 Opcode_l16si_encode_fns, 0, 0 },
11007 0,
11008 Opcode_l32i_encode_fns, 0, 0 },
11010 0,
11011 Opcode_l32r_encode_fns, 0, 0 },
11013 0,
11014 Opcode_l8ui_encode_fns, 0, 0 },
11017 Opcode_loop_encode_fns, 0, 0 },
11020 Opcode_loopnez_encode_fns, 0, 0 },
11023 Opcode_loopgtz_encode_fns, 0, 0 },
11025 0,
11026 Opcode_movi_encode_fns, 0, 0 },
11028 0,
11029 Opcode_moveqz_encode_fns, 0, 0 },
11031 0,
11032 Opcode_movnez_encode_fns, 0, 0 },
11034 0,
11035 Opcode_movltz_encode_fns, 0, 0 },
11037 0,
11038 Opcode_movgez_encode_fns, 0, 0 },
11040 0,
11041 Opcode_neg_encode_fns, 0, 0 },
11043 0,
11044 Opcode_abs_encode_fns, 0, 0 },
11046 0,
11047 Opcode_nop_encode_fns, 0, 0 },
11050 Opcode_ret_encode_fns, 0, 0 },
11052 0,
11053 Opcode_s16i_encode_fns, 0, 0 },
11055 0,
11056 Opcode_s32i_encode_fns, 0, 0 },
11058 0,
11059 Opcode_s8i_encode_fns, 0, 0 },
11061 0,
11062 Opcode_ssr_encode_fns, 0, 0 },
11064 0,
11065 Opcode_ssl_encode_fns, 0, 0 },
11067 0,
11068 Opcode_ssa8l_encode_fns, 0, 0 },
11070 0,
11071 Opcode_ssa8b_encode_fns, 0, 0 },
11073 0,
11074 Opcode_ssai_encode_fns, 0, 0 },
11076 0,
11077 Opcode_sll_encode_fns, 0, 0 },
11079 0,
11080 Opcode_src_encode_fns, 0, 0 },
11082 0,
11083 Opcode_srl_encode_fns, 0, 0 },
11085 0,
11086 Opcode_sra_encode_fns, 0, 0 },
11088 0,
11089 Opcode_slli_encode_fns, 0, 0 },
11091 0,
11092 Opcode_srai_encode_fns, 0, 0 },
11094 0,
11095 Opcode_srli_encode_fns, 0, 0 },
11097 0,
11098 Opcode_memw_encode_fns, 0, 0 },
11100 0,
11101 Opcode_extw_encode_fns, 0, 0 },
11103 0,
11104 Opcode_isync_encode_fns, 0, 0 },
11106 0,
11107 Opcode_rsync_encode_fns, 0, 0 },
11109 0,
11110 Opcode_esync_encode_fns, 0, 0 },
11112 0,
11113 Opcode_dsync_encode_fns, 0, 0 },
11115 0,
11116 Opcode_rsil_encode_fns, 0, 0 },
11118 0,
11119 Opcode_rsr_lend_encode_fns, 0, 0 },
11121 0,
11122 Opcode_wsr_lend_encode_fns, 0, 0 },
11124 0,
11125 Opcode_xsr_lend_encode_fns, 0, 0 },
11127 0,
11128 Opcode_rsr_lcount_encode_fns, 0, 0 },
11130 0,
11131 Opcode_wsr_lcount_encode_fns, 0, 0 },
11133 0,
11134 Opcode_xsr_lcount_encode_fns, 0, 0 },
11136 0,
11137 Opcode_rsr_lbeg_encode_fns, 0, 0 },
11139 0,
11140 Opcode_wsr_lbeg_encode_fns, 0, 0 },
11142 0,
11143 Opcode_xsr_lbeg_encode_fns, 0, 0 },
11145 0,
11146 Opcode_rsr_sar_encode_fns, 0, 0 },
11148 0,
11149 Opcode_wsr_sar_encode_fns, 0, 0 },
11151 0,
11152 Opcode_xsr_sar_encode_fns, 0, 0 },
11154 0,
11155 Opcode_rsr_litbase_encode_fns, 0, 0 },
11157 0,
11158 Opcode_wsr_litbase_encode_fns, 0, 0 },
11160 0,
11161 Opcode_xsr_litbase_encode_fns, 0, 0 },
11163 0,
11164 Opcode_rsr_176_encode_fns, 0, 0 },
11166 0,
11167 Opcode_rsr_208_encode_fns, 0, 0 },
11169 0,
11170 Opcode_rsr_ps_encode_fns, 0, 0 },
11172 0,
11173 Opcode_wsr_ps_encode_fns, 0, 0 },
11175 0,
11176 Opcode_xsr_ps_encode_fns, 0, 0 },
11178 0,
11179 Opcode_rsr_epc1_encode_fns, 0, 0 },
11181 0,
11182 Opcode_wsr_epc1_encode_fns, 0, 0 },
11184 0,
11185 Opcode_xsr_epc1_encode_fns, 0, 0 },
11187 0,
11188 Opcode_rsr_excsave1_encode_fns, 0, 0 },
11190 0,
11191 Opcode_wsr_excsave1_encode_fns, 0, 0 },
11193 0,
11194 Opcode_xsr_excsave1_encode_fns, 0, 0 },
11196 0,
11197 Opcode_rsr_epc2_encode_fns, 0, 0 },
11199 0,
11200 Opcode_wsr_epc2_encode_fns, 0, 0 },
11202 0,
11203 Opcode_xsr_epc2_encode_fns, 0, 0 },
11205 0,
11206 Opcode_rsr_excsave2_encode_fns, 0, 0 },
11208 0,
11209 Opcode_wsr_excsave2_encode_fns, 0, 0 },
11211 0,
11212 Opcode_xsr_excsave2_encode_fns, 0, 0 },
11214 0,
11215 Opcode_rsr_epc3_encode_fns, 0, 0 },
11217 0,
11218 Opcode_wsr_epc3_encode_fns, 0, 0 },
11220 0,
11221 Opcode_xsr_epc3_encode_fns, 0, 0 },
11223 0,
11224 Opcode_rsr_excsave3_encode_fns, 0, 0 },
11226 0,
11227 Opcode_wsr_excsave3_encode_fns, 0, 0 },
11229 0,
11230 Opcode_xsr_excsave3_encode_fns, 0, 0 },
11232 0,
11233 Opcode_rsr_epc4_encode_fns, 0, 0 },
11235 0,
11236 Opcode_wsr_epc4_encode_fns, 0, 0 },
11238 0,
11239 Opcode_xsr_epc4_encode_fns, 0, 0 },
11241 0,
11242 Opcode_rsr_excsave4_encode_fns, 0, 0 },
11244 0,
11245 Opcode_wsr_excsave4_encode_fns, 0, 0 },
11247 0,
11248 Opcode_xsr_excsave4_encode_fns, 0, 0 },
11250 0,
11251 Opcode_rsr_epc5_encode_fns, 0, 0 },
11253 0,
11254 Opcode_wsr_epc5_encode_fns, 0, 0 },
11256 0,
11257 Opcode_xsr_epc5_encode_fns, 0, 0 },
11259 0,
11260 Opcode_rsr_excsave5_encode_fns, 0, 0 },
11262 0,
11263 Opcode_wsr_excsave5_encode_fns, 0, 0 },
11265 0,
11266 Opcode_xsr_excsave5_encode_fns, 0, 0 },
11268 0,
11269 Opcode_rsr_epc6_encode_fns, 0, 0 },
11271 0,
11272 Opcode_wsr_epc6_encode_fns, 0, 0 },
11274 0,
11275 Opcode_xsr_epc6_encode_fns, 0, 0 },
11277 0,
11278 Opcode_rsr_excsave6_encode_fns, 0, 0 },
11280 0,
11281 Opcode_wsr_excsave6_encode_fns, 0, 0 },
11283 0,
11284 Opcode_xsr_excsave6_encode_fns, 0, 0 },
11286 0,
11287 Opcode_rsr_epc7_encode_fns, 0, 0 },
11289 0,
11290 Opcode_wsr_epc7_encode_fns, 0, 0 },
11292 0,
11293 Opcode_xsr_epc7_encode_fns, 0, 0 },
11295 0,
11296 Opcode_rsr_excsave7_encode_fns, 0, 0 },
11298 0,
11299 Opcode_wsr_excsave7_encode_fns, 0, 0 },
11301 0,
11302 Opcode_xsr_excsave7_encode_fns, 0, 0 },
11304 0,
11305 Opcode_rsr_eps2_encode_fns, 0, 0 },
11307 0,
11308 Opcode_wsr_eps2_encode_fns, 0, 0 },
11310 0,
11311 Opcode_xsr_eps2_encode_fns, 0, 0 },
11313 0,
11314 Opcode_rsr_eps3_encode_fns, 0, 0 },
11316 0,
11317 Opcode_wsr_eps3_encode_fns, 0, 0 },
11319 0,
11320 Opcode_xsr_eps3_encode_fns, 0, 0 },
11322 0,
11323 Opcode_rsr_eps4_encode_fns, 0, 0 },
11325 0,
11326 Opcode_wsr_eps4_encode_fns, 0, 0 },
11328 0,
11329 Opcode_xsr_eps4_encode_fns, 0, 0 },
11331 0,
11332 Opcode_rsr_eps5_encode_fns, 0, 0 },
11334 0,
11335 Opcode_wsr_eps5_encode_fns, 0, 0 },
11337 0,
11338 Opcode_xsr_eps5_encode_fns, 0, 0 },
11340 0,
11341 Opcode_rsr_eps6_encode_fns, 0, 0 },
11343 0,
11344 Opcode_wsr_eps6_encode_fns, 0, 0 },
11346 0,
11347 Opcode_xsr_eps6_encode_fns, 0, 0 },
11349 0,
11350 Opcode_rsr_eps7_encode_fns, 0, 0 },
11352 0,
11353 Opcode_wsr_eps7_encode_fns, 0, 0 },
11355 0,
11356 Opcode_xsr_eps7_encode_fns, 0, 0 },
11358 0,
11359 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
11361 0,
11362 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
11364 0,
11365 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
11367 0,
11368 Opcode_rsr_depc_encode_fns, 0, 0 },
11370 0,
11371 Opcode_wsr_depc_encode_fns, 0, 0 },
11373 0,
11374 Opcode_xsr_depc_encode_fns, 0, 0 },
11376 0,
11377 Opcode_rsr_exccause_encode_fns, 0, 0 },
11379 0,
11380 Opcode_wsr_exccause_encode_fns, 0, 0 },
11382 0,
11383 Opcode_xsr_exccause_encode_fns, 0, 0 },
11385 0,
11386 Opcode_rsr_misc0_encode_fns, 0, 0 },
11388 0,
11389 Opcode_wsr_misc0_encode_fns, 0, 0 },
11391 0,
11392 Opcode_xsr_misc0_encode_fns, 0, 0 },
11394 0,
11395 Opcode_rsr_misc1_encode_fns, 0, 0 },
11397 0,
11398 Opcode_wsr_misc1_encode_fns, 0, 0 },
11400 0,
11401 Opcode_xsr_misc1_encode_fns, 0, 0 },
11403 0,
11404 Opcode_rsr_prid_encode_fns, 0, 0 },
11406 0,
11407 Opcode_rsr_vecbase_encode_fns, 0, 0 },
11409 0,
11410 Opcode_wsr_vecbase_encode_fns, 0, 0 },
11412 0,
11413 Opcode_xsr_vecbase_encode_fns, 0, 0 },
11415 0,
11416 Opcode_mul_aa_ll_encode_fns, 0, 0 },
11418 0,
11419 Opcode_mul_aa_hl_encode_fns, 0, 0 },
11421 0,
11422 Opcode_mul_aa_lh_encode_fns, 0, 0 },
11424 0,
11425 Opcode_mul_aa_hh_encode_fns, 0, 0 },
11427 0,
11428 Opcode_umul_aa_ll_encode_fns, 0, 0 },
11430 0,
11431 Opcode_umul_aa_hl_encode_fns, 0, 0 },
11433 0,
11434 Opcode_umul_aa_lh_encode_fns, 0, 0 },
11436 0,
11437 Opcode_umul_aa_hh_encode_fns, 0, 0 },
11439 0,
11440 Opcode_mul_ad_ll_encode_fns, 0, 0 },
11442 0,
11443 Opcode_mul_ad_hl_encode_fns, 0, 0 },
11445 0,
11446 Opcode_mul_ad_lh_encode_fns, 0, 0 },
11448 0,
11449 Opcode_mul_ad_hh_encode_fns, 0, 0 },
11451 0,
11452 Opcode_mul_da_ll_encode_fns, 0, 0 },
11454 0,
11455 Opcode_mul_da_hl_encode_fns, 0, 0 },
11457 0,
11458 Opcode_mul_da_lh_encode_fns, 0, 0 },
11460 0,
11461 Opcode_mul_da_hh_encode_fns, 0, 0 },
11463 0,
11464 Opcode_mul_dd_ll_encode_fns, 0, 0 },
11466 0,
11467 Opcode_mul_dd_hl_encode_fns, 0, 0 },
11469 0,
11470 Opcode_mul_dd_lh_encode_fns, 0, 0 },
11472 0,
11473 Opcode_mul_dd_hh_encode_fns, 0, 0 },
11475 0,
11476 Opcode_mula_aa_ll_encode_fns, 0, 0 },
11478 0,
11479 Opcode_mula_aa_hl_encode_fns, 0, 0 },
11481 0,
11482 Opcode_mula_aa_lh_encode_fns, 0, 0 },
11484 0,
11485 Opcode_mula_aa_hh_encode_fns, 0, 0 },
11487 0,
11488 Opcode_muls_aa_ll_encode_fns, 0, 0 },
11490 0,
11491 Opcode_muls_aa_hl_encode_fns, 0, 0 },
11493 0,
11494 Opcode_muls_aa_lh_encode_fns, 0, 0 },
11496 0,
11497 Opcode_muls_aa_hh_encode_fns, 0, 0 },
11499 0,
11500 Opcode_mula_ad_ll_encode_fns, 0, 0 },
11502 0,
11503 Opcode_mula_ad_hl_encode_fns, 0, 0 },
11505 0,
11506 Opcode_mula_ad_lh_encode_fns, 0, 0 },
11508 0,
11509 Opcode_mula_ad_hh_encode_fns, 0, 0 },
11511 0,
11512 Opcode_muls_ad_ll_encode_fns, 0, 0 },
11514 0,
11515 Opcode_muls_ad_hl_encode_fns, 0, 0 },
11517 0,
11518 Opcode_muls_ad_lh_encode_fns, 0, 0 },
11520 0,
11521 Opcode_muls_ad_hh_encode_fns, 0, 0 },
11523 0,
11524 Opcode_mula_da_ll_encode_fns, 0, 0 },
11526 0,
11527 Opcode_mula_da_hl_encode_fns, 0, 0 },
11529 0,
11530 Opcode_mula_da_lh_encode_fns, 0, 0 },
11532 0,
11533 Opcode_mula_da_hh_encode_fns, 0, 0 },
11535 0,
11536 Opcode_muls_da_ll_encode_fns, 0, 0 },
11538 0,
11539 Opcode_muls_da_hl_encode_fns, 0, 0 },
11541 0,
11542 Opcode_muls_da_lh_encode_fns, 0, 0 },
11544 0,
11545 Opcode_muls_da_hh_encode_fns, 0, 0 },
11547 0,
11548 Opcode_mula_dd_ll_encode_fns, 0, 0 },
11550 0,
11551 Opcode_mula_dd_hl_encode_fns, 0, 0 },
11553 0,
11554 Opcode_mula_dd_lh_encode_fns, 0, 0 },
11556 0,
11557 Opcode_mula_dd_hh_encode_fns, 0, 0 },
11559 0,
11560 Opcode_muls_dd_ll_encode_fns, 0, 0 },
11562 0,
11563 Opcode_muls_dd_hl_encode_fns, 0, 0 },
11565 0,
11566 Opcode_muls_dd_lh_encode_fns, 0, 0 },
11568 0,
11569 Opcode_muls_dd_hh_encode_fns, 0, 0 },
11571 0,
11572 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
11574 0,
11575 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
11577 0,
11578 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
11580 0,
11581 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
11583 0,
11584 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
11586 0,
11587 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
11589 0,
11590 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
11592 0,
11593 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
11595 0,
11596 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
11598 0,
11599 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
11601 0,
11602 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
11604 0,
11605 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
11607 0,
11608 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
11610 0,
11611 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
11613 0,
11614 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
11616 0,
11617 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
11619 0,
11620 Opcode_lddec_encode_fns, 0, 0 },
11622 0,
11623 Opcode_ldinc_encode_fns, 0, 0 },
11625 0,
11626 Opcode_mul16u_encode_fns, 0, 0 },
11628 0,
11629 Opcode_mul16s_encode_fns, 0, 0 },
11631 0,
11632 Opcode_rsr_m0_encode_fns, 0, 0 },
11634 0,
11635 Opcode_wsr_m0_encode_fns, 0, 0 },
11637 0,
11638 Opcode_xsr_m0_encode_fns, 0, 0 },
11640 0,
11641 Opcode_rsr_m1_encode_fns, 0, 0 },
11643 0,
11644 Opcode_wsr_m1_encode_fns, 0, 0 },
11646 0,
11647 Opcode_xsr_m1_encode_fns, 0, 0 },
11649 0,
11650 Opcode_rsr_m2_encode_fns, 0, 0 },
11652 0,
11653 Opcode_wsr_m2_encode_fns, 0, 0 },
11655 0,
11656 Opcode_xsr_m2_encode_fns, 0, 0 },
11658 0,
11659 Opcode_rsr_m3_encode_fns, 0, 0 },
11661 0,
11662 Opcode_wsr_m3_encode_fns, 0, 0 },
11664 0,
11665 Opcode_xsr_m3_encode_fns, 0, 0 },
11667 0,
11668 Opcode_rsr_acclo_encode_fns, 0, 0 },
11670 0,
11671 Opcode_wsr_acclo_encode_fns, 0, 0 },
11673 0,
11674 Opcode_xsr_acclo_encode_fns, 0, 0 },
11676 0,
11677 Opcode_rsr_acchi_encode_fns, 0, 0 },
11679 0,
11680 Opcode_wsr_acchi_encode_fns, 0, 0 },
11682 0,
11683 Opcode_xsr_acchi_encode_fns, 0, 0 },
11686 Opcode_rfi_encode_fns, 0, 0 },
11688 0,
11689 Opcode_waiti_encode_fns, 0, 0 },
11691 0,
11692 Opcode_rsr_interrupt_encode_fns, 0, 0 },
11694 0,
11695 Opcode_wsr_intset_encode_fns, 0, 0 },
11697 0,
11698 Opcode_wsr_intclear_encode_fns, 0, 0 },
11700 0,
11701 Opcode_rsr_intenable_encode_fns, 0, 0 },
11703 0,
11704 Opcode_wsr_intenable_encode_fns, 0, 0 },
11706 0,
11707 Opcode_xsr_intenable_encode_fns, 0, 0 },
11709 0,
11710 Opcode_break_encode_fns, 0, 0 },
11712 0,
11713 Opcode_break_n_encode_fns, 0, 0 },
11715 0,
11716 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
11718 0,
11719 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
11721 0,
11722 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
11724 0,
11725 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
11727 0,
11728 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
11730 0,
11731 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
11733 0,
11734 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
11736 0,
11737 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
11739 0,
11740 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
11742 0,
11743 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
11745 0,
11746 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
11748 0,
11749 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
11751 0,
11752 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
11754 0,
11755 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
11757 0,
11758 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
11760 0,
11761 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
11763 0,
11764 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
11766 0,
11767 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
11769 0,
11770 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
11772 0,
11773 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
11775 0,
11776 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
11778 0,
11779 Opcode_rsr_debugcause_encode_fns, 0, 0 },
11781 0,
11782 Opcode_wsr_debugcause_encode_fns, 0, 0 },
11784 0,
11785 Opcode_xsr_debugcause_encode_fns, 0, 0 },
11787 0,
11788 Opcode_rsr_icount_encode_fns, 0, 0 },
11790 0,
11791 Opcode_wsr_icount_encode_fns, 0, 0 },
11793 0,
11794 Opcode_xsr_icount_encode_fns, 0, 0 },
11796 0,
11797 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
11799 0,
11800 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
11802 0,
11803 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
11805 0,
11806 Opcode_rsr_ddr_encode_fns, 0, 0 },
11808 0,
11809 Opcode_wsr_ddr_encode_fns, 0, 0 },
11811 0,
11812 Opcode_xsr_ddr_encode_fns, 0, 0 },
11815 Opcode_rfdo_encode_fns, 0, 0 },
11818 Opcode_rfdd_encode_fns, 0, 0 },
11820 0,
11821 Opcode_wsr_mmid_encode_fns, 0, 0 },
11823 0,
11824 Opcode_rsr_ccount_encode_fns, 0, 0 },
11826 0,
11827 Opcode_wsr_ccount_encode_fns, 0, 0 },
11829 0,
11830 Opcode_xsr_ccount_encode_fns, 0, 0 },
11832 0,
11833 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
11835 0,
11836 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
11838 0,
11839 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
11841 0,
11842 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
11844 0,
11845 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
11847 0,
11848 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
11850 0,
11851 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
11853 0,
11854 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
11856 0,
11857 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
11859 0,
11860 Opcode_ipf_encode_fns, 0, 0 },
11862 0,
11863 Opcode_ihi_encode_fns, 0, 0 },
11865 0,
11866 Opcode_ipfl_encode_fns, 0, 0 },
11868 0,
11869 Opcode_ihu_encode_fns, 0, 0 },
11871 0,
11872 Opcode_iiu_encode_fns, 0, 0 },
11874 0,
11875 Opcode_iii_encode_fns, 0, 0 },
11877 0,
11878 Opcode_lict_encode_fns, 0, 0 },
11880 0,
11881 Opcode_licw_encode_fns, 0, 0 },
11883 0,
11884 Opcode_sict_encode_fns, 0, 0 },
11886 0,
11887 Opcode_sicw_encode_fns, 0, 0 },
11889 0,
11890 Opcode_dhwb_encode_fns, 0, 0 },
11892 0,
11893 Opcode_dhwbi_encode_fns, 0, 0 },
11895 0,
11896 Opcode_diwb_encode_fns, 0, 0 },
11898 0,
11899 Opcode_diwbi_encode_fns, 0, 0 },
11901 0,
11902 Opcode_dhi_encode_fns, 0, 0 },
11904 0,
11905 Opcode_dii_encode_fns, 0, 0 },
11907 0,
11908 Opcode_dpfr_encode_fns, 0, 0 },
11910 0,
11911 Opcode_dpfw_encode_fns, 0, 0 },
11913 0,
11914 Opcode_dpfro_encode_fns, 0, 0 },
11916 0,
11917 Opcode_dpfwo_encode_fns, 0, 0 },
11919 0,
11920 Opcode_dpfl_encode_fns, 0, 0 },
11922 0,
11923 Opcode_dhu_encode_fns, 0, 0 },
11925 0,
11926 Opcode_diu_encode_fns, 0, 0 },
11928 0,
11929 Opcode_sdct_encode_fns, 0, 0 },
11931 0,
11932 Opcode_ldct_encode_fns, 0, 0 },
11934 0,
11935 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
11937 0,
11938 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
11940 0,
11941 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
11943 0,
11944 Opcode_rsr_rasid_encode_fns, 0, 0 },
11946 0,
11947 Opcode_wsr_rasid_encode_fns, 0, 0 },
11949 0,
11950 Opcode_xsr_rasid_encode_fns, 0, 0 },
11952 0,
11953 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
11955 0,
11956 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
11958 0,
11959 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
11961 0,
11962 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
11964 0,
11965 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
11967 0,
11968 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
11970 0,
11971 Opcode_idtlb_encode_fns, 0, 0 },
11973 0,
11974 Opcode_pdtlb_encode_fns, 0, 0 },
11976 0,
11977 Opcode_rdtlb0_encode_fns, 0, 0 },
11979 0,
11980 Opcode_rdtlb1_encode_fns, 0, 0 },
11982 0,
11983 Opcode_wdtlb_encode_fns, 0, 0 },
11985 0,
11986 Opcode_iitlb_encode_fns, 0, 0 },
11988 0,
11989 Opcode_pitlb_encode_fns, 0, 0 },
11991 0,
11992 Opcode_ritlb0_encode_fns, 0, 0 },
11994 0,
11995 Opcode_ritlb1_encode_fns, 0, 0 },
11997 0,
11998 Opcode_witlb_encode_fns, 0, 0 },
12000 0,
12001 Opcode_ldpte_encode_fns, 0, 0 },
12004 Opcode_hwwitlba_encode_fns, 0, 0 },
12006 0,
12007 Opcode_hwwdtlba_encode_fns, 0, 0 },
12009 0,
12010 Opcode_rsr_cpenable_encode_fns, 0, 0 },
12012 0,
12013 Opcode_wsr_cpenable_encode_fns, 0, 0 },
12015 0,
12016 Opcode_xsr_cpenable_encode_fns, 0, 0 },
12018 0,
12019 Opcode_clamps_encode_fns, 0, 0 },
12021 0,
12022 Opcode_min_encode_fns, 0, 0 },
12024 0,
12025 Opcode_max_encode_fns, 0, 0 },
12027 0,
12028 Opcode_minu_encode_fns, 0, 0 },
12030 0,
12031 Opcode_maxu_encode_fns, 0, 0 },
12033 0,
12034 Opcode_nsa_encode_fns, 0, 0 },
12036 0,
12037 Opcode_nsau_encode_fns, 0, 0 },
12039 0,
12040 Opcode_sext_encode_fns, 0, 0 },
12042 0,
12043 Opcode_l32ai_encode_fns, 0, 0 },
12045 0,
12046 Opcode_s32ri_encode_fns, 0, 0 },
12048 0,
12049 Opcode_s32c1i_encode_fns, 0, 0 },
12051 0,
12052 Opcode_rsr_scompare1_encode_fns, 0, 0 },
12054 0,
12055 Opcode_wsr_scompare1_encode_fns, 0, 0 },
12057 0,
12058 Opcode_xsr_scompare1_encode_fns, 0, 0 },
12060 0,
12061 Opcode_quou_encode_fns, 0, 0 },
12063 0,
12064 Opcode_quos_encode_fns, 0, 0 },
12066 0,
12067 Opcode_remu_encode_fns, 0, 0 },
12069 0,
12070 Opcode_rems_encode_fns, 0, 0 },
12072 0,
12073 Opcode_mull_encode_fns, 0, 0 },
12075 0,
12076 Opcode_rur_expstate_encode_fns, 0, 0 },
12078 0,
12079 Opcode_wur_expstate_encode_fns, 0, 0 },
12081 0,
12082 Opcode_read_impwire_encode_fns, 0, 0 },
12084 0,
12085 Opcode_setb_expstate_encode_fns, 0, 0 },
12087 0,
12088 Opcode_clrb_expstate_encode_fns, 0, 0 },
12090 0,
12091 Opcode_wrmsk_expstate_encode_fns, 0, 0 }
12102 case 0:
12105 case 0:
12108 case 0:
12111 case 0:
12114 case 0:
12115 if (Field_s_Slot_inst_get (insn) == 0 &&
12116 Field_n_Slot_inst_get (insn) == 0)
12122 case 0:
12133 case 0:
12148 if (Field_s_Slot_inst_get (insn) == 0)
12152 case 0:
12161 return 0; /* excw */
12174 case 0:
12177 case 0:
12196 case 0:
12197 if (Field_t_Slot_inst_get (insn) == 0)
12201 if (Field_t_Slot_inst_get (insn) == 0)
12209 if (Field_t_Slot_inst_get (insn) == 0)
12223 case 0:
12224 if (Field_t_Slot_inst_get (insn) == 0)
12228 if (Field_t_Slot_inst_get (insn) == 0)
12232 if (Field_t_Slot_inst_get (insn) == 0)
12236 if (Field_t_Slot_inst_get (insn) == 0)
12240 if (Field_thi3_Slot_inst_get (insn) == 0)
12244 if (Field_s_Slot_inst_get (insn) == 0)
12261 if (Field_t_Slot_inst_get (insn) == 0)
12275 if (Field_t_Slot_inst_get (insn) == 0)
12289 case 0:
12316 case 0:
12327 case 0:
12456 if (Field_s_Slot_inst_get (insn) == 0)
12460 if (Field_t_Slot_inst_get (insn) == 0)
12464 if (Field_s_Slot_inst_get (insn) == 0)
12474 case 0:
12487 if (Field_t_Slot_inst_get (insn) == 0)
12516 case 0:
12519 case 0:
12656 case 0:
12834 case 0:
12843 case 0:
12844 if (Field_s_Slot_inst_get (insn) == 0 &&
12845 Field_op2_Slot_inst_get (insn) == 0 &&
12850 if (Field_s3to1_Slot_inst_get (insn) == 0 &&
12851 Field_op2_Slot_inst_get (insn) == 0 &&
12855 Field_op2_Slot_inst_get (insn) == 0 &&
12860 if (Field_op2_Slot_inst_get (insn) == 0 &&
12871 case 0:
12886 case 0:
12905 case 0:
12922 case 0:
12955 case 0:
12959 if (Field_t3_Slot_inst_get (insn) == 0 &&
12960 Field_tlo_Slot_inst_get (insn) == 0 &&
12961 Field_r3_Slot_inst_get (insn) == 0)
12965 if (Field_t3_Slot_inst_get (insn) == 0 &&
12966 Field_tlo_Slot_inst_get (insn) == 0 &&
12967 Field_r3_Slot_inst_get (insn) == 0)
12971 if (Field_t3_Slot_inst_get (insn) == 0 &&
12972 Field_tlo_Slot_inst_get (insn) == 0 &&
12973 Field_r3_Slot_inst_get (insn) == 0)
12977 if (Field_t3_Slot_inst_get (insn) == 0 &&
12978 Field_tlo_Slot_inst_get (insn) == 0 &&
12979 Field_r3_Slot_inst_get (insn) == 0)
12988 if (Field_t3_Slot_inst_get (insn) == 0 &&
12989 Field_tlo_Slot_inst_get (insn) == 0 &&
12990 Field_r3_Slot_inst_get (insn) == 0)
12994 if (Field_t3_Slot_inst_get (insn) == 0 &&
12995 Field_tlo_Slot_inst_get (insn) == 0 &&
12996 Field_r3_Slot_inst_get (insn) == 0)
13000 if (Field_t3_Slot_inst_get (insn) == 0 &&
13001 Field_tlo_Slot_inst_get (insn) == 0 &&
13002 Field_r3_Slot_inst_get (insn) == 0)
13006 if (Field_t3_Slot_inst_get (insn) == 0 &&
13007 Field_tlo_Slot_inst_get (insn) == 0 &&
13008 Field_r3_Slot_inst_get (insn) == 0)
13017 if (Field_s_Slot_inst_get (insn) == 0 &&
13018 Field_w_Slot_inst_get (insn) == 0 &&
13019 Field_r3_Slot_inst_get (insn) == 0 &&
13020 Field_t3_Slot_inst_get (insn) == 0 &&
13021 Field_tlo_Slot_inst_get (insn) == 0)
13025 if (Field_s_Slot_inst_get (insn) == 0 &&
13026 Field_w_Slot_inst_get (insn) == 0 &&
13027 Field_r3_Slot_inst_get (insn) == 0 &&
13028 Field_t3_Slot_inst_get (insn) == 0 &&
13029 Field_tlo_Slot_inst_get (insn) == 0)
13033 if (Field_s_Slot_inst_get (insn) == 0 &&
13034 Field_w_Slot_inst_get (insn) == 0 &&
13035 Field_r3_Slot_inst_get (insn) == 0 &&
13036 Field_t3_Slot_inst_get (insn) == 0 &&
13037 Field_tlo_Slot_inst_get (insn) == 0)
13041 if (Field_s_Slot_inst_get (insn) == 0 &&
13042 Field_w_Slot_inst_get (insn) == 0 &&
13043 Field_r3_Slot_inst_get (insn) == 0 &&
13044 Field_t3_Slot_inst_get (insn) == 0 &&
13045 Field_tlo_Slot_inst_get (insn) == 0)
13049 if (Field_s_Slot_inst_get (insn) == 0 &&
13050 Field_w_Slot_inst_get (insn) == 0 &&
13051 Field_r3_Slot_inst_get (insn) == 0 &&
13052 Field_t3_Slot_inst_get (insn) == 0 &&
13053 Field_tlo_Slot_inst_get (insn) == 0)
13057 if (Field_s_Slot_inst_get (insn) == 0 &&
13058 Field_w_Slot_inst_get (insn) == 0 &&
13059 Field_r3_Slot_inst_get (insn) == 0 &&
13060 Field_t3_Slot_inst_get (insn) == 0 &&
13061 Field_tlo_Slot_inst_get (insn) == 0)
13065 if (Field_s_Slot_inst_get (insn) == 0 &&
13066 Field_w_Slot_inst_get (insn) == 0 &&
13067 Field_r3_Slot_inst_get (insn) == 0 &&
13068 Field_t3_Slot_inst_get (insn) == 0 &&
13069 Field_tlo_Slot_inst_get (insn) == 0)
13073 if (Field_s_Slot_inst_get (insn) == 0 &&
13074 Field_w_Slot_inst_get (insn) == 0 &&
13075 Field_r3_Slot_inst_get (insn) == 0 &&
13076 Field_t3_Slot_inst_get (insn) == 0 &&
13077 Field_tlo_Slot_inst_get (insn) == 0)
13081 if (Field_s_Slot_inst_get (insn) == 0 &&
13082 Field_w_Slot_inst_get (insn) == 0 &&
13083 Field_r3_Slot_inst_get (insn) == 0 &&
13084 Field_t3_Slot_inst_get (insn) == 0 &&
13085 Field_tlo_Slot_inst_get (insn) == 0)
13089 if (Field_s_Slot_inst_get (insn) == 0 &&
13090 Field_w_Slot_inst_get (insn) == 0 &&
13091 Field_r3_Slot_inst_get (insn) == 0 &&
13092 Field_t3_Slot_inst_get (insn) == 0 &&
13093 Field_tlo_Slot_inst_get (insn) == 0)
13097 if (Field_s_Slot_inst_get (insn) == 0 &&
13098 Field_w_Slot_inst_get (insn) == 0 &&
13099 Field_r3_Slot_inst_get (insn) == 0 &&
13100 Field_t3_Slot_inst_get (insn) == 0 &&
13101 Field_tlo_Slot_inst_get (insn) == 0)
13105 if (Field_s_Slot_inst_get (insn) == 0 &&
13106 Field_w_Slot_inst_get (insn) == 0 &&
13107 Field_r3_Slot_inst_get (insn) == 0 &&
13108 Field_t3_Slot_inst_get (insn) == 0 &&
13109 Field_tlo_Slot_inst_get (insn) == 0)
13118 if (Field_r_Slot_inst_get (insn) == 0 &&
13119 Field_t3_Slot_inst_get (insn) == 0 &&
13120 Field_tlo_Slot_inst_get (insn) == 0)
13124 if (Field_r_Slot_inst_get (insn) == 0 &&
13125 Field_t3_Slot_inst_get (insn) == 0 &&
13126 Field_tlo_Slot_inst_get (insn) == 0)
13130 if (Field_r_Slot_inst_get (insn) == 0 &&
13131 Field_t3_Slot_inst_get (insn) == 0 &&
13132 Field_tlo_Slot_inst_get (insn) == 0)
13136 if (Field_r_Slot_inst_get (insn) == 0 &&
13137 Field_t3_Slot_inst_get (insn) == 0 &&
13138 Field_tlo_Slot_inst_get (insn) == 0)
13142 if (Field_r_Slot_inst_get (insn) == 0 &&
13143 Field_t3_Slot_inst_get (insn) == 0 &&
13144 Field_tlo_Slot_inst_get (insn) == 0)
13148 if (Field_r_Slot_inst_get (insn) == 0 &&
13149 Field_t3_Slot_inst_get (insn) == 0 &&
13150 Field_tlo_Slot_inst_get (insn) == 0)
13154 if (Field_r_Slot_inst_get (insn) == 0 &&
13155 Field_t3_Slot_inst_get (insn) == 0 &&
13156 Field_tlo_Slot_inst_get (insn) == 0)
13160 if (Field_r_Slot_inst_get (insn) == 0 &&
13161 Field_t3_Slot_inst_get (insn) == 0 &&
13162 Field_tlo_Slot_inst_get (insn) == 0)
13166 if (Field_r_Slot_inst_get (insn) == 0 &&
13167 Field_t3_Slot_inst_get (insn) == 0 &&
13168 Field_tlo_Slot_inst_get (insn) == 0)
13172 if (Field_r_Slot_inst_get (insn) == 0 &&
13173 Field_t3_Slot_inst_get (insn) == 0 &&
13174 Field_tlo_Slot_inst_get (insn) == 0)
13178 if (Field_r_Slot_inst_get (insn) == 0 &&
13179 Field_t3_Slot_inst_get (insn) == 0 &&
13180 Field_tlo_Slot_inst_get (insn) == 0)
13184 if (Field_r_Slot_inst_get (insn) == 0 &&
13185 Field_t3_Slot_inst_get (insn) == 0 &&
13186 Field_tlo_Slot_inst_get (insn) == 0)
13195 if (Field_r3_Slot_inst_get (insn) == 0)
13199 if (Field_r3_Slot_inst_get (insn) == 0)
13203 if (Field_r3_Slot_inst_get (insn) == 0)
13207 if (Field_r3_Slot_inst_get (insn) == 0)
13216 if (Field_r3_Slot_inst_get (insn) == 0)
13220 if (Field_r3_Slot_inst_get (insn) == 0)
13224 if (Field_r3_Slot_inst_get (insn) == 0)
13228 if (Field_r3_Slot_inst_get (insn) == 0)
13237 if (Field_s_Slot_inst_get (insn) == 0 &&
13238 Field_w_Slot_inst_get (insn) == 0 &&
13239 Field_r3_Slot_inst_get (insn) == 0)
13243 if (Field_s_Slot_inst_get (insn) == 0 &&
13244 Field_w_Slot_inst_get (insn) == 0 &&
13245 Field_r3_Slot_inst_get (insn) == 0)
13249 if (Field_s_Slot_inst_get (insn) == 0 &&
13250 Field_w_Slot_inst_get (insn) == 0 &&
13251 Field_r3_Slot_inst_get (insn) == 0)
13255 if (Field_s_Slot_inst_get (insn) == 0 &&
13256 Field_w_Slot_inst_get (insn) == 0 &&
13257 Field_r3_Slot_inst_get (insn) == 0)
13261 if (Field_s_Slot_inst_get (insn) == 0 &&
13262 Field_w_Slot_inst_get (insn) == 0 &&
13263 Field_r3_Slot_inst_get (insn) == 0)
13267 if (Field_s_Slot_inst_get (insn) == 0 &&
13268 Field_w_Slot_inst_get (insn) == 0 &&
13269 Field_r3_Slot_inst_get (insn) == 0)
13273 if (Field_s_Slot_inst_get (insn) == 0 &&
13274 Field_w_Slot_inst_get (insn) == 0 &&
13275 Field_r3_Slot_inst_get (insn) == 0)
13279 if (Field_s_Slot_inst_get (insn) == 0 &&
13280 Field_w_Slot_inst_get (insn) == 0 &&
13281 Field_r3_Slot_inst_get (insn) == 0)
13285 if (Field_s_Slot_inst_get (insn) == 0 &&
13286 Field_w_Slot_inst_get (insn) == 0 &&
13287 Field_r3_Slot_inst_get (insn) == 0)
13291 if (Field_s_Slot_inst_get (insn) == 0 &&
13292 Field_w_Slot_inst_get (insn) == 0 &&
13293 Field_r3_Slot_inst_get (insn) == 0)
13297 if (Field_s_Slot_inst_get (insn) == 0 &&
13298 Field_w_Slot_inst_get (insn) == 0 &&
13299 Field_r3_Slot_inst_get (insn) == 0)
13303 if (Field_s_Slot_inst_get (insn) == 0 &&
13304 Field_w_Slot_inst_get (insn) == 0 &&
13305 Field_r3_Slot_inst_get (insn) == 0)
13313 case 0:
13314 if (Field_r_Slot_inst_get (insn) == 0)
13318 if (Field_r_Slot_inst_get (insn) == 0)
13322 if (Field_r_Slot_inst_get (insn) == 0)
13326 if (Field_r_Slot_inst_get (insn) == 0)
13330 if (Field_r_Slot_inst_get (insn) == 0)
13334 if (Field_r_Slot_inst_get (insn) == 0)
13338 if (Field_r_Slot_inst_get (insn) == 0)
13342 if (Field_r_Slot_inst_get (insn) == 0)
13346 if (Field_r_Slot_inst_get (insn) == 0)
13350 if (Field_r_Slot_inst_get (insn) == 0)
13354 if (Field_r_Slot_inst_get (insn) == 0)
13358 if (Field_r_Slot_inst_get (insn) == 0)
13362 if (Field_r_Slot_inst_get (insn) == 0)
13366 if (Field_r_Slot_inst_get (insn) == 0)
13370 if (Field_r_Slot_inst_get (insn) == 0)
13374 if (Field_r_Slot_inst_get (insn) == 0)
13380 if (Field_op1_Slot_inst_get (insn) == 0 &&
13381 Field_t_Slot_inst_get (insn) == 0 &&
13382 Field_rhi_Slot_inst_get (insn) == 0)
13386 if (Field_op1_Slot_inst_get (insn) == 0 &&
13387 Field_t_Slot_inst_get (insn) == 0 &&
13388 Field_rhi_Slot_inst_get (insn) == 0)
13396 case 0:
13409 case 0:
13414 case 0:
13427 case 0:
13440 case 0:
13464 case 0:
13508 case 0:
13513 case 0:
13524 case 0:
13529 case 0:
13536 if (Field_s_Slot_inst16b_get (insn) == 0)
13540 if (Field_s_Slot_inst16b_get (insn) == 0)
13575 slotbuf[0] = (insn[0] & 0xffffff);
13582 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
13589 slotbuf[0] = (insn[0] & 0xffff);
13596 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13603 slotbuf[0] = (insn[0] & 0xffff);
13610 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13642 0,
13643 0,
13644 0,
13645 0,
13646 0,
13647 0,
13648 0,
13649 0,
13702 0,
13703 0,
13704 0,
13705 0,
13706 0,
13707 0,
13708 0,
13709 0,
13736 0,
13737 0,
13738 0,
13739 0,
13741 0,
13742 0,
13743 0,
13744 0,
13745 0,
13747 0,
13748 0,
13750 0,
13751 0,
13752 0,
13753 0,
13754 0,
13755 0,
13756 0,
13759 0,
13761 0,
13770 0,
13771 0,
13772 0,
13773 0,
13774 0,
13775 0,
13776 0,
13777 0,
13778 0,
13779 0,
13780 0,
13796 0,
13797 0,
13798 0,
13799 0,
13801 0,
13802 0,
13803 0,
13804 0,
13805 0,
13807 0,
13808 0,
13810 0,
13811 0,
13812 0,
13813 0,
13814 0,
13815 0,
13816 0,
13819 0,
13821 0,
13830 0,
13831 0,
13832 0,
13833 0,
13834 0,
13835 0,
13836 0,
13837 0,
13838 0,
13839 0,
13840 0,
13856 0,
13857 0,
13858 0,
13859 0,
13861 0,
13862 0,
13863 0,
13864 0,
13865 0,
13867 0,
13868 0,
13870 0,
13871 0,
13872 0,
13873 0,
13874 0,
13875 0,
13876 0,
13879 0,
13881 0,
13890 0,
13891 0,
13892 0,
13893 0,
13894 0,
13895 0,
13896 0,
13897 0,
13898 0,
13899 0,
13900 0,
13916 0,
13917 0,
13918 0,
13919 0,
13921 0,
13922 0,
13923 0,
13924 0,
13925 0,
13927 0,
13928 0,
13930 0,
13931 0,
13932 0,
13933 0,
13934 0,
13935 0,
13936 0,
13939 0,
13941 0,
13950 0,
13951 0,
13952 0,
13953 0,
13954 0,
13955 0,
13956 0,
13957 0,
13958 0,
13959 0,
13960 0,
13974 { "Inst", "x24", 0,
13978 { "Inst16a", "x16a", 0,
13982 { "Inst16b", "x16b", 0,
13994 insn[0] = 0;
14000 insn[0] = 0x8;
14006 insn[0] = 0xc;
14009 static int Format_x24_slots[] = { 0 };
14025 if ((insn[0] & 0x8) == 0)
14026 return 0; /* x24 */
14027 if ((insn[0] & 0xc) == 0x8)
14029 if ((insn[0] & 0xe) == 0xc)
14056 int op0 = insn[0] & 0xf;
14064 0 /* little-endian */,
14065 3 /* insn_size */, 0,
14071 446, opcodes, 0,
14073 NUM_STATES, states, 0,
14074 NUM_SYSREGS, sysregs, 0,
14075 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
14076 1, interfaces, 0,
14077 0, funcUnits, 0