Lines Matching +full:0 +full:xd00000
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
71 #define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */
72 #define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
75 #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */
76 #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */
77 #define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */
78 #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */
79 #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
80 #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode */
81 #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode */
82 #define SH7750_PTEL_C 0x00000008 /* Cacheability */
83 /* (0 - page not cacheable) */
84 #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been */
86 #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are */
88 #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the */
90 /* 0 - Copy-back mode */
94 #define SH7750_PTEA_REGOFS 0x000034 /* offset */
97 #define SH7750_PTEA_TC 0x00000008 /* Timing Control bit */
98 /* 0 - use area 5 wait states */
100 #define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */
101 #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */
102 #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */
103 #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */
104 #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */
105 #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space */
106 #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space */
107 #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */
108 #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */
112 #define SH7750_TTB_REGOFS 0x000008 /* offset */
117 #define SH7750_TEA_REGOFS 0x00000c /* offset */
122 #define SH7750_MMUCR_REGOFS 0x000010 /* offset */
125 #define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */
126 #define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */
127 #define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */
128 #define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */
129 #define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */
131 #define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */
133 #define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */
146 #define SH7750_CCR_REGOFS 0x00001c /* offset */
150 #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */
151 #define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: */
153 #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */
154 #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */
155 #define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit */
156 /* if you set OCE = 0, */
157 /* you should set ORA = 0 */
158 #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */
159 #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
160 #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */
161 #define SH7750_CCR_OCE 0x00000001 /* OC enable bit */
163 /* Queue address control register 0 - QACR0 */
164 #define SH7750_QACR0_REGOFS 0x000038 /* offset */
169 #define SH7750_QACR1_REGOFS 0x00003c /* offset */
179 #define SH7750_TRA_REGOFS 0x000020 /* offset */
183 #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */
187 #define SH7750_EXPEVT_REGOFS 0x000024
191 #define SH7750_EXPEVT_EX 0x00000fff /* Exception code */
192 #define SH7750_EXPEVT_EX_S 0
195 #define SH7750_INTEVT_REGOFS 0x000028
198 #define SH7750_INTEVT_EX 0x00000fff /* Exception code */
199 #define SH7750_INTEVT_EX_S 0
207 #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */
208 #define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */
209 #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */
212 #define SH7750_EVT_USER_BREAK 0x1E0 /* User break */
213 #define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */
214 #define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / */
216 #define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation, */
219 #define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction */
221 #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction */
223 #define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception */
224 #define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */
225 #define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */
226 #define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */
227 #define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */
228 #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation */
230 #define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */
231 #define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */
232 #define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */
235 #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */
236 #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */
237 #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */
238 #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */
239 #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */
240 #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */
241 #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */
242 #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */
243 #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */
244 #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */
245 #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */
246 #define SH7750_EVT_IRQA 0x340 /* External Interrupt A */
247 #define SH7750_EVT_IRQB 0x360 /* External Interrupt B */
248 #define SH7750_EVT_IRQC 0x380 /* External Interrupt C */
249 #define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */
250 #define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */
253 #define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */
254 #define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */
255 #define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */
256 #define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2 */
259 #define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */
260 #define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */
261 #define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */
264 #define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */
265 #define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */
266 #define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */
267 #define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */
270 #define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt */
275 #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
276 #define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow */
280 #define SH7750_EVT_HUDI 0x600 /* UDI interrupt */
283 #define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */
286 #define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt */
287 #define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt */
288 #define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt */
289 #define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt */
290 #define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */
293 #define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */
294 #define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or */
296 #define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */
297 #define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */
302 #define SH7750_STBCR_REGOFS 0xC00004 /* offset */
306 #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: */
307 /* 0 Transition to SLEEP mode on SLEEP */
309 #define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in */
311 /* 0 normal state */
314 #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls */
315 #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */
317 #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */
319 #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */
321 #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */
323 #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */
326 #define SH7750_STBCR_STBY 0x80
329 #define SH7750_STBCR2_REGOFS 0xC00010 /* offset */
333 #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode */
334 /* 0 transition to sleep or standby mode */
338 #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to the */
341 #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the */
348 #define SH7750_FRQCR_REGOFS 0xC00000 /* offset */
352 #define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable */
353 /* 0 - CKIO pin goes to HiZ/pullup */
355 #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
356 #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */
358 #define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */
359 #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */
360 #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */
361 #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */
362 #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */
363 #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */
364 #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */
366 #define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */
367 #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */
368 #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */
369 #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */
370 #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */
371 #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */
372 #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */
374 #define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency */
376 #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */
377 #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */
378 #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */
379 #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */
380 #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */
387 #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */
390 #define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, you */
391 /* have to set the upper byte to 0x5A */
394 #define SH7750_WTCSR_REGOFS 0xC0000C /* offset */
397 #define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, you */
398 /* have to set the upper byte to 0xA5 */
399 #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */
400 #define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */
401 #define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */
402 #define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */
403 #define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */
404 #define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */
405 #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */
406 #define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */
407 #define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */
408 #define SH7750_WTCSR_CKS 0x07 /* Clock Select: */
409 #define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */
410 #define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */
411 #define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */
412 #define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */
413 #define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */
414 #define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */
415 #define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */
416 #define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */
422 #define SH7750_R64CNT_REGOFS 0xC80000 /* offset */
427 #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */
432 #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */
437 #define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */
442 #define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */
446 #define SH7750_RWKCNT_SUN 0 /* Sunday */
455 #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */
460 #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */
465 #define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */
470 #define SH7750_RSECAR_REGOFS 0xC80020 /* offset */
473 #define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */
476 #define SH7750_RMINAR_REGOFS 0xC80024 /* offset */
479 #define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */
482 #define SH7750_RHRAR_REGOFS 0xC80028 /* offset */
485 #define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */
488 #define SH7750_RWKAR_REGOFS 0xC8002C /* offset */
491 #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */
493 #define SH7750_RWKAR_SUN 0 /* Sunday */
502 #define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */
505 #define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */
508 #define SH7750_RMONAR_REGOFS 0xC80034 /* offset */
511 #define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */
514 #define SH7750_RCR1_REGOFS 0xC80038 /* offset */
517 #define SH7750_RCR1_CF 0x80 /* Carry Flag */
518 #define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */
519 #define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */
520 #define SH7750_RCR1_AF 0x01 /* Alarm Flag */
523 #define SH7750_RCR2_REGOFS 0xC8003C /* offset */
526 #define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */
527 #define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */
528 #define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */
529 #define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */
530 #define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */
531 #define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */
532 #define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */
533 #define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */
534 #define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */
535 #define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */
536 #define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */
537 #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */
538 #define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset */
539 #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, */
547 #define SH7750_BCR1_REGOFS 0x800000 /* offset */
550 #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */
551 #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */
552 #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
553 #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: */
554 /* 0 - pull-up resistor is on for */
557 #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: */
558 /* 0 - pull-up resistor is on for */
561 #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: */
562 /* 0 - Area 1 SRAM is set to */
566 #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: */
567 /* 0 - Area 4 SRAM is set to */
571 #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: */
572 /* 0 - External requests are not */
576 #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: */
577 /* 0 - Master Mode */
579 #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: */
580 /* 0 - SRAM/burst ROM interface */
582 #define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. */
583 /* Specifies the state of A[25:0], */
587 /* 0 - signals go to High-Z mode */
589 #define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. */
595 /* 0 - signals go to High-Z mode */
597 #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */
598 #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */
599 #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM */
601 #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM */
603 #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM */
605 #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM */
608 #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */
609 #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */
610 #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM */
612 #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM */
614 #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM */
616 #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM */
619 #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */
620 #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */
621 #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM */
623 #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM */
625 #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM */
627 #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM */
630 #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */
631 #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or */
633 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 */
635 #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are */
637 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 */
639 #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM */
642 #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: */
643 /* 0 - SRAM interface */
647 #define SH7750_BCR2_REGOFS 0x800004 /* offset */
651 #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */
653 #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */
655 #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */
657 #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */
659 #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */
661 #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */
663 #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */
665 #define SH7750_BCR2_SZ_64 0 /* 64 bits */
669 #define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable */
670 /* 0 - D51-D32 are not used as a port */
674 #define SH7750_WCR1_REGOFS 0x800008 /* offset */
677 #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle */
680 #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
682 #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
684 #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
686 #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
688 #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
690 #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
692 #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
693 #define SH7750_WCR1_A0IW_S 0
696 #define SH7750_WCR2_REGOFS 0x80000C /* offset */
700 #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */
702 #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */
704 #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */
706 #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */
708 #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */
710 #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */
712 #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */
714 #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */
716 #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */
718 #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */
719 #define SH7750_WCR2_A0B_S 0
721 #define SH7750_WCR2_WS0 0 /* 0 wait states inserted */
730 #define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */
740 #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */
757 #define SH7750_WCR3_REGOFS 0x800010 /* offset */
761 #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */
762 #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */
764 #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */
765 #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */
767 #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */
768 #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */
770 #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */
771 #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */
773 #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */
774 #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */
776 #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */
777 #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */
779 #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */
780 #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */
781 #define SH7750_WCR3_A0H_S 0
783 #define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */
788 #define SH7750_MCR_REGOFS 0x800014 /* offset */
792 #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */
793 #define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */
794 #define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */
795 #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of */
797 #define SH7750_MCR_TRC_0 0x00000000 /* 0 */
798 #define SH7750_MCR_TRC_3 0x08000000 /* 3 */
799 #define SH7750_MCR_TRC_6 0x10000000 /* 6 */
800 #define SH7750_MCR_TRC_9 0x18000000 /* 9 */
801 #define SH7750_MCR_TRC_12 0x20000000 /* 12 */
802 #define SH7750_MCR_TRC_15 0x28000000 /* 15 */
803 #define SH7750_MCR_TRC_18 0x30000000 /* 18 */
804 #define SH7750_MCR_TRC_21 0x38000000 /* 21 */
806 #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */
807 #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */
808 #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */
810 #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period */
815 #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
816 #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
817 #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
818 #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
819 #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
820 #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
821 #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */
822 #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */
824 #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay */
828 #define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */
829 #define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */
830 #define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */
831 #define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */
832 #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */
833 #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */
834 #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */
836 #define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */
837 #define SH7750_MCR_TRWL_1 0x00000000 /* 1 */
838 #define SH7750_MCR_TRWL_2 0x00002000 /* 2 */
839 #define SH7750_MCR_TRWL_3 0x00004000 /* 3 */
840 #define SH7750_MCR_TRWL_4 0x00006000 /* 4 */
841 #define SH7750_MCR_TRWL_5 0x00008000 /* 5 */
843 #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS */
847 #define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */
848 #define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */
849 #define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */
850 #define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */
851 #define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */
852 #define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */
853 #define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */
854 #define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */
856 #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */
857 #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */
858 #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */
859 #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */
860 #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */
861 #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */
862 #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */
863 #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */
865 #define SH7750_MCR_BE 0x00000200 /* Burst Enable */
866 #define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */
867 #define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */
868 #define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */
869 #define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */
871 #define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */
873 #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */
874 #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */
875 #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */
876 #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */
877 #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */
880 #define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */
881 #define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */
882 #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */
883 #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */
884 #define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */
887 #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000
888 #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000
896 #define SH7750_PCR_REGOFS 0x800018 /* offset */
900 #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait */
904 #define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */
905 #define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */
906 #define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */
907 #define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */
909 #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait */
913 #define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */
914 #define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */
915 #define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */
916 #define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */
918 #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Addr-OE\/WE\ Assertion Delay */
923 #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Addr-OE\/WE\ Assertion Delay */
926 #define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */
935 #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Addr delay, */
941 #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay */
942 #define SH7750_PCR_A6TEH_S 0
944 #define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */
954 #define SH7750_RTCSR_REGOFS 0x80001C /* offset */
958 #define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */
959 #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a */
962 #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */
963 #define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */
964 #define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */
965 #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */
966 #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */
967 #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */
968 #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */
969 #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */
970 #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */
971 #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */
973 #define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */
974 #define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt */
976 #define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */
977 #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */
978 #define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */
981 #define SH7750_RTCNT_REGOFS 0x800020 /* offset */
985 #define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */
988 #define SH7750_RTCOR_REGOFS 0x800024 /* offset */
992 #define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */
995 #define SH7750_RFCR_REGOFS 0x800028 /* offset */
999 #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
1002 #define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
1003 #define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
1007 #define SH7750_SDMR3_REGOFS 0x940000 /* offset */
1008 #define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
1017 #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n) * 16)) /* offset */
1020 #define SH7750_SAR0 SH7750_SAR(0)
1024 #define SH7750_SAR0_A7 SH7750_SAR_A7(0)
1030 #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n) * 16)) /* offset */
1033 #define SH7750_DAR0 SH7750_DAR(0)
1037 #define SH7750_DAR0_A7 SH7750_DAR_A7(0)
1043 #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n) * 16)) /* offset */
1046 #define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
1050 #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0)
1056 #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n) * 16)) /* offset */
1059 #define SH7750_CHCR0 SH7750_CHCR(0)
1063 #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0)
1068 #define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */
1069 #define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
1070 #define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */
1071 #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */
1072 #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */
1073 #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */
1074 #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */
1075 #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */
1076 #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */
1078 #define SH7750_CHCR_STC 0x10000000 /* Source Addr Wait Control Select */
1082 #define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */
1083 #define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
1084 #define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */
1085 #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */
1086 #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */
1087 #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */
1088 #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */
1089 #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */
1090 #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
1092 #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control */
1097 #define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */
1098 #define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */
1099 #define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */
1101 #define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */
1102 #define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */
1103 #define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */
1105 #define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */
1106 #define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */
1107 #define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle */
1109 #define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */
1110 #define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */
1111 #define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */
1113 #define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */
1114 #define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */
1115 #define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */
1116 #define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */
1118 #define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */
1119 #define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */
1120 #define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */
1121 #define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */
1123 #define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */
1124 #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Addr */
1127 #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single */
1130 #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single */
1134 #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr */
1137 #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr */
1140 #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip */
1143 #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr */
1146 #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr */
1149 #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF TX-Data-Empty intr */
1152 #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr */
1155 #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture */
1159 #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture */
1163 #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture */
1168 #define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */
1169 #define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */
1170 #define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */
1172 #define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */
1173 #define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */
1174 #define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */
1175 #define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */
1176 #define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */
1177 #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */
1179 #define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */
1180 #define SH7750_CHCR_TE 0x00000002 /* Transfer End */
1181 #define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */
1184 #define SH7750_DMAOR_REGOFS 0xA00040 /* offset */
1188 #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */
1190 #define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */
1191 #define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */
1192 #define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */
1193 #define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */
1194 #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */
1196 #define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */
1197 #define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */
1198 #define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */
1199 #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */
1205 #define SH7750_PCTRA_REGOFS 0x80002C /* offset */
1209 #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
1211 #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
1215 #define SH7750_PDTRA_REGOFS 0x800030 /* offset */
1222 #define SH7750_PCTRB_REGOFS 0x800040 /* offset */
1226 #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
1228 #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
1232 #define SH7750_PDTRB_REGOFS 0x800044 /* offset */
1239 #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */
1249 #define SH7750_ICR_REGOFS 0xD00000 /* offset */
1253 #define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */
1254 #define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */
1256 #define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */
1257 #define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while */
1259 #define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL */
1262 #define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */
1263 #define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on */
1265 #define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on */
1268 #define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */
1269 #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded */
1271 #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four */
1277 #define SH7750_BARA 0x200000 /* Break address register A */
1278 #define SH7750_BAMRA 0x200004 /* Break address mask register A */
1279 #define SH7750_BBRA 0x200008 /* Break bus cycle register A */
1280 #define SH7750_BARB 0x20000c /* Break address register B */
1281 #define SH7750_BAMRB 0x200010 /* Break address mask register B */
1282 #define SH7750_BBRB 0x200014 /* Break bus cycle register B */
1283 #define SH7750_BASRB 0x000018 /* Break ASID register B */
1284 #define SH7750_BDRB 0x200018 /* Break data register B */
1285 #define SH7750_BDMRB 0x20001c /* Break data mask register B */
1286 #define SH7750_BRCR 0x200020 /* Break control register */
1288 #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */
1293 #define SH7750_BCR3_A7 0x1f800050
1294 #define SH7750_BCR4_A7 0x1e0a00f0