#
b77af26e |
| 13-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Replace CPUState.env_ptr with cpu_env()
Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
#
ad75a51e |
| 13-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
#
95eac43c |
| 28-Jul-2023 |
Daniel Henrique Barboza <danielhb413@gmail.com> |
target/ppc: use g_free() in test_opcode_table()
table[i] is allocated in create_new_table() using g_new().
Use g_free(table[i]) instead of free(table[i]) to comply with QEMU low level memory manage
target/ppc: use g_free() in test_opcode_table()
table[i] is allocated in create_new_table() using g_new().
Use g_free(table[i]) instead of free(table[i]) to comply with QEMU low level memory management guidelines.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> [Mjt: minor commit comment tweak]
show more ...
|
#
cdab53dd |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Fix CPU reservation migration for record-replay
ppc only migrates reserve_addr, so the destination machine can get a valid reservation with an incorrect reservation value of 0. Prior to
target/ppc: Fix CPU reservation migration for record-replay
ppc only migrates reserve_addr, so the destination machine can get a valid reservation with an incorrect reservation value of 0. Prior to commit 392d328abe753 ("target/ppc: Ensure stcx size matches larx"), this could permit a stcx. to incorrectly succeed. That commit inadvertently fixed that bug because the target machine starts with an impossible reservation size of 0, so any stcx. will fail.
This behaviour is permitted by the ISA because reservation loss may have implementation-dependent cause. What's more, with KVM machines it is impossible save or reasonably restore reservation state. However if the vmstate is being used for record-replay, the reservation must be saved and restored exactly in order for execution from snapshot to match the record.
This patch deprecates the existing incomplete reserve_addr vmstate, and adds a new vmstate subsection with complete reservation state. The new vmstate is needed only when record-replay mode is active.
Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
d5ee641c |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Implement watchpoint debug facility for v2.07S
ISA v2.07S introduced the watchpoint facility based on the DAWR0 and DAWRX0 SPRs. Implement this in TCG.
Signed-off-by: Nicholas Piggin <n
target/ppc: Implement watchpoint debug facility for v2.07S
ISA v2.07S introduced the watchpoint facility based on the DAWR0 and DAWRX0 SPRs. Implement this in TCG.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
14192307 |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Implement breakpoint debug facility for v2.07S
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG.
Signed-off-by: Nicholas Piggin <npiggin@gmail
target/ppc: Implement breakpoint debug facility for v2.07S
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
a11e3a15 |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Suppress single step interrupts on rfi-type instructions
BookS does not take single step interrupts on completion of rfi and similar (rfid, hrfid, rfscv). This is not a completely clean
target/ppc: Suppress single step interrupts on rfi-type instructions
BookS does not take single step interrupts on completion of rfi and similar (rfid, hrfid, rfscv). This is not a completely clean way to do it, but in general non-branch instructions that change NIP on completion are excluded.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
14895384 |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Improve book3s branch trace interrupt for v2.07S
Improve the emulation accuracy of the single step and branch trace interrupts for v2.07S. Set SRR1[33]=1, and set SIAR to completed instr
target/ppc: Improve book3s branch trace interrupt for v2.07S
Improve the emulation accuracy of the single step and branch trace interrupts for v2.07S. Set SRR1[33]=1, and set SIAR to completed instruction address.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
98a18f4d |
| 07-Aug-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Remove single-step suppression inside 0x100-0xf00
Single-step interrupts are suppressed if the nip is between 0x100 and 0xf00. This has been the case for a long time and it's not clear w
target/ppc: Remove single-step suppression inside 0x100-0xf00
Single-step interrupts are suppressed if the nip is between 0x100 and 0xf00. This has been the case for a long time and it's not clear what the intention is. Likely either an attempt to suppress trace interrupts for instructions that cause an interrupt on completion, or a workaround to prevent software tripping over itself single stepping its interrupt handlers.
BookE interrupt vectors are set by IVOR registers, and BookS has AIL modes and new interrupt types, so there are many interrupts including the debug interrupt which can be outside this range. So any effect it might have had does not cover most cases (including Linux on recent BookS CPUs).
Remove this special case.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg : fixed typo in commit logs ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
73c19706 |
| 28-Aug-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loo
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-8-philmd@linaro.org>
show more ...
|
#
026ad97e |
| 28-Aug-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/translate: Remove unnecessary 'exec/cpu_ldst.h' header
All these files only access the translator_ld/st API declared in "exec/translator.h". The CPU ld/st API from declared in "exec/cpu_ldst.
target/translate: Remove unnecessary 'exec/cpu_ldst.h' header
All these files only access the translator_ld/st API declared in "exec/translator.h". The CPU ld/st API from declared in "exec/cpu_ldst.h" is not used, remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-5-philmd@linaro.org>
show more ...
|
#
2e718e66 |
| 28-Jul-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/ppc: Disable goto_tb with architectural singlestep
The change to use translator_use_goto_tb went too far, as the CF_SINGLE_STEP flag managed by the translator only handles gdb single stepping
target/ppc: Disable goto_tb with architectural singlestep
The change to use translator_use_goto_tb went too far, as the CF_SINGLE_STEP flag managed by the translator only handles gdb single stepping and not the architectural single stepping modeled in DisasContext.singlestep_enabled.
Fixes: 6e9cc373ec5 ("target/ppc: Use translator_use_goto_tb") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1795 Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
#
9cdfd1b9 |
| 05-Jul-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: SMT support for the HID SPR
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core.
Reviewed-by: Cédric Le
target/ppc: SMT support for the HID SPR
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
3401ea3c |
| 05-Jul-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add LPAR-per-core vs per-thread mode flag
The Power ISA has the concept of sub-processors:
Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that ap
target/ppc: Add LPAR-per-core vs per-thread mode flag
The Power ISA has the concept of sub-processors:
Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads.
POWER9 and POWER10 have two modes, either every thread is a sub-processor or all threads appear as one multi-threaded processor. In the user manuals these are known as "LPAR per thread" / "Thread LPAR", and "LPAR per core" / "1 LPAR", respectively.
The practical difference is: in thread LPAR mode, non-hypervisor SPRs are not shared between threads and msgsndp can not be used to message siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable. Thrad LPAR allows multiple partitions to run concurrently on the same core, and is a requirement for KVM to run on POWER9/10 (which does not gang-schedule an LPAR on all threads of a core like POWER8 KVM).
Traditionally, SMT in PAPR environments including PowerVM and the pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode. In OPAL systems, Thread LPAR is used. When adding SMT to the powernv machine, it is therefore preferable to emulate Thread LPAR.
To account for this difference between pseries and powernv, an LPAR mode flag is added such that SPRs can be implemented as per-LPAR shared, and that becomes either per-thread or per-core depending on the flag.
Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
08d7cfd0 |
| 15-Jun-2023 |
BALATON Zoltan <balaton@eik.bme.hu> |
target/ppd: Remove unused define
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Phili
target/ppd: Remove unused define
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop the unused define as well.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
c32654af |
| 25-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Fix icount access for some hypervisor instructions
Several instructions and register access require icount reads and are missing translator_io_start().
Signed-off-by: Nicholas Piggin <n
target/ppc: Fix icount access for some hypervisor instructions
Several instructions and register access require icount reads and are missing translator_io_start().
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230625103700.8992-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
b25f2ffa |
| 25-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add TFMR SPR implementation with read and write helpers
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (ge
target/ppc: Add TFMR SPR implementation with read and write helpers
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS).
Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for now behaviour is unchanged.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
d24e80b2 |
| 22-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add msgsnd/p and DPDES SMT support
Doorbells in SMT need to coordinate msgsnd/msgclr and DPDES access from multiple threads that affect the same state.
Signed-off-by: Nicholas Piggin <n
target/ppc: Add msgsnd/p and DPDES SMT support
Doorbells in SMT need to coordinate msgsnd/msgclr and DPDES access from multiple threads that affect the same state.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
c5d98a7b |
| 22-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register where reads and writes need to synchronise against state changes by other threads
target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register where reads and writes need to synchronise against state changes by other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
b769d4c8 |
| 22-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add initial flags and helpers for SMT support
TGC SMT emulation needs to know whether it is running with SMT siblings, to be able to iterate over siblings in a core, and to serialise thr
target/ppc: Add initial flags and helpers for SMT support
TGC SMT emulation needs to know whether it is running with SMT siblings, to be able to iterate over siblings in a core, and to serialise threads to access per-core shared SPRs. Add infrastructure to do these things.
For now the sibling iteration and serialisation are implemented in a simple but inefficient way. SMT shared state and sibling access is not too common, and SMT configurations are mainly useful to test system code, so performance is not to critical.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: fix build breakage with clang ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
984eda58 |
| 21-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Fix sc instruction handling of LEV field
The top bits of the LEV field of the sc instruction are to be treated as as a reserved field rather than a reserved value, meaning LEV is effecti
target/ppc: Fix sc instruction handling of LEV field
The top bits of the LEV field of the sc instruction are to be treated as as a reserved field rather than a reserved value, meaning LEV is effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be a hypercall, for example.
This changes the instruction execution to just set lev from the low bit of the field. Processors which don't support the LEV field will continue to ignore it.
ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall instruction. TCG does not support Ultravisor, so don't worry about that bit.
Suggested-by: "Harsh Prateek Bora" <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
488aad11 |
| 20-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Better CTRL SPR implementation
The CTRL register is able to write the bit in the RUN field, which gets reflected into the TS field which is read-only and contains the state of the RUN fi
target/ppc: Better CTRL SPR implementation
The CTRL register is able to write the bit in the RUN field, which gets reflected into the TS field which is read-only and contains the state of the RUN field for all threads in the core.
TCG does not implement SMT, so the correct implementation just requires mirroring the RUN bit into the first bit of the TS field.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
21ee07e7 |
| 04-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Rework store conditional to avoid branch
Rework store conditional to avoid a branch in the success case. Change some of the variable names and layout while here so gen_conditional_store
target/ppc: Rework store conditional to avoid branch
Rework store conditional to avoid a branch in the success case. Change some of the variable names and layout while here so gen_conditional_store more closely matches gen_stqcx_.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230605025445.161932-4-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
2c901dca |
| 04-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Remove larx/stcx. memory barrier semantics
larx and stcx. are not defined to order any memory operations. Remove the barriers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.o
target/ppc: Remove larx/stcx. memory barrier semantics
larx and stcx. are not defined to order any memory operations. Remove the barriers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230605025445.161932-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|
#
392d328a |
| 04-Jun-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Ensure stcx size matches larx
Differently-sized larx/stcx. pairs can succeed if the starting address matches. Add a check to require the size of stcx. exactly match the larx that establi
target/ppc: Ensure stcx size matches larx
Differently-sized larx/stcx. pairs can succeed if the starting address matches. Add a check to require the size of stcx. exactly match the larx that established the reservation. Use the term "reserve_length" for this state, which matches the terminology used in the ISA.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20230605025445.161932-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
|