1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 static inline bool gen_serialize(DisasContext *ctx) 238 { 239 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240 /* Restart with exclusive lock. */ 241 gen_helper_exit_atomic(cpu_env); 242 ctx->base.is_jmp = DISAS_NORETURN; 243 return false; 244 } 245 return true; 246 } 247 248 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249 static inline bool gen_serialize_core(DisasContext *ctx) 250 { 251 if (ctx->flags & POWERPC_FLAG_SMT) { 252 return gen_serialize(ctx); 253 } 254 255 return true; 256 } 257 #endif 258 259 /* SPR load/store helpers */ 260 static inline void gen_load_spr(TCGv t, int reg) 261 { 262 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 263 } 264 265 static inline void gen_store_spr(int reg, TCGv t) 266 { 267 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 268 } 269 270 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271 { 272 if (ctx->need_access_type && ctx->access_type != access_type) { 273 tcg_gen_movi_i32(cpu_access_type, access_type); 274 ctx->access_type = access_type; 275 } 276 } 277 278 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279 { 280 if (NARROW_MODE(ctx)) { 281 nip = (uint32_t)nip; 282 } 283 tcg_gen_movi_tl(cpu_nip, nip); 284 } 285 286 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287 { 288 TCGv_i32 t0, t1; 289 290 /* 291 * These are all synchronous exceptions, we set the PC back to the 292 * faulting instruction 293 */ 294 gen_update_nip(ctx, ctx->cia); 295 t0 = tcg_constant_i32(excp); 296 t1 = tcg_constant_i32(error); 297 gen_helper_raise_exception_err(cpu_env, t0, t1); 298 ctx->base.is_jmp = DISAS_NORETURN; 299 } 300 301 static void gen_exception(DisasContext *ctx, uint32_t excp) 302 { 303 TCGv_i32 t0; 304 305 /* 306 * These are all synchronous exceptions, we set the PC back to the 307 * faulting instruction 308 */ 309 gen_update_nip(ctx, ctx->cia); 310 t0 = tcg_constant_i32(excp); 311 gen_helper_raise_exception(cpu_env, t0); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316 target_ulong nip) 317 { 318 TCGv_i32 t0; 319 320 gen_update_nip(ctx, nip); 321 t0 = tcg_constant_i32(excp); 322 gen_helper_raise_exception(cpu_env, t0); 323 ctx->base.is_jmp = DISAS_NORETURN; 324 } 325 326 #if !defined(CONFIG_USER_ONLY) 327 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 328 { 329 translator_io_start(&ctx->base); 330 gen_helper_ppc_maybe_interrupt(cpu_env); 331 } 332 #endif 333 334 /* 335 * Tells the caller what is the appropriate exception to generate and prepares 336 * SPR registers for this exception. 337 * 338 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339 * POWERPC_EXCP_DEBUG (on BookE). 340 */ 341 static uint32_t gen_prep_dbgex(DisasContext *ctx) 342 { 343 if (ctx->flags & POWERPC_FLAG_DE) { 344 target_ulong dbsr = 0; 345 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 346 dbsr = DBCR0_ICMP; 347 } else { 348 /* Must have been branch */ 349 dbsr = DBCR0_BRT; 350 } 351 TCGv t0 = tcg_temp_new(); 352 gen_load_spr(t0, SPR_BOOKE_DBSR); 353 tcg_gen_ori_tl(t0, t0, dbsr); 354 gen_store_spr(SPR_BOOKE_DBSR, t0); 355 return POWERPC_EXCP_DEBUG; 356 } else { 357 return POWERPC_EXCP_TRACE; 358 } 359 } 360 361 static void gen_debug_exception(DisasContext *ctx) 362 { 363 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 364 ctx->base.is_jmp = DISAS_NORETURN; 365 } 366 367 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368 { 369 /* Will be converted to program check if needed */ 370 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371 } 372 373 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374 { 375 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376 } 377 378 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379 { 380 /* Will be converted to program check if needed */ 381 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382 } 383 384 /*****************************************************************************/ 385 /* SPR READ/WRITE CALLBACKS */ 386 387 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 388 { 389 #if 0 390 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 391 printf("ERROR: try to access SPR %d !\n", sprn); 392 #endif 393 } 394 395 /* #define PPC_DUMP_SPR_ACCESSES */ 396 397 /* 398 * Generic callbacks: 399 * do nothing but store/retrieve spr value 400 */ 401 static void spr_load_dump_spr(int sprn) 402 { 403 #ifdef PPC_DUMP_SPR_ACCESSES 404 TCGv_i32 t0 = tcg_constant_i32(sprn); 405 gen_helper_load_dump_spr(cpu_env, t0); 406 #endif 407 } 408 409 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 410 { 411 gen_load_spr(cpu_gpr[gprn], sprn); 412 spr_load_dump_spr(sprn); 413 } 414 415 static void spr_store_dump_spr(int sprn) 416 { 417 #ifdef PPC_DUMP_SPR_ACCESSES 418 TCGv_i32 t0 = tcg_constant_i32(sprn); 419 gen_helper_store_dump_spr(cpu_env, t0); 420 #endif 421 } 422 423 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 424 { 425 gen_store_spr(sprn, cpu_gpr[gprn]); 426 spr_store_dump_spr(sprn); 427 } 428 429 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 430 { 431 #ifdef TARGET_PPC64 432 TCGv t0 = tcg_temp_new(); 433 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 434 gen_store_spr(sprn, t0); 435 spr_store_dump_spr(sprn); 436 #else 437 spr_write_generic(ctx, sprn, gprn); 438 #endif 439 } 440 441 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 442 { 443 /* This does not implement >1 thread */ 444 TCGv t0 = tcg_temp_new(); 445 TCGv t1 = tcg_temp_new(); 446 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448 tcg_gen_or_tl(t1, t1, t0); 449 gen_store_spr(sprn, t1); 450 spr_store_dump_spr(sprn); 451 452 /* 453 * SPR_CTRL writes must force a new translation block, 454 * allowing the PMU to calculate the run latch events with 455 * more accuracy. 456 */ 457 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 458 } 459 460 #if !defined(CONFIG_USER_ONLY) 461 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 462 { 463 TCGv t0 = tcg_temp_new(); 464 TCGv t1 = tcg_temp_new(); 465 gen_load_spr(t0, sprn); 466 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 467 tcg_gen_and_tl(t0, t0, t1); 468 gen_store_spr(sprn, t0); 469 } 470 471 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 472 { 473 } 474 475 #endif 476 477 /* SPR common to all PowerPC */ 478 /* XER */ 479 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 480 { 481 TCGv dst = cpu_gpr[gprn]; 482 TCGv t0 = tcg_temp_new(); 483 TCGv t1 = tcg_temp_new(); 484 TCGv t2 = tcg_temp_new(); 485 tcg_gen_mov_tl(dst, cpu_xer); 486 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 487 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 488 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 489 tcg_gen_or_tl(t0, t0, t1); 490 tcg_gen_or_tl(dst, dst, t2); 491 tcg_gen_or_tl(dst, dst, t0); 492 if (is_isa300(ctx)) { 493 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 494 tcg_gen_or_tl(dst, dst, t0); 495 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 496 tcg_gen_or_tl(dst, dst, t0); 497 } 498 } 499 500 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 501 { 502 TCGv src = cpu_gpr[gprn]; 503 /* Write all flags, while reading back check for isa300 */ 504 tcg_gen_andi_tl(cpu_xer, src, 505 ~((1u << XER_SO) | 506 (1u << XER_OV) | (1u << XER_OV32) | 507 (1u << XER_CA) | (1u << XER_CA32))); 508 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 509 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 510 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 511 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 512 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 513 } 514 515 /* LR */ 516 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 517 { 518 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 519 } 520 521 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 522 { 523 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 524 } 525 526 /* CFAR */ 527 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 528 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 529 { 530 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 531 } 532 533 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 534 { 535 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 536 } 537 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 538 539 /* CTR */ 540 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 541 { 542 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 543 } 544 545 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 546 { 547 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 548 } 549 550 /* User read access to SPR */ 551 /* USPRx */ 552 /* UMMCRx */ 553 /* UPMCx */ 554 /* USIA */ 555 /* UDECR */ 556 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 557 { 558 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 559 } 560 561 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 562 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 563 { 564 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 565 } 566 #endif 567 568 /* SPR common to all non-embedded PowerPC */ 569 /* DECR */ 570 #if !defined(CONFIG_USER_ONLY) 571 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 572 { 573 translator_io_start(&ctx->base); 574 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 575 } 576 577 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 578 { 579 translator_io_start(&ctx->base); 580 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 581 } 582 #endif 583 584 /* SPR common to all non-embedded PowerPC, except 601 */ 585 /* Time base */ 586 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 587 { 588 translator_io_start(&ctx->base); 589 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 590 } 591 592 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 593 { 594 translator_io_start(&ctx->base); 595 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 596 } 597 598 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 599 { 600 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 601 } 602 603 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 604 { 605 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 606 } 607 608 #if !defined(CONFIG_USER_ONLY) 609 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 610 { 611 translator_io_start(&ctx->base); 612 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 613 } 614 615 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 616 { 617 translator_io_start(&ctx->base); 618 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 619 } 620 621 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 622 { 623 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 624 } 625 626 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 627 { 628 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 629 } 630 631 #if defined(TARGET_PPC64) 632 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 633 { 634 translator_io_start(&ctx->base); 635 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 636 } 637 638 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 639 { 640 translator_io_start(&ctx->base); 641 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 642 } 643 644 /* HDECR */ 645 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 646 { 647 translator_io_start(&ctx->base); 648 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 649 } 650 651 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 652 { 653 translator_io_start(&ctx->base); 654 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 655 } 656 657 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 658 { 659 translator_io_start(&ctx->base); 660 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 661 } 662 663 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 664 { 665 translator_io_start(&ctx->base); 666 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 667 } 668 669 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 670 { 671 translator_io_start(&ctx->base); 672 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 673 } 674 675 #endif 676 #endif 677 678 #if !defined(CONFIG_USER_ONLY) 679 /* IBAT0U...IBAT0U */ 680 /* IBAT0L...IBAT7L */ 681 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 682 { 683 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 684 offsetof(CPUPPCState, 685 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 686 } 687 688 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 689 { 690 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 691 offsetof(CPUPPCState, 692 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 693 } 694 695 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 696 { 697 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 698 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 699 } 700 701 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 702 { 703 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 704 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 705 } 706 707 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 708 { 709 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 710 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 711 } 712 713 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 714 { 715 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 716 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 717 } 718 719 /* DBAT0U...DBAT7U */ 720 /* DBAT0L...DBAT7L */ 721 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 722 { 723 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 724 offsetof(CPUPPCState, 725 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 726 } 727 728 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 729 { 730 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 731 offsetof(CPUPPCState, 732 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 733 } 734 735 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 736 { 737 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 738 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 739 } 740 741 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 742 { 743 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 744 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 745 } 746 747 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 748 { 749 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 750 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 751 } 752 753 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 754 { 755 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 756 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 757 } 758 759 /* SDR1 */ 760 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 761 { 762 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 763 } 764 765 #if defined(TARGET_PPC64) 766 /* 64 bits PowerPC specific SPRs */ 767 /* PIDR */ 768 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 769 { 770 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 771 } 772 773 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 774 { 775 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 776 } 777 778 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 779 { 780 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 781 } 782 783 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 784 { 785 TCGv t0 = tcg_temp_new(); 786 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 787 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 788 } 789 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 790 { 791 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 792 } 793 794 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 795 { 796 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 797 } 798 799 /* DPDES */ 800 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 801 { 802 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 803 } 804 805 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 806 { 807 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 808 } 809 #endif 810 #endif 811 812 /* PowerPC 40x specific registers */ 813 #if !defined(CONFIG_USER_ONLY) 814 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 815 { 816 translator_io_start(&ctx->base); 817 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 818 } 819 820 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 821 { 822 translator_io_start(&ctx->base); 823 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 824 } 825 826 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 827 { 828 translator_io_start(&ctx->base); 829 gen_store_spr(sprn, cpu_gpr[gprn]); 830 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 831 /* We must stop translation as we may have rebooted */ 832 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 833 } 834 835 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 836 { 837 translator_io_start(&ctx->base); 838 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 839 } 840 841 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 842 { 843 translator_io_start(&ctx->base); 844 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 845 } 846 847 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 848 { 849 translator_io_start(&ctx->base); 850 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 851 } 852 853 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 854 { 855 TCGv t0 = tcg_temp_new(); 856 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 857 gen_helper_store_40x_pid(cpu_env, t0); 858 } 859 860 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 861 { 862 translator_io_start(&ctx->base); 863 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 864 } 865 866 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 867 { 868 translator_io_start(&ctx->base); 869 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 870 } 871 #endif 872 873 /* PIR */ 874 #if !defined(CONFIG_USER_ONLY) 875 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 876 { 877 TCGv t0 = tcg_temp_new(); 878 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 879 gen_store_spr(SPR_PIR, t0); 880 } 881 #endif 882 883 /* SPE specific registers */ 884 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 885 { 886 TCGv_i32 t0 = tcg_temp_new_i32(); 887 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 888 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 889 } 890 891 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 892 { 893 TCGv_i32 t0 = tcg_temp_new_i32(); 894 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 895 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 896 } 897 898 #if !defined(CONFIG_USER_ONLY) 899 /* Callback used to write the exception vector base */ 900 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 901 { 902 TCGv t0 = tcg_temp_new(); 903 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 904 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 905 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 906 gen_store_spr(sprn, t0); 907 } 908 909 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 910 { 911 int sprn_offs; 912 913 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 914 sprn_offs = sprn - SPR_BOOKE_IVOR0; 915 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 916 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 917 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 918 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 919 } else { 920 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 921 " vector 0x%03x\n", sprn); 922 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 923 return; 924 } 925 926 TCGv t0 = tcg_temp_new(); 927 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 928 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 929 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 930 gen_store_spr(sprn, t0); 931 } 932 #endif 933 934 #ifdef TARGET_PPC64 935 #ifndef CONFIG_USER_ONLY 936 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 937 { 938 TCGv t0 = tcg_temp_new(); 939 TCGv t1 = tcg_temp_new(); 940 TCGv t2 = tcg_temp_new(); 941 942 /* 943 * Note, the HV=1 PR=0 case is handled earlier by simply using 944 * spr_write_generic for HV mode in the SPR table 945 */ 946 947 /* Build insertion mask into t1 based on context */ 948 if (ctx->pr) { 949 gen_load_spr(t1, SPR_UAMOR); 950 } else { 951 gen_load_spr(t1, SPR_AMOR); 952 } 953 954 /* Mask new bits into t2 */ 955 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 956 957 /* Load AMR and clear new bits in t0 */ 958 gen_load_spr(t0, SPR_AMR); 959 tcg_gen_andc_tl(t0, t0, t1); 960 961 /* Or'in new bits and write it out */ 962 tcg_gen_or_tl(t0, t0, t2); 963 gen_store_spr(SPR_AMR, t0); 964 spr_store_dump_spr(SPR_AMR); 965 } 966 967 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 968 { 969 TCGv t0 = tcg_temp_new(); 970 TCGv t1 = tcg_temp_new(); 971 TCGv t2 = tcg_temp_new(); 972 973 /* 974 * Note, the HV=1 case is handled earlier by simply using 975 * spr_write_generic for HV mode in the SPR table 976 */ 977 978 /* Build insertion mask into t1 based on context */ 979 gen_load_spr(t1, SPR_AMOR); 980 981 /* Mask new bits into t2 */ 982 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 983 984 /* Load AMR and clear new bits in t0 */ 985 gen_load_spr(t0, SPR_UAMOR); 986 tcg_gen_andc_tl(t0, t0, t1); 987 988 /* Or'in new bits and write it out */ 989 tcg_gen_or_tl(t0, t0, t2); 990 gen_store_spr(SPR_UAMOR, t0); 991 spr_store_dump_spr(SPR_UAMOR); 992 } 993 994 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 995 { 996 TCGv t0 = tcg_temp_new(); 997 TCGv t1 = tcg_temp_new(); 998 TCGv t2 = tcg_temp_new(); 999 1000 /* 1001 * Note, the HV=1 case is handled earlier by simply using 1002 * spr_write_generic for HV mode in the SPR table 1003 */ 1004 1005 /* Build insertion mask into t1 based on context */ 1006 gen_load_spr(t1, SPR_AMOR); 1007 1008 /* Mask new bits into t2 */ 1009 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1010 1011 /* Load AMR and clear new bits in t0 */ 1012 gen_load_spr(t0, SPR_IAMR); 1013 tcg_gen_andc_tl(t0, t0, t1); 1014 1015 /* Or'in new bits and write it out */ 1016 tcg_gen_or_tl(t0, t0, t2); 1017 gen_store_spr(SPR_IAMR, t0); 1018 spr_store_dump_spr(SPR_IAMR); 1019 } 1020 #endif 1021 #endif 1022 1023 #ifndef CONFIG_USER_ONLY 1024 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1025 { 1026 gen_helper_fixup_thrm(cpu_env); 1027 gen_load_spr(cpu_gpr[gprn], sprn); 1028 spr_load_dump_spr(sprn); 1029 } 1030 #endif /* !CONFIG_USER_ONLY */ 1031 1032 #if !defined(CONFIG_USER_ONLY) 1033 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1034 { 1035 TCGv t0 = tcg_temp_new(); 1036 1037 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1038 gen_store_spr(sprn, t0); 1039 } 1040 1041 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1042 { 1043 TCGv t0 = tcg_temp_new(); 1044 1045 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1046 gen_store_spr(sprn, t0); 1047 } 1048 1049 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1050 { 1051 TCGv t0 = tcg_temp_new(); 1052 1053 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1054 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1055 gen_store_spr(sprn, t0); 1056 } 1057 1058 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1059 { 1060 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1061 } 1062 1063 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1064 { 1065 TCGv_i32 t0 = tcg_constant_i32(sprn); 1066 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1067 } 1068 1069 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1070 { 1071 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1072 } 1073 1074 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1075 { 1076 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1077 } 1078 1079 #endif 1080 1081 #if !defined(CONFIG_USER_ONLY) 1082 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1083 { 1084 TCGv val = tcg_temp_new(); 1085 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1086 gen_store_spr(SPR_BOOKE_MAS3, val); 1087 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1088 gen_store_spr(SPR_BOOKE_MAS7, val); 1089 } 1090 1091 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1092 { 1093 TCGv mas7 = tcg_temp_new(); 1094 TCGv mas3 = tcg_temp_new(); 1095 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1096 tcg_gen_shli_tl(mas7, mas7, 32); 1097 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1098 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1099 } 1100 1101 #endif 1102 1103 #ifdef TARGET_PPC64 1104 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1105 int bit, int sprn, int cause) 1106 { 1107 TCGv_i32 t1 = tcg_constant_i32(bit); 1108 TCGv_i32 t2 = tcg_constant_i32(sprn); 1109 TCGv_i32 t3 = tcg_constant_i32(cause); 1110 1111 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1112 } 1113 1114 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1115 int bit, int sprn, int cause) 1116 { 1117 TCGv_i32 t1 = tcg_constant_i32(bit); 1118 TCGv_i32 t2 = tcg_constant_i32(sprn); 1119 TCGv_i32 t3 = tcg_constant_i32(cause); 1120 1121 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1122 } 1123 1124 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1125 { 1126 TCGv spr_up = tcg_temp_new(); 1127 TCGv spr = tcg_temp_new(); 1128 1129 gen_load_spr(spr, sprn - 1); 1130 tcg_gen_shri_tl(spr_up, spr, 32); 1131 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1132 } 1133 1134 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1135 { 1136 TCGv spr = tcg_temp_new(); 1137 1138 gen_load_spr(spr, sprn - 1); 1139 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1140 gen_store_spr(sprn - 1, spr); 1141 } 1142 1143 #if !defined(CONFIG_USER_ONLY) 1144 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1145 { 1146 TCGv hmer = tcg_temp_new(); 1147 1148 gen_load_spr(hmer, sprn); 1149 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1150 gen_store_spr(sprn, hmer); 1151 spr_store_dump_spr(sprn); 1152 } 1153 1154 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1155 { 1156 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1157 } 1158 #endif /* !defined(CONFIG_USER_ONLY) */ 1159 1160 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1161 { 1162 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1163 spr_read_generic(ctx, gprn, sprn); 1164 } 1165 1166 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1167 { 1168 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1169 spr_write_generic(ctx, sprn, gprn); 1170 } 1171 1172 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1173 { 1174 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1175 spr_read_generic(ctx, gprn, sprn); 1176 } 1177 1178 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1179 { 1180 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1181 spr_write_generic(ctx, sprn, gprn); 1182 } 1183 1184 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1185 { 1186 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1187 spr_read_prev_upper32(ctx, gprn, sprn); 1188 } 1189 1190 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1191 { 1192 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1193 spr_write_prev_upper32(ctx, sprn, gprn); 1194 } 1195 1196 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1197 { 1198 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1199 spr_read_generic(ctx, gprn, sprn); 1200 } 1201 1202 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1203 { 1204 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1205 spr_write_generic(ctx, sprn, gprn); 1206 } 1207 1208 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1209 { 1210 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1211 spr_read_prev_upper32(ctx, gprn, sprn); 1212 } 1213 1214 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1215 { 1216 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1217 spr_write_prev_upper32(ctx, sprn, gprn); 1218 } 1219 1220 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1221 { 1222 TCGv t0 = tcg_temp_new(); 1223 1224 /* 1225 * Access to the (H)DEXCR in problem state is done using separated 1226 * SPR indexes which are 16 below the SPR indexes which have full 1227 * access to the (H)DEXCR in privileged state. Problem state can 1228 * only read bits 32:63, bits 0:31 return 0. 1229 * 1230 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1231 */ 1232 1233 gen_load_spr(t0, sprn + 16); 1234 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1235 } 1236 #endif 1237 1238 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1239 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1240 1241 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1242 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1243 1244 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1245 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1246 1247 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1248 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1249 1250 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1251 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1252 1253 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1254 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1255 1256 typedef struct opcode_t { 1257 unsigned char opc1, opc2, opc3, opc4; 1258 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1259 unsigned char pad[4]; 1260 #endif 1261 opc_handler_t handler; 1262 const char *oname; 1263 } opcode_t; 1264 1265 static void gen_priv_opc(DisasContext *ctx) 1266 { 1267 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1268 } 1269 1270 /* Helpers for priv. check */ 1271 #define GEN_PRIV(CTX) \ 1272 do { \ 1273 gen_priv_opc(CTX); return; \ 1274 } while (0) 1275 1276 #if defined(CONFIG_USER_ONLY) 1277 #define CHK_HV(CTX) GEN_PRIV(CTX) 1278 #define CHK_SV(CTX) GEN_PRIV(CTX) 1279 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1280 #else 1281 #define CHK_HV(CTX) \ 1282 do { \ 1283 if (unlikely(ctx->pr || !ctx->hv)) {\ 1284 GEN_PRIV(CTX); \ 1285 } \ 1286 } while (0) 1287 #define CHK_SV(CTX) \ 1288 do { \ 1289 if (unlikely(ctx->pr)) { \ 1290 GEN_PRIV(CTX); \ 1291 } \ 1292 } while (0) 1293 #define CHK_HVRM(CTX) \ 1294 do { \ 1295 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1296 GEN_PRIV(CTX); \ 1297 } \ 1298 } while (0) 1299 #endif 1300 1301 #define CHK_NONE(CTX) 1302 1303 /*****************************************************************************/ 1304 /* PowerPC instructions table */ 1305 1306 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1307 { \ 1308 .opc1 = op1, \ 1309 .opc2 = op2, \ 1310 .opc3 = op3, \ 1311 .opc4 = 0xff, \ 1312 .handler = { \ 1313 .inval1 = invl, \ 1314 .type = _typ, \ 1315 .type2 = _typ2, \ 1316 .handler = &gen_##name, \ 1317 }, \ 1318 .oname = stringify(name), \ 1319 } 1320 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1321 { \ 1322 .opc1 = op1, \ 1323 .opc2 = op2, \ 1324 .opc3 = op3, \ 1325 .opc4 = 0xff, \ 1326 .handler = { \ 1327 .inval1 = invl1, \ 1328 .inval2 = invl2, \ 1329 .type = _typ, \ 1330 .type2 = _typ2, \ 1331 .handler = &gen_##name, \ 1332 }, \ 1333 .oname = stringify(name), \ 1334 } 1335 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1336 { \ 1337 .opc1 = op1, \ 1338 .opc2 = op2, \ 1339 .opc3 = op3, \ 1340 .opc4 = 0xff, \ 1341 .handler = { \ 1342 .inval1 = invl, \ 1343 .type = _typ, \ 1344 .type2 = _typ2, \ 1345 .handler = &gen_##name, \ 1346 }, \ 1347 .oname = onam, \ 1348 } 1349 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1350 { \ 1351 .opc1 = op1, \ 1352 .opc2 = op2, \ 1353 .opc3 = op3, \ 1354 .opc4 = op4, \ 1355 .handler = { \ 1356 .inval1 = invl, \ 1357 .type = _typ, \ 1358 .type2 = _typ2, \ 1359 .handler = &gen_##name, \ 1360 }, \ 1361 .oname = stringify(name), \ 1362 } 1363 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1364 { \ 1365 .opc1 = op1, \ 1366 .opc2 = op2, \ 1367 .opc3 = op3, \ 1368 .opc4 = op4, \ 1369 .handler = { \ 1370 .inval1 = invl, \ 1371 .type = _typ, \ 1372 .type2 = _typ2, \ 1373 .handler = &gen_##name, \ 1374 }, \ 1375 .oname = onam, \ 1376 } 1377 1378 /* Invalid instruction */ 1379 static void gen_invalid(DisasContext *ctx) 1380 { 1381 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1382 } 1383 1384 static opc_handler_t invalid_handler = { 1385 .inval1 = 0xFFFFFFFF, 1386 .inval2 = 0xFFFFFFFF, 1387 .type = PPC_NONE, 1388 .type2 = PPC_NONE, 1389 .handler = gen_invalid, 1390 }; 1391 1392 /*** Integer comparison ***/ 1393 1394 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1395 { 1396 TCGv t0 = tcg_temp_new(); 1397 TCGv t1 = tcg_temp_new(); 1398 TCGv_i32 t = tcg_temp_new_i32(); 1399 1400 tcg_gen_movi_tl(t0, CRF_EQ); 1401 tcg_gen_movi_tl(t1, CRF_LT); 1402 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1403 t0, arg0, arg1, t1, t0); 1404 tcg_gen_movi_tl(t1, CRF_GT); 1405 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1406 t0, arg0, arg1, t1, t0); 1407 1408 tcg_gen_trunc_tl_i32(t, t0); 1409 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1410 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1411 } 1412 1413 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1414 { 1415 TCGv t0 = tcg_constant_tl(arg1); 1416 gen_op_cmp(arg0, t0, s, crf); 1417 } 1418 1419 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1420 { 1421 TCGv t0, t1; 1422 t0 = tcg_temp_new(); 1423 t1 = tcg_temp_new(); 1424 if (s) { 1425 tcg_gen_ext32s_tl(t0, arg0); 1426 tcg_gen_ext32s_tl(t1, arg1); 1427 } else { 1428 tcg_gen_ext32u_tl(t0, arg0); 1429 tcg_gen_ext32u_tl(t1, arg1); 1430 } 1431 gen_op_cmp(t0, t1, s, crf); 1432 } 1433 1434 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1435 { 1436 TCGv t0 = tcg_constant_tl(arg1); 1437 gen_op_cmp32(arg0, t0, s, crf); 1438 } 1439 1440 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1441 { 1442 if (NARROW_MODE(ctx)) { 1443 gen_op_cmpi32(reg, 0, 1, 0); 1444 } else { 1445 gen_op_cmpi(reg, 0, 1, 0); 1446 } 1447 } 1448 1449 /* cmprb - range comparison: isupper, isaplha, islower*/ 1450 static void gen_cmprb(DisasContext *ctx) 1451 { 1452 TCGv_i32 src1 = tcg_temp_new_i32(); 1453 TCGv_i32 src2 = tcg_temp_new_i32(); 1454 TCGv_i32 src2lo = tcg_temp_new_i32(); 1455 TCGv_i32 src2hi = tcg_temp_new_i32(); 1456 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1457 1458 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1459 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1460 1461 tcg_gen_andi_i32(src1, src1, 0xFF); 1462 tcg_gen_ext8u_i32(src2lo, src2); 1463 tcg_gen_shri_i32(src2, src2, 8); 1464 tcg_gen_ext8u_i32(src2hi, src2); 1465 1466 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1467 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1468 tcg_gen_and_i32(crf, src2lo, src2hi); 1469 1470 if (ctx->opcode & 0x00200000) { 1471 tcg_gen_shri_i32(src2, src2, 8); 1472 tcg_gen_ext8u_i32(src2lo, src2); 1473 tcg_gen_shri_i32(src2, src2, 8); 1474 tcg_gen_ext8u_i32(src2hi, src2); 1475 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1476 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1477 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1478 tcg_gen_or_i32(crf, crf, src2lo); 1479 } 1480 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1481 } 1482 1483 #if defined(TARGET_PPC64) 1484 /* cmpeqb */ 1485 static void gen_cmpeqb(DisasContext *ctx) 1486 { 1487 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488 cpu_gpr[rB(ctx->opcode)]); 1489 } 1490 #endif 1491 1492 /* isel (PowerPC 2.03 specification) */ 1493 static void gen_isel(DisasContext *ctx) 1494 { 1495 uint32_t bi = rC(ctx->opcode); 1496 uint32_t mask = 0x08 >> (bi & 0x03); 1497 TCGv t0 = tcg_temp_new(); 1498 TCGv zr; 1499 1500 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1501 tcg_gen_andi_tl(t0, t0, mask); 1502 1503 zr = tcg_constant_tl(0); 1504 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1505 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1506 cpu_gpr[rB(ctx->opcode)]); 1507 } 1508 1509 /* cmpb: PowerPC 2.05 specification */ 1510 static void gen_cmpb(DisasContext *ctx) 1511 { 1512 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1513 cpu_gpr[rB(ctx->opcode)]); 1514 } 1515 1516 /*** Integer arithmetic ***/ 1517 1518 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1519 TCGv arg1, TCGv arg2, int sub) 1520 { 1521 TCGv t0 = tcg_temp_new(); 1522 1523 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1524 tcg_gen_xor_tl(t0, arg1, arg2); 1525 if (sub) { 1526 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1527 } else { 1528 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1529 } 1530 if (NARROW_MODE(ctx)) { 1531 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1532 if (is_isa300(ctx)) { 1533 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1534 } 1535 } else { 1536 if (is_isa300(ctx)) { 1537 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1538 } 1539 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1540 } 1541 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1542 } 1543 1544 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1545 TCGv res, TCGv arg0, TCGv arg1, 1546 TCGv ca32, int sub) 1547 { 1548 TCGv t0; 1549 1550 if (!is_isa300(ctx)) { 1551 return; 1552 } 1553 1554 t0 = tcg_temp_new(); 1555 if (sub) { 1556 tcg_gen_eqv_tl(t0, arg0, arg1); 1557 } else { 1558 tcg_gen_xor_tl(t0, arg0, arg1); 1559 } 1560 tcg_gen_xor_tl(t0, t0, res); 1561 tcg_gen_extract_tl(ca32, t0, 32, 1); 1562 } 1563 1564 /* Common add function */ 1565 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1566 TCGv arg2, TCGv ca, TCGv ca32, 1567 bool add_ca, bool compute_ca, 1568 bool compute_ov, bool compute_rc0) 1569 { 1570 TCGv t0 = ret; 1571 1572 if (compute_ca || compute_ov) { 1573 t0 = tcg_temp_new(); 1574 } 1575 1576 if (compute_ca) { 1577 if (NARROW_MODE(ctx)) { 1578 /* 1579 * Caution: a non-obvious corner case of the spec is that 1580 * we must produce the *entire* 64-bit addition, but 1581 * produce the carry into bit 32. 1582 */ 1583 TCGv t1 = tcg_temp_new(); 1584 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1585 tcg_gen_add_tl(t0, arg1, arg2); 1586 if (add_ca) { 1587 tcg_gen_add_tl(t0, t0, ca); 1588 } 1589 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1590 tcg_gen_extract_tl(ca, ca, 32, 1); 1591 if (is_isa300(ctx)) { 1592 tcg_gen_mov_tl(ca32, ca); 1593 } 1594 } else { 1595 TCGv zero = tcg_constant_tl(0); 1596 if (add_ca) { 1597 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1598 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1599 } else { 1600 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1601 } 1602 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1603 } 1604 } else { 1605 tcg_gen_add_tl(t0, arg1, arg2); 1606 if (add_ca) { 1607 tcg_gen_add_tl(t0, t0, ca); 1608 } 1609 } 1610 1611 if (compute_ov) { 1612 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1613 } 1614 if (unlikely(compute_rc0)) { 1615 gen_set_Rc0(ctx, t0); 1616 } 1617 1618 if (t0 != ret) { 1619 tcg_gen_mov_tl(ret, t0); 1620 } 1621 } 1622 /* Add functions with two operands */ 1623 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1624 static void glue(gen_, name)(DisasContext *ctx) \ 1625 { \ 1626 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1627 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1628 ca, glue(ca, 32), \ 1629 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1630 } 1631 /* Add functions with one operand and one immediate */ 1632 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1633 add_ca, compute_ca, compute_ov) \ 1634 static void glue(gen_, name)(DisasContext *ctx) \ 1635 { \ 1636 TCGv t0 = tcg_constant_tl(const_val); \ 1637 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1638 cpu_gpr[rA(ctx->opcode)], t0, \ 1639 ca, glue(ca, 32), \ 1640 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1641 } 1642 1643 /* add add. addo addo. */ 1644 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1645 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1646 /* addc addc. addco addco. */ 1647 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1648 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1649 /* adde adde. addeo addeo. */ 1650 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1651 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1652 /* addme addme. addmeo addmeo. */ 1653 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1654 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1655 /* addex */ 1656 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1657 /* addze addze. addzeo addzeo.*/ 1658 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1659 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1660 /* addic addic.*/ 1661 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1662 { 1663 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1664 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1665 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1666 } 1667 1668 static void gen_addic(DisasContext *ctx) 1669 { 1670 gen_op_addic(ctx, 0); 1671 } 1672 1673 static void gen_addic_(DisasContext *ctx) 1674 { 1675 gen_op_addic(ctx, 1); 1676 } 1677 1678 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1679 TCGv arg2, int sign, int compute_ov) 1680 { 1681 TCGv_i32 t0 = tcg_temp_new_i32(); 1682 TCGv_i32 t1 = tcg_temp_new_i32(); 1683 TCGv_i32 t2 = tcg_temp_new_i32(); 1684 TCGv_i32 t3 = tcg_temp_new_i32(); 1685 1686 tcg_gen_trunc_tl_i32(t0, arg1); 1687 tcg_gen_trunc_tl_i32(t1, arg2); 1688 if (sign) { 1689 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1690 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1691 tcg_gen_and_i32(t2, t2, t3); 1692 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1693 tcg_gen_or_i32(t2, t2, t3); 1694 tcg_gen_movi_i32(t3, 0); 1695 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1696 tcg_gen_div_i32(t3, t0, t1); 1697 tcg_gen_extu_i32_tl(ret, t3); 1698 } else { 1699 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1700 tcg_gen_movi_i32(t3, 0); 1701 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1702 tcg_gen_divu_i32(t3, t0, t1); 1703 tcg_gen_extu_i32_tl(ret, t3); 1704 } 1705 if (compute_ov) { 1706 tcg_gen_extu_i32_tl(cpu_ov, t2); 1707 if (is_isa300(ctx)) { 1708 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1709 } 1710 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1711 } 1712 1713 if (unlikely(Rc(ctx->opcode) != 0)) { 1714 gen_set_Rc0(ctx, ret); 1715 } 1716 } 1717 /* Div functions */ 1718 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1719 static void glue(gen_, name)(DisasContext *ctx) \ 1720 { \ 1721 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1722 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1723 sign, compute_ov); \ 1724 } 1725 /* divwu divwu. divwuo divwuo. */ 1726 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1727 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1728 /* divw divw. divwo divwo. */ 1729 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1730 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1731 1732 /* div[wd]eu[o][.] */ 1733 #define GEN_DIVE(name, hlpr, compute_ov) \ 1734 static void gen_##name(DisasContext *ctx) \ 1735 { \ 1736 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1737 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1738 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1739 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1740 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1741 } \ 1742 } 1743 1744 GEN_DIVE(divweu, divweu, 0); 1745 GEN_DIVE(divweuo, divweu, 1); 1746 GEN_DIVE(divwe, divwe, 0); 1747 GEN_DIVE(divweo, divwe, 1); 1748 1749 #if defined(TARGET_PPC64) 1750 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1751 TCGv arg2, int sign, int compute_ov) 1752 { 1753 TCGv_i64 t0 = tcg_temp_new_i64(); 1754 TCGv_i64 t1 = tcg_temp_new_i64(); 1755 TCGv_i64 t2 = tcg_temp_new_i64(); 1756 TCGv_i64 t3 = tcg_temp_new_i64(); 1757 1758 tcg_gen_mov_i64(t0, arg1); 1759 tcg_gen_mov_i64(t1, arg2); 1760 if (sign) { 1761 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1762 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1763 tcg_gen_and_i64(t2, t2, t3); 1764 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1765 tcg_gen_or_i64(t2, t2, t3); 1766 tcg_gen_movi_i64(t3, 0); 1767 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1768 tcg_gen_div_i64(ret, t0, t1); 1769 } else { 1770 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1771 tcg_gen_movi_i64(t3, 0); 1772 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1773 tcg_gen_divu_i64(ret, t0, t1); 1774 } 1775 if (compute_ov) { 1776 tcg_gen_mov_tl(cpu_ov, t2); 1777 if (is_isa300(ctx)) { 1778 tcg_gen_mov_tl(cpu_ov32, t2); 1779 } 1780 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1781 } 1782 1783 if (unlikely(Rc(ctx->opcode) != 0)) { 1784 gen_set_Rc0(ctx, ret); 1785 } 1786 } 1787 1788 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1789 static void glue(gen_, name)(DisasContext *ctx) \ 1790 { \ 1791 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1792 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1793 sign, compute_ov); \ 1794 } 1795 /* divdu divdu. divduo divduo. */ 1796 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1797 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1798 /* divd divd. divdo divdo. */ 1799 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1800 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1801 1802 GEN_DIVE(divdeu, divdeu, 0); 1803 GEN_DIVE(divdeuo, divdeu, 1); 1804 GEN_DIVE(divde, divde, 0); 1805 GEN_DIVE(divdeo, divde, 1); 1806 #endif 1807 1808 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1809 TCGv arg2, int sign) 1810 { 1811 TCGv_i32 t0 = tcg_temp_new_i32(); 1812 TCGv_i32 t1 = tcg_temp_new_i32(); 1813 1814 tcg_gen_trunc_tl_i32(t0, arg1); 1815 tcg_gen_trunc_tl_i32(t1, arg2); 1816 if (sign) { 1817 TCGv_i32 t2 = tcg_temp_new_i32(); 1818 TCGv_i32 t3 = tcg_temp_new_i32(); 1819 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1820 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1821 tcg_gen_and_i32(t2, t2, t3); 1822 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1823 tcg_gen_or_i32(t2, t2, t3); 1824 tcg_gen_movi_i32(t3, 0); 1825 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1826 tcg_gen_rem_i32(t3, t0, t1); 1827 tcg_gen_ext_i32_tl(ret, t3); 1828 } else { 1829 TCGv_i32 t2 = tcg_constant_i32(1); 1830 TCGv_i32 t3 = tcg_constant_i32(0); 1831 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1832 tcg_gen_remu_i32(t0, t0, t1); 1833 tcg_gen_extu_i32_tl(ret, t0); 1834 } 1835 } 1836 1837 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1838 static void glue(gen_, name)(DisasContext *ctx) \ 1839 { \ 1840 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1841 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1842 sign); \ 1843 } 1844 1845 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1846 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1847 1848 #if defined(TARGET_PPC64) 1849 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1850 TCGv arg2, int sign) 1851 { 1852 TCGv_i64 t0 = tcg_temp_new_i64(); 1853 TCGv_i64 t1 = tcg_temp_new_i64(); 1854 1855 tcg_gen_mov_i64(t0, arg1); 1856 tcg_gen_mov_i64(t1, arg2); 1857 if (sign) { 1858 TCGv_i64 t2 = tcg_temp_new_i64(); 1859 TCGv_i64 t3 = tcg_temp_new_i64(); 1860 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1861 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1862 tcg_gen_and_i64(t2, t2, t3); 1863 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1864 tcg_gen_or_i64(t2, t2, t3); 1865 tcg_gen_movi_i64(t3, 0); 1866 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1867 tcg_gen_rem_i64(ret, t0, t1); 1868 } else { 1869 TCGv_i64 t2 = tcg_constant_i64(1); 1870 TCGv_i64 t3 = tcg_constant_i64(0); 1871 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1872 tcg_gen_remu_i64(ret, t0, t1); 1873 } 1874 } 1875 1876 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1877 static void glue(gen_, name)(DisasContext *ctx) \ 1878 { \ 1879 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1880 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1881 sign); \ 1882 } 1883 1884 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1885 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1886 #endif 1887 1888 /* mulhw mulhw. */ 1889 static void gen_mulhw(DisasContext *ctx) 1890 { 1891 TCGv_i32 t0 = tcg_temp_new_i32(); 1892 TCGv_i32 t1 = tcg_temp_new_i32(); 1893 1894 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1895 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1896 tcg_gen_muls2_i32(t0, t1, t0, t1); 1897 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1898 if (unlikely(Rc(ctx->opcode) != 0)) { 1899 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1900 } 1901 } 1902 1903 /* mulhwu mulhwu. */ 1904 static void gen_mulhwu(DisasContext *ctx) 1905 { 1906 TCGv_i32 t0 = tcg_temp_new_i32(); 1907 TCGv_i32 t1 = tcg_temp_new_i32(); 1908 1909 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1910 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1911 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1912 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1913 if (unlikely(Rc(ctx->opcode) != 0)) { 1914 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1915 } 1916 } 1917 1918 /* mullw mullw. */ 1919 static void gen_mullw(DisasContext *ctx) 1920 { 1921 #if defined(TARGET_PPC64) 1922 TCGv_i64 t0, t1; 1923 t0 = tcg_temp_new_i64(); 1924 t1 = tcg_temp_new_i64(); 1925 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1926 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1927 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1928 #else 1929 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1930 cpu_gpr[rB(ctx->opcode)]); 1931 #endif 1932 if (unlikely(Rc(ctx->opcode) != 0)) { 1933 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1934 } 1935 } 1936 1937 /* mullwo mullwo. */ 1938 static void gen_mullwo(DisasContext *ctx) 1939 { 1940 TCGv_i32 t0 = tcg_temp_new_i32(); 1941 TCGv_i32 t1 = tcg_temp_new_i32(); 1942 1943 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1944 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1945 tcg_gen_muls2_i32(t0, t1, t0, t1); 1946 #if defined(TARGET_PPC64) 1947 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1948 #else 1949 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1950 #endif 1951 1952 tcg_gen_sari_i32(t0, t0, 31); 1953 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1954 tcg_gen_extu_i32_tl(cpu_ov, t0); 1955 if (is_isa300(ctx)) { 1956 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1957 } 1958 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1959 1960 if (unlikely(Rc(ctx->opcode) != 0)) { 1961 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1962 } 1963 } 1964 1965 /* mulli */ 1966 static void gen_mulli(DisasContext *ctx) 1967 { 1968 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1969 SIMM(ctx->opcode)); 1970 } 1971 1972 #if defined(TARGET_PPC64) 1973 /* mulhd mulhd. */ 1974 static void gen_mulhd(DisasContext *ctx) 1975 { 1976 TCGv lo = tcg_temp_new(); 1977 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1979 if (unlikely(Rc(ctx->opcode) != 0)) { 1980 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1981 } 1982 } 1983 1984 /* mulhdu mulhdu. */ 1985 static void gen_mulhdu(DisasContext *ctx) 1986 { 1987 TCGv lo = tcg_temp_new(); 1988 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1989 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1990 if (unlikely(Rc(ctx->opcode) != 0)) { 1991 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1992 } 1993 } 1994 1995 /* mulld mulld. */ 1996 static void gen_mulld(DisasContext *ctx) 1997 { 1998 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1999 cpu_gpr[rB(ctx->opcode)]); 2000 if (unlikely(Rc(ctx->opcode) != 0)) { 2001 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2002 } 2003 } 2004 2005 /* mulldo mulldo. */ 2006 static void gen_mulldo(DisasContext *ctx) 2007 { 2008 TCGv_i64 t0 = tcg_temp_new_i64(); 2009 TCGv_i64 t1 = tcg_temp_new_i64(); 2010 2011 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2012 cpu_gpr[rB(ctx->opcode)]); 2013 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2014 2015 tcg_gen_sari_i64(t0, t0, 63); 2016 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2017 if (is_isa300(ctx)) { 2018 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2019 } 2020 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2021 2022 if (unlikely(Rc(ctx->opcode) != 0)) { 2023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2024 } 2025 } 2026 #endif 2027 2028 /* Common subf function */ 2029 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2030 TCGv arg2, bool add_ca, bool compute_ca, 2031 bool compute_ov, bool compute_rc0) 2032 { 2033 TCGv t0 = ret; 2034 2035 if (compute_ca || compute_ov) { 2036 t0 = tcg_temp_new(); 2037 } 2038 2039 if (compute_ca) { 2040 /* dest = ~arg1 + arg2 [+ ca]. */ 2041 if (NARROW_MODE(ctx)) { 2042 /* 2043 * Caution: a non-obvious corner case of the spec is that 2044 * we must produce the *entire* 64-bit addition, but 2045 * produce the carry into bit 32. 2046 */ 2047 TCGv inv1 = tcg_temp_new(); 2048 TCGv t1 = tcg_temp_new(); 2049 tcg_gen_not_tl(inv1, arg1); 2050 if (add_ca) { 2051 tcg_gen_add_tl(t0, arg2, cpu_ca); 2052 } else { 2053 tcg_gen_addi_tl(t0, arg2, 1); 2054 } 2055 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2056 tcg_gen_add_tl(t0, t0, inv1); 2057 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2058 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2059 if (is_isa300(ctx)) { 2060 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2061 } 2062 } else if (add_ca) { 2063 TCGv zero, inv1 = tcg_temp_new(); 2064 tcg_gen_not_tl(inv1, arg1); 2065 zero = tcg_constant_tl(0); 2066 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2067 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2068 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2069 } else { 2070 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2071 tcg_gen_sub_tl(t0, arg2, arg1); 2072 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2073 } 2074 } else if (add_ca) { 2075 /* 2076 * Since we're ignoring carry-out, we can simplify the 2077 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2078 */ 2079 tcg_gen_sub_tl(t0, arg2, arg1); 2080 tcg_gen_add_tl(t0, t0, cpu_ca); 2081 tcg_gen_subi_tl(t0, t0, 1); 2082 } else { 2083 tcg_gen_sub_tl(t0, arg2, arg1); 2084 } 2085 2086 if (compute_ov) { 2087 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2088 } 2089 if (unlikely(compute_rc0)) { 2090 gen_set_Rc0(ctx, t0); 2091 } 2092 2093 if (t0 != ret) { 2094 tcg_gen_mov_tl(ret, t0); 2095 } 2096 } 2097 /* Sub functions with Two operands functions */ 2098 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2099 static void glue(gen_, name)(DisasContext *ctx) \ 2100 { \ 2101 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2102 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2103 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2104 } 2105 /* Sub functions with one operand and one immediate */ 2106 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2107 add_ca, compute_ca, compute_ov) \ 2108 static void glue(gen_, name)(DisasContext *ctx) \ 2109 { \ 2110 TCGv t0 = tcg_constant_tl(const_val); \ 2111 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2112 cpu_gpr[rA(ctx->opcode)], t0, \ 2113 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2114 } 2115 /* subf subf. subfo subfo. */ 2116 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2117 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2118 /* subfc subfc. subfco subfco. */ 2119 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2120 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2121 /* subfe subfe. subfeo subfo. */ 2122 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2123 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2124 /* subfme subfme. subfmeo subfmeo. */ 2125 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2126 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2127 /* subfze subfze. subfzeo subfzeo.*/ 2128 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2129 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2130 2131 /* subfic */ 2132 static void gen_subfic(DisasContext *ctx) 2133 { 2134 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2135 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2136 c, 0, 1, 0, 0); 2137 } 2138 2139 /* neg neg. nego nego. */ 2140 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2141 { 2142 TCGv zero = tcg_constant_tl(0); 2143 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2144 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2145 } 2146 2147 static void gen_neg(DisasContext *ctx) 2148 { 2149 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2150 if (unlikely(Rc(ctx->opcode))) { 2151 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2152 } 2153 } 2154 2155 static void gen_nego(DisasContext *ctx) 2156 { 2157 gen_op_arith_neg(ctx, 1); 2158 } 2159 2160 /*** Integer logical ***/ 2161 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2162 static void glue(gen_, name)(DisasContext *ctx) \ 2163 { \ 2164 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2165 cpu_gpr[rB(ctx->opcode)]); \ 2166 if (unlikely(Rc(ctx->opcode) != 0)) \ 2167 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2168 } 2169 2170 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2171 static void glue(gen_, name)(DisasContext *ctx) \ 2172 { \ 2173 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2174 if (unlikely(Rc(ctx->opcode) != 0)) \ 2175 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2176 } 2177 2178 /* and & and. */ 2179 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2180 /* andc & andc. */ 2181 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2182 2183 /* andi. */ 2184 static void gen_andi_(DisasContext *ctx) 2185 { 2186 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2187 UIMM(ctx->opcode)); 2188 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2189 } 2190 2191 /* andis. */ 2192 static void gen_andis_(DisasContext *ctx) 2193 { 2194 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2195 UIMM(ctx->opcode) << 16); 2196 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2197 } 2198 2199 /* cntlzw */ 2200 static void gen_cntlzw(DisasContext *ctx) 2201 { 2202 TCGv_i32 t = tcg_temp_new_i32(); 2203 2204 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2205 tcg_gen_clzi_i32(t, t, 32); 2206 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2207 2208 if (unlikely(Rc(ctx->opcode) != 0)) { 2209 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2210 } 2211 } 2212 2213 /* cnttzw */ 2214 static void gen_cnttzw(DisasContext *ctx) 2215 { 2216 TCGv_i32 t = tcg_temp_new_i32(); 2217 2218 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2219 tcg_gen_ctzi_i32(t, t, 32); 2220 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2221 2222 if (unlikely(Rc(ctx->opcode) != 0)) { 2223 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2224 } 2225 } 2226 2227 /* eqv & eqv. */ 2228 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2229 /* extsb & extsb. */ 2230 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2231 /* extsh & extsh. */ 2232 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2233 /* nand & nand. */ 2234 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2235 /* nor & nor. */ 2236 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2237 2238 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2239 static void gen_pause(DisasContext *ctx) 2240 { 2241 TCGv_i32 t0 = tcg_constant_i32(0); 2242 tcg_gen_st_i32(t0, cpu_env, 2243 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2244 2245 /* Stop translation, this gives other CPUs a chance to run */ 2246 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2247 } 2248 #endif /* defined(TARGET_PPC64) */ 2249 2250 /* or & or. */ 2251 static void gen_or(DisasContext *ctx) 2252 { 2253 int rs, ra, rb; 2254 2255 rs = rS(ctx->opcode); 2256 ra = rA(ctx->opcode); 2257 rb = rB(ctx->opcode); 2258 /* Optimisation for mr. ri case */ 2259 if (rs != ra || rs != rb) { 2260 if (rs != rb) { 2261 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2262 } else { 2263 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2264 } 2265 if (unlikely(Rc(ctx->opcode) != 0)) { 2266 gen_set_Rc0(ctx, cpu_gpr[ra]); 2267 } 2268 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2269 gen_set_Rc0(ctx, cpu_gpr[rs]); 2270 #if defined(TARGET_PPC64) 2271 } else if (rs != 0) { /* 0 is nop */ 2272 int prio = 0; 2273 2274 switch (rs) { 2275 case 1: 2276 /* Set process priority to low */ 2277 prio = 2; 2278 break; 2279 case 6: 2280 /* Set process priority to medium-low */ 2281 prio = 3; 2282 break; 2283 case 2: 2284 /* Set process priority to normal */ 2285 prio = 4; 2286 break; 2287 #if !defined(CONFIG_USER_ONLY) 2288 case 31: 2289 if (!ctx->pr) { 2290 /* Set process priority to very low */ 2291 prio = 1; 2292 } 2293 break; 2294 case 5: 2295 if (!ctx->pr) { 2296 /* Set process priority to medium-hight */ 2297 prio = 5; 2298 } 2299 break; 2300 case 3: 2301 if (!ctx->pr) { 2302 /* Set process priority to high */ 2303 prio = 6; 2304 } 2305 break; 2306 case 7: 2307 if (ctx->hv && !ctx->pr) { 2308 /* Set process priority to very high */ 2309 prio = 7; 2310 } 2311 break; 2312 #endif 2313 default: 2314 break; 2315 } 2316 if (prio) { 2317 TCGv t0 = tcg_temp_new(); 2318 gen_load_spr(t0, SPR_PPR); 2319 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2320 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2321 gen_store_spr(SPR_PPR, t0); 2322 } 2323 #if !defined(CONFIG_USER_ONLY) 2324 /* 2325 * Pause out of TCG otherwise spin loops with smt_low eat too 2326 * much CPU and the kernel hangs. This applies to all 2327 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2328 * mdoio(29), mdoom(30), and all currently undefined. 2329 */ 2330 gen_pause(ctx); 2331 #endif 2332 #endif 2333 } 2334 } 2335 /* orc & orc. */ 2336 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2337 2338 /* xor & xor. */ 2339 static void gen_xor(DisasContext *ctx) 2340 { 2341 /* Optimisation for "set to zero" case */ 2342 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2343 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2344 cpu_gpr[rB(ctx->opcode)]); 2345 } else { 2346 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2347 } 2348 if (unlikely(Rc(ctx->opcode) != 0)) { 2349 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2350 } 2351 } 2352 2353 /* ori */ 2354 static void gen_ori(DisasContext *ctx) 2355 { 2356 target_ulong uimm = UIMM(ctx->opcode); 2357 2358 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2359 return; 2360 } 2361 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2362 } 2363 2364 /* oris */ 2365 static void gen_oris(DisasContext *ctx) 2366 { 2367 target_ulong uimm = UIMM(ctx->opcode); 2368 2369 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2370 /* NOP */ 2371 return; 2372 } 2373 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2374 uimm << 16); 2375 } 2376 2377 /* xori */ 2378 static void gen_xori(DisasContext *ctx) 2379 { 2380 target_ulong uimm = UIMM(ctx->opcode); 2381 2382 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2383 /* NOP */ 2384 return; 2385 } 2386 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2387 } 2388 2389 /* xoris */ 2390 static void gen_xoris(DisasContext *ctx) 2391 { 2392 target_ulong uimm = UIMM(ctx->opcode); 2393 2394 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2395 /* NOP */ 2396 return; 2397 } 2398 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2399 uimm << 16); 2400 } 2401 2402 /* popcntb : PowerPC 2.03 specification */ 2403 static void gen_popcntb(DisasContext *ctx) 2404 { 2405 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2406 } 2407 2408 static void gen_popcntw(DisasContext *ctx) 2409 { 2410 #if defined(TARGET_PPC64) 2411 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2412 #else 2413 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2414 #endif 2415 } 2416 2417 #if defined(TARGET_PPC64) 2418 /* popcntd: PowerPC 2.06 specification */ 2419 static void gen_popcntd(DisasContext *ctx) 2420 { 2421 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2422 } 2423 #endif 2424 2425 /* prtyw: PowerPC 2.05 specification */ 2426 static void gen_prtyw(DisasContext *ctx) 2427 { 2428 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2429 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2430 TCGv t0 = tcg_temp_new(); 2431 tcg_gen_shri_tl(t0, rs, 16); 2432 tcg_gen_xor_tl(ra, rs, t0); 2433 tcg_gen_shri_tl(t0, ra, 8); 2434 tcg_gen_xor_tl(ra, ra, t0); 2435 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2436 } 2437 2438 #if defined(TARGET_PPC64) 2439 /* prtyd: PowerPC 2.05 specification */ 2440 static void gen_prtyd(DisasContext *ctx) 2441 { 2442 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2443 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2444 TCGv t0 = tcg_temp_new(); 2445 tcg_gen_shri_tl(t0, rs, 32); 2446 tcg_gen_xor_tl(ra, rs, t0); 2447 tcg_gen_shri_tl(t0, ra, 16); 2448 tcg_gen_xor_tl(ra, ra, t0); 2449 tcg_gen_shri_tl(t0, ra, 8); 2450 tcg_gen_xor_tl(ra, ra, t0); 2451 tcg_gen_andi_tl(ra, ra, 1); 2452 } 2453 #endif 2454 2455 #if defined(TARGET_PPC64) 2456 /* bpermd */ 2457 static void gen_bpermd(DisasContext *ctx) 2458 { 2459 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2460 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2461 } 2462 #endif 2463 2464 #if defined(TARGET_PPC64) 2465 /* extsw & extsw. */ 2466 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2467 2468 /* cntlzd */ 2469 static void gen_cntlzd(DisasContext *ctx) 2470 { 2471 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2472 if (unlikely(Rc(ctx->opcode) != 0)) { 2473 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2474 } 2475 } 2476 2477 /* cnttzd */ 2478 static void gen_cnttzd(DisasContext *ctx) 2479 { 2480 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2481 if (unlikely(Rc(ctx->opcode) != 0)) { 2482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2483 } 2484 } 2485 2486 /* darn */ 2487 static void gen_darn(DisasContext *ctx) 2488 { 2489 int l = L(ctx->opcode); 2490 2491 if (l > 2) { 2492 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2493 } else { 2494 translator_io_start(&ctx->base); 2495 if (l == 0) { 2496 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2497 } else { 2498 /* Return 64-bit random for both CRN and RRN */ 2499 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2500 } 2501 } 2502 } 2503 #endif 2504 2505 /*** Integer rotate ***/ 2506 2507 /* rlwimi & rlwimi. */ 2508 static void gen_rlwimi(DisasContext *ctx) 2509 { 2510 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2511 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2512 uint32_t sh = SH(ctx->opcode); 2513 uint32_t mb = MB(ctx->opcode); 2514 uint32_t me = ME(ctx->opcode); 2515 2516 if (sh == (31 - me) && mb <= me) { 2517 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2518 } else { 2519 target_ulong mask; 2520 bool mask_in_32b = true; 2521 TCGv t1; 2522 2523 #if defined(TARGET_PPC64) 2524 mb += 32; 2525 me += 32; 2526 #endif 2527 mask = MASK(mb, me); 2528 2529 #if defined(TARGET_PPC64) 2530 if (mask > 0xffffffffu) { 2531 mask_in_32b = false; 2532 } 2533 #endif 2534 t1 = tcg_temp_new(); 2535 if (mask_in_32b) { 2536 TCGv_i32 t0 = tcg_temp_new_i32(); 2537 tcg_gen_trunc_tl_i32(t0, t_rs); 2538 tcg_gen_rotli_i32(t0, t0, sh); 2539 tcg_gen_extu_i32_tl(t1, t0); 2540 } else { 2541 #if defined(TARGET_PPC64) 2542 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2543 tcg_gen_rotli_i64(t1, t1, sh); 2544 #else 2545 g_assert_not_reached(); 2546 #endif 2547 } 2548 2549 tcg_gen_andi_tl(t1, t1, mask); 2550 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2551 tcg_gen_or_tl(t_ra, t_ra, t1); 2552 } 2553 if (unlikely(Rc(ctx->opcode) != 0)) { 2554 gen_set_Rc0(ctx, t_ra); 2555 } 2556 } 2557 2558 /* rlwinm & rlwinm. */ 2559 static void gen_rlwinm(DisasContext *ctx) 2560 { 2561 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2562 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2563 int sh = SH(ctx->opcode); 2564 int mb = MB(ctx->opcode); 2565 int me = ME(ctx->opcode); 2566 int len = me - mb + 1; 2567 int rsh = (32 - sh) & 31; 2568 2569 if (sh != 0 && len > 0 && me == (31 - sh)) { 2570 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2571 } else if (me == 31 && rsh + len <= 32) { 2572 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2573 } else { 2574 target_ulong mask; 2575 bool mask_in_32b = true; 2576 #if defined(TARGET_PPC64) 2577 mb += 32; 2578 me += 32; 2579 #endif 2580 mask = MASK(mb, me); 2581 #if defined(TARGET_PPC64) 2582 if (mask > 0xffffffffu) { 2583 mask_in_32b = false; 2584 } 2585 #endif 2586 if (mask_in_32b) { 2587 if (sh == 0) { 2588 tcg_gen_andi_tl(t_ra, t_rs, mask); 2589 } else { 2590 TCGv_i32 t0 = tcg_temp_new_i32(); 2591 tcg_gen_trunc_tl_i32(t0, t_rs); 2592 tcg_gen_rotli_i32(t0, t0, sh); 2593 tcg_gen_andi_i32(t0, t0, mask); 2594 tcg_gen_extu_i32_tl(t_ra, t0); 2595 } 2596 } else { 2597 #if defined(TARGET_PPC64) 2598 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2599 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2600 tcg_gen_andi_i64(t_ra, t_ra, mask); 2601 #else 2602 g_assert_not_reached(); 2603 #endif 2604 } 2605 } 2606 if (unlikely(Rc(ctx->opcode) != 0)) { 2607 gen_set_Rc0(ctx, t_ra); 2608 } 2609 } 2610 2611 /* rlwnm & rlwnm. */ 2612 static void gen_rlwnm(DisasContext *ctx) 2613 { 2614 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2615 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2616 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2617 uint32_t mb = MB(ctx->opcode); 2618 uint32_t me = ME(ctx->opcode); 2619 target_ulong mask; 2620 bool mask_in_32b = true; 2621 2622 #if defined(TARGET_PPC64) 2623 mb += 32; 2624 me += 32; 2625 #endif 2626 mask = MASK(mb, me); 2627 2628 #if defined(TARGET_PPC64) 2629 if (mask > 0xffffffffu) { 2630 mask_in_32b = false; 2631 } 2632 #endif 2633 if (mask_in_32b) { 2634 TCGv_i32 t0 = tcg_temp_new_i32(); 2635 TCGv_i32 t1 = tcg_temp_new_i32(); 2636 tcg_gen_trunc_tl_i32(t0, t_rb); 2637 tcg_gen_trunc_tl_i32(t1, t_rs); 2638 tcg_gen_andi_i32(t0, t0, 0x1f); 2639 tcg_gen_rotl_i32(t1, t1, t0); 2640 tcg_gen_extu_i32_tl(t_ra, t1); 2641 } else { 2642 #if defined(TARGET_PPC64) 2643 TCGv_i64 t0 = tcg_temp_new_i64(); 2644 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2645 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2646 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2647 #else 2648 g_assert_not_reached(); 2649 #endif 2650 } 2651 2652 tcg_gen_andi_tl(t_ra, t_ra, mask); 2653 2654 if (unlikely(Rc(ctx->opcode) != 0)) { 2655 gen_set_Rc0(ctx, t_ra); 2656 } 2657 } 2658 2659 #if defined(TARGET_PPC64) 2660 #define GEN_PPC64_R2(name, opc1, opc2) \ 2661 static void glue(gen_, name##0)(DisasContext *ctx) \ 2662 { \ 2663 gen_##name(ctx, 0); \ 2664 } \ 2665 \ 2666 static void glue(gen_, name##1)(DisasContext *ctx) \ 2667 { \ 2668 gen_##name(ctx, 1); \ 2669 } 2670 #define GEN_PPC64_R4(name, opc1, opc2) \ 2671 static void glue(gen_, name##0)(DisasContext *ctx) \ 2672 { \ 2673 gen_##name(ctx, 0, 0); \ 2674 } \ 2675 \ 2676 static void glue(gen_, name##1)(DisasContext *ctx) \ 2677 { \ 2678 gen_##name(ctx, 0, 1); \ 2679 } \ 2680 \ 2681 static void glue(gen_, name##2)(DisasContext *ctx) \ 2682 { \ 2683 gen_##name(ctx, 1, 0); \ 2684 } \ 2685 \ 2686 static void glue(gen_, name##3)(DisasContext *ctx) \ 2687 { \ 2688 gen_##name(ctx, 1, 1); \ 2689 } 2690 2691 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2692 { 2693 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2694 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2695 int len = me - mb + 1; 2696 int rsh = (64 - sh) & 63; 2697 2698 if (sh != 0 && len > 0 && me == (63 - sh)) { 2699 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2700 } else if (me == 63 && rsh + len <= 64) { 2701 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2702 } else { 2703 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2704 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2705 } 2706 if (unlikely(Rc(ctx->opcode) != 0)) { 2707 gen_set_Rc0(ctx, t_ra); 2708 } 2709 } 2710 2711 /* rldicl - rldicl. */ 2712 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2713 { 2714 uint32_t sh, mb; 2715 2716 sh = SH(ctx->opcode) | (shn << 5); 2717 mb = MB(ctx->opcode) | (mbn << 5); 2718 gen_rldinm(ctx, mb, 63, sh); 2719 } 2720 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2721 2722 /* rldicr - rldicr. */ 2723 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2724 { 2725 uint32_t sh, me; 2726 2727 sh = SH(ctx->opcode) | (shn << 5); 2728 me = MB(ctx->opcode) | (men << 5); 2729 gen_rldinm(ctx, 0, me, sh); 2730 } 2731 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2732 2733 /* rldic - rldic. */ 2734 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2735 { 2736 uint32_t sh, mb; 2737 2738 sh = SH(ctx->opcode) | (shn << 5); 2739 mb = MB(ctx->opcode) | (mbn << 5); 2740 gen_rldinm(ctx, mb, 63 - sh, sh); 2741 } 2742 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2743 2744 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2745 { 2746 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2747 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2748 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2749 TCGv t0; 2750 2751 t0 = tcg_temp_new(); 2752 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2753 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2754 2755 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2756 if (unlikely(Rc(ctx->opcode) != 0)) { 2757 gen_set_Rc0(ctx, t_ra); 2758 } 2759 } 2760 2761 /* rldcl - rldcl. */ 2762 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2763 { 2764 uint32_t mb; 2765 2766 mb = MB(ctx->opcode) | (mbn << 5); 2767 gen_rldnm(ctx, mb, 63); 2768 } 2769 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2770 2771 /* rldcr - rldcr. */ 2772 static inline void gen_rldcr(DisasContext *ctx, int men) 2773 { 2774 uint32_t me; 2775 2776 me = MB(ctx->opcode) | (men << 5); 2777 gen_rldnm(ctx, 0, me); 2778 } 2779 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2780 2781 /* rldimi - rldimi. */ 2782 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2783 { 2784 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2785 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2786 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2787 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2788 uint32_t me = 63 - sh; 2789 2790 if (mb <= me) { 2791 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2792 } else { 2793 target_ulong mask = MASK(mb, me); 2794 TCGv t1 = tcg_temp_new(); 2795 2796 tcg_gen_rotli_tl(t1, t_rs, sh); 2797 tcg_gen_andi_tl(t1, t1, mask); 2798 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2799 tcg_gen_or_tl(t_ra, t_ra, t1); 2800 } 2801 if (unlikely(Rc(ctx->opcode) != 0)) { 2802 gen_set_Rc0(ctx, t_ra); 2803 } 2804 } 2805 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2806 #endif 2807 2808 /*** Integer shift ***/ 2809 2810 /* slw & slw. */ 2811 static void gen_slw(DisasContext *ctx) 2812 { 2813 TCGv t0, t1; 2814 2815 t0 = tcg_temp_new(); 2816 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2817 #if defined(TARGET_PPC64) 2818 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2819 tcg_gen_sari_tl(t0, t0, 0x3f); 2820 #else 2821 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2822 tcg_gen_sari_tl(t0, t0, 0x1f); 2823 #endif 2824 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2825 t1 = tcg_temp_new(); 2826 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2827 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2828 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2829 if (unlikely(Rc(ctx->opcode) != 0)) { 2830 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2831 } 2832 } 2833 2834 /* sraw & sraw. */ 2835 static void gen_sraw(DisasContext *ctx) 2836 { 2837 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2838 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2839 if (unlikely(Rc(ctx->opcode) != 0)) { 2840 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2841 } 2842 } 2843 2844 /* srawi & srawi. */ 2845 static void gen_srawi(DisasContext *ctx) 2846 { 2847 int sh = SH(ctx->opcode); 2848 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2849 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2850 if (sh == 0) { 2851 tcg_gen_ext32s_tl(dst, src); 2852 tcg_gen_movi_tl(cpu_ca, 0); 2853 if (is_isa300(ctx)) { 2854 tcg_gen_movi_tl(cpu_ca32, 0); 2855 } 2856 } else { 2857 TCGv t0; 2858 tcg_gen_ext32s_tl(dst, src); 2859 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2860 t0 = tcg_temp_new(); 2861 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2862 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2863 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2864 if (is_isa300(ctx)) { 2865 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2866 } 2867 tcg_gen_sari_tl(dst, dst, sh); 2868 } 2869 if (unlikely(Rc(ctx->opcode) != 0)) { 2870 gen_set_Rc0(ctx, dst); 2871 } 2872 } 2873 2874 /* srw & srw. */ 2875 static void gen_srw(DisasContext *ctx) 2876 { 2877 TCGv t0, t1; 2878 2879 t0 = tcg_temp_new(); 2880 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2881 #if defined(TARGET_PPC64) 2882 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2883 tcg_gen_sari_tl(t0, t0, 0x3f); 2884 #else 2885 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2886 tcg_gen_sari_tl(t0, t0, 0x1f); 2887 #endif 2888 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2889 tcg_gen_ext32u_tl(t0, t0); 2890 t1 = tcg_temp_new(); 2891 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2892 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2893 if (unlikely(Rc(ctx->opcode) != 0)) { 2894 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2895 } 2896 } 2897 2898 #if defined(TARGET_PPC64) 2899 /* sld & sld. */ 2900 static void gen_sld(DisasContext *ctx) 2901 { 2902 TCGv t0, t1; 2903 2904 t0 = tcg_temp_new(); 2905 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2906 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2907 tcg_gen_sari_tl(t0, t0, 0x3f); 2908 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2909 t1 = tcg_temp_new(); 2910 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2911 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2912 if (unlikely(Rc(ctx->opcode) != 0)) { 2913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2914 } 2915 } 2916 2917 /* srad & srad. */ 2918 static void gen_srad(DisasContext *ctx) 2919 { 2920 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2921 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2922 if (unlikely(Rc(ctx->opcode) != 0)) { 2923 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2924 } 2925 } 2926 /* sradi & sradi. */ 2927 static inline void gen_sradi(DisasContext *ctx, int n) 2928 { 2929 int sh = SH(ctx->opcode) + (n << 5); 2930 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2931 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2932 if (sh == 0) { 2933 tcg_gen_mov_tl(dst, src); 2934 tcg_gen_movi_tl(cpu_ca, 0); 2935 if (is_isa300(ctx)) { 2936 tcg_gen_movi_tl(cpu_ca32, 0); 2937 } 2938 } else { 2939 TCGv t0; 2940 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2941 t0 = tcg_temp_new(); 2942 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2943 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2944 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2945 if (is_isa300(ctx)) { 2946 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2947 } 2948 tcg_gen_sari_tl(dst, src, sh); 2949 } 2950 if (unlikely(Rc(ctx->opcode) != 0)) { 2951 gen_set_Rc0(ctx, dst); 2952 } 2953 } 2954 2955 static void gen_sradi0(DisasContext *ctx) 2956 { 2957 gen_sradi(ctx, 0); 2958 } 2959 2960 static void gen_sradi1(DisasContext *ctx) 2961 { 2962 gen_sradi(ctx, 1); 2963 } 2964 2965 /* extswsli & extswsli. */ 2966 static inline void gen_extswsli(DisasContext *ctx, int n) 2967 { 2968 int sh = SH(ctx->opcode) + (n << 5); 2969 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2970 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2971 2972 tcg_gen_ext32s_tl(dst, src); 2973 tcg_gen_shli_tl(dst, dst, sh); 2974 if (unlikely(Rc(ctx->opcode) != 0)) { 2975 gen_set_Rc0(ctx, dst); 2976 } 2977 } 2978 2979 static void gen_extswsli0(DisasContext *ctx) 2980 { 2981 gen_extswsli(ctx, 0); 2982 } 2983 2984 static void gen_extswsli1(DisasContext *ctx) 2985 { 2986 gen_extswsli(ctx, 1); 2987 } 2988 2989 /* srd & srd. */ 2990 static void gen_srd(DisasContext *ctx) 2991 { 2992 TCGv t0, t1; 2993 2994 t0 = tcg_temp_new(); 2995 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2996 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2997 tcg_gen_sari_tl(t0, t0, 0x3f); 2998 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2999 t1 = tcg_temp_new(); 3000 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3001 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3002 if (unlikely(Rc(ctx->opcode) != 0)) { 3003 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3004 } 3005 } 3006 #endif 3007 3008 /*** Addressing modes ***/ 3009 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3010 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3011 target_long maskl) 3012 { 3013 target_long simm = SIMM(ctx->opcode); 3014 3015 simm &= ~maskl; 3016 if (rA(ctx->opcode) == 0) { 3017 if (NARROW_MODE(ctx)) { 3018 simm = (uint32_t)simm; 3019 } 3020 tcg_gen_movi_tl(EA, simm); 3021 } else if (likely(simm != 0)) { 3022 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3023 if (NARROW_MODE(ctx)) { 3024 tcg_gen_ext32u_tl(EA, EA); 3025 } 3026 } else { 3027 if (NARROW_MODE(ctx)) { 3028 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3029 } else { 3030 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3031 } 3032 } 3033 } 3034 3035 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3036 { 3037 if (rA(ctx->opcode) == 0) { 3038 if (NARROW_MODE(ctx)) { 3039 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3040 } else { 3041 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3042 } 3043 } else { 3044 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3045 if (NARROW_MODE(ctx)) { 3046 tcg_gen_ext32u_tl(EA, EA); 3047 } 3048 } 3049 } 3050 3051 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3052 { 3053 if (rA(ctx->opcode) == 0) { 3054 tcg_gen_movi_tl(EA, 0); 3055 } else if (NARROW_MODE(ctx)) { 3056 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3057 } else { 3058 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3059 } 3060 } 3061 3062 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3063 target_long val) 3064 { 3065 tcg_gen_addi_tl(ret, arg1, val); 3066 if (NARROW_MODE(ctx)) { 3067 tcg_gen_ext32u_tl(ret, ret); 3068 } 3069 } 3070 3071 static inline void gen_align_no_le(DisasContext *ctx) 3072 { 3073 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3074 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3075 } 3076 3077 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3078 { 3079 TCGv ea = tcg_temp_new(); 3080 if (ra) { 3081 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3082 } else { 3083 tcg_gen_mov_tl(ea, displ); 3084 } 3085 if (NARROW_MODE(ctx)) { 3086 tcg_gen_ext32u_tl(ea, ea); 3087 } 3088 return ea; 3089 } 3090 3091 /*** Integer load ***/ 3092 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3093 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3094 3095 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3096 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3097 TCGv val, \ 3098 TCGv addr) \ 3099 { \ 3100 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3101 } 3102 3103 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3104 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3105 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3106 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3107 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3108 3109 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3110 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3111 3112 #define GEN_QEMU_LOAD_64(ldop, op) \ 3113 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3114 TCGv_i64 val, \ 3115 TCGv addr) \ 3116 { \ 3117 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3118 } 3119 3120 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3121 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3122 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3123 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3124 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3125 3126 #if defined(TARGET_PPC64) 3127 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3128 #endif 3129 3130 #define GEN_QEMU_STORE_TL(stop, op) \ 3131 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3132 TCGv val, \ 3133 TCGv addr) \ 3134 { \ 3135 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3136 } 3137 3138 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3139 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3140 #endif 3141 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3142 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3143 3144 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3145 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3146 3147 #define GEN_QEMU_STORE_64(stop, op) \ 3148 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3149 TCGv_i64 val, \ 3150 TCGv addr) \ 3151 { \ 3152 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3153 } 3154 3155 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3156 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3157 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3158 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3159 3160 #if defined(TARGET_PPC64) 3161 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3162 #endif 3163 3164 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3165 static void glue(gen_, name##x)(DisasContext *ctx) \ 3166 { \ 3167 TCGv EA; \ 3168 chk(ctx); \ 3169 gen_set_access_type(ctx, ACCESS_INT); \ 3170 EA = tcg_temp_new(); \ 3171 gen_addr_reg_index(ctx, EA); \ 3172 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3173 } 3174 3175 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3176 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3177 3178 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3179 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3180 3181 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3182 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3183 { \ 3184 TCGv EA; \ 3185 CHK_SV(ctx); \ 3186 gen_set_access_type(ctx, ACCESS_INT); \ 3187 EA = tcg_temp_new(); \ 3188 gen_addr_reg_index(ctx, EA); \ 3189 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3190 } 3191 3192 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3193 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3194 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3195 #if defined(TARGET_PPC64) 3196 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3197 #endif 3198 3199 #if defined(TARGET_PPC64) 3200 /* CI load/store variants */ 3201 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3202 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3203 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3204 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3205 #endif 3206 3207 /*** Integer store ***/ 3208 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3209 static void glue(gen_, name##x)(DisasContext *ctx) \ 3210 { \ 3211 TCGv EA; \ 3212 chk(ctx); \ 3213 gen_set_access_type(ctx, ACCESS_INT); \ 3214 EA = tcg_temp_new(); \ 3215 gen_addr_reg_index(ctx, EA); \ 3216 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3217 } 3218 #define GEN_STX(name, stop, opc2, opc3, type) \ 3219 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3220 3221 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3222 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3223 3224 #define GEN_STEPX(name, stop, opc2, opc3) \ 3225 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3226 { \ 3227 TCGv EA; \ 3228 CHK_SV(ctx); \ 3229 gen_set_access_type(ctx, ACCESS_INT); \ 3230 EA = tcg_temp_new(); \ 3231 gen_addr_reg_index(ctx, EA); \ 3232 tcg_gen_qemu_st_tl( \ 3233 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3234 } 3235 3236 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3237 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3238 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3239 #if defined(TARGET_PPC64) 3240 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3241 #endif 3242 3243 #if defined(TARGET_PPC64) 3244 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3245 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3246 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3247 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3248 #endif 3249 /*** Integer load and store with byte reverse ***/ 3250 3251 /* lhbrx */ 3252 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3253 3254 /* lwbrx */ 3255 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3256 3257 #if defined(TARGET_PPC64) 3258 /* ldbrx */ 3259 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3260 /* stdbrx */ 3261 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3262 #endif /* TARGET_PPC64 */ 3263 3264 /* sthbrx */ 3265 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3266 /* stwbrx */ 3267 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3268 3269 /*** Integer load and store multiple ***/ 3270 3271 /* lmw */ 3272 static void gen_lmw(DisasContext *ctx) 3273 { 3274 TCGv t0; 3275 TCGv_i32 t1; 3276 3277 if (ctx->le_mode) { 3278 gen_align_no_le(ctx); 3279 return; 3280 } 3281 gen_set_access_type(ctx, ACCESS_INT); 3282 t0 = tcg_temp_new(); 3283 t1 = tcg_constant_i32(rD(ctx->opcode)); 3284 gen_addr_imm_index(ctx, t0, 0); 3285 gen_helper_lmw(cpu_env, t0, t1); 3286 } 3287 3288 /* stmw */ 3289 static void gen_stmw(DisasContext *ctx) 3290 { 3291 TCGv t0; 3292 TCGv_i32 t1; 3293 3294 if (ctx->le_mode) { 3295 gen_align_no_le(ctx); 3296 return; 3297 } 3298 gen_set_access_type(ctx, ACCESS_INT); 3299 t0 = tcg_temp_new(); 3300 t1 = tcg_constant_i32(rS(ctx->opcode)); 3301 gen_addr_imm_index(ctx, t0, 0); 3302 gen_helper_stmw(cpu_env, t0, t1); 3303 } 3304 3305 /*** Integer load and store strings ***/ 3306 3307 /* lswi */ 3308 /* 3309 * PowerPC32 specification says we must generate an exception if rA is 3310 * in the range of registers to be loaded. In an other hand, IBM says 3311 * this is valid, but rA won't be loaded. For now, I'll follow the 3312 * spec... 3313 */ 3314 static void gen_lswi(DisasContext *ctx) 3315 { 3316 TCGv t0; 3317 TCGv_i32 t1, t2; 3318 int nb = NB(ctx->opcode); 3319 int start = rD(ctx->opcode); 3320 int ra = rA(ctx->opcode); 3321 int nr; 3322 3323 if (ctx->le_mode) { 3324 gen_align_no_le(ctx); 3325 return; 3326 } 3327 if (nb == 0) { 3328 nb = 32; 3329 } 3330 nr = DIV_ROUND_UP(nb, 4); 3331 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3332 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3333 return; 3334 } 3335 gen_set_access_type(ctx, ACCESS_INT); 3336 t0 = tcg_temp_new(); 3337 gen_addr_register(ctx, t0); 3338 t1 = tcg_constant_i32(nb); 3339 t2 = tcg_constant_i32(start); 3340 gen_helper_lsw(cpu_env, t0, t1, t2); 3341 } 3342 3343 /* lswx */ 3344 static void gen_lswx(DisasContext *ctx) 3345 { 3346 TCGv t0; 3347 TCGv_i32 t1, t2, t3; 3348 3349 if (ctx->le_mode) { 3350 gen_align_no_le(ctx); 3351 return; 3352 } 3353 gen_set_access_type(ctx, ACCESS_INT); 3354 t0 = tcg_temp_new(); 3355 gen_addr_reg_index(ctx, t0); 3356 t1 = tcg_constant_i32(rD(ctx->opcode)); 3357 t2 = tcg_constant_i32(rA(ctx->opcode)); 3358 t3 = tcg_constant_i32(rB(ctx->opcode)); 3359 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3360 } 3361 3362 /* stswi */ 3363 static void gen_stswi(DisasContext *ctx) 3364 { 3365 TCGv t0; 3366 TCGv_i32 t1, t2; 3367 int nb = NB(ctx->opcode); 3368 3369 if (ctx->le_mode) { 3370 gen_align_no_le(ctx); 3371 return; 3372 } 3373 gen_set_access_type(ctx, ACCESS_INT); 3374 t0 = tcg_temp_new(); 3375 gen_addr_register(ctx, t0); 3376 if (nb == 0) { 3377 nb = 32; 3378 } 3379 t1 = tcg_constant_i32(nb); 3380 t2 = tcg_constant_i32(rS(ctx->opcode)); 3381 gen_helper_stsw(cpu_env, t0, t1, t2); 3382 } 3383 3384 /* stswx */ 3385 static void gen_stswx(DisasContext *ctx) 3386 { 3387 TCGv t0; 3388 TCGv_i32 t1, t2; 3389 3390 if (ctx->le_mode) { 3391 gen_align_no_le(ctx); 3392 return; 3393 } 3394 gen_set_access_type(ctx, ACCESS_INT); 3395 t0 = tcg_temp_new(); 3396 gen_addr_reg_index(ctx, t0); 3397 t1 = tcg_temp_new_i32(); 3398 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3399 tcg_gen_andi_i32(t1, t1, 0x7F); 3400 t2 = tcg_constant_i32(rS(ctx->opcode)); 3401 gen_helper_stsw(cpu_env, t0, t1, t2); 3402 } 3403 3404 /*** Memory synchronisation ***/ 3405 /* eieio */ 3406 static void gen_eieio(DisasContext *ctx) 3407 { 3408 TCGBar bar = TCG_MO_ALL; 3409 3410 /* 3411 * eieio has complex semanitcs. It provides memory ordering between 3412 * operations in the set: 3413 * - loads from CI memory. 3414 * - stores to CI memory. 3415 * - stores to WT memory. 3416 * 3417 * It separately also orders memory for operations in the set: 3418 * - stores to cacheble memory. 3419 * 3420 * It also serializes instructions: 3421 * - dcbt and dcbst. 3422 * 3423 * It separately serializes: 3424 * - tlbie and tlbsync. 3425 * 3426 * And separately serializes: 3427 * - slbieg, slbiag, and slbsync. 3428 * 3429 * The end result is that CI memory ordering requires TCG_MO_ALL 3430 * and it is not possible to special-case more relaxed ordering for 3431 * cacheable accesses. TCG_BAR_SC is required to provide this 3432 * serialization. 3433 */ 3434 3435 /* 3436 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3437 * tell the CPU it is a store-forwarding barrier. 3438 */ 3439 if (ctx->opcode & 0x2000000) { 3440 /* 3441 * ISA says that "Reserved fields in instructions are ignored 3442 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3443 * as this is not an instruction software should be using, 3444 * complain to the user. 3445 */ 3446 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3447 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3448 TARGET_FMT_lx "\n", ctx->cia); 3449 } else { 3450 bar = TCG_MO_ST_LD; 3451 } 3452 } 3453 3454 tcg_gen_mb(bar | TCG_BAR_SC); 3455 } 3456 3457 #if !defined(CONFIG_USER_ONLY) 3458 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3459 { 3460 TCGv_i32 t; 3461 TCGLabel *l; 3462 3463 if (!ctx->lazy_tlb_flush) { 3464 return; 3465 } 3466 l = gen_new_label(); 3467 t = tcg_temp_new_i32(); 3468 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3469 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3470 if (global) { 3471 gen_helper_check_tlb_flush_global(cpu_env); 3472 } else { 3473 gen_helper_check_tlb_flush_local(cpu_env); 3474 } 3475 gen_set_label(l); 3476 } 3477 #else 3478 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3479 #endif 3480 3481 /* isync */ 3482 static void gen_isync(DisasContext *ctx) 3483 { 3484 /* 3485 * We need to check for a pending TLB flush. This can only happen in 3486 * kernel mode however so check MSR_PR 3487 */ 3488 if (!ctx->pr) { 3489 gen_check_tlb_flush(ctx, false); 3490 } 3491 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3492 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3493 } 3494 3495 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3496 3497 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3498 { 3499 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3500 TCGv t0 = tcg_temp_new(); 3501 3502 gen_set_access_type(ctx, ACCESS_RES); 3503 gen_addr_reg_index(ctx, t0); 3504 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3505 tcg_gen_mov_tl(cpu_reserve, t0); 3506 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3507 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3508 } 3509 3510 #define LARX(name, memop) \ 3511 static void gen_##name(DisasContext *ctx) \ 3512 { \ 3513 gen_load_locked(ctx, memop); \ 3514 } 3515 3516 /* lwarx */ 3517 LARX(lbarx, DEF_MEMOP(MO_UB)) 3518 LARX(lharx, DEF_MEMOP(MO_UW)) 3519 LARX(lwarx, DEF_MEMOP(MO_UL)) 3520 3521 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3522 TCGv EA, TCGCond cond, int addend) 3523 { 3524 TCGv t = tcg_temp_new(); 3525 TCGv t2 = tcg_temp_new(); 3526 TCGv u = tcg_temp_new(); 3527 3528 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3529 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3530 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3531 tcg_gen_addi_tl(u, t, addend); 3532 3533 /* E.g. for fetch and increment bounded... */ 3534 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3535 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3536 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3537 3538 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3539 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3540 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3541 } 3542 3543 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3544 { 3545 uint32_t gpr_FC = FC(ctx->opcode); 3546 TCGv EA = tcg_temp_new(); 3547 int rt = rD(ctx->opcode); 3548 bool need_serial; 3549 TCGv src, dst; 3550 3551 gen_addr_register(ctx, EA); 3552 dst = cpu_gpr[rt]; 3553 src = cpu_gpr[(rt + 1) & 31]; 3554 3555 need_serial = false; 3556 memop |= MO_ALIGN; 3557 switch (gpr_FC) { 3558 case 0: /* Fetch and add */ 3559 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3560 break; 3561 case 1: /* Fetch and xor */ 3562 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3563 break; 3564 case 2: /* Fetch and or */ 3565 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3566 break; 3567 case 3: /* Fetch and 'and' */ 3568 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3569 break; 3570 case 4: /* Fetch and max unsigned */ 3571 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3572 break; 3573 case 5: /* Fetch and max signed */ 3574 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3575 break; 3576 case 6: /* Fetch and min unsigned */ 3577 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3578 break; 3579 case 7: /* Fetch and min signed */ 3580 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3581 break; 3582 case 8: /* Swap */ 3583 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3584 break; 3585 3586 case 16: /* Compare and swap not equal */ 3587 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3588 need_serial = true; 3589 } else { 3590 TCGv t0 = tcg_temp_new(); 3591 TCGv t1 = tcg_temp_new(); 3592 3593 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3594 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3595 tcg_gen_mov_tl(t1, src); 3596 } else { 3597 tcg_gen_ext32u_tl(t1, src); 3598 } 3599 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3600 cpu_gpr[(rt + 2) & 31], t0); 3601 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3602 tcg_gen_mov_tl(dst, t0); 3603 } 3604 break; 3605 3606 case 24: /* Fetch and increment bounded */ 3607 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3608 need_serial = true; 3609 } else { 3610 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3611 } 3612 break; 3613 case 25: /* Fetch and increment equal */ 3614 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3615 need_serial = true; 3616 } else { 3617 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3618 } 3619 break; 3620 case 28: /* Fetch and decrement bounded */ 3621 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3622 need_serial = true; 3623 } else { 3624 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3625 } 3626 break; 3627 3628 default: 3629 /* invoke data storage error handler */ 3630 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3631 } 3632 3633 if (need_serial) { 3634 /* Restart with exclusive lock. */ 3635 gen_helper_exit_atomic(cpu_env); 3636 ctx->base.is_jmp = DISAS_NORETURN; 3637 } 3638 } 3639 3640 static void gen_lwat(DisasContext *ctx) 3641 { 3642 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3643 } 3644 3645 #ifdef TARGET_PPC64 3646 static void gen_ldat(DisasContext *ctx) 3647 { 3648 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3649 } 3650 #endif 3651 3652 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3653 { 3654 uint32_t gpr_FC = FC(ctx->opcode); 3655 TCGv EA = tcg_temp_new(); 3656 TCGv src, discard; 3657 3658 gen_addr_register(ctx, EA); 3659 src = cpu_gpr[rD(ctx->opcode)]; 3660 discard = tcg_temp_new(); 3661 3662 memop |= MO_ALIGN; 3663 switch (gpr_FC) { 3664 case 0: /* add and Store */ 3665 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3666 break; 3667 case 1: /* xor and Store */ 3668 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3669 break; 3670 case 2: /* Or and Store */ 3671 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3672 break; 3673 case 3: /* 'and' and Store */ 3674 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3675 break; 3676 case 4: /* Store max unsigned */ 3677 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3678 break; 3679 case 5: /* Store max signed */ 3680 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3681 break; 3682 case 6: /* Store min unsigned */ 3683 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3684 break; 3685 case 7: /* Store min signed */ 3686 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3687 break; 3688 case 24: /* Store twin */ 3689 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3690 /* Restart with exclusive lock. */ 3691 gen_helper_exit_atomic(cpu_env); 3692 ctx->base.is_jmp = DISAS_NORETURN; 3693 } else { 3694 TCGv t = tcg_temp_new(); 3695 TCGv t2 = tcg_temp_new(); 3696 TCGv s = tcg_temp_new(); 3697 TCGv s2 = tcg_temp_new(); 3698 TCGv ea_plus_s = tcg_temp_new(); 3699 3700 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3701 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3702 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3703 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3704 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3705 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3706 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3707 } 3708 break; 3709 default: 3710 /* invoke data storage error handler */ 3711 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3712 } 3713 } 3714 3715 static void gen_stwat(DisasContext *ctx) 3716 { 3717 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3718 } 3719 3720 #ifdef TARGET_PPC64 3721 static void gen_stdat(DisasContext *ctx) 3722 { 3723 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3724 } 3725 #endif 3726 3727 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3728 { 3729 TCGLabel *lfail; 3730 TCGv EA; 3731 TCGv cr0; 3732 TCGv t0; 3733 int rs = rS(ctx->opcode); 3734 3735 lfail = gen_new_label(); 3736 EA = tcg_temp_new(); 3737 cr0 = tcg_temp_new(); 3738 t0 = tcg_temp_new(); 3739 3740 tcg_gen_mov_tl(cr0, cpu_so); 3741 gen_set_access_type(ctx, ACCESS_RES); 3742 gen_addr_reg_index(ctx, EA); 3743 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3744 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3745 3746 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3747 cpu_gpr[rs], ctx->mem_idx, 3748 DEF_MEMOP(memop) | MO_ALIGN); 3749 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3750 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3751 tcg_gen_or_tl(cr0, cr0, t0); 3752 3753 gen_set_label(lfail); 3754 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3755 tcg_gen_movi_tl(cpu_reserve, -1); 3756 } 3757 3758 #define STCX(name, memop) \ 3759 static void gen_##name(DisasContext *ctx) \ 3760 { \ 3761 gen_conditional_store(ctx, memop); \ 3762 } 3763 3764 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3765 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3766 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3767 3768 #if defined(TARGET_PPC64) 3769 /* ldarx */ 3770 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3771 /* stdcx. */ 3772 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3773 3774 /* lqarx */ 3775 static void gen_lqarx(DisasContext *ctx) 3776 { 3777 int rd = rD(ctx->opcode); 3778 TCGv EA, hi, lo; 3779 TCGv_i128 t16; 3780 3781 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3782 (rd == rB(ctx->opcode)))) { 3783 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3784 return; 3785 } 3786 3787 gen_set_access_type(ctx, ACCESS_RES); 3788 EA = tcg_temp_new(); 3789 gen_addr_reg_index(ctx, EA); 3790 3791 /* Note that the low part is always in RD+1, even in LE mode. */ 3792 lo = cpu_gpr[rd + 1]; 3793 hi = cpu_gpr[rd]; 3794 3795 t16 = tcg_temp_new_i128(); 3796 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3797 tcg_gen_extr_i128_i64(lo, hi, t16); 3798 3799 tcg_gen_mov_tl(cpu_reserve, EA); 3800 tcg_gen_movi_tl(cpu_reserve_length, 16); 3801 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3802 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3803 } 3804 3805 /* stqcx. */ 3806 static void gen_stqcx_(DisasContext *ctx) 3807 { 3808 TCGLabel *lfail; 3809 TCGv EA, t0, t1; 3810 TCGv cr0; 3811 TCGv_i128 cmp, val; 3812 int rs = rS(ctx->opcode); 3813 3814 if (unlikely(rs & 1)) { 3815 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3816 return; 3817 } 3818 3819 lfail = gen_new_label(); 3820 EA = tcg_temp_new(); 3821 cr0 = tcg_temp_new(); 3822 3823 tcg_gen_mov_tl(cr0, cpu_so); 3824 gen_set_access_type(ctx, ACCESS_RES); 3825 gen_addr_reg_index(ctx, EA); 3826 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3827 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3828 3829 cmp = tcg_temp_new_i128(); 3830 val = tcg_temp_new_i128(); 3831 3832 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3833 3834 /* Note that the low part is always in RS+1, even in LE mode. */ 3835 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3836 3837 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3838 DEF_MEMOP(MO_128 | MO_ALIGN)); 3839 3840 t0 = tcg_temp_new(); 3841 t1 = tcg_temp_new(); 3842 tcg_gen_extr_i128_i64(t1, t0, val); 3843 3844 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3845 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3846 tcg_gen_or_tl(t0, t0, t1); 3847 3848 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3849 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3850 tcg_gen_or_tl(cr0, cr0, t0); 3851 3852 gen_set_label(lfail); 3853 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3854 tcg_gen_movi_tl(cpu_reserve, -1); 3855 } 3856 #endif /* defined(TARGET_PPC64) */ 3857 3858 /* sync */ 3859 static void gen_sync(DisasContext *ctx) 3860 { 3861 TCGBar bar = TCG_MO_ALL; 3862 uint32_t l = (ctx->opcode >> 21) & 3; 3863 3864 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3865 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3866 } 3867 3868 /* 3869 * We may need to check for a pending TLB flush. 3870 * 3871 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3872 * 3873 * Additionally, this can only happen in kernel mode however so 3874 * check MSR_PR as well. 3875 */ 3876 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3877 gen_check_tlb_flush(ctx, true); 3878 } 3879 3880 tcg_gen_mb(bar | TCG_BAR_SC); 3881 } 3882 3883 /* wait */ 3884 static void gen_wait(DisasContext *ctx) 3885 { 3886 uint32_t wc; 3887 3888 if (ctx->insns_flags & PPC_WAIT) { 3889 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3890 3891 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3892 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3893 wc = WC(ctx->opcode); 3894 } else { 3895 wc = 0; 3896 } 3897 3898 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3899 /* v3.0 defines a new 'wait' encoding. */ 3900 wc = WC(ctx->opcode); 3901 if (ctx->insns_flags2 & PPC2_ISA310) { 3902 uint32_t pl = PL(ctx->opcode); 3903 3904 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3905 if (wc == 3) { 3906 gen_invalid(ctx); 3907 return; 3908 } 3909 3910 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3911 if (pl > 0 && wc != 2) { 3912 gen_invalid(ctx); 3913 return; 3914 } 3915 3916 } else { /* ISA300 */ 3917 /* WC 1-3 are reserved */ 3918 if (wc > 0) { 3919 gen_invalid(ctx); 3920 return; 3921 } 3922 } 3923 3924 } else { 3925 warn_report("wait instruction decoded with wrong ISA flags."); 3926 gen_invalid(ctx); 3927 return; 3928 } 3929 3930 /* 3931 * wait without WC field or with WC=0 waits for an exception / interrupt 3932 * to occur. 3933 */ 3934 if (wc == 0) { 3935 TCGv_i32 t0 = tcg_constant_i32(1); 3936 tcg_gen_st_i32(t0, cpu_env, 3937 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3938 /* Stop translation, as the CPU is supposed to sleep from now */ 3939 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3940 } 3941 3942 /* 3943 * Other wait types must not just wait until an exception occurs because 3944 * ignoring their other wake-up conditions could cause a hang. 3945 * 3946 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3947 * no-ops. 3948 * 3949 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3950 * 3951 * wc=2 waits for an implementation-specific condition, such could be 3952 * always true, so it can be implemented as a no-op. 3953 * 3954 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3955 * 3956 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3957 * Reservation-loss may have implementation-specific conditions, so it 3958 * can be implemented as a no-op. 3959 * 3960 * wc=2 waits for an exception or an amount of time to pass. This 3961 * amount is implementation-specific so it can be implemented as a 3962 * no-op. 3963 * 3964 * ISA v3.1 allows for execution to resume "in the rare case of 3965 * an implementation-dependent event", so in any case software must 3966 * not depend on the architected resumption condition to become 3967 * true, so no-op implementations should be architecturally correct 3968 * (if suboptimal). 3969 */ 3970 } 3971 3972 #if defined(TARGET_PPC64) 3973 static void gen_doze(DisasContext *ctx) 3974 { 3975 #if defined(CONFIG_USER_ONLY) 3976 GEN_PRIV(ctx); 3977 #else 3978 TCGv_i32 t; 3979 3980 CHK_HV(ctx); 3981 t = tcg_constant_i32(PPC_PM_DOZE); 3982 gen_helper_pminsn(cpu_env, t); 3983 /* Stop translation, as the CPU is supposed to sleep from now */ 3984 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3985 #endif /* defined(CONFIG_USER_ONLY) */ 3986 } 3987 3988 static void gen_nap(DisasContext *ctx) 3989 { 3990 #if defined(CONFIG_USER_ONLY) 3991 GEN_PRIV(ctx); 3992 #else 3993 TCGv_i32 t; 3994 3995 CHK_HV(ctx); 3996 t = tcg_constant_i32(PPC_PM_NAP); 3997 gen_helper_pminsn(cpu_env, t); 3998 /* Stop translation, as the CPU is supposed to sleep from now */ 3999 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4000 #endif /* defined(CONFIG_USER_ONLY) */ 4001 } 4002 4003 static void gen_stop(DisasContext *ctx) 4004 { 4005 #if defined(CONFIG_USER_ONLY) 4006 GEN_PRIV(ctx); 4007 #else 4008 TCGv_i32 t; 4009 4010 CHK_HV(ctx); 4011 t = tcg_constant_i32(PPC_PM_STOP); 4012 gen_helper_pminsn(cpu_env, t); 4013 /* Stop translation, as the CPU is supposed to sleep from now */ 4014 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4015 #endif /* defined(CONFIG_USER_ONLY) */ 4016 } 4017 4018 static void gen_sleep(DisasContext *ctx) 4019 { 4020 #if defined(CONFIG_USER_ONLY) 4021 GEN_PRIV(ctx); 4022 #else 4023 TCGv_i32 t; 4024 4025 CHK_HV(ctx); 4026 t = tcg_constant_i32(PPC_PM_SLEEP); 4027 gen_helper_pminsn(cpu_env, t); 4028 /* Stop translation, as the CPU is supposed to sleep from now */ 4029 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4030 #endif /* defined(CONFIG_USER_ONLY) */ 4031 } 4032 4033 static void gen_rvwinkle(DisasContext *ctx) 4034 { 4035 #if defined(CONFIG_USER_ONLY) 4036 GEN_PRIV(ctx); 4037 #else 4038 TCGv_i32 t; 4039 4040 CHK_HV(ctx); 4041 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4042 gen_helper_pminsn(cpu_env, t); 4043 /* Stop translation, as the CPU is supposed to sleep from now */ 4044 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4045 #endif /* defined(CONFIG_USER_ONLY) */ 4046 } 4047 #endif /* #if defined(TARGET_PPC64) */ 4048 4049 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4050 { 4051 #if defined(TARGET_PPC64) 4052 if (ctx->has_cfar) { 4053 tcg_gen_movi_tl(cpu_cfar, nip); 4054 } 4055 #endif 4056 } 4057 4058 #if defined(TARGET_PPC64) 4059 static void pmu_count_insns(DisasContext *ctx) 4060 { 4061 /* 4062 * Do not bother calling the helper if the PMU isn't counting 4063 * instructions. 4064 */ 4065 if (!ctx->pmu_insn_cnt) { 4066 return; 4067 } 4068 4069 #if !defined(CONFIG_USER_ONLY) 4070 TCGLabel *l; 4071 TCGv t0; 4072 4073 /* 4074 * The PMU insns_inc() helper stops the internal PMU timer if a 4075 * counter overflows happens. In that case, if the guest is 4076 * running with icount and we do not handle it beforehand, 4077 * the helper can trigger a 'bad icount read'. 4078 */ 4079 translator_io_start(&ctx->base); 4080 4081 /* Avoid helper calls when only PMC5-6 are enabled. */ 4082 if (!ctx->pmc_other) { 4083 l = gen_new_label(); 4084 t0 = tcg_temp_new(); 4085 4086 gen_load_spr(t0, SPR_POWER_PMC5); 4087 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4088 gen_store_spr(SPR_POWER_PMC5, t0); 4089 /* Check for overflow, if it's enabled */ 4090 if (ctx->mmcr0_pmcjce) { 4091 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4092 gen_helper_handle_pmc5_overflow(cpu_env); 4093 } 4094 4095 gen_set_label(l); 4096 } else { 4097 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4098 } 4099 #else 4100 /* 4101 * User mode can read (but not write) PMC5 and start/stop 4102 * the PMU via MMCR0_FC. In this case just increment 4103 * PMC5 with base.num_insns. 4104 */ 4105 TCGv t0 = tcg_temp_new(); 4106 4107 gen_load_spr(t0, SPR_POWER_PMC5); 4108 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4109 gen_store_spr(SPR_POWER_PMC5, t0); 4110 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4111 } 4112 #else 4113 static void pmu_count_insns(DisasContext *ctx) 4114 { 4115 return; 4116 } 4117 #endif /* #if defined(TARGET_PPC64) */ 4118 4119 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4120 { 4121 return translator_use_goto_tb(&ctx->base, dest); 4122 } 4123 4124 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4125 { 4126 if (unlikely(ctx->singlestep_enabled)) { 4127 gen_debug_exception(ctx); 4128 } else { 4129 /* 4130 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4131 * CF_NO_GOTO_PTR is set. Count insns now. 4132 */ 4133 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4134 pmu_count_insns(ctx); 4135 } 4136 4137 tcg_gen_lookup_and_goto_ptr(); 4138 } 4139 } 4140 4141 /*** Branch ***/ 4142 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4143 { 4144 if (NARROW_MODE(ctx)) { 4145 dest = (uint32_t) dest; 4146 } 4147 if (use_goto_tb(ctx, dest)) { 4148 pmu_count_insns(ctx); 4149 tcg_gen_goto_tb(n); 4150 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4151 tcg_gen_exit_tb(ctx->base.tb, n); 4152 } else { 4153 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4154 gen_lookup_and_goto_ptr(ctx); 4155 } 4156 } 4157 4158 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4159 { 4160 if (NARROW_MODE(ctx)) { 4161 nip = (uint32_t)nip; 4162 } 4163 tcg_gen_movi_tl(cpu_lr, nip); 4164 } 4165 4166 /* b ba bl bla */ 4167 static void gen_b(DisasContext *ctx) 4168 { 4169 target_ulong li, target; 4170 4171 /* sign extend LI */ 4172 li = LI(ctx->opcode); 4173 li = (li ^ 0x02000000) - 0x02000000; 4174 if (likely(AA(ctx->opcode) == 0)) { 4175 target = ctx->cia + li; 4176 } else { 4177 target = li; 4178 } 4179 if (LK(ctx->opcode)) { 4180 gen_setlr(ctx, ctx->base.pc_next); 4181 } 4182 gen_update_cfar(ctx, ctx->cia); 4183 gen_goto_tb(ctx, 0, target); 4184 ctx->base.is_jmp = DISAS_NORETURN; 4185 } 4186 4187 #define BCOND_IM 0 4188 #define BCOND_LR 1 4189 #define BCOND_CTR 2 4190 #define BCOND_TAR 3 4191 4192 static void gen_bcond(DisasContext *ctx, int type) 4193 { 4194 uint32_t bo = BO(ctx->opcode); 4195 TCGLabel *l1; 4196 TCGv target; 4197 4198 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4199 target = tcg_temp_new(); 4200 if (type == BCOND_CTR) { 4201 tcg_gen_mov_tl(target, cpu_ctr); 4202 } else if (type == BCOND_TAR) { 4203 gen_load_spr(target, SPR_TAR); 4204 } else { 4205 tcg_gen_mov_tl(target, cpu_lr); 4206 } 4207 } else { 4208 target = NULL; 4209 } 4210 if (LK(ctx->opcode)) { 4211 gen_setlr(ctx, ctx->base.pc_next); 4212 } 4213 l1 = gen_new_label(); 4214 if ((bo & 0x4) == 0) { 4215 /* Decrement and test CTR */ 4216 TCGv temp = tcg_temp_new(); 4217 4218 if (type == BCOND_CTR) { 4219 /* 4220 * All ISAs up to v3 describe this form of bcctr as invalid but 4221 * some processors, ie. 64-bit server processors compliant with 4222 * arch 2.x, do implement a "test and decrement" logic instead, 4223 * as described in their respective UMs. This logic involves CTR 4224 * to act as both the branch target and a counter, which makes 4225 * it basically useless and thus never used in real code. 4226 * 4227 * This form was hence chosen to trigger extra micro-architectural 4228 * side-effect on real HW needed for the Spectre v2 workaround. 4229 * It is up to guests that implement such workaround, ie. linux, to 4230 * use this form in a way it just triggers the side-effect without 4231 * doing anything else harmful. 4232 */ 4233 if (unlikely(!is_book3s_arch2x(ctx))) { 4234 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4235 return; 4236 } 4237 4238 if (NARROW_MODE(ctx)) { 4239 tcg_gen_ext32u_tl(temp, cpu_ctr); 4240 } else { 4241 tcg_gen_mov_tl(temp, cpu_ctr); 4242 } 4243 if (bo & 0x2) { 4244 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4245 } else { 4246 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4247 } 4248 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4249 } else { 4250 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4251 if (NARROW_MODE(ctx)) { 4252 tcg_gen_ext32u_tl(temp, cpu_ctr); 4253 } else { 4254 tcg_gen_mov_tl(temp, cpu_ctr); 4255 } 4256 if (bo & 0x2) { 4257 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4258 } else { 4259 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4260 } 4261 } 4262 } 4263 if ((bo & 0x10) == 0) { 4264 /* Test CR */ 4265 uint32_t bi = BI(ctx->opcode); 4266 uint32_t mask = 0x08 >> (bi & 0x03); 4267 TCGv_i32 temp = tcg_temp_new_i32(); 4268 4269 if (bo & 0x8) { 4270 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4271 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4272 } else { 4273 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4274 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4275 } 4276 } 4277 gen_update_cfar(ctx, ctx->cia); 4278 if (type == BCOND_IM) { 4279 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4280 if (likely(AA(ctx->opcode) == 0)) { 4281 gen_goto_tb(ctx, 0, ctx->cia + li); 4282 } else { 4283 gen_goto_tb(ctx, 0, li); 4284 } 4285 } else { 4286 if (NARROW_MODE(ctx)) { 4287 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4288 } else { 4289 tcg_gen_andi_tl(cpu_nip, target, ~3); 4290 } 4291 gen_lookup_and_goto_ptr(ctx); 4292 } 4293 if ((bo & 0x14) != 0x14) { 4294 /* fallthrough case */ 4295 gen_set_label(l1); 4296 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4297 } 4298 ctx->base.is_jmp = DISAS_NORETURN; 4299 } 4300 4301 static void gen_bc(DisasContext *ctx) 4302 { 4303 gen_bcond(ctx, BCOND_IM); 4304 } 4305 4306 static void gen_bcctr(DisasContext *ctx) 4307 { 4308 gen_bcond(ctx, BCOND_CTR); 4309 } 4310 4311 static void gen_bclr(DisasContext *ctx) 4312 { 4313 gen_bcond(ctx, BCOND_LR); 4314 } 4315 4316 static void gen_bctar(DisasContext *ctx) 4317 { 4318 gen_bcond(ctx, BCOND_TAR); 4319 } 4320 4321 /*** Condition register logical ***/ 4322 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4323 static void glue(gen_, name)(DisasContext *ctx) \ 4324 { \ 4325 uint8_t bitmask; \ 4326 int sh; \ 4327 TCGv_i32 t0, t1; \ 4328 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4329 t0 = tcg_temp_new_i32(); \ 4330 if (sh > 0) \ 4331 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4332 else if (sh < 0) \ 4333 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4334 else \ 4335 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4336 t1 = tcg_temp_new_i32(); \ 4337 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4338 if (sh > 0) \ 4339 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4340 else if (sh < 0) \ 4341 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4342 else \ 4343 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4344 tcg_op(t0, t0, t1); \ 4345 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4346 tcg_gen_andi_i32(t0, t0, bitmask); \ 4347 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4348 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4349 } 4350 4351 /* crand */ 4352 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4353 /* crandc */ 4354 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4355 /* creqv */ 4356 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4357 /* crnand */ 4358 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4359 /* crnor */ 4360 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4361 /* cror */ 4362 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4363 /* crorc */ 4364 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4365 /* crxor */ 4366 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4367 4368 /* mcrf */ 4369 static void gen_mcrf(DisasContext *ctx) 4370 { 4371 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4372 } 4373 4374 /*** System linkage ***/ 4375 4376 /* rfi (supervisor only) */ 4377 static void gen_rfi(DisasContext *ctx) 4378 { 4379 #if defined(CONFIG_USER_ONLY) 4380 GEN_PRIV(ctx); 4381 #else 4382 /* 4383 * This instruction doesn't exist anymore on 64-bit server 4384 * processors compliant with arch 2.x 4385 */ 4386 if (is_book3s_arch2x(ctx)) { 4387 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4388 return; 4389 } 4390 /* Restore CPU state */ 4391 CHK_SV(ctx); 4392 translator_io_start(&ctx->base); 4393 gen_update_cfar(ctx, ctx->cia); 4394 gen_helper_rfi(cpu_env); 4395 ctx->base.is_jmp = DISAS_EXIT; 4396 #endif 4397 } 4398 4399 #if defined(TARGET_PPC64) 4400 static void gen_rfid(DisasContext *ctx) 4401 { 4402 #if defined(CONFIG_USER_ONLY) 4403 GEN_PRIV(ctx); 4404 #else 4405 /* Restore CPU state */ 4406 CHK_SV(ctx); 4407 translator_io_start(&ctx->base); 4408 gen_update_cfar(ctx, ctx->cia); 4409 gen_helper_rfid(cpu_env); 4410 ctx->base.is_jmp = DISAS_EXIT; 4411 #endif 4412 } 4413 4414 #if !defined(CONFIG_USER_ONLY) 4415 static void gen_rfscv(DisasContext *ctx) 4416 { 4417 #if defined(CONFIG_USER_ONLY) 4418 GEN_PRIV(ctx); 4419 #else 4420 /* Restore CPU state */ 4421 CHK_SV(ctx); 4422 translator_io_start(&ctx->base); 4423 gen_update_cfar(ctx, ctx->cia); 4424 gen_helper_rfscv(cpu_env); 4425 ctx->base.is_jmp = DISAS_EXIT; 4426 #endif 4427 } 4428 #endif 4429 4430 static void gen_hrfid(DisasContext *ctx) 4431 { 4432 #if defined(CONFIG_USER_ONLY) 4433 GEN_PRIV(ctx); 4434 #else 4435 /* Restore CPU state */ 4436 CHK_HV(ctx); 4437 gen_helper_hrfid(cpu_env); 4438 ctx->base.is_jmp = DISAS_EXIT; 4439 #endif 4440 } 4441 #endif 4442 4443 /* sc */ 4444 #if defined(CONFIG_USER_ONLY) 4445 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4446 #else 4447 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4448 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4449 #endif 4450 static void gen_sc(DisasContext *ctx) 4451 { 4452 uint32_t lev; 4453 4454 /* 4455 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4456 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4457 * for Ultravisor which TCG does not support, so just ignore the top 6. 4458 */ 4459 lev = (ctx->opcode >> 5) & 0x1; 4460 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4461 } 4462 4463 #if defined(TARGET_PPC64) 4464 #if !defined(CONFIG_USER_ONLY) 4465 static void gen_scv(DisasContext *ctx) 4466 { 4467 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4468 4469 /* Set the PC back to the faulting instruction. */ 4470 gen_update_nip(ctx, ctx->cia); 4471 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4472 4473 ctx->base.is_jmp = DISAS_NORETURN; 4474 } 4475 #endif 4476 #endif 4477 4478 /*** Trap ***/ 4479 4480 /* Check for unconditional traps (always or never) */ 4481 static bool check_unconditional_trap(DisasContext *ctx) 4482 { 4483 /* Trap never */ 4484 if (TO(ctx->opcode) == 0) { 4485 return true; 4486 } 4487 /* Trap always */ 4488 if (TO(ctx->opcode) == 31) { 4489 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4490 return true; 4491 } 4492 return false; 4493 } 4494 4495 /* tw */ 4496 static void gen_tw(DisasContext *ctx) 4497 { 4498 TCGv_i32 t0; 4499 4500 if (check_unconditional_trap(ctx)) { 4501 return; 4502 } 4503 t0 = tcg_constant_i32(TO(ctx->opcode)); 4504 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4505 t0); 4506 } 4507 4508 /* twi */ 4509 static void gen_twi(DisasContext *ctx) 4510 { 4511 TCGv t0; 4512 TCGv_i32 t1; 4513 4514 if (check_unconditional_trap(ctx)) { 4515 return; 4516 } 4517 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4518 t1 = tcg_constant_i32(TO(ctx->opcode)); 4519 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4520 } 4521 4522 #if defined(TARGET_PPC64) 4523 /* td */ 4524 static void gen_td(DisasContext *ctx) 4525 { 4526 TCGv_i32 t0; 4527 4528 if (check_unconditional_trap(ctx)) { 4529 return; 4530 } 4531 t0 = tcg_constant_i32(TO(ctx->opcode)); 4532 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4533 t0); 4534 } 4535 4536 /* tdi */ 4537 static void gen_tdi(DisasContext *ctx) 4538 { 4539 TCGv t0; 4540 TCGv_i32 t1; 4541 4542 if (check_unconditional_trap(ctx)) { 4543 return; 4544 } 4545 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4546 t1 = tcg_constant_i32(TO(ctx->opcode)); 4547 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4548 } 4549 #endif 4550 4551 /*** Processor control ***/ 4552 4553 /* mcrxr */ 4554 static void gen_mcrxr(DisasContext *ctx) 4555 { 4556 TCGv_i32 t0 = tcg_temp_new_i32(); 4557 TCGv_i32 t1 = tcg_temp_new_i32(); 4558 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4559 4560 tcg_gen_trunc_tl_i32(t0, cpu_so); 4561 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4562 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4563 tcg_gen_shli_i32(t0, t0, 3); 4564 tcg_gen_shli_i32(t1, t1, 2); 4565 tcg_gen_shli_i32(dst, dst, 1); 4566 tcg_gen_or_i32(dst, dst, t0); 4567 tcg_gen_or_i32(dst, dst, t1); 4568 4569 tcg_gen_movi_tl(cpu_so, 0); 4570 tcg_gen_movi_tl(cpu_ov, 0); 4571 tcg_gen_movi_tl(cpu_ca, 0); 4572 } 4573 4574 #ifdef TARGET_PPC64 4575 /* mcrxrx */ 4576 static void gen_mcrxrx(DisasContext *ctx) 4577 { 4578 TCGv t0 = tcg_temp_new(); 4579 TCGv t1 = tcg_temp_new(); 4580 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4581 4582 /* copy OV and OV32 */ 4583 tcg_gen_shli_tl(t0, cpu_ov, 1); 4584 tcg_gen_or_tl(t0, t0, cpu_ov32); 4585 tcg_gen_shli_tl(t0, t0, 2); 4586 /* copy CA and CA32 */ 4587 tcg_gen_shli_tl(t1, cpu_ca, 1); 4588 tcg_gen_or_tl(t1, t1, cpu_ca32); 4589 tcg_gen_or_tl(t0, t0, t1); 4590 tcg_gen_trunc_tl_i32(dst, t0); 4591 } 4592 #endif 4593 4594 /* mfcr mfocrf */ 4595 static void gen_mfcr(DisasContext *ctx) 4596 { 4597 uint32_t crm, crn; 4598 4599 if (likely(ctx->opcode & 0x00100000)) { 4600 crm = CRM(ctx->opcode); 4601 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4602 crn = ctz32(crm); 4603 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4604 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4605 cpu_gpr[rD(ctx->opcode)], crn * 4); 4606 } 4607 } else { 4608 TCGv_i32 t0 = tcg_temp_new_i32(); 4609 tcg_gen_mov_i32(t0, cpu_crf[0]); 4610 tcg_gen_shli_i32(t0, t0, 4); 4611 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4612 tcg_gen_shli_i32(t0, t0, 4); 4613 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4614 tcg_gen_shli_i32(t0, t0, 4); 4615 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4616 tcg_gen_shli_i32(t0, t0, 4); 4617 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4618 tcg_gen_shli_i32(t0, t0, 4); 4619 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4620 tcg_gen_shli_i32(t0, t0, 4); 4621 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4622 tcg_gen_shli_i32(t0, t0, 4); 4623 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4624 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4625 } 4626 } 4627 4628 /* mfmsr */ 4629 static void gen_mfmsr(DisasContext *ctx) 4630 { 4631 CHK_SV(ctx); 4632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4633 } 4634 4635 /* mfspr */ 4636 static inline void gen_op_mfspr(DisasContext *ctx) 4637 { 4638 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4639 uint32_t sprn = SPR(ctx->opcode); 4640 4641 #if defined(CONFIG_USER_ONLY) 4642 read_cb = ctx->spr_cb[sprn].uea_read; 4643 #else 4644 if (ctx->pr) { 4645 read_cb = ctx->spr_cb[sprn].uea_read; 4646 } else if (ctx->hv) { 4647 read_cb = ctx->spr_cb[sprn].hea_read; 4648 } else { 4649 read_cb = ctx->spr_cb[sprn].oea_read; 4650 } 4651 #endif 4652 if (likely(read_cb != NULL)) { 4653 if (likely(read_cb != SPR_NOACCESS)) { 4654 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4655 } else { 4656 /* Privilege exception */ 4657 /* 4658 * This is a hack to avoid warnings when running Linux: 4659 * this OS breaks the PowerPC virtualisation model, 4660 * allowing userland application to read the PVR 4661 */ 4662 if (sprn != SPR_PVR) { 4663 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4664 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4665 ctx->cia); 4666 } 4667 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4668 } 4669 } else { 4670 /* ISA 2.07 defines these as no-ops */ 4671 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4672 (sprn >= 808 && sprn <= 811)) { 4673 /* This is a nop */ 4674 return; 4675 } 4676 /* Not defined */ 4677 qemu_log_mask(LOG_GUEST_ERROR, 4678 "Trying to read invalid spr %d (0x%03x) at " 4679 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4680 4681 /* 4682 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4683 * generate a priv, a hv emu or a no-op 4684 */ 4685 if (sprn & 0x10) { 4686 if (ctx->pr) { 4687 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4688 } 4689 } else { 4690 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4691 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4692 } 4693 } 4694 } 4695 } 4696 4697 static void gen_mfspr(DisasContext *ctx) 4698 { 4699 gen_op_mfspr(ctx); 4700 } 4701 4702 /* mftb */ 4703 static void gen_mftb(DisasContext *ctx) 4704 { 4705 gen_op_mfspr(ctx); 4706 } 4707 4708 /* mtcrf mtocrf*/ 4709 static void gen_mtcrf(DisasContext *ctx) 4710 { 4711 uint32_t crm, crn; 4712 4713 crm = CRM(ctx->opcode); 4714 if (likely((ctx->opcode & 0x00100000))) { 4715 if (crm && ((crm & (crm - 1)) == 0)) { 4716 TCGv_i32 temp = tcg_temp_new_i32(); 4717 crn = ctz32(crm); 4718 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4719 tcg_gen_shri_i32(temp, temp, crn * 4); 4720 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4721 } 4722 } else { 4723 TCGv_i32 temp = tcg_temp_new_i32(); 4724 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4725 for (crn = 0 ; crn < 8 ; crn++) { 4726 if (crm & (1 << crn)) { 4727 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4728 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4729 } 4730 } 4731 } 4732 } 4733 4734 /* mtmsr */ 4735 #if defined(TARGET_PPC64) 4736 static void gen_mtmsrd(DisasContext *ctx) 4737 { 4738 if (unlikely(!is_book3s_arch2x(ctx))) { 4739 gen_invalid(ctx); 4740 return; 4741 } 4742 4743 CHK_SV(ctx); 4744 4745 #if !defined(CONFIG_USER_ONLY) 4746 TCGv t0, t1; 4747 target_ulong mask; 4748 4749 t0 = tcg_temp_new(); 4750 t1 = tcg_temp_new(); 4751 4752 translator_io_start(&ctx->base); 4753 4754 if (ctx->opcode & 0x00010000) { 4755 /* L=1 form only updates EE and RI */ 4756 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4757 } else { 4758 /* mtmsrd does not alter HV, S, ME, or LE */ 4759 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4760 (1ULL << MSR_HV)); 4761 /* 4762 * XXX: we need to update nip before the store if we enter 4763 * power saving mode, we will exit the loop directly from 4764 * ppc_store_msr 4765 */ 4766 gen_update_nip(ctx, ctx->base.pc_next); 4767 } 4768 4769 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4770 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4771 tcg_gen_or_tl(t0, t0, t1); 4772 4773 gen_helper_store_msr(cpu_env, t0); 4774 4775 /* Must stop the translation as machine state (may have) changed */ 4776 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4777 #endif /* !defined(CONFIG_USER_ONLY) */ 4778 } 4779 #endif /* defined(TARGET_PPC64) */ 4780 4781 static void gen_mtmsr(DisasContext *ctx) 4782 { 4783 CHK_SV(ctx); 4784 4785 #if !defined(CONFIG_USER_ONLY) 4786 TCGv t0, t1; 4787 target_ulong mask = 0xFFFFFFFF; 4788 4789 t0 = tcg_temp_new(); 4790 t1 = tcg_temp_new(); 4791 4792 translator_io_start(&ctx->base); 4793 if (ctx->opcode & 0x00010000) { 4794 /* L=1 form only updates EE and RI */ 4795 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4796 } else { 4797 /* mtmsr does not alter S, ME, or LE */ 4798 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4799 4800 /* 4801 * XXX: we need to update nip before the store if we enter 4802 * power saving mode, we will exit the loop directly from 4803 * ppc_store_msr 4804 */ 4805 gen_update_nip(ctx, ctx->base.pc_next); 4806 } 4807 4808 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4809 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4810 tcg_gen_or_tl(t0, t0, t1); 4811 4812 gen_helper_store_msr(cpu_env, t0); 4813 4814 /* Must stop the translation as machine state (may have) changed */ 4815 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4816 #endif 4817 } 4818 4819 /* mtspr */ 4820 static void gen_mtspr(DisasContext *ctx) 4821 { 4822 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4823 uint32_t sprn = SPR(ctx->opcode); 4824 4825 #if defined(CONFIG_USER_ONLY) 4826 write_cb = ctx->spr_cb[sprn].uea_write; 4827 #else 4828 if (ctx->pr) { 4829 write_cb = ctx->spr_cb[sprn].uea_write; 4830 } else if (ctx->hv) { 4831 write_cb = ctx->spr_cb[sprn].hea_write; 4832 } else { 4833 write_cb = ctx->spr_cb[sprn].oea_write; 4834 } 4835 #endif 4836 if (likely(write_cb != NULL)) { 4837 if (likely(write_cb != SPR_NOACCESS)) { 4838 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4839 } else { 4840 /* Privilege exception */ 4841 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4842 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4843 ctx->cia); 4844 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4845 } 4846 } else { 4847 /* ISA 2.07 defines these as no-ops */ 4848 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4849 (sprn >= 808 && sprn <= 811)) { 4850 /* This is a nop */ 4851 return; 4852 } 4853 4854 /* Not defined */ 4855 qemu_log_mask(LOG_GUEST_ERROR, 4856 "Trying to write invalid spr %d (0x%03x) at " 4857 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4858 4859 4860 /* 4861 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4862 * generate a priv, a hv emu or a no-op 4863 */ 4864 if (sprn & 0x10) { 4865 if (ctx->pr) { 4866 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4867 } 4868 } else { 4869 if (ctx->pr || sprn == 0) { 4870 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4871 } 4872 } 4873 } 4874 } 4875 4876 #if defined(TARGET_PPC64) 4877 /* setb */ 4878 static void gen_setb(DisasContext *ctx) 4879 { 4880 TCGv_i32 t0 = tcg_temp_new_i32(); 4881 TCGv_i32 t8 = tcg_constant_i32(8); 4882 TCGv_i32 tm1 = tcg_constant_i32(-1); 4883 int crf = crfS(ctx->opcode); 4884 4885 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4886 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4887 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4888 } 4889 #endif 4890 4891 /*** Cache management ***/ 4892 4893 /* dcbf */ 4894 static void gen_dcbf(DisasContext *ctx) 4895 { 4896 /* XXX: specification says this is treated as a load by the MMU */ 4897 TCGv t0; 4898 gen_set_access_type(ctx, ACCESS_CACHE); 4899 t0 = tcg_temp_new(); 4900 gen_addr_reg_index(ctx, t0); 4901 gen_qemu_ld8u(ctx, t0, t0); 4902 } 4903 4904 /* dcbfep (external PID dcbf) */ 4905 static void gen_dcbfep(DisasContext *ctx) 4906 { 4907 /* XXX: specification says this is treated as a load by the MMU */ 4908 TCGv t0; 4909 CHK_SV(ctx); 4910 gen_set_access_type(ctx, ACCESS_CACHE); 4911 t0 = tcg_temp_new(); 4912 gen_addr_reg_index(ctx, t0); 4913 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4914 } 4915 4916 /* dcbi (Supervisor only) */ 4917 static void gen_dcbi(DisasContext *ctx) 4918 { 4919 #if defined(CONFIG_USER_ONLY) 4920 GEN_PRIV(ctx); 4921 #else 4922 TCGv EA, val; 4923 4924 CHK_SV(ctx); 4925 EA = tcg_temp_new(); 4926 gen_set_access_type(ctx, ACCESS_CACHE); 4927 gen_addr_reg_index(ctx, EA); 4928 val = tcg_temp_new(); 4929 /* XXX: specification says this should be treated as a store by the MMU */ 4930 gen_qemu_ld8u(ctx, val, EA); 4931 gen_qemu_st8(ctx, val, EA); 4932 #endif /* defined(CONFIG_USER_ONLY) */ 4933 } 4934 4935 /* dcdst */ 4936 static void gen_dcbst(DisasContext *ctx) 4937 { 4938 /* XXX: specification say this is treated as a load by the MMU */ 4939 TCGv t0; 4940 gen_set_access_type(ctx, ACCESS_CACHE); 4941 t0 = tcg_temp_new(); 4942 gen_addr_reg_index(ctx, t0); 4943 gen_qemu_ld8u(ctx, t0, t0); 4944 } 4945 4946 /* dcbstep (dcbstep External PID version) */ 4947 static void gen_dcbstep(DisasContext *ctx) 4948 { 4949 /* XXX: specification say this is treated as a load by the MMU */ 4950 TCGv t0; 4951 gen_set_access_type(ctx, ACCESS_CACHE); 4952 t0 = tcg_temp_new(); 4953 gen_addr_reg_index(ctx, t0); 4954 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4955 } 4956 4957 /* dcbt */ 4958 static void gen_dcbt(DisasContext *ctx) 4959 { 4960 /* 4961 * interpreted as no-op 4962 * XXX: specification say this is treated as a load by the MMU but 4963 * does not generate any exception 4964 */ 4965 } 4966 4967 /* dcbtep */ 4968 static void gen_dcbtep(DisasContext *ctx) 4969 { 4970 /* 4971 * interpreted as no-op 4972 * XXX: specification say this is treated as a load by the MMU but 4973 * does not generate any exception 4974 */ 4975 } 4976 4977 /* dcbtst */ 4978 static void gen_dcbtst(DisasContext *ctx) 4979 { 4980 /* 4981 * interpreted as no-op 4982 * XXX: specification say this is treated as a load by the MMU but 4983 * does not generate any exception 4984 */ 4985 } 4986 4987 /* dcbtstep */ 4988 static void gen_dcbtstep(DisasContext *ctx) 4989 { 4990 /* 4991 * interpreted as no-op 4992 * XXX: specification say this is treated as a load by the MMU but 4993 * does not generate any exception 4994 */ 4995 } 4996 4997 /* dcbtls */ 4998 static void gen_dcbtls(DisasContext *ctx) 4999 { 5000 /* Always fails locking the cache */ 5001 TCGv t0 = tcg_temp_new(); 5002 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5003 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5004 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5005 } 5006 5007 /* dcblc */ 5008 static void gen_dcblc(DisasContext *ctx) 5009 { 5010 /* 5011 * interpreted as no-op 5012 */ 5013 } 5014 5015 /* dcbz */ 5016 static void gen_dcbz(DisasContext *ctx) 5017 { 5018 TCGv tcgv_addr; 5019 TCGv_i32 tcgv_op; 5020 5021 gen_set_access_type(ctx, ACCESS_CACHE); 5022 tcgv_addr = tcg_temp_new(); 5023 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5024 gen_addr_reg_index(ctx, tcgv_addr); 5025 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5026 } 5027 5028 /* dcbzep */ 5029 static void gen_dcbzep(DisasContext *ctx) 5030 { 5031 TCGv tcgv_addr; 5032 TCGv_i32 tcgv_op; 5033 5034 gen_set_access_type(ctx, ACCESS_CACHE); 5035 tcgv_addr = tcg_temp_new(); 5036 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5037 gen_addr_reg_index(ctx, tcgv_addr); 5038 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5039 } 5040 5041 /* dst / dstt */ 5042 static void gen_dst(DisasContext *ctx) 5043 { 5044 if (rA(ctx->opcode) == 0) { 5045 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5046 } else { 5047 /* interpreted as no-op */ 5048 } 5049 } 5050 5051 /* dstst /dststt */ 5052 static void gen_dstst(DisasContext *ctx) 5053 { 5054 if (rA(ctx->opcode) == 0) { 5055 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5056 } else { 5057 /* interpreted as no-op */ 5058 } 5059 5060 } 5061 5062 /* dss / dssall */ 5063 static void gen_dss(DisasContext *ctx) 5064 { 5065 /* interpreted as no-op */ 5066 } 5067 5068 /* icbi */ 5069 static void gen_icbi(DisasContext *ctx) 5070 { 5071 TCGv t0; 5072 gen_set_access_type(ctx, ACCESS_CACHE); 5073 t0 = tcg_temp_new(); 5074 gen_addr_reg_index(ctx, t0); 5075 gen_helper_icbi(cpu_env, t0); 5076 } 5077 5078 /* icbiep */ 5079 static void gen_icbiep(DisasContext *ctx) 5080 { 5081 TCGv t0; 5082 gen_set_access_type(ctx, ACCESS_CACHE); 5083 t0 = tcg_temp_new(); 5084 gen_addr_reg_index(ctx, t0); 5085 gen_helper_icbiep(cpu_env, t0); 5086 } 5087 5088 /* Optional: */ 5089 /* dcba */ 5090 static void gen_dcba(DisasContext *ctx) 5091 { 5092 /* 5093 * interpreted as no-op 5094 * XXX: specification say this is treated as a store by the MMU 5095 * but does not generate any exception 5096 */ 5097 } 5098 5099 /*** Segment register manipulation ***/ 5100 /* Supervisor only: */ 5101 5102 /* mfsr */ 5103 static void gen_mfsr(DisasContext *ctx) 5104 { 5105 #if defined(CONFIG_USER_ONLY) 5106 GEN_PRIV(ctx); 5107 #else 5108 TCGv t0; 5109 5110 CHK_SV(ctx); 5111 t0 = tcg_constant_tl(SR(ctx->opcode)); 5112 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5113 #endif /* defined(CONFIG_USER_ONLY) */ 5114 } 5115 5116 /* mfsrin */ 5117 static void gen_mfsrin(DisasContext *ctx) 5118 { 5119 #if defined(CONFIG_USER_ONLY) 5120 GEN_PRIV(ctx); 5121 #else 5122 TCGv t0; 5123 5124 CHK_SV(ctx); 5125 t0 = tcg_temp_new(); 5126 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5127 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5128 #endif /* defined(CONFIG_USER_ONLY) */ 5129 } 5130 5131 /* mtsr */ 5132 static void gen_mtsr(DisasContext *ctx) 5133 { 5134 #if defined(CONFIG_USER_ONLY) 5135 GEN_PRIV(ctx); 5136 #else 5137 TCGv t0; 5138 5139 CHK_SV(ctx); 5140 t0 = tcg_constant_tl(SR(ctx->opcode)); 5141 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5142 #endif /* defined(CONFIG_USER_ONLY) */ 5143 } 5144 5145 /* mtsrin */ 5146 static void gen_mtsrin(DisasContext *ctx) 5147 { 5148 #if defined(CONFIG_USER_ONLY) 5149 GEN_PRIV(ctx); 5150 #else 5151 TCGv t0; 5152 CHK_SV(ctx); 5153 5154 t0 = tcg_temp_new(); 5155 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5156 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5157 #endif /* defined(CONFIG_USER_ONLY) */ 5158 } 5159 5160 #if defined(TARGET_PPC64) 5161 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5162 5163 /* mfsr */ 5164 static void gen_mfsr_64b(DisasContext *ctx) 5165 { 5166 #if defined(CONFIG_USER_ONLY) 5167 GEN_PRIV(ctx); 5168 #else 5169 TCGv t0; 5170 5171 CHK_SV(ctx); 5172 t0 = tcg_constant_tl(SR(ctx->opcode)); 5173 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5174 #endif /* defined(CONFIG_USER_ONLY) */ 5175 } 5176 5177 /* mfsrin */ 5178 static void gen_mfsrin_64b(DisasContext *ctx) 5179 { 5180 #if defined(CONFIG_USER_ONLY) 5181 GEN_PRIV(ctx); 5182 #else 5183 TCGv t0; 5184 5185 CHK_SV(ctx); 5186 t0 = tcg_temp_new(); 5187 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5188 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5189 #endif /* defined(CONFIG_USER_ONLY) */ 5190 } 5191 5192 /* mtsr */ 5193 static void gen_mtsr_64b(DisasContext *ctx) 5194 { 5195 #if defined(CONFIG_USER_ONLY) 5196 GEN_PRIV(ctx); 5197 #else 5198 TCGv t0; 5199 5200 CHK_SV(ctx); 5201 t0 = tcg_constant_tl(SR(ctx->opcode)); 5202 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5203 #endif /* defined(CONFIG_USER_ONLY) */ 5204 } 5205 5206 /* mtsrin */ 5207 static void gen_mtsrin_64b(DisasContext *ctx) 5208 { 5209 #if defined(CONFIG_USER_ONLY) 5210 GEN_PRIV(ctx); 5211 #else 5212 TCGv t0; 5213 5214 CHK_SV(ctx); 5215 t0 = tcg_temp_new(); 5216 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5217 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5218 #endif /* defined(CONFIG_USER_ONLY) */ 5219 } 5220 5221 #endif /* defined(TARGET_PPC64) */ 5222 5223 /*** Lookaside buffer management ***/ 5224 /* Optional & supervisor only: */ 5225 5226 /* tlbia */ 5227 static void gen_tlbia(DisasContext *ctx) 5228 { 5229 #if defined(CONFIG_USER_ONLY) 5230 GEN_PRIV(ctx); 5231 #else 5232 CHK_HV(ctx); 5233 5234 gen_helper_tlbia(cpu_env); 5235 #endif /* defined(CONFIG_USER_ONLY) */ 5236 } 5237 5238 /* tlbsync */ 5239 static void gen_tlbsync(DisasContext *ctx) 5240 { 5241 #if defined(CONFIG_USER_ONLY) 5242 GEN_PRIV(ctx); 5243 #else 5244 5245 if (ctx->gtse) { 5246 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5247 } else { 5248 CHK_HV(ctx); /* Else hypervisor privileged */ 5249 } 5250 5251 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5252 if (ctx->insns_flags & PPC_BOOKE) { 5253 gen_check_tlb_flush(ctx, true); 5254 } 5255 #endif /* defined(CONFIG_USER_ONLY) */ 5256 } 5257 5258 /*** External control ***/ 5259 /* Optional: */ 5260 5261 /* eciwx */ 5262 static void gen_eciwx(DisasContext *ctx) 5263 { 5264 TCGv t0; 5265 /* Should check EAR[E] ! */ 5266 gen_set_access_type(ctx, ACCESS_EXT); 5267 t0 = tcg_temp_new(); 5268 gen_addr_reg_index(ctx, t0); 5269 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5270 DEF_MEMOP(MO_UL | MO_ALIGN)); 5271 } 5272 5273 /* ecowx */ 5274 static void gen_ecowx(DisasContext *ctx) 5275 { 5276 TCGv t0; 5277 /* Should check EAR[E] ! */ 5278 gen_set_access_type(ctx, ACCESS_EXT); 5279 t0 = tcg_temp_new(); 5280 gen_addr_reg_index(ctx, t0); 5281 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5282 DEF_MEMOP(MO_UL | MO_ALIGN)); 5283 } 5284 5285 /* 602 - 603 - G2 TLB management */ 5286 5287 /* tlbld */ 5288 static void gen_tlbld_6xx(DisasContext *ctx) 5289 { 5290 #if defined(CONFIG_USER_ONLY) 5291 GEN_PRIV(ctx); 5292 #else 5293 CHK_SV(ctx); 5294 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5295 #endif /* defined(CONFIG_USER_ONLY) */ 5296 } 5297 5298 /* tlbli */ 5299 static void gen_tlbli_6xx(DisasContext *ctx) 5300 { 5301 #if defined(CONFIG_USER_ONLY) 5302 GEN_PRIV(ctx); 5303 #else 5304 CHK_SV(ctx); 5305 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5306 #endif /* defined(CONFIG_USER_ONLY) */ 5307 } 5308 5309 /* BookE specific instructions */ 5310 5311 /* XXX: not implemented on 440 ? */ 5312 static void gen_mfapidi(DisasContext *ctx) 5313 { 5314 /* XXX: TODO */ 5315 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5316 } 5317 5318 /* XXX: not implemented on 440 ? */ 5319 static void gen_tlbiva(DisasContext *ctx) 5320 { 5321 #if defined(CONFIG_USER_ONLY) 5322 GEN_PRIV(ctx); 5323 #else 5324 TCGv t0; 5325 5326 CHK_SV(ctx); 5327 t0 = tcg_temp_new(); 5328 gen_addr_reg_index(ctx, t0); 5329 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5330 #endif /* defined(CONFIG_USER_ONLY) */ 5331 } 5332 5333 /* All 405 MAC instructions are translated here */ 5334 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5335 int ra, int rb, int rt, int Rc) 5336 { 5337 TCGv t0, t1; 5338 5339 t0 = tcg_temp_new(); 5340 t1 = tcg_temp_new(); 5341 5342 switch (opc3 & 0x0D) { 5343 case 0x05: 5344 /* macchw - macchw. - macchwo - macchwo. */ 5345 /* macchws - macchws. - macchwso - macchwso. */ 5346 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5347 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5348 /* mulchw - mulchw. */ 5349 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5350 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5351 tcg_gen_ext16s_tl(t1, t1); 5352 break; 5353 case 0x04: 5354 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5355 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5356 /* mulchwu - mulchwu. */ 5357 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5358 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5359 tcg_gen_ext16u_tl(t1, t1); 5360 break; 5361 case 0x01: 5362 /* machhw - machhw. - machhwo - machhwo. */ 5363 /* machhws - machhws. - machhwso - machhwso. */ 5364 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5365 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5366 /* mulhhw - mulhhw. */ 5367 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5368 tcg_gen_ext16s_tl(t0, t0); 5369 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5370 tcg_gen_ext16s_tl(t1, t1); 5371 break; 5372 case 0x00: 5373 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5374 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5375 /* mulhhwu - mulhhwu. */ 5376 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5377 tcg_gen_ext16u_tl(t0, t0); 5378 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5379 tcg_gen_ext16u_tl(t1, t1); 5380 break; 5381 case 0x0D: 5382 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5383 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5384 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5385 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5386 /* mullhw - mullhw. */ 5387 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5388 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5389 break; 5390 case 0x0C: 5391 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5392 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5393 /* mullhwu - mullhwu. */ 5394 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5395 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5396 break; 5397 } 5398 if (opc2 & 0x04) { 5399 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5400 tcg_gen_mul_tl(t1, t0, t1); 5401 if (opc2 & 0x02) { 5402 /* nmultiply-and-accumulate (0x0E) */ 5403 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5404 } else { 5405 /* multiply-and-accumulate (0x0C) */ 5406 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5407 } 5408 5409 if (opc3 & 0x12) { 5410 /* Check overflow and/or saturate */ 5411 TCGLabel *l1 = gen_new_label(); 5412 5413 if (opc3 & 0x10) { 5414 /* Start with XER OV disabled, the most likely case */ 5415 tcg_gen_movi_tl(cpu_ov, 0); 5416 } 5417 if (opc3 & 0x01) { 5418 /* Signed */ 5419 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5420 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5421 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5422 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5423 if (opc3 & 0x02) { 5424 /* Saturate */ 5425 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5426 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5427 } 5428 } else { 5429 /* Unsigned */ 5430 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5431 if (opc3 & 0x02) { 5432 /* Saturate */ 5433 tcg_gen_movi_tl(t0, UINT32_MAX); 5434 } 5435 } 5436 if (opc3 & 0x10) { 5437 /* Check overflow */ 5438 tcg_gen_movi_tl(cpu_ov, 1); 5439 tcg_gen_movi_tl(cpu_so, 1); 5440 } 5441 gen_set_label(l1); 5442 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5443 } 5444 } else { 5445 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5446 } 5447 if (unlikely(Rc) != 0) { 5448 /* Update Rc0 */ 5449 gen_set_Rc0(ctx, cpu_gpr[rt]); 5450 } 5451 } 5452 5453 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5454 static void glue(gen_, name)(DisasContext *ctx) \ 5455 { \ 5456 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5457 rD(ctx->opcode), Rc(ctx->opcode)); \ 5458 } 5459 5460 /* macchw - macchw. */ 5461 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5462 /* macchwo - macchwo. */ 5463 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5464 /* macchws - macchws. */ 5465 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5466 /* macchwso - macchwso. */ 5467 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5468 /* macchwsu - macchwsu. */ 5469 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5470 /* macchwsuo - macchwsuo. */ 5471 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5472 /* macchwu - macchwu. */ 5473 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5474 /* macchwuo - macchwuo. */ 5475 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5476 /* machhw - machhw. */ 5477 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5478 /* machhwo - machhwo. */ 5479 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5480 /* machhws - machhws. */ 5481 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5482 /* machhwso - machhwso. */ 5483 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5484 /* machhwsu - machhwsu. */ 5485 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5486 /* machhwsuo - machhwsuo. */ 5487 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5488 /* machhwu - machhwu. */ 5489 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5490 /* machhwuo - machhwuo. */ 5491 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5492 /* maclhw - maclhw. */ 5493 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5494 /* maclhwo - maclhwo. */ 5495 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5496 /* maclhws - maclhws. */ 5497 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5498 /* maclhwso - maclhwso. */ 5499 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5500 /* maclhwu - maclhwu. */ 5501 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5502 /* maclhwuo - maclhwuo. */ 5503 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5504 /* maclhwsu - maclhwsu. */ 5505 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5506 /* maclhwsuo - maclhwsuo. */ 5507 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5508 /* nmacchw - nmacchw. */ 5509 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5510 /* nmacchwo - nmacchwo. */ 5511 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5512 /* nmacchws - nmacchws. */ 5513 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5514 /* nmacchwso - nmacchwso. */ 5515 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5516 /* nmachhw - nmachhw. */ 5517 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5518 /* nmachhwo - nmachhwo. */ 5519 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5520 /* nmachhws - nmachhws. */ 5521 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5522 /* nmachhwso - nmachhwso. */ 5523 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5524 /* nmaclhw - nmaclhw. */ 5525 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5526 /* nmaclhwo - nmaclhwo. */ 5527 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5528 /* nmaclhws - nmaclhws. */ 5529 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5530 /* nmaclhwso - nmaclhwso. */ 5531 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5532 5533 /* mulchw - mulchw. */ 5534 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5535 /* mulchwu - mulchwu. */ 5536 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5537 /* mulhhw - mulhhw. */ 5538 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5539 /* mulhhwu - mulhhwu. */ 5540 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5541 /* mullhw - mullhw. */ 5542 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5543 /* mullhwu - mullhwu. */ 5544 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5545 5546 /* mfdcr */ 5547 static void gen_mfdcr(DisasContext *ctx) 5548 { 5549 #if defined(CONFIG_USER_ONLY) 5550 GEN_PRIV(ctx); 5551 #else 5552 TCGv dcrn; 5553 5554 CHK_SV(ctx); 5555 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5556 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5557 #endif /* defined(CONFIG_USER_ONLY) */ 5558 } 5559 5560 /* mtdcr */ 5561 static void gen_mtdcr(DisasContext *ctx) 5562 { 5563 #if defined(CONFIG_USER_ONLY) 5564 GEN_PRIV(ctx); 5565 #else 5566 TCGv dcrn; 5567 5568 CHK_SV(ctx); 5569 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5570 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5571 #endif /* defined(CONFIG_USER_ONLY) */ 5572 } 5573 5574 /* mfdcrx */ 5575 /* XXX: not implemented on 440 ? */ 5576 static void gen_mfdcrx(DisasContext *ctx) 5577 { 5578 #if defined(CONFIG_USER_ONLY) 5579 GEN_PRIV(ctx); 5580 #else 5581 CHK_SV(ctx); 5582 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5583 cpu_gpr[rA(ctx->opcode)]); 5584 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5585 #endif /* defined(CONFIG_USER_ONLY) */ 5586 } 5587 5588 /* mtdcrx */ 5589 /* XXX: not implemented on 440 ? */ 5590 static void gen_mtdcrx(DisasContext *ctx) 5591 { 5592 #if defined(CONFIG_USER_ONLY) 5593 GEN_PRIV(ctx); 5594 #else 5595 CHK_SV(ctx); 5596 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5597 cpu_gpr[rS(ctx->opcode)]); 5598 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5599 #endif /* defined(CONFIG_USER_ONLY) */ 5600 } 5601 5602 /* dccci */ 5603 static void gen_dccci(DisasContext *ctx) 5604 { 5605 CHK_SV(ctx); 5606 /* interpreted as no-op */ 5607 } 5608 5609 /* dcread */ 5610 static void gen_dcread(DisasContext *ctx) 5611 { 5612 #if defined(CONFIG_USER_ONLY) 5613 GEN_PRIV(ctx); 5614 #else 5615 TCGv EA, val; 5616 5617 CHK_SV(ctx); 5618 gen_set_access_type(ctx, ACCESS_CACHE); 5619 EA = tcg_temp_new(); 5620 gen_addr_reg_index(ctx, EA); 5621 val = tcg_temp_new(); 5622 gen_qemu_ld32u(ctx, val, EA); 5623 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5624 #endif /* defined(CONFIG_USER_ONLY) */ 5625 } 5626 5627 /* icbt */ 5628 static void gen_icbt_40x(DisasContext *ctx) 5629 { 5630 /* 5631 * interpreted as no-op 5632 * XXX: specification say this is treated as a load by the MMU but 5633 * does not generate any exception 5634 */ 5635 } 5636 5637 /* iccci */ 5638 static void gen_iccci(DisasContext *ctx) 5639 { 5640 CHK_SV(ctx); 5641 /* interpreted as no-op */ 5642 } 5643 5644 /* icread */ 5645 static void gen_icread(DisasContext *ctx) 5646 { 5647 CHK_SV(ctx); 5648 /* interpreted as no-op */ 5649 } 5650 5651 /* rfci (supervisor only) */ 5652 static void gen_rfci_40x(DisasContext *ctx) 5653 { 5654 #if defined(CONFIG_USER_ONLY) 5655 GEN_PRIV(ctx); 5656 #else 5657 CHK_SV(ctx); 5658 /* Restore CPU state */ 5659 gen_helper_40x_rfci(cpu_env); 5660 ctx->base.is_jmp = DISAS_EXIT; 5661 #endif /* defined(CONFIG_USER_ONLY) */ 5662 } 5663 5664 static void gen_rfci(DisasContext *ctx) 5665 { 5666 #if defined(CONFIG_USER_ONLY) 5667 GEN_PRIV(ctx); 5668 #else 5669 CHK_SV(ctx); 5670 /* Restore CPU state */ 5671 gen_helper_rfci(cpu_env); 5672 ctx->base.is_jmp = DISAS_EXIT; 5673 #endif /* defined(CONFIG_USER_ONLY) */ 5674 } 5675 5676 /* BookE specific */ 5677 5678 /* XXX: not implemented on 440 ? */ 5679 static void gen_rfdi(DisasContext *ctx) 5680 { 5681 #if defined(CONFIG_USER_ONLY) 5682 GEN_PRIV(ctx); 5683 #else 5684 CHK_SV(ctx); 5685 /* Restore CPU state */ 5686 gen_helper_rfdi(cpu_env); 5687 ctx->base.is_jmp = DISAS_EXIT; 5688 #endif /* defined(CONFIG_USER_ONLY) */ 5689 } 5690 5691 /* XXX: not implemented on 440 ? */ 5692 static void gen_rfmci(DisasContext *ctx) 5693 { 5694 #if defined(CONFIG_USER_ONLY) 5695 GEN_PRIV(ctx); 5696 #else 5697 CHK_SV(ctx); 5698 /* Restore CPU state */ 5699 gen_helper_rfmci(cpu_env); 5700 ctx->base.is_jmp = DISAS_EXIT; 5701 #endif /* defined(CONFIG_USER_ONLY) */ 5702 } 5703 5704 /* TLB management - PowerPC 405 implementation */ 5705 5706 /* tlbre */ 5707 static void gen_tlbre_40x(DisasContext *ctx) 5708 { 5709 #if defined(CONFIG_USER_ONLY) 5710 GEN_PRIV(ctx); 5711 #else 5712 CHK_SV(ctx); 5713 switch (rB(ctx->opcode)) { 5714 case 0: 5715 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5716 cpu_gpr[rA(ctx->opcode)]); 5717 break; 5718 case 1: 5719 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5720 cpu_gpr[rA(ctx->opcode)]); 5721 break; 5722 default: 5723 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5724 break; 5725 } 5726 #endif /* defined(CONFIG_USER_ONLY) */ 5727 } 5728 5729 /* tlbsx - tlbsx. */ 5730 static void gen_tlbsx_40x(DisasContext *ctx) 5731 { 5732 #if defined(CONFIG_USER_ONLY) 5733 GEN_PRIV(ctx); 5734 #else 5735 TCGv t0; 5736 5737 CHK_SV(ctx); 5738 t0 = tcg_temp_new(); 5739 gen_addr_reg_index(ctx, t0); 5740 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5741 if (Rc(ctx->opcode)) { 5742 TCGLabel *l1 = gen_new_label(); 5743 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5744 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5745 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5746 gen_set_label(l1); 5747 } 5748 #endif /* defined(CONFIG_USER_ONLY) */ 5749 } 5750 5751 /* tlbwe */ 5752 static void gen_tlbwe_40x(DisasContext *ctx) 5753 { 5754 #if defined(CONFIG_USER_ONLY) 5755 GEN_PRIV(ctx); 5756 #else 5757 CHK_SV(ctx); 5758 5759 switch (rB(ctx->opcode)) { 5760 case 0: 5761 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5762 cpu_gpr[rS(ctx->opcode)]); 5763 break; 5764 case 1: 5765 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5766 cpu_gpr[rS(ctx->opcode)]); 5767 break; 5768 default: 5769 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5770 break; 5771 } 5772 #endif /* defined(CONFIG_USER_ONLY) */ 5773 } 5774 5775 /* TLB management - PowerPC 440 implementation */ 5776 5777 /* tlbre */ 5778 static void gen_tlbre_440(DisasContext *ctx) 5779 { 5780 #if defined(CONFIG_USER_ONLY) 5781 GEN_PRIV(ctx); 5782 #else 5783 CHK_SV(ctx); 5784 5785 switch (rB(ctx->opcode)) { 5786 case 0: 5787 case 1: 5788 case 2: 5789 { 5790 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5791 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5792 t0, cpu_gpr[rA(ctx->opcode)]); 5793 } 5794 break; 5795 default: 5796 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5797 break; 5798 } 5799 #endif /* defined(CONFIG_USER_ONLY) */ 5800 } 5801 5802 /* tlbsx - tlbsx. */ 5803 static void gen_tlbsx_440(DisasContext *ctx) 5804 { 5805 #if defined(CONFIG_USER_ONLY) 5806 GEN_PRIV(ctx); 5807 #else 5808 TCGv t0; 5809 5810 CHK_SV(ctx); 5811 t0 = tcg_temp_new(); 5812 gen_addr_reg_index(ctx, t0); 5813 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5814 if (Rc(ctx->opcode)) { 5815 TCGLabel *l1 = gen_new_label(); 5816 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5817 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5818 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5819 gen_set_label(l1); 5820 } 5821 #endif /* defined(CONFIG_USER_ONLY) */ 5822 } 5823 5824 /* tlbwe */ 5825 static void gen_tlbwe_440(DisasContext *ctx) 5826 { 5827 #if defined(CONFIG_USER_ONLY) 5828 GEN_PRIV(ctx); 5829 #else 5830 CHK_SV(ctx); 5831 switch (rB(ctx->opcode)) { 5832 case 0: 5833 case 1: 5834 case 2: 5835 { 5836 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5837 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5838 cpu_gpr[rS(ctx->opcode)]); 5839 } 5840 break; 5841 default: 5842 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5843 break; 5844 } 5845 #endif /* defined(CONFIG_USER_ONLY) */ 5846 } 5847 5848 /* TLB management - PowerPC BookE 2.06 implementation */ 5849 5850 /* tlbre */ 5851 static void gen_tlbre_booke206(DisasContext *ctx) 5852 { 5853 #if defined(CONFIG_USER_ONLY) 5854 GEN_PRIV(ctx); 5855 #else 5856 CHK_SV(ctx); 5857 gen_helper_booke206_tlbre(cpu_env); 5858 #endif /* defined(CONFIG_USER_ONLY) */ 5859 } 5860 5861 /* tlbsx - tlbsx. */ 5862 static void gen_tlbsx_booke206(DisasContext *ctx) 5863 { 5864 #if defined(CONFIG_USER_ONLY) 5865 GEN_PRIV(ctx); 5866 #else 5867 TCGv t0; 5868 5869 CHK_SV(ctx); 5870 if (rA(ctx->opcode)) { 5871 t0 = tcg_temp_new(); 5872 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5873 } else { 5874 t0 = cpu_gpr[rB(ctx->opcode)]; 5875 } 5876 gen_helper_booke206_tlbsx(cpu_env, t0); 5877 #endif /* defined(CONFIG_USER_ONLY) */ 5878 } 5879 5880 /* tlbwe */ 5881 static void gen_tlbwe_booke206(DisasContext *ctx) 5882 { 5883 #if defined(CONFIG_USER_ONLY) 5884 GEN_PRIV(ctx); 5885 #else 5886 CHK_SV(ctx); 5887 gen_helper_booke206_tlbwe(cpu_env); 5888 #endif /* defined(CONFIG_USER_ONLY) */ 5889 } 5890 5891 static void gen_tlbivax_booke206(DisasContext *ctx) 5892 { 5893 #if defined(CONFIG_USER_ONLY) 5894 GEN_PRIV(ctx); 5895 #else 5896 TCGv t0; 5897 5898 CHK_SV(ctx); 5899 t0 = tcg_temp_new(); 5900 gen_addr_reg_index(ctx, t0); 5901 gen_helper_booke206_tlbivax(cpu_env, t0); 5902 #endif /* defined(CONFIG_USER_ONLY) */ 5903 } 5904 5905 static void gen_tlbilx_booke206(DisasContext *ctx) 5906 { 5907 #if defined(CONFIG_USER_ONLY) 5908 GEN_PRIV(ctx); 5909 #else 5910 TCGv t0; 5911 5912 CHK_SV(ctx); 5913 t0 = tcg_temp_new(); 5914 gen_addr_reg_index(ctx, t0); 5915 5916 switch ((ctx->opcode >> 21) & 0x3) { 5917 case 0: 5918 gen_helper_booke206_tlbilx0(cpu_env, t0); 5919 break; 5920 case 1: 5921 gen_helper_booke206_tlbilx1(cpu_env, t0); 5922 break; 5923 case 3: 5924 gen_helper_booke206_tlbilx3(cpu_env, t0); 5925 break; 5926 default: 5927 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5928 break; 5929 } 5930 #endif /* defined(CONFIG_USER_ONLY) */ 5931 } 5932 5933 /* wrtee */ 5934 static void gen_wrtee(DisasContext *ctx) 5935 { 5936 #if defined(CONFIG_USER_ONLY) 5937 GEN_PRIV(ctx); 5938 #else 5939 TCGv t0; 5940 5941 CHK_SV(ctx); 5942 t0 = tcg_temp_new(); 5943 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5944 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5945 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5946 gen_ppc_maybe_interrupt(ctx); 5947 /* 5948 * Stop translation to have a chance to raise an exception if we 5949 * just set msr_ee to 1 5950 */ 5951 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5952 #endif /* defined(CONFIG_USER_ONLY) */ 5953 } 5954 5955 /* wrteei */ 5956 static void gen_wrteei(DisasContext *ctx) 5957 { 5958 #if defined(CONFIG_USER_ONLY) 5959 GEN_PRIV(ctx); 5960 #else 5961 CHK_SV(ctx); 5962 if (ctx->opcode & 0x00008000) { 5963 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5964 gen_ppc_maybe_interrupt(ctx); 5965 /* Stop translation to have a chance to raise an exception */ 5966 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5967 } else { 5968 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5969 } 5970 #endif /* defined(CONFIG_USER_ONLY) */ 5971 } 5972 5973 /* PowerPC 440 specific instructions */ 5974 5975 /* dlmzb */ 5976 static void gen_dlmzb(DisasContext *ctx) 5977 { 5978 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5979 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 5980 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5981 } 5982 5983 /* mbar replaces eieio on 440 */ 5984 static void gen_mbar(DisasContext *ctx) 5985 { 5986 /* interpreted as no-op */ 5987 } 5988 5989 /* msync replaces sync on 440 */ 5990 static void gen_msync_4xx(DisasContext *ctx) 5991 { 5992 /* Only e500 seems to treat reserved bits as invalid */ 5993 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 5994 (ctx->opcode & 0x03FFF801)) { 5995 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5996 } 5997 /* otherwise interpreted as no-op */ 5998 } 5999 6000 /* icbt */ 6001 static void gen_icbt_440(DisasContext *ctx) 6002 { 6003 /* 6004 * interpreted as no-op 6005 * XXX: specification say this is treated as a load by the MMU but 6006 * does not generate any exception 6007 */ 6008 } 6009 6010 #if defined(TARGET_PPC64) 6011 static void gen_maddld(DisasContext *ctx) 6012 { 6013 TCGv_i64 t1 = tcg_temp_new_i64(); 6014 6015 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6016 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6017 } 6018 6019 /* maddhd maddhdu */ 6020 static void gen_maddhd_maddhdu(DisasContext *ctx) 6021 { 6022 TCGv_i64 lo = tcg_temp_new_i64(); 6023 TCGv_i64 hi = tcg_temp_new_i64(); 6024 TCGv_i64 t1 = tcg_temp_new_i64(); 6025 6026 if (Rc(ctx->opcode)) { 6027 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6028 cpu_gpr[rB(ctx->opcode)]); 6029 tcg_gen_movi_i64(t1, 0); 6030 } else { 6031 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6032 cpu_gpr[rB(ctx->opcode)]); 6033 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6034 } 6035 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6036 cpu_gpr[rC(ctx->opcode)], t1); 6037 } 6038 #endif /* defined(TARGET_PPC64) */ 6039 6040 static void gen_tbegin(DisasContext *ctx) 6041 { 6042 if (unlikely(!ctx->tm_enabled)) { 6043 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6044 return; 6045 } 6046 gen_helper_tbegin(cpu_env); 6047 } 6048 6049 #define GEN_TM_NOOP(name) \ 6050 static inline void gen_##name(DisasContext *ctx) \ 6051 { \ 6052 if (unlikely(!ctx->tm_enabled)) { \ 6053 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6054 return; \ 6055 } \ 6056 /* \ 6057 * Because tbegin always fails in QEMU, these user \ 6058 * space instructions all have a simple implementation: \ 6059 * \ 6060 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6061 * = 0b0 || 0b00 || 0b0 \ 6062 */ \ 6063 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6064 } 6065 6066 GEN_TM_NOOP(tend); 6067 GEN_TM_NOOP(tabort); 6068 GEN_TM_NOOP(tabortwc); 6069 GEN_TM_NOOP(tabortwci); 6070 GEN_TM_NOOP(tabortdc); 6071 GEN_TM_NOOP(tabortdci); 6072 GEN_TM_NOOP(tsr); 6073 6074 static inline void gen_cp_abort(DisasContext *ctx) 6075 { 6076 /* Do Nothing */ 6077 } 6078 6079 #define GEN_CP_PASTE_NOOP(name) \ 6080 static inline void gen_##name(DisasContext *ctx) \ 6081 { \ 6082 /* \ 6083 * Generate invalid exception until we have an \ 6084 * implementation of the copy paste facility \ 6085 */ \ 6086 gen_invalid(ctx); \ 6087 } 6088 6089 GEN_CP_PASTE_NOOP(copy) 6090 GEN_CP_PASTE_NOOP(paste) 6091 6092 static void gen_tcheck(DisasContext *ctx) 6093 { 6094 if (unlikely(!ctx->tm_enabled)) { 6095 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6096 return; 6097 } 6098 /* 6099 * Because tbegin always fails, the tcheck implementation is 6100 * simple: 6101 * 6102 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6103 * = 0b1 || 0b00 || 0b0 6104 */ 6105 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6106 } 6107 6108 #if defined(CONFIG_USER_ONLY) 6109 #define GEN_TM_PRIV_NOOP(name) \ 6110 static inline void gen_##name(DisasContext *ctx) \ 6111 { \ 6112 gen_priv_opc(ctx); \ 6113 } 6114 6115 #else 6116 6117 #define GEN_TM_PRIV_NOOP(name) \ 6118 static inline void gen_##name(DisasContext *ctx) \ 6119 { \ 6120 CHK_SV(ctx); \ 6121 if (unlikely(!ctx->tm_enabled)) { \ 6122 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6123 return; \ 6124 } \ 6125 /* \ 6126 * Because tbegin always fails, the implementation is \ 6127 * simple: \ 6128 * \ 6129 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6130 * = 0b0 || 0b00 | 0b0 \ 6131 */ \ 6132 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6133 } 6134 6135 #endif 6136 6137 GEN_TM_PRIV_NOOP(treclaim); 6138 GEN_TM_PRIV_NOOP(trechkpt); 6139 6140 static inline void get_fpr(TCGv_i64 dst, int regno) 6141 { 6142 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6143 } 6144 6145 static inline void set_fpr(int regno, TCGv_i64 src) 6146 { 6147 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6148 /* 6149 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6150 * corresponding to the target FPR was undefined. However, 6151 * most (if not all) real hardware were setting the result to 0. 6152 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6153 * to be 0. 6154 */ 6155 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6156 } 6157 6158 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6159 { 6160 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6161 } 6162 6163 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6164 { 6165 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6166 } 6167 6168 /* 6169 * Helpers for decodetree used by !function for decoding arguments. 6170 */ 6171 static int times_2(DisasContext *ctx, int x) 6172 { 6173 return x * 2; 6174 } 6175 6176 static int times_4(DisasContext *ctx, int x) 6177 { 6178 return x * 4; 6179 } 6180 6181 static int times_16(DisasContext *ctx, int x) 6182 { 6183 return x * 16; 6184 } 6185 6186 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6187 { 6188 return deposit64(0xfffffffffffffe00, 3, 6, x); 6189 } 6190 6191 /* 6192 * Helpers for trans_* functions to check for specific insns flags. 6193 * Use token pasting to ensure that we use the proper flag with the 6194 * proper variable. 6195 */ 6196 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6197 do { \ 6198 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6199 return false; \ 6200 } \ 6201 } while (0) 6202 6203 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6204 do { \ 6205 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6206 return false; \ 6207 } \ 6208 } while (0) 6209 6210 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6211 #if TARGET_LONG_BITS == 32 6212 # define REQUIRE_64BIT(CTX) return false 6213 #else 6214 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6215 #endif 6216 6217 #define REQUIRE_VECTOR(CTX) \ 6218 do { \ 6219 if (unlikely(!(CTX)->altivec_enabled)) { \ 6220 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6221 return true; \ 6222 } \ 6223 } while (0) 6224 6225 #define REQUIRE_VSX(CTX) \ 6226 do { \ 6227 if (unlikely(!(CTX)->vsx_enabled)) { \ 6228 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6229 return true; \ 6230 } \ 6231 } while (0) 6232 6233 #define REQUIRE_FPU(ctx) \ 6234 do { \ 6235 if (unlikely(!(ctx)->fpu_enabled)) { \ 6236 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6237 return true; \ 6238 } \ 6239 } while (0) 6240 6241 #if !defined(CONFIG_USER_ONLY) 6242 #define REQUIRE_SV(CTX) \ 6243 do { \ 6244 if (unlikely((CTX)->pr)) { \ 6245 gen_priv_opc(CTX); \ 6246 return true; \ 6247 } \ 6248 } while (0) 6249 6250 #define REQUIRE_HV(CTX) \ 6251 do { \ 6252 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6253 gen_priv_opc(CTX); \ 6254 return true; \ 6255 } \ 6256 } while (0) 6257 #else 6258 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6259 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6260 #endif 6261 6262 /* 6263 * Helpers for implementing sets of trans_* functions. 6264 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6265 */ 6266 #define TRANS(NAME, FUNC, ...) \ 6267 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6268 { return FUNC(ctx, a, __VA_ARGS__); } 6269 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6270 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6271 { \ 6272 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6273 return FUNC(ctx, a, __VA_ARGS__); \ 6274 } 6275 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6276 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6277 { \ 6278 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6279 return FUNC(ctx, a, __VA_ARGS__); \ 6280 } 6281 6282 #define TRANS64(NAME, FUNC, ...) \ 6283 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6284 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6285 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6286 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6287 { \ 6288 REQUIRE_64BIT(ctx); \ 6289 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6290 return FUNC(ctx, a, __VA_ARGS__); \ 6291 } 6292 6293 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6294 6295 6296 #include "decode-insn32.c.inc" 6297 #include "decode-insn64.c.inc" 6298 #include "power8-pmu-regs.c.inc" 6299 6300 /* 6301 * Incorporate CIA into the constant when R=1. 6302 * Validate that when R=1, RA=0. 6303 */ 6304 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6305 { 6306 d->rt = a->rt; 6307 d->ra = a->ra; 6308 d->si = a->si; 6309 if (a->r) { 6310 if (unlikely(a->ra != 0)) { 6311 gen_invalid(ctx); 6312 return false; 6313 } 6314 d->si += ctx->cia; 6315 } 6316 return true; 6317 } 6318 6319 #include "translate/fixedpoint-impl.c.inc" 6320 6321 #include "translate/fp-impl.c.inc" 6322 6323 #include "translate/vmx-impl.c.inc" 6324 6325 #include "translate/vsx-impl.c.inc" 6326 6327 #include "translate/dfp-impl.c.inc" 6328 6329 #include "translate/spe-impl.c.inc" 6330 6331 #include "translate/branch-impl.c.inc" 6332 6333 #include "translate/processor-ctrl-impl.c.inc" 6334 6335 #include "translate/storage-ctrl-impl.c.inc" 6336 6337 /* Handles lfdp */ 6338 static void gen_dform39(DisasContext *ctx) 6339 { 6340 if ((ctx->opcode & 0x3) == 0) { 6341 if (ctx->insns_flags2 & PPC2_ISA205) { 6342 return gen_lfdp(ctx); 6343 } 6344 } 6345 return gen_invalid(ctx); 6346 } 6347 6348 /* Handles stfdp */ 6349 static void gen_dform3D(DisasContext *ctx) 6350 { 6351 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6352 /* stfdp */ 6353 if (ctx->insns_flags2 & PPC2_ISA205) { 6354 return gen_stfdp(ctx); 6355 } 6356 } 6357 return gen_invalid(ctx); 6358 } 6359 6360 #if defined(TARGET_PPC64) 6361 /* brd */ 6362 static void gen_brd(DisasContext *ctx) 6363 { 6364 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6365 } 6366 6367 /* brw */ 6368 static void gen_brw(DisasContext *ctx) 6369 { 6370 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6371 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6372 6373 } 6374 6375 /* brh */ 6376 static void gen_brh(DisasContext *ctx) 6377 { 6378 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6379 TCGv_i64 t1 = tcg_temp_new_i64(); 6380 TCGv_i64 t2 = tcg_temp_new_i64(); 6381 6382 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6383 tcg_gen_and_i64(t2, t1, mask); 6384 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6385 tcg_gen_shli_i64(t1, t1, 8); 6386 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6387 } 6388 #endif 6389 6390 static opcode_t opcodes[] = { 6391 #if defined(TARGET_PPC64) 6392 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6393 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6394 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6395 #endif 6396 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6397 #if defined(TARGET_PPC64) 6398 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6399 #endif 6400 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6401 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6402 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6403 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6404 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6405 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6406 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6407 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6408 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6409 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6410 #if defined(TARGET_PPC64) 6411 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6412 #endif 6413 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6414 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6415 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6416 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6417 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6418 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6419 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6420 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6421 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6422 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6423 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6424 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6425 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6426 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6427 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6428 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6429 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6430 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6431 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6432 #if defined(TARGET_PPC64) 6433 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6434 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6435 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6436 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6437 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6438 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6439 #endif 6440 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6441 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6442 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6443 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6444 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6445 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6446 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6447 #if defined(TARGET_PPC64) 6448 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6449 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6450 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6451 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6452 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6453 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6454 PPC_NONE, PPC2_ISA300), 6455 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6456 PPC_NONE, PPC2_ISA300), 6457 #endif 6458 /* handles lfdp, lxsd, lxssp */ 6459 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6460 /* handles stfdp, stxsd, stxssp */ 6461 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6462 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6464 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6465 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6466 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6467 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6468 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6469 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6470 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6471 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6472 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6473 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6474 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6475 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6476 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6477 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6478 #if defined(TARGET_PPC64) 6479 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6480 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6481 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6482 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6483 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6484 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6485 #endif 6486 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6487 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6488 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6489 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6490 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6491 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6492 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6493 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6494 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6495 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6496 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6497 #if defined(TARGET_PPC64) 6498 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6499 #if !defined(CONFIG_USER_ONLY) 6500 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6501 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6502 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6503 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6504 #endif 6505 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6506 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6507 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6508 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6509 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6510 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6511 #endif 6512 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6513 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6514 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6515 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6516 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6517 #if defined(TARGET_PPC64) 6518 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6519 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6520 #endif 6521 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6522 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6523 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6524 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6525 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6526 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6527 #if defined(TARGET_PPC64) 6528 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6529 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6530 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6531 #endif 6532 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6533 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6534 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6535 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6536 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6537 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6538 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6539 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6540 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6541 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6542 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6543 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6544 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6545 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6546 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6547 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6548 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6549 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6550 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6551 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6552 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6553 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6554 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6555 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6556 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6557 #if defined(TARGET_PPC64) 6558 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6559 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6560 PPC_SEGMENT_64B), 6561 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6562 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6563 PPC_SEGMENT_64B), 6564 #endif 6565 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6566 /* 6567 * XXX Those instructions will need to be handled differently for 6568 * different ISA versions 6569 */ 6570 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6571 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6572 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6573 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6574 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6575 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6576 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6577 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6578 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6579 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6580 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6581 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6582 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6583 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6584 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6585 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6586 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6587 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6588 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6589 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6590 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6591 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6592 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6593 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6594 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6595 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6596 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6597 PPC_NONE, PPC2_BOOKE206), 6598 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6599 PPC_NONE, PPC2_BOOKE206), 6600 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6601 PPC_NONE, PPC2_BOOKE206), 6602 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6603 PPC_NONE, PPC2_BOOKE206), 6604 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6605 PPC_NONE, PPC2_BOOKE206), 6606 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6607 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6608 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6609 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6610 PPC_BOOKE, PPC2_BOOKE206), 6611 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6612 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6613 PPC_BOOKE, PPC2_BOOKE206), 6614 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6615 PPC_440_SPEC), 6616 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6617 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6618 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6619 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6620 #if defined(TARGET_PPC64) 6621 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6622 PPC2_ISA300), 6623 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6624 #endif 6625 6626 #undef GEN_INT_ARITH_ADD 6627 #undef GEN_INT_ARITH_ADD_CONST 6628 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6629 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6630 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6631 add_ca, compute_ca, compute_ov) \ 6632 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6633 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6634 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6635 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6636 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6637 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6638 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6639 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6640 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6641 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6642 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6643 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6644 6645 #undef GEN_INT_ARITH_DIVW 6646 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6647 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6648 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6649 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6650 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6651 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6652 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6653 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6654 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6655 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6656 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6657 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6658 6659 #if defined(TARGET_PPC64) 6660 #undef GEN_INT_ARITH_DIVD 6661 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6662 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6663 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6664 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6665 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6666 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6667 6668 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6669 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6670 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6671 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6672 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6673 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6674 6675 #undef GEN_INT_ARITH_MUL_HELPER 6676 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6677 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6678 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6679 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6680 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6681 #endif 6682 6683 #undef GEN_INT_ARITH_SUBF 6684 #undef GEN_INT_ARITH_SUBF_CONST 6685 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6686 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6687 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6688 add_ca, compute_ca, compute_ov) \ 6689 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6690 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6691 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6692 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6693 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6694 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6695 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6696 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6697 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6698 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6699 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6700 6701 #undef GEN_LOGICAL1 6702 #undef GEN_LOGICAL2 6703 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6704 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6705 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6706 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6707 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6708 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6709 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6710 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6711 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6712 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6713 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6714 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6715 #if defined(TARGET_PPC64) 6716 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6717 #endif 6718 6719 #if defined(TARGET_PPC64) 6720 #undef GEN_PPC64_R2 6721 #undef GEN_PPC64_R4 6722 #define GEN_PPC64_R2(name, opc1, opc2) \ 6723 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6724 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6725 PPC_64B) 6726 #define GEN_PPC64_R4(name, opc1, opc2) \ 6727 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6728 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6729 PPC_64B), \ 6730 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6731 PPC_64B), \ 6732 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6733 PPC_64B) 6734 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6735 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6736 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6737 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6738 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6739 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6740 #endif 6741 6742 #undef GEN_LDX_E 6743 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6744 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6745 6746 #if defined(TARGET_PPC64) 6747 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6748 6749 /* HV/P7 and later only */ 6750 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6751 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6752 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6753 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6754 #endif 6755 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6756 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6757 6758 /* External PID based load */ 6759 #undef GEN_LDEPX 6760 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6761 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6762 0x00000001, PPC_NONE, PPC2_BOOKE206), 6763 6764 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6765 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6766 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6767 #if defined(TARGET_PPC64) 6768 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6769 #endif 6770 6771 #undef GEN_STX_E 6772 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6773 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6774 6775 #if defined(TARGET_PPC64) 6776 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6777 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6778 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6779 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6780 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6781 #endif 6782 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6783 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6784 6785 #undef GEN_STEPX 6786 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6787 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6788 0x00000001, PPC_NONE, PPC2_BOOKE206), 6789 6790 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6791 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6792 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6793 #if defined(TARGET_PPC64) 6794 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6795 #endif 6796 6797 #undef GEN_CRLOGIC 6798 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6799 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6800 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6801 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6802 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6803 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6804 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6805 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6806 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6807 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6808 6809 #undef GEN_MAC_HANDLER 6810 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6811 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6812 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6813 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6814 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6815 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6816 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6817 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6818 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6819 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6820 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6821 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6822 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6823 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6824 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6825 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6826 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6827 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6828 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6829 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6830 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6831 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6832 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6833 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6834 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6835 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6836 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6837 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6838 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6839 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6840 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6841 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6842 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6843 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6844 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6845 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6846 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6847 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6848 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6849 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6850 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6851 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6852 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6853 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6854 6855 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6856 PPC_NONE, PPC2_TM), 6857 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6858 PPC_NONE, PPC2_TM), 6859 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6860 PPC_NONE, PPC2_TM), 6861 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6862 PPC_NONE, PPC2_TM), 6863 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6864 PPC_NONE, PPC2_TM), 6865 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6866 PPC_NONE, PPC2_TM), 6867 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6868 PPC_NONE, PPC2_TM), 6869 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6870 PPC_NONE, PPC2_TM), 6871 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6872 PPC_NONE, PPC2_TM), 6873 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6874 PPC_NONE, PPC2_TM), 6875 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6876 PPC_NONE, PPC2_TM), 6877 6878 #include "translate/fp-ops.c.inc" 6879 6880 #include "translate/vmx-ops.c.inc" 6881 6882 #include "translate/vsx-ops.c.inc" 6883 6884 #include "translate/spe-ops.c.inc" 6885 }; 6886 6887 /*****************************************************************************/ 6888 /* Opcode types */ 6889 enum { 6890 PPC_DIRECT = 0, /* Opcode routine */ 6891 PPC_INDIRECT = 1, /* Indirect opcode table */ 6892 }; 6893 6894 #define PPC_OPCODE_MASK 0x3 6895 6896 static inline int is_indirect_opcode(void *handler) 6897 { 6898 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6899 } 6900 6901 static inline opc_handler_t **ind_table(void *handler) 6902 { 6903 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6904 } 6905 6906 /* Instruction table creation */ 6907 /* Opcodes tables creation */ 6908 static void fill_new_table(opc_handler_t **table, int len) 6909 { 6910 int i; 6911 6912 for (i = 0; i < len; i++) { 6913 table[i] = &invalid_handler; 6914 } 6915 } 6916 6917 static int create_new_table(opc_handler_t **table, unsigned char idx) 6918 { 6919 opc_handler_t **tmp; 6920 6921 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6922 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6923 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6924 6925 return 0; 6926 } 6927 6928 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6929 opc_handler_t *handler) 6930 { 6931 if (table[idx] != &invalid_handler) { 6932 return -1; 6933 } 6934 table[idx] = handler; 6935 6936 return 0; 6937 } 6938 6939 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6940 unsigned char idx, opc_handler_t *handler) 6941 { 6942 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6943 printf("*** ERROR: opcode %02x already assigned in main " 6944 "opcode table\n", idx); 6945 return -1; 6946 } 6947 6948 return 0; 6949 } 6950 6951 static int register_ind_in_table(opc_handler_t **table, 6952 unsigned char idx1, unsigned char idx2, 6953 opc_handler_t *handler) 6954 { 6955 if (table[idx1] == &invalid_handler) { 6956 if (create_new_table(table, idx1) < 0) { 6957 printf("*** ERROR: unable to create indirect table " 6958 "idx=%02x\n", idx1); 6959 return -1; 6960 } 6961 } else { 6962 if (!is_indirect_opcode(table[idx1])) { 6963 printf("*** ERROR: idx %02x already assigned to a direct " 6964 "opcode\n", idx1); 6965 return -1; 6966 } 6967 } 6968 if (handler != NULL && 6969 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6970 printf("*** ERROR: opcode %02x already assigned in " 6971 "opcode table %02x\n", idx2, idx1); 6972 return -1; 6973 } 6974 6975 return 0; 6976 } 6977 6978 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6979 unsigned char idx1, unsigned char idx2, 6980 opc_handler_t *handler) 6981 { 6982 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6983 } 6984 6985 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6986 unsigned char idx1, unsigned char idx2, 6987 unsigned char idx3, opc_handler_t *handler) 6988 { 6989 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6990 printf("*** ERROR: unable to join indirect table idx " 6991 "[%02x-%02x]\n", idx1, idx2); 6992 return -1; 6993 } 6994 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6995 handler) < 0) { 6996 printf("*** ERROR: unable to insert opcode " 6997 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6998 return -1; 6999 } 7000 7001 return 0; 7002 } 7003 7004 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7005 unsigned char idx1, unsigned char idx2, 7006 unsigned char idx3, unsigned char idx4, 7007 opc_handler_t *handler) 7008 { 7009 opc_handler_t **table; 7010 7011 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7012 printf("*** ERROR: unable to join indirect table idx " 7013 "[%02x-%02x]\n", idx1, idx2); 7014 return -1; 7015 } 7016 table = ind_table(ppc_opcodes[idx1]); 7017 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7018 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7019 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7020 return -1; 7021 } 7022 table = ind_table(table[idx2]); 7023 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7024 printf("*** ERROR: unable to insert opcode " 7025 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7026 return -1; 7027 } 7028 return 0; 7029 } 7030 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7031 { 7032 if (insn->opc2 != 0xFF) { 7033 if (insn->opc3 != 0xFF) { 7034 if (insn->opc4 != 0xFF) { 7035 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7036 insn->opc3, insn->opc4, 7037 &insn->handler) < 0) { 7038 return -1; 7039 } 7040 } else { 7041 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7042 insn->opc3, &insn->handler) < 0) { 7043 return -1; 7044 } 7045 } 7046 } else { 7047 if (register_ind_insn(ppc_opcodes, insn->opc1, 7048 insn->opc2, &insn->handler) < 0) { 7049 return -1; 7050 } 7051 } 7052 } else { 7053 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7054 return -1; 7055 } 7056 } 7057 7058 return 0; 7059 } 7060 7061 static int test_opcode_table(opc_handler_t **table, int len) 7062 { 7063 int i, count, tmp; 7064 7065 for (i = 0, count = 0; i < len; i++) { 7066 /* Consistency fixup */ 7067 if (table[i] == NULL) { 7068 table[i] = &invalid_handler; 7069 } 7070 if (table[i] != &invalid_handler) { 7071 if (is_indirect_opcode(table[i])) { 7072 tmp = test_opcode_table(ind_table(table[i]), 7073 PPC_CPU_INDIRECT_OPCODES_LEN); 7074 if (tmp == 0) { 7075 free(table[i]); 7076 table[i] = &invalid_handler; 7077 } else { 7078 count++; 7079 } 7080 } else { 7081 count++; 7082 } 7083 } 7084 } 7085 7086 return count; 7087 } 7088 7089 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7090 { 7091 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7092 printf("*** WARNING: no opcode defined !\n"); 7093 } 7094 } 7095 7096 /*****************************************************************************/ 7097 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7098 { 7099 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7100 opcode_t *opc; 7101 7102 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7103 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7104 if (((opc->handler.type & pcc->insns_flags) != 0) || 7105 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7106 if (register_insn(cpu->opcodes, opc) < 0) { 7107 error_setg(errp, "ERROR initializing PowerPC instruction " 7108 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7109 opc->opc3); 7110 return; 7111 } 7112 } 7113 } 7114 fix_opcode_tables(cpu->opcodes); 7115 fflush(stdout); 7116 fflush(stderr); 7117 } 7118 7119 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7120 { 7121 opc_handler_t **table, **table_2; 7122 int i, j, k; 7123 7124 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7125 if (cpu->opcodes[i] == &invalid_handler) { 7126 continue; 7127 } 7128 if (is_indirect_opcode(cpu->opcodes[i])) { 7129 table = ind_table(cpu->opcodes[i]); 7130 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7131 if (table[j] == &invalid_handler) { 7132 continue; 7133 } 7134 if (is_indirect_opcode(table[j])) { 7135 table_2 = ind_table(table[j]); 7136 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7137 if (table_2[k] != &invalid_handler && 7138 is_indirect_opcode(table_2[k])) { 7139 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7140 ~PPC_INDIRECT)); 7141 } 7142 } 7143 g_free((opc_handler_t *)((uintptr_t)table[j] & 7144 ~PPC_INDIRECT)); 7145 } 7146 } 7147 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7148 ~PPC_INDIRECT)); 7149 } 7150 } 7151 } 7152 7153 int ppc_fixup_cpu(PowerPCCPU *cpu) 7154 { 7155 CPUPPCState *env = &cpu->env; 7156 7157 /* 7158 * TCG doesn't (yet) emulate some groups of instructions that are 7159 * implemented on some otherwise supported CPUs (e.g. VSX and 7160 * decimal floating point instructions on POWER7). We remove 7161 * unsupported instruction groups from the cpu state's instruction 7162 * masks and hope the guest can cope. For at least the pseries 7163 * machine, the unavailability of these instructions can be 7164 * advertised to the guest via the device tree. 7165 */ 7166 if ((env->insns_flags & ~PPC_TCG_INSNS) 7167 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7168 warn_report("Disabling some instructions which are not " 7169 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7170 env->insns_flags & ~PPC_TCG_INSNS, 7171 env->insns_flags2 & ~PPC_TCG_INSNS2); 7172 } 7173 env->insns_flags &= PPC_TCG_INSNS; 7174 env->insns_flags2 &= PPC_TCG_INSNS2; 7175 return 0; 7176 } 7177 7178 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7179 { 7180 opc_handler_t **table, *handler; 7181 uint32_t inval; 7182 7183 ctx->opcode = insn; 7184 7185 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7186 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7187 ctx->le_mode ? "little" : "big"); 7188 7189 table = cpu->opcodes; 7190 handler = table[opc1(insn)]; 7191 if (is_indirect_opcode(handler)) { 7192 table = ind_table(handler); 7193 handler = table[opc2(insn)]; 7194 if (is_indirect_opcode(handler)) { 7195 table = ind_table(handler); 7196 handler = table[opc3(insn)]; 7197 if (is_indirect_opcode(handler)) { 7198 table = ind_table(handler); 7199 handler = table[opc4(insn)]; 7200 } 7201 } 7202 } 7203 7204 /* Is opcode *REALLY* valid ? */ 7205 if (unlikely(handler->handler == &gen_invalid)) { 7206 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7207 "%02x - %02x - %02x - %02x (%08x) " 7208 TARGET_FMT_lx "\n", 7209 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7210 insn, ctx->cia); 7211 return false; 7212 } 7213 7214 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7215 && Rc(insn))) { 7216 inval = handler->inval2; 7217 } else { 7218 inval = handler->inval1; 7219 } 7220 7221 if (unlikely((insn & inval) != 0)) { 7222 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7223 "%02x - %02x - %02x - %02x (%08x) " 7224 TARGET_FMT_lx "\n", insn & inval, 7225 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7226 insn, ctx->cia); 7227 return false; 7228 } 7229 7230 handler->handler(ctx); 7231 return true; 7232 } 7233 7234 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7235 { 7236 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7237 CPUPPCState *env = cs->env_ptr; 7238 uint32_t hflags = ctx->base.tb->flags; 7239 7240 ctx->spr_cb = env->spr_cb; 7241 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7242 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7243 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7244 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7245 ctx->insns_flags = env->insns_flags; 7246 ctx->insns_flags2 = env->insns_flags2; 7247 ctx->access_type = -1; 7248 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7249 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7250 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7251 ctx->flags = env->flags; 7252 #if defined(TARGET_PPC64) 7253 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7254 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7255 #endif 7256 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7257 || env->mmu_model & POWERPC_MMU_64; 7258 7259 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7260 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7261 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7262 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7263 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7264 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7265 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7266 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7267 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7268 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7269 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7270 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7271 7272 ctx->singlestep_enabled = 0; 7273 if ((hflags >> HFLAGS_SE) & 1) { 7274 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7275 ctx->base.max_insns = 1; 7276 } 7277 if ((hflags >> HFLAGS_BE) & 1) { 7278 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7279 } 7280 } 7281 7282 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7283 { 7284 } 7285 7286 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7287 { 7288 tcg_gen_insn_start(dcbase->pc_next); 7289 } 7290 7291 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7292 { 7293 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7294 return opc1(insn) == 1; 7295 } 7296 7297 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7298 { 7299 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7300 PowerPCCPU *cpu = POWERPC_CPU(cs); 7301 CPUPPCState *env = cs->env_ptr; 7302 target_ulong pc; 7303 uint32_t insn; 7304 bool ok; 7305 7306 LOG_DISAS("----------------\n"); 7307 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7308 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7309 7310 ctx->cia = pc = ctx->base.pc_next; 7311 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7312 ctx->base.pc_next = pc += 4; 7313 7314 if (!is_prefix_insn(ctx, insn)) { 7315 ok = (decode_insn32(ctx, insn) || 7316 decode_legacy(cpu, ctx, insn)); 7317 } else if ((pc & 63) == 0) { 7318 /* 7319 * Power v3.1, section 1.9 Exceptions: 7320 * attempt to execute a prefixed instruction that crosses a 7321 * 64-byte address boundary (system alignment error). 7322 */ 7323 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7324 ok = true; 7325 } else { 7326 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7327 need_byteswap(ctx)); 7328 ctx->base.pc_next = pc += 4; 7329 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7330 } 7331 if (!ok) { 7332 gen_invalid(ctx); 7333 } 7334 7335 /* End the TB when crossing a page boundary. */ 7336 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7337 ctx->base.is_jmp = DISAS_TOO_MANY; 7338 } 7339 } 7340 7341 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7342 { 7343 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7344 DisasJumpType is_jmp = ctx->base.is_jmp; 7345 target_ulong nip = ctx->base.pc_next; 7346 7347 if (is_jmp == DISAS_NORETURN) { 7348 /* We have already exited the TB. */ 7349 return; 7350 } 7351 7352 /* Honor single stepping. */ 7353 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7354 && (nip <= 0x100 || nip > 0xf00)) { 7355 switch (is_jmp) { 7356 case DISAS_TOO_MANY: 7357 case DISAS_EXIT_UPDATE: 7358 case DISAS_CHAIN_UPDATE: 7359 gen_update_nip(ctx, nip); 7360 break; 7361 case DISAS_EXIT: 7362 case DISAS_CHAIN: 7363 break; 7364 default: 7365 g_assert_not_reached(); 7366 } 7367 7368 gen_debug_exception(ctx); 7369 return; 7370 } 7371 7372 switch (is_jmp) { 7373 case DISAS_TOO_MANY: 7374 if (use_goto_tb(ctx, nip)) { 7375 pmu_count_insns(ctx); 7376 tcg_gen_goto_tb(0); 7377 gen_update_nip(ctx, nip); 7378 tcg_gen_exit_tb(ctx->base.tb, 0); 7379 break; 7380 } 7381 /* fall through */ 7382 case DISAS_CHAIN_UPDATE: 7383 gen_update_nip(ctx, nip); 7384 /* fall through */ 7385 case DISAS_CHAIN: 7386 /* 7387 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7388 * CF_NO_GOTO_PTR is set. Count insns now. 7389 */ 7390 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7391 pmu_count_insns(ctx); 7392 } 7393 7394 tcg_gen_lookup_and_goto_ptr(); 7395 break; 7396 7397 case DISAS_EXIT_UPDATE: 7398 gen_update_nip(ctx, nip); 7399 /* fall through */ 7400 case DISAS_EXIT: 7401 pmu_count_insns(ctx); 7402 tcg_gen_exit_tb(NULL, 0); 7403 break; 7404 7405 default: 7406 g_assert_not_reached(); 7407 } 7408 } 7409 7410 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7411 CPUState *cs, FILE *logfile) 7412 { 7413 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7414 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7415 } 7416 7417 static const TranslatorOps ppc_tr_ops = { 7418 .init_disas_context = ppc_tr_init_disas_context, 7419 .tb_start = ppc_tr_tb_start, 7420 .insn_start = ppc_tr_insn_start, 7421 .translate_insn = ppc_tr_translate_insn, 7422 .tb_stop = ppc_tr_tb_stop, 7423 .disas_log = ppc_tr_disas_log, 7424 }; 7425 7426 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7427 target_ulong pc, void *host_pc) 7428 { 7429 DisasContext ctx; 7430 7431 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7432 } 7433