1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 /* SPR load/store helpers */ 238 static inline void gen_load_spr(TCGv t, int reg) 239 { 240 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 241 } 242 243 static inline void gen_store_spr(int reg, TCGv t) 244 { 245 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 246 } 247 248 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 249 { 250 if (ctx->need_access_type && ctx->access_type != access_type) { 251 tcg_gen_movi_i32(cpu_access_type, access_type); 252 ctx->access_type = access_type; 253 } 254 } 255 256 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 257 { 258 if (NARROW_MODE(ctx)) { 259 nip = (uint32_t)nip; 260 } 261 tcg_gen_movi_tl(cpu_nip, nip); 262 } 263 264 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 265 { 266 TCGv_i32 t0, t1; 267 268 /* 269 * These are all synchronous exceptions, we set the PC back to the 270 * faulting instruction 271 */ 272 gen_update_nip(ctx, ctx->cia); 273 t0 = tcg_constant_i32(excp); 274 t1 = tcg_constant_i32(error); 275 gen_helper_raise_exception_err(cpu_env, t0, t1); 276 ctx->base.is_jmp = DISAS_NORETURN; 277 } 278 279 static void gen_exception(DisasContext *ctx, uint32_t excp) 280 { 281 TCGv_i32 t0; 282 283 /* 284 * These are all synchronous exceptions, we set the PC back to the 285 * faulting instruction 286 */ 287 gen_update_nip(ctx, ctx->cia); 288 t0 = tcg_constant_i32(excp); 289 gen_helper_raise_exception(cpu_env, t0); 290 ctx->base.is_jmp = DISAS_NORETURN; 291 } 292 293 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 294 target_ulong nip) 295 { 296 TCGv_i32 t0; 297 298 gen_update_nip(ctx, nip); 299 t0 = tcg_constant_i32(excp); 300 gen_helper_raise_exception(cpu_env, t0); 301 ctx->base.is_jmp = DISAS_NORETURN; 302 } 303 304 #if !defined(CONFIG_USER_ONLY) 305 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 306 { 307 translator_io_start(&ctx->base); 308 gen_helper_ppc_maybe_interrupt(cpu_env); 309 } 310 #endif 311 312 /* 313 * Tells the caller what is the appropriate exception to generate and prepares 314 * SPR registers for this exception. 315 * 316 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 317 * POWERPC_EXCP_DEBUG (on BookE). 318 */ 319 static uint32_t gen_prep_dbgex(DisasContext *ctx) 320 { 321 if (ctx->flags & POWERPC_FLAG_DE) { 322 target_ulong dbsr = 0; 323 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 324 dbsr = DBCR0_ICMP; 325 } else { 326 /* Must have been branch */ 327 dbsr = DBCR0_BRT; 328 } 329 TCGv t0 = tcg_temp_new(); 330 gen_load_spr(t0, SPR_BOOKE_DBSR); 331 tcg_gen_ori_tl(t0, t0, dbsr); 332 gen_store_spr(SPR_BOOKE_DBSR, t0); 333 return POWERPC_EXCP_DEBUG; 334 } else { 335 return POWERPC_EXCP_TRACE; 336 } 337 } 338 339 static void gen_debug_exception(DisasContext *ctx) 340 { 341 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 342 ctx->base.is_jmp = DISAS_NORETURN; 343 } 344 345 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 346 { 347 /* Will be converted to program check if needed */ 348 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 349 } 350 351 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 352 { 353 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 354 } 355 356 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 357 { 358 /* Will be converted to program check if needed */ 359 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 360 } 361 362 /*****************************************************************************/ 363 /* SPR READ/WRITE CALLBACKS */ 364 365 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 366 { 367 #if 0 368 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 369 printf("ERROR: try to access SPR %d !\n", sprn); 370 #endif 371 } 372 373 /* #define PPC_DUMP_SPR_ACCESSES */ 374 375 /* 376 * Generic callbacks: 377 * do nothing but store/retrieve spr value 378 */ 379 static void spr_load_dump_spr(int sprn) 380 { 381 #ifdef PPC_DUMP_SPR_ACCESSES 382 TCGv_i32 t0 = tcg_constant_i32(sprn); 383 gen_helper_load_dump_spr(cpu_env, t0); 384 #endif 385 } 386 387 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 388 { 389 gen_load_spr(cpu_gpr[gprn], sprn); 390 spr_load_dump_spr(sprn); 391 } 392 393 static void spr_store_dump_spr(int sprn) 394 { 395 #ifdef PPC_DUMP_SPR_ACCESSES 396 TCGv_i32 t0 = tcg_constant_i32(sprn); 397 gen_helper_store_dump_spr(cpu_env, t0); 398 #endif 399 } 400 401 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 402 { 403 gen_store_spr(sprn, cpu_gpr[gprn]); 404 spr_store_dump_spr(sprn); 405 } 406 407 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 408 { 409 #ifdef TARGET_PPC64 410 TCGv t0 = tcg_temp_new(); 411 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 412 gen_store_spr(sprn, t0); 413 spr_store_dump_spr(sprn); 414 #else 415 spr_write_generic(ctx, sprn, gprn); 416 #endif 417 } 418 419 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 420 { 421 spr_write_generic32(ctx, sprn, gprn); 422 423 /* 424 * SPR_CTRL writes must force a new translation block, 425 * allowing the PMU to calculate the run latch events with 426 * more accuracy. 427 */ 428 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 429 } 430 431 #if !defined(CONFIG_USER_ONLY) 432 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 433 { 434 TCGv t0 = tcg_temp_new(); 435 TCGv t1 = tcg_temp_new(); 436 gen_load_spr(t0, sprn); 437 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 438 tcg_gen_and_tl(t0, t0, t1); 439 gen_store_spr(sprn, t0); 440 } 441 442 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 443 { 444 } 445 446 #endif 447 448 /* SPR common to all PowerPC */ 449 /* XER */ 450 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 451 { 452 TCGv dst = cpu_gpr[gprn]; 453 TCGv t0 = tcg_temp_new(); 454 TCGv t1 = tcg_temp_new(); 455 TCGv t2 = tcg_temp_new(); 456 tcg_gen_mov_tl(dst, cpu_xer); 457 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 458 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 459 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 460 tcg_gen_or_tl(t0, t0, t1); 461 tcg_gen_or_tl(dst, dst, t2); 462 tcg_gen_or_tl(dst, dst, t0); 463 if (is_isa300(ctx)) { 464 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 465 tcg_gen_or_tl(dst, dst, t0); 466 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 467 tcg_gen_or_tl(dst, dst, t0); 468 } 469 } 470 471 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 472 { 473 TCGv src = cpu_gpr[gprn]; 474 /* Write all flags, while reading back check for isa300 */ 475 tcg_gen_andi_tl(cpu_xer, src, 476 ~((1u << XER_SO) | 477 (1u << XER_OV) | (1u << XER_OV32) | 478 (1u << XER_CA) | (1u << XER_CA32))); 479 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 480 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 481 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 482 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 483 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 484 } 485 486 /* LR */ 487 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 488 { 489 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 490 } 491 492 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 493 { 494 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 495 } 496 497 /* CFAR */ 498 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 499 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 500 { 501 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 502 } 503 504 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 505 { 506 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 507 } 508 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 509 510 /* CTR */ 511 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 512 { 513 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 514 } 515 516 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 517 { 518 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 519 } 520 521 /* User read access to SPR */ 522 /* USPRx */ 523 /* UMMCRx */ 524 /* UPMCx */ 525 /* USIA */ 526 /* UDECR */ 527 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 528 { 529 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 530 } 531 532 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 533 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 534 { 535 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 536 } 537 #endif 538 539 /* SPR common to all non-embedded PowerPC */ 540 /* DECR */ 541 #if !defined(CONFIG_USER_ONLY) 542 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 543 { 544 translator_io_start(&ctx->base); 545 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 546 } 547 548 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 549 { 550 translator_io_start(&ctx->base); 551 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 552 } 553 #endif 554 555 /* SPR common to all non-embedded PowerPC, except 601 */ 556 /* Time base */ 557 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 558 { 559 translator_io_start(&ctx->base); 560 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 561 } 562 563 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 564 { 565 translator_io_start(&ctx->base); 566 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 567 } 568 569 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 570 { 571 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 572 } 573 574 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 575 { 576 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 577 } 578 579 #if !defined(CONFIG_USER_ONLY) 580 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 581 { 582 translator_io_start(&ctx->base); 583 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 584 } 585 586 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 587 { 588 translator_io_start(&ctx->base); 589 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 590 } 591 592 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 593 { 594 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 595 } 596 597 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 598 { 599 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 600 } 601 602 #if defined(TARGET_PPC64) 603 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 604 { 605 translator_io_start(&ctx->base); 606 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 607 } 608 609 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 610 { 611 translator_io_start(&ctx->base); 612 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 613 } 614 615 /* HDECR */ 616 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 617 { 618 translator_io_start(&ctx->base); 619 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 620 } 621 622 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 623 { 624 translator_io_start(&ctx->base); 625 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 626 } 627 628 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 629 { 630 translator_io_start(&ctx->base); 631 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 632 } 633 634 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 635 { 636 translator_io_start(&ctx->base); 637 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 638 } 639 640 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 641 { 642 translator_io_start(&ctx->base); 643 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 644 } 645 646 #endif 647 #endif 648 649 #if !defined(CONFIG_USER_ONLY) 650 /* IBAT0U...IBAT0U */ 651 /* IBAT0L...IBAT7L */ 652 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 653 { 654 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 655 offsetof(CPUPPCState, 656 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 657 } 658 659 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 660 { 661 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 662 offsetof(CPUPPCState, 663 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 664 } 665 666 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 667 { 668 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 669 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 670 } 671 672 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 673 { 674 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 675 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 676 } 677 678 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 679 { 680 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 681 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 682 } 683 684 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 685 { 686 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 687 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 688 } 689 690 /* DBAT0U...DBAT7U */ 691 /* DBAT0L...DBAT7L */ 692 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 693 { 694 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 695 offsetof(CPUPPCState, 696 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 697 } 698 699 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 700 { 701 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 702 offsetof(CPUPPCState, 703 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 704 } 705 706 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 707 { 708 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 709 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 710 } 711 712 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 713 { 714 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 715 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 716 } 717 718 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 719 { 720 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 721 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 722 } 723 724 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 725 { 726 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 727 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 728 } 729 730 /* SDR1 */ 731 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 732 { 733 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 734 } 735 736 #if defined(TARGET_PPC64) 737 /* 64 bits PowerPC specific SPRs */ 738 /* PIDR */ 739 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 740 { 741 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 742 } 743 744 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 745 { 746 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 747 } 748 749 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 750 { 751 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 752 } 753 754 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 755 { 756 TCGv t0 = tcg_temp_new(); 757 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 758 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 759 } 760 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 761 { 762 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 763 } 764 765 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 766 { 767 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 768 } 769 770 /* DPDES */ 771 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 772 { 773 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 774 } 775 776 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 777 { 778 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 779 } 780 #endif 781 #endif 782 783 /* PowerPC 40x specific registers */ 784 #if !defined(CONFIG_USER_ONLY) 785 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 786 { 787 translator_io_start(&ctx->base); 788 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 789 } 790 791 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 792 { 793 translator_io_start(&ctx->base); 794 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 795 } 796 797 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 798 { 799 translator_io_start(&ctx->base); 800 gen_store_spr(sprn, cpu_gpr[gprn]); 801 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 802 /* We must stop translation as we may have rebooted */ 803 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 804 } 805 806 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 807 { 808 translator_io_start(&ctx->base); 809 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 810 } 811 812 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 813 { 814 translator_io_start(&ctx->base); 815 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 816 } 817 818 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 819 { 820 translator_io_start(&ctx->base); 821 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 822 } 823 824 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 825 { 826 TCGv t0 = tcg_temp_new(); 827 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 828 gen_helper_store_40x_pid(cpu_env, t0); 829 } 830 831 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 832 { 833 translator_io_start(&ctx->base); 834 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 835 } 836 837 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 838 { 839 translator_io_start(&ctx->base); 840 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 841 } 842 #endif 843 844 /* PIR */ 845 #if !defined(CONFIG_USER_ONLY) 846 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 847 { 848 TCGv t0 = tcg_temp_new(); 849 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 850 gen_store_spr(SPR_PIR, t0); 851 } 852 #endif 853 854 /* SPE specific registers */ 855 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 856 { 857 TCGv_i32 t0 = tcg_temp_new_i32(); 858 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 859 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 860 } 861 862 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 863 { 864 TCGv_i32 t0 = tcg_temp_new_i32(); 865 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 866 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 867 } 868 869 #if !defined(CONFIG_USER_ONLY) 870 /* Callback used to write the exception vector base */ 871 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 872 { 873 TCGv t0 = tcg_temp_new(); 874 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 875 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 876 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 877 gen_store_spr(sprn, t0); 878 } 879 880 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 881 { 882 int sprn_offs; 883 884 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 885 sprn_offs = sprn - SPR_BOOKE_IVOR0; 886 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 887 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 888 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 889 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 890 } else { 891 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 892 " vector 0x%03x\n", sprn); 893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 894 return; 895 } 896 897 TCGv t0 = tcg_temp_new(); 898 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 899 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 900 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 901 gen_store_spr(sprn, t0); 902 } 903 #endif 904 905 #ifdef TARGET_PPC64 906 #ifndef CONFIG_USER_ONLY 907 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 908 { 909 TCGv t0 = tcg_temp_new(); 910 TCGv t1 = tcg_temp_new(); 911 TCGv t2 = tcg_temp_new(); 912 913 /* 914 * Note, the HV=1 PR=0 case is handled earlier by simply using 915 * spr_write_generic for HV mode in the SPR table 916 */ 917 918 /* Build insertion mask into t1 based on context */ 919 if (ctx->pr) { 920 gen_load_spr(t1, SPR_UAMOR); 921 } else { 922 gen_load_spr(t1, SPR_AMOR); 923 } 924 925 /* Mask new bits into t2 */ 926 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 927 928 /* Load AMR and clear new bits in t0 */ 929 gen_load_spr(t0, SPR_AMR); 930 tcg_gen_andc_tl(t0, t0, t1); 931 932 /* Or'in new bits and write it out */ 933 tcg_gen_or_tl(t0, t0, t2); 934 gen_store_spr(SPR_AMR, t0); 935 spr_store_dump_spr(SPR_AMR); 936 } 937 938 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 939 { 940 TCGv t0 = tcg_temp_new(); 941 TCGv t1 = tcg_temp_new(); 942 TCGv t2 = tcg_temp_new(); 943 944 /* 945 * Note, the HV=1 case is handled earlier by simply using 946 * spr_write_generic for HV mode in the SPR table 947 */ 948 949 /* Build insertion mask into t1 based on context */ 950 gen_load_spr(t1, SPR_AMOR); 951 952 /* Mask new bits into t2 */ 953 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 954 955 /* Load AMR and clear new bits in t0 */ 956 gen_load_spr(t0, SPR_UAMOR); 957 tcg_gen_andc_tl(t0, t0, t1); 958 959 /* Or'in new bits and write it out */ 960 tcg_gen_or_tl(t0, t0, t2); 961 gen_store_spr(SPR_UAMOR, t0); 962 spr_store_dump_spr(SPR_UAMOR); 963 } 964 965 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 966 { 967 TCGv t0 = tcg_temp_new(); 968 TCGv t1 = tcg_temp_new(); 969 TCGv t2 = tcg_temp_new(); 970 971 /* 972 * Note, the HV=1 case is handled earlier by simply using 973 * spr_write_generic for HV mode in the SPR table 974 */ 975 976 /* Build insertion mask into t1 based on context */ 977 gen_load_spr(t1, SPR_AMOR); 978 979 /* Mask new bits into t2 */ 980 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 981 982 /* Load AMR and clear new bits in t0 */ 983 gen_load_spr(t0, SPR_IAMR); 984 tcg_gen_andc_tl(t0, t0, t1); 985 986 /* Or'in new bits and write it out */ 987 tcg_gen_or_tl(t0, t0, t2); 988 gen_store_spr(SPR_IAMR, t0); 989 spr_store_dump_spr(SPR_IAMR); 990 } 991 #endif 992 #endif 993 994 #ifndef CONFIG_USER_ONLY 995 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 996 { 997 gen_helper_fixup_thrm(cpu_env); 998 gen_load_spr(cpu_gpr[gprn], sprn); 999 spr_load_dump_spr(sprn); 1000 } 1001 #endif /* !CONFIG_USER_ONLY */ 1002 1003 #if !defined(CONFIG_USER_ONLY) 1004 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1005 { 1006 TCGv t0 = tcg_temp_new(); 1007 1008 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1009 gen_store_spr(sprn, t0); 1010 } 1011 1012 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1013 { 1014 TCGv t0 = tcg_temp_new(); 1015 1016 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1017 gen_store_spr(sprn, t0); 1018 } 1019 1020 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1021 { 1022 TCGv t0 = tcg_temp_new(); 1023 1024 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1025 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1026 gen_store_spr(sprn, t0); 1027 } 1028 1029 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1030 { 1031 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1032 } 1033 1034 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1035 { 1036 TCGv_i32 t0 = tcg_constant_i32(sprn); 1037 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1038 } 1039 1040 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1041 { 1042 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1043 } 1044 1045 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1046 { 1047 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1048 } 1049 1050 #endif 1051 1052 #if !defined(CONFIG_USER_ONLY) 1053 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1054 { 1055 TCGv val = tcg_temp_new(); 1056 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1057 gen_store_spr(SPR_BOOKE_MAS3, val); 1058 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1059 gen_store_spr(SPR_BOOKE_MAS7, val); 1060 } 1061 1062 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1063 { 1064 TCGv mas7 = tcg_temp_new(); 1065 TCGv mas3 = tcg_temp_new(); 1066 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1067 tcg_gen_shli_tl(mas7, mas7, 32); 1068 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1069 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1070 } 1071 1072 #endif 1073 1074 #ifdef TARGET_PPC64 1075 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1076 int bit, int sprn, int cause) 1077 { 1078 TCGv_i32 t1 = tcg_constant_i32(bit); 1079 TCGv_i32 t2 = tcg_constant_i32(sprn); 1080 TCGv_i32 t3 = tcg_constant_i32(cause); 1081 1082 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1083 } 1084 1085 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1086 int bit, int sprn, int cause) 1087 { 1088 TCGv_i32 t1 = tcg_constant_i32(bit); 1089 TCGv_i32 t2 = tcg_constant_i32(sprn); 1090 TCGv_i32 t3 = tcg_constant_i32(cause); 1091 1092 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1093 } 1094 1095 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1096 { 1097 TCGv spr_up = tcg_temp_new(); 1098 TCGv spr = tcg_temp_new(); 1099 1100 gen_load_spr(spr, sprn - 1); 1101 tcg_gen_shri_tl(spr_up, spr, 32); 1102 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1103 } 1104 1105 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1106 { 1107 TCGv spr = tcg_temp_new(); 1108 1109 gen_load_spr(spr, sprn - 1); 1110 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1111 gen_store_spr(sprn - 1, spr); 1112 } 1113 1114 #if !defined(CONFIG_USER_ONLY) 1115 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1116 { 1117 TCGv hmer = tcg_temp_new(); 1118 1119 gen_load_spr(hmer, sprn); 1120 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1121 gen_store_spr(sprn, hmer); 1122 spr_store_dump_spr(sprn); 1123 } 1124 1125 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1126 { 1127 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1128 } 1129 #endif /* !defined(CONFIG_USER_ONLY) */ 1130 1131 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1132 { 1133 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1134 spr_read_generic(ctx, gprn, sprn); 1135 } 1136 1137 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1138 { 1139 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1140 spr_write_generic(ctx, sprn, gprn); 1141 } 1142 1143 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1144 { 1145 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1146 spr_read_generic(ctx, gprn, sprn); 1147 } 1148 1149 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1150 { 1151 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1152 spr_write_generic(ctx, sprn, gprn); 1153 } 1154 1155 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1156 { 1157 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1158 spr_read_prev_upper32(ctx, gprn, sprn); 1159 } 1160 1161 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1162 { 1163 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1164 spr_write_prev_upper32(ctx, sprn, gprn); 1165 } 1166 1167 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1168 { 1169 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1170 spr_read_generic(ctx, gprn, sprn); 1171 } 1172 1173 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1174 { 1175 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1176 spr_write_generic(ctx, sprn, gprn); 1177 } 1178 1179 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1180 { 1181 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1182 spr_read_prev_upper32(ctx, gprn, sprn); 1183 } 1184 1185 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1186 { 1187 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1188 spr_write_prev_upper32(ctx, sprn, gprn); 1189 } 1190 1191 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1192 { 1193 TCGv t0 = tcg_temp_new(); 1194 1195 /* 1196 * Access to the (H)DEXCR in problem state is done using separated 1197 * SPR indexes which are 16 below the SPR indexes which have full 1198 * access to the (H)DEXCR in privileged state. Problem state can 1199 * only read bits 32:63, bits 0:31 return 0. 1200 * 1201 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1202 */ 1203 1204 gen_load_spr(t0, sprn + 16); 1205 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1206 } 1207 #endif 1208 1209 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1210 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1211 1212 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1213 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1214 1215 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1216 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1217 1218 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1219 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1220 1221 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1222 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1223 1224 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1225 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1226 1227 typedef struct opcode_t { 1228 unsigned char opc1, opc2, opc3, opc4; 1229 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1230 unsigned char pad[4]; 1231 #endif 1232 opc_handler_t handler; 1233 const char *oname; 1234 } opcode_t; 1235 1236 static void gen_priv_opc(DisasContext *ctx) 1237 { 1238 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1239 } 1240 1241 /* Helpers for priv. check */ 1242 #define GEN_PRIV(CTX) \ 1243 do { \ 1244 gen_priv_opc(CTX); return; \ 1245 } while (0) 1246 1247 #if defined(CONFIG_USER_ONLY) 1248 #define CHK_HV(CTX) GEN_PRIV(CTX) 1249 #define CHK_SV(CTX) GEN_PRIV(CTX) 1250 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1251 #else 1252 #define CHK_HV(CTX) \ 1253 do { \ 1254 if (unlikely(ctx->pr || !ctx->hv)) {\ 1255 GEN_PRIV(CTX); \ 1256 } \ 1257 } while (0) 1258 #define CHK_SV(CTX) \ 1259 do { \ 1260 if (unlikely(ctx->pr)) { \ 1261 GEN_PRIV(CTX); \ 1262 } \ 1263 } while (0) 1264 #define CHK_HVRM(CTX) \ 1265 do { \ 1266 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1267 GEN_PRIV(CTX); \ 1268 } \ 1269 } while (0) 1270 #endif 1271 1272 #define CHK_NONE(CTX) 1273 1274 /*****************************************************************************/ 1275 /* PowerPC instructions table */ 1276 1277 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1278 { \ 1279 .opc1 = op1, \ 1280 .opc2 = op2, \ 1281 .opc3 = op3, \ 1282 .opc4 = 0xff, \ 1283 .handler = { \ 1284 .inval1 = invl, \ 1285 .type = _typ, \ 1286 .type2 = _typ2, \ 1287 .handler = &gen_##name, \ 1288 }, \ 1289 .oname = stringify(name), \ 1290 } 1291 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1292 { \ 1293 .opc1 = op1, \ 1294 .opc2 = op2, \ 1295 .opc3 = op3, \ 1296 .opc4 = 0xff, \ 1297 .handler = { \ 1298 .inval1 = invl1, \ 1299 .inval2 = invl2, \ 1300 .type = _typ, \ 1301 .type2 = _typ2, \ 1302 .handler = &gen_##name, \ 1303 }, \ 1304 .oname = stringify(name), \ 1305 } 1306 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1307 { \ 1308 .opc1 = op1, \ 1309 .opc2 = op2, \ 1310 .opc3 = op3, \ 1311 .opc4 = 0xff, \ 1312 .handler = { \ 1313 .inval1 = invl, \ 1314 .type = _typ, \ 1315 .type2 = _typ2, \ 1316 .handler = &gen_##name, \ 1317 }, \ 1318 .oname = onam, \ 1319 } 1320 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1321 { \ 1322 .opc1 = op1, \ 1323 .opc2 = op2, \ 1324 .opc3 = op3, \ 1325 .opc4 = op4, \ 1326 .handler = { \ 1327 .inval1 = invl, \ 1328 .type = _typ, \ 1329 .type2 = _typ2, \ 1330 .handler = &gen_##name, \ 1331 }, \ 1332 .oname = stringify(name), \ 1333 } 1334 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1335 { \ 1336 .opc1 = op1, \ 1337 .opc2 = op2, \ 1338 .opc3 = op3, \ 1339 .opc4 = op4, \ 1340 .handler = { \ 1341 .inval1 = invl, \ 1342 .type = _typ, \ 1343 .type2 = _typ2, \ 1344 .handler = &gen_##name, \ 1345 }, \ 1346 .oname = onam, \ 1347 } 1348 1349 /* Invalid instruction */ 1350 static void gen_invalid(DisasContext *ctx) 1351 { 1352 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1353 } 1354 1355 static opc_handler_t invalid_handler = { 1356 .inval1 = 0xFFFFFFFF, 1357 .inval2 = 0xFFFFFFFF, 1358 .type = PPC_NONE, 1359 .type2 = PPC_NONE, 1360 .handler = gen_invalid, 1361 }; 1362 1363 /*** Integer comparison ***/ 1364 1365 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1366 { 1367 TCGv t0 = tcg_temp_new(); 1368 TCGv t1 = tcg_temp_new(); 1369 TCGv_i32 t = tcg_temp_new_i32(); 1370 1371 tcg_gen_movi_tl(t0, CRF_EQ); 1372 tcg_gen_movi_tl(t1, CRF_LT); 1373 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1374 t0, arg0, arg1, t1, t0); 1375 tcg_gen_movi_tl(t1, CRF_GT); 1376 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1377 t0, arg0, arg1, t1, t0); 1378 1379 tcg_gen_trunc_tl_i32(t, t0); 1380 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1381 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1382 } 1383 1384 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1385 { 1386 TCGv t0 = tcg_constant_tl(arg1); 1387 gen_op_cmp(arg0, t0, s, crf); 1388 } 1389 1390 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1391 { 1392 TCGv t0, t1; 1393 t0 = tcg_temp_new(); 1394 t1 = tcg_temp_new(); 1395 if (s) { 1396 tcg_gen_ext32s_tl(t0, arg0); 1397 tcg_gen_ext32s_tl(t1, arg1); 1398 } else { 1399 tcg_gen_ext32u_tl(t0, arg0); 1400 tcg_gen_ext32u_tl(t1, arg1); 1401 } 1402 gen_op_cmp(t0, t1, s, crf); 1403 } 1404 1405 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1406 { 1407 TCGv t0 = tcg_constant_tl(arg1); 1408 gen_op_cmp32(arg0, t0, s, crf); 1409 } 1410 1411 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1412 { 1413 if (NARROW_MODE(ctx)) { 1414 gen_op_cmpi32(reg, 0, 1, 0); 1415 } else { 1416 gen_op_cmpi(reg, 0, 1, 0); 1417 } 1418 } 1419 1420 /* cmprb - range comparison: isupper, isaplha, islower*/ 1421 static void gen_cmprb(DisasContext *ctx) 1422 { 1423 TCGv_i32 src1 = tcg_temp_new_i32(); 1424 TCGv_i32 src2 = tcg_temp_new_i32(); 1425 TCGv_i32 src2lo = tcg_temp_new_i32(); 1426 TCGv_i32 src2hi = tcg_temp_new_i32(); 1427 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1428 1429 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1430 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1431 1432 tcg_gen_andi_i32(src1, src1, 0xFF); 1433 tcg_gen_ext8u_i32(src2lo, src2); 1434 tcg_gen_shri_i32(src2, src2, 8); 1435 tcg_gen_ext8u_i32(src2hi, src2); 1436 1437 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1438 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1439 tcg_gen_and_i32(crf, src2lo, src2hi); 1440 1441 if (ctx->opcode & 0x00200000) { 1442 tcg_gen_shri_i32(src2, src2, 8); 1443 tcg_gen_ext8u_i32(src2lo, src2); 1444 tcg_gen_shri_i32(src2, src2, 8); 1445 tcg_gen_ext8u_i32(src2hi, src2); 1446 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1447 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1448 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1449 tcg_gen_or_i32(crf, crf, src2lo); 1450 } 1451 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1452 } 1453 1454 #if defined(TARGET_PPC64) 1455 /* cmpeqb */ 1456 static void gen_cmpeqb(DisasContext *ctx) 1457 { 1458 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1459 cpu_gpr[rB(ctx->opcode)]); 1460 } 1461 #endif 1462 1463 /* isel (PowerPC 2.03 specification) */ 1464 static void gen_isel(DisasContext *ctx) 1465 { 1466 uint32_t bi = rC(ctx->opcode); 1467 uint32_t mask = 0x08 >> (bi & 0x03); 1468 TCGv t0 = tcg_temp_new(); 1469 TCGv zr; 1470 1471 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1472 tcg_gen_andi_tl(t0, t0, mask); 1473 1474 zr = tcg_constant_tl(0); 1475 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1476 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1477 cpu_gpr[rB(ctx->opcode)]); 1478 } 1479 1480 /* cmpb: PowerPC 2.05 specification */ 1481 static void gen_cmpb(DisasContext *ctx) 1482 { 1483 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1484 cpu_gpr[rB(ctx->opcode)]); 1485 } 1486 1487 /*** Integer arithmetic ***/ 1488 1489 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1490 TCGv arg1, TCGv arg2, int sub) 1491 { 1492 TCGv t0 = tcg_temp_new(); 1493 1494 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1495 tcg_gen_xor_tl(t0, arg1, arg2); 1496 if (sub) { 1497 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1498 } else { 1499 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1500 } 1501 if (NARROW_MODE(ctx)) { 1502 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1503 if (is_isa300(ctx)) { 1504 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1505 } 1506 } else { 1507 if (is_isa300(ctx)) { 1508 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1509 } 1510 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1511 } 1512 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1513 } 1514 1515 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1516 TCGv res, TCGv arg0, TCGv arg1, 1517 TCGv ca32, int sub) 1518 { 1519 TCGv t0; 1520 1521 if (!is_isa300(ctx)) { 1522 return; 1523 } 1524 1525 t0 = tcg_temp_new(); 1526 if (sub) { 1527 tcg_gen_eqv_tl(t0, arg0, arg1); 1528 } else { 1529 tcg_gen_xor_tl(t0, arg0, arg1); 1530 } 1531 tcg_gen_xor_tl(t0, t0, res); 1532 tcg_gen_extract_tl(ca32, t0, 32, 1); 1533 } 1534 1535 /* Common add function */ 1536 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1537 TCGv arg2, TCGv ca, TCGv ca32, 1538 bool add_ca, bool compute_ca, 1539 bool compute_ov, bool compute_rc0) 1540 { 1541 TCGv t0 = ret; 1542 1543 if (compute_ca || compute_ov) { 1544 t0 = tcg_temp_new(); 1545 } 1546 1547 if (compute_ca) { 1548 if (NARROW_MODE(ctx)) { 1549 /* 1550 * Caution: a non-obvious corner case of the spec is that 1551 * we must produce the *entire* 64-bit addition, but 1552 * produce the carry into bit 32. 1553 */ 1554 TCGv t1 = tcg_temp_new(); 1555 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1556 tcg_gen_add_tl(t0, arg1, arg2); 1557 if (add_ca) { 1558 tcg_gen_add_tl(t0, t0, ca); 1559 } 1560 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1561 tcg_gen_extract_tl(ca, ca, 32, 1); 1562 if (is_isa300(ctx)) { 1563 tcg_gen_mov_tl(ca32, ca); 1564 } 1565 } else { 1566 TCGv zero = tcg_constant_tl(0); 1567 if (add_ca) { 1568 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1569 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1570 } else { 1571 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1572 } 1573 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1574 } 1575 } else { 1576 tcg_gen_add_tl(t0, arg1, arg2); 1577 if (add_ca) { 1578 tcg_gen_add_tl(t0, t0, ca); 1579 } 1580 } 1581 1582 if (compute_ov) { 1583 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1584 } 1585 if (unlikely(compute_rc0)) { 1586 gen_set_Rc0(ctx, t0); 1587 } 1588 1589 if (t0 != ret) { 1590 tcg_gen_mov_tl(ret, t0); 1591 } 1592 } 1593 /* Add functions with two operands */ 1594 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1595 static void glue(gen_, name)(DisasContext *ctx) \ 1596 { \ 1597 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1598 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1599 ca, glue(ca, 32), \ 1600 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1601 } 1602 /* Add functions with one operand and one immediate */ 1603 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1604 add_ca, compute_ca, compute_ov) \ 1605 static void glue(gen_, name)(DisasContext *ctx) \ 1606 { \ 1607 TCGv t0 = tcg_constant_tl(const_val); \ 1608 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1609 cpu_gpr[rA(ctx->opcode)], t0, \ 1610 ca, glue(ca, 32), \ 1611 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1612 } 1613 1614 /* add add. addo addo. */ 1615 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1616 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1617 /* addc addc. addco addco. */ 1618 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1619 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1620 /* adde adde. addeo addeo. */ 1621 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1622 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1623 /* addme addme. addmeo addmeo. */ 1624 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1625 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1626 /* addex */ 1627 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1628 /* addze addze. addzeo addzeo.*/ 1629 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1630 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1631 /* addic addic.*/ 1632 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1633 { 1634 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1635 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1636 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1637 } 1638 1639 static void gen_addic(DisasContext *ctx) 1640 { 1641 gen_op_addic(ctx, 0); 1642 } 1643 1644 static void gen_addic_(DisasContext *ctx) 1645 { 1646 gen_op_addic(ctx, 1); 1647 } 1648 1649 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1650 TCGv arg2, int sign, int compute_ov) 1651 { 1652 TCGv_i32 t0 = tcg_temp_new_i32(); 1653 TCGv_i32 t1 = tcg_temp_new_i32(); 1654 TCGv_i32 t2 = tcg_temp_new_i32(); 1655 TCGv_i32 t3 = tcg_temp_new_i32(); 1656 1657 tcg_gen_trunc_tl_i32(t0, arg1); 1658 tcg_gen_trunc_tl_i32(t1, arg2); 1659 if (sign) { 1660 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1661 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1662 tcg_gen_and_i32(t2, t2, t3); 1663 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1664 tcg_gen_or_i32(t2, t2, t3); 1665 tcg_gen_movi_i32(t3, 0); 1666 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1667 tcg_gen_div_i32(t3, t0, t1); 1668 tcg_gen_extu_i32_tl(ret, t3); 1669 } else { 1670 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1671 tcg_gen_movi_i32(t3, 0); 1672 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1673 tcg_gen_divu_i32(t3, t0, t1); 1674 tcg_gen_extu_i32_tl(ret, t3); 1675 } 1676 if (compute_ov) { 1677 tcg_gen_extu_i32_tl(cpu_ov, t2); 1678 if (is_isa300(ctx)) { 1679 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1680 } 1681 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1682 } 1683 1684 if (unlikely(Rc(ctx->opcode) != 0)) { 1685 gen_set_Rc0(ctx, ret); 1686 } 1687 } 1688 /* Div functions */ 1689 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1690 static void glue(gen_, name)(DisasContext *ctx) \ 1691 { \ 1692 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1693 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1694 sign, compute_ov); \ 1695 } 1696 /* divwu divwu. divwuo divwuo. */ 1697 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1698 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1699 /* divw divw. divwo divwo. */ 1700 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1701 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1702 1703 /* div[wd]eu[o][.] */ 1704 #define GEN_DIVE(name, hlpr, compute_ov) \ 1705 static void gen_##name(DisasContext *ctx) \ 1706 { \ 1707 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1708 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1709 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1710 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1711 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1712 } \ 1713 } 1714 1715 GEN_DIVE(divweu, divweu, 0); 1716 GEN_DIVE(divweuo, divweu, 1); 1717 GEN_DIVE(divwe, divwe, 0); 1718 GEN_DIVE(divweo, divwe, 1); 1719 1720 #if defined(TARGET_PPC64) 1721 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1722 TCGv arg2, int sign, int compute_ov) 1723 { 1724 TCGv_i64 t0 = tcg_temp_new_i64(); 1725 TCGv_i64 t1 = tcg_temp_new_i64(); 1726 TCGv_i64 t2 = tcg_temp_new_i64(); 1727 TCGv_i64 t3 = tcg_temp_new_i64(); 1728 1729 tcg_gen_mov_i64(t0, arg1); 1730 tcg_gen_mov_i64(t1, arg2); 1731 if (sign) { 1732 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1733 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1734 tcg_gen_and_i64(t2, t2, t3); 1735 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1736 tcg_gen_or_i64(t2, t2, t3); 1737 tcg_gen_movi_i64(t3, 0); 1738 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1739 tcg_gen_div_i64(ret, t0, t1); 1740 } else { 1741 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1742 tcg_gen_movi_i64(t3, 0); 1743 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1744 tcg_gen_divu_i64(ret, t0, t1); 1745 } 1746 if (compute_ov) { 1747 tcg_gen_mov_tl(cpu_ov, t2); 1748 if (is_isa300(ctx)) { 1749 tcg_gen_mov_tl(cpu_ov32, t2); 1750 } 1751 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1752 } 1753 1754 if (unlikely(Rc(ctx->opcode) != 0)) { 1755 gen_set_Rc0(ctx, ret); 1756 } 1757 } 1758 1759 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1760 static void glue(gen_, name)(DisasContext *ctx) \ 1761 { \ 1762 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1763 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1764 sign, compute_ov); \ 1765 } 1766 /* divdu divdu. divduo divduo. */ 1767 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1768 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1769 /* divd divd. divdo divdo. */ 1770 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1771 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1772 1773 GEN_DIVE(divdeu, divdeu, 0); 1774 GEN_DIVE(divdeuo, divdeu, 1); 1775 GEN_DIVE(divde, divde, 0); 1776 GEN_DIVE(divdeo, divde, 1); 1777 #endif 1778 1779 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1780 TCGv arg2, int sign) 1781 { 1782 TCGv_i32 t0 = tcg_temp_new_i32(); 1783 TCGv_i32 t1 = tcg_temp_new_i32(); 1784 1785 tcg_gen_trunc_tl_i32(t0, arg1); 1786 tcg_gen_trunc_tl_i32(t1, arg2); 1787 if (sign) { 1788 TCGv_i32 t2 = tcg_temp_new_i32(); 1789 TCGv_i32 t3 = tcg_temp_new_i32(); 1790 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1791 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1792 tcg_gen_and_i32(t2, t2, t3); 1793 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1794 tcg_gen_or_i32(t2, t2, t3); 1795 tcg_gen_movi_i32(t3, 0); 1796 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1797 tcg_gen_rem_i32(t3, t0, t1); 1798 tcg_gen_ext_i32_tl(ret, t3); 1799 } else { 1800 TCGv_i32 t2 = tcg_constant_i32(1); 1801 TCGv_i32 t3 = tcg_constant_i32(0); 1802 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1803 tcg_gen_remu_i32(t0, t0, t1); 1804 tcg_gen_extu_i32_tl(ret, t0); 1805 } 1806 } 1807 1808 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1809 static void glue(gen_, name)(DisasContext *ctx) \ 1810 { \ 1811 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1812 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1813 sign); \ 1814 } 1815 1816 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1817 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1818 1819 #if defined(TARGET_PPC64) 1820 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1821 TCGv arg2, int sign) 1822 { 1823 TCGv_i64 t0 = tcg_temp_new_i64(); 1824 TCGv_i64 t1 = tcg_temp_new_i64(); 1825 1826 tcg_gen_mov_i64(t0, arg1); 1827 tcg_gen_mov_i64(t1, arg2); 1828 if (sign) { 1829 TCGv_i64 t2 = tcg_temp_new_i64(); 1830 TCGv_i64 t3 = tcg_temp_new_i64(); 1831 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1832 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1833 tcg_gen_and_i64(t2, t2, t3); 1834 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1835 tcg_gen_or_i64(t2, t2, t3); 1836 tcg_gen_movi_i64(t3, 0); 1837 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1838 tcg_gen_rem_i64(ret, t0, t1); 1839 } else { 1840 TCGv_i64 t2 = tcg_constant_i64(1); 1841 TCGv_i64 t3 = tcg_constant_i64(0); 1842 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1843 tcg_gen_remu_i64(ret, t0, t1); 1844 } 1845 } 1846 1847 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1848 static void glue(gen_, name)(DisasContext *ctx) \ 1849 { \ 1850 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1851 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1852 sign); \ 1853 } 1854 1855 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1856 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1857 #endif 1858 1859 /* mulhw mulhw. */ 1860 static void gen_mulhw(DisasContext *ctx) 1861 { 1862 TCGv_i32 t0 = tcg_temp_new_i32(); 1863 TCGv_i32 t1 = tcg_temp_new_i32(); 1864 1865 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1866 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1867 tcg_gen_muls2_i32(t0, t1, t0, t1); 1868 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1869 if (unlikely(Rc(ctx->opcode) != 0)) { 1870 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1871 } 1872 } 1873 1874 /* mulhwu mulhwu. */ 1875 static void gen_mulhwu(DisasContext *ctx) 1876 { 1877 TCGv_i32 t0 = tcg_temp_new_i32(); 1878 TCGv_i32 t1 = tcg_temp_new_i32(); 1879 1880 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1881 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1882 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1883 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1884 if (unlikely(Rc(ctx->opcode) != 0)) { 1885 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1886 } 1887 } 1888 1889 /* mullw mullw. */ 1890 static void gen_mullw(DisasContext *ctx) 1891 { 1892 #if defined(TARGET_PPC64) 1893 TCGv_i64 t0, t1; 1894 t0 = tcg_temp_new_i64(); 1895 t1 = tcg_temp_new_i64(); 1896 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1897 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1898 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1899 #else 1900 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1901 cpu_gpr[rB(ctx->opcode)]); 1902 #endif 1903 if (unlikely(Rc(ctx->opcode) != 0)) { 1904 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1905 } 1906 } 1907 1908 /* mullwo mullwo. */ 1909 static void gen_mullwo(DisasContext *ctx) 1910 { 1911 TCGv_i32 t0 = tcg_temp_new_i32(); 1912 TCGv_i32 t1 = tcg_temp_new_i32(); 1913 1914 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1915 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1916 tcg_gen_muls2_i32(t0, t1, t0, t1); 1917 #if defined(TARGET_PPC64) 1918 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1919 #else 1920 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1921 #endif 1922 1923 tcg_gen_sari_i32(t0, t0, 31); 1924 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1925 tcg_gen_extu_i32_tl(cpu_ov, t0); 1926 if (is_isa300(ctx)) { 1927 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1928 } 1929 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1930 1931 if (unlikely(Rc(ctx->opcode) != 0)) { 1932 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1933 } 1934 } 1935 1936 /* mulli */ 1937 static void gen_mulli(DisasContext *ctx) 1938 { 1939 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1940 SIMM(ctx->opcode)); 1941 } 1942 1943 #if defined(TARGET_PPC64) 1944 /* mulhd mulhd. */ 1945 static void gen_mulhd(DisasContext *ctx) 1946 { 1947 TCGv lo = tcg_temp_new(); 1948 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1949 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1950 if (unlikely(Rc(ctx->opcode) != 0)) { 1951 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1952 } 1953 } 1954 1955 /* mulhdu mulhdu. */ 1956 static void gen_mulhdu(DisasContext *ctx) 1957 { 1958 TCGv lo = tcg_temp_new(); 1959 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1960 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1961 if (unlikely(Rc(ctx->opcode) != 0)) { 1962 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1963 } 1964 } 1965 1966 /* mulld mulld. */ 1967 static void gen_mulld(DisasContext *ctx) 1968 { 1969 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1970 cpu_gpr[rB(ctx->opcode)]); 1971 if (unlikely(Rc(ctx->opcode) != 0)) { 1972 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1973 } 1974 } 1975 1976 /* mulldo mulldo. */ 1977 static void gen_mulldo(DisasContext *ctx) 1978 { 1979 TCGv_i64 t0 = tcg_temp_new_i64(); 1980 TCGv_i64 t1 = tcg_temp_new_i64(); 1981 1982 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1983 cpu_gpr[rB(ctx->opcode)]); 1984 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1985 1986 tcg_gen_sari_i64(t0, t0, 63); 1987 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1988 if (is_isa300(ctx)) { 1989 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1990 } 1991 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1992 1993 if (unlikely(Rc(ctx->opcode) != 0)) { 1994 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1995 } 1996 } 1997 #endif 1998 1999 /* Common subf function */ 2000 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2001 TCGv arg2, bool add_ca, bool compute_ca, 2002 bool compute_ov, bool compute_rc0) 2003 { 2004 TCGv t0 = ret; 2005 2006 if (compute_ca || compute_ov) { 2007 t0 = tcg_temp_new(); 2008 } 2009 2010 if (compute_ca) { 2011 /* dest = ~arg1 + arg2 [+ ca]. */ 2012 if (NARROW_MODE(ctx)) { 2013 /* 2014 * Caution: a non-obvious corner case of the spec is that 2015 * we must produce the *entire* 64-bit addition, but 2016 * produce the carry into bit 32. 2017 */ 2018 TCGv inv1 = tcg_temp_new(); 2019 TCGv t1 = tcg_temp_new(); 2020 tcg_gen_not_tl(inv1, arg1); 2021 if (add_ca) { 2022 tcg_gen_add_tl(t0, arg2, cpu_ca); 2023 } else { 2024 tcg_gen_addi_tl(t0, arg2, 1); 2025 } 2026 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2027 tcg_gen_add_tl(t0, t0, inv1); 2028 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2029 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2030 if (is_isa300(ctx)) { 2031 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2032 } 2033 } else if (add_ca) { 2034 TCGv zero, inv1 = tcg_temp_new(); 2035 tcg_gen_not_tl(inv1, arg1); 2036 zero = tcg_constant_tl(0); 2037 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2038 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2039 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2040 } else { 2041 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2042 tcg_gen_sub_tl(t0, arg2, arg1); 2043 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2044 } 2045 } else if (add_ca) { 2046 /* 2047 * Since we're ignoring carry-out, we can simplify the 2048 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2049 */ 2050 tcg_gen_sub_tl(t0, arg2, arg1); 2051 tcg_gen_add_tl(t0, t0, cpu_ca); 2052 tcg_gen_subi_tl(t0, t0, 1); 2053 } else { 2054 tcg_gen_sub_tl(t0, arg2, arg1); 2055 } 2056 2057 if (compute_ov) { 2058 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2059 } 2060 if (unlikely(compute_rc0)) { 2061 gen_set_Rc0(ctx, t0); 2062 } 2063 2064 if (t0 != ret) { 2065 tcg_gen_mov_tl(ret, t0); 2066 } 2067 } 2068 /* Sub functions with Two operands functions */ 2069 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2070 static void glue(gen_, name)(DisasContext *ctx) \ 2071 { \ 2072 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2074 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2075 } 2076 /* Sub functions with one operand and one immediate */ 2077 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2078 add_ca, compute_ca, compute_ov) \ 2079 static void glue(gen_, name)(DisasContext *ctx) \ 2080 { \ 2081 TCGv t0 = tcg_constant_tl(const_val); \ 2082 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2083 cpu_gpr[rA(ctx->opcode)], t0, \ 2084 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2085 } 2086 /* subf subf. subfo subfo. */ 2087 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2088 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2089 /* subfc subfc. subfco subfco. */ 2090 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2091 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2092 /* subfe subfe. subfeo subfo. */ 2093 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2094 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2095 /* subfme subfme. subfmeo subfmeo. */ 2096 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2097 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2098 /* subfze subfze. subfzeo subfzeo.*/ 2099 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2100 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2101 2102 /* subfic */ 2103 static void gen_subfic(DisasContext *ctx) 2104 { 2105 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2106 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2107 c, 0, 1, 0, 0); 2108 } 2109 2110 /* neg neg. nego nego. */ 2111 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2112 { 2113 TCGv zero = tcg_constant_tl(0); 2114 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2115 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2116 } 2117 2118 static void gen_neg(DisasContext *ctx) 2119 { 2120 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2121 if (unlikely(Rc(ctx->opcode))) { 2122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2123 } 2124 } 2125 2126 static void gen_nego(DisasContext *ctx) 2127 { 2128 gen_op_arith_neg(ctx, 1); 2129 } 2130 2131 /*** Integer logical ***/ 2132 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2133 static void glue(gen_, name)(DisasContext *ctx) \ 2134 { \ 2135 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2136 cpu_gpr[rB(ctx->opcode)]); \ 2137 if (unlikely(Rc(ctx->opcode) != 0)) \ 2138 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2139 } 2140 2141 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2142 static void glue(gen_, name)(DisasContext *ctx) \ 2143 { \ 2144 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2145 if (unlikely(Rc(ctx->opcode) != 0)) \ 2146 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2147 } 2148 2149 /* and & and. */ 2150 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2151 /* andc & andc. */ 2152 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2153 2154 /* andi. */ 2155 static void gen_andi_(DisasContext *ctx) 2156 { 2157 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2158 UIMM(ctx->opcode)); 2159 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2160 } 2161 2162 /* andis. */ 2163 static void gen_andis_(DisasContext *ctx) 2164 { 2165 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2166 UIMM(ctx->opcode) << 16); 2167 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2168 } 2169 2170 /* cntlzw */ 2171 static void gen_cntlzw(DisasContext *ctx) 2172 { 2173 TCGv_i32 t = tcg_temp_new_i32(); 2174 2175 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2176 tcg_gen_clzi_i32(t, t, 32); 2177 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2178 2179 if (unlikely(Rc(ctx->opcode) != 0)) { 2180 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2181 } 2182 } 2183 2184 /* cnttzw */ 2185 static void gen_cnttzw(DisasContext *ctx) 2186 { 2187 TCGv_i32 t = tcg_temp_new_i32(); 2188 2189 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2190 tcg_gen_ctzi_i32(t, t, 32); 2191 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2192 2193 if (unlikely(Rc(ctx->opcode) != 0)) { 2194 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2195 } 2196 } 2197 2198 /* eqv & eqv. */ 2199 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2200 /* extsb & extsb. */ 2201 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2202 /* extsh & extsh. */ 2203 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2204 /* nand & nand. */ 2205 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2206 /* nor & nor. */ 2207 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2208 2209 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2210 static void gen_pause(DisasContext *ctx) 2211 { 2212 TCGv_i32 t0 = tcg_constant_i32(0); 2213 tcg_gen_st_i32(t0, cpu_env, 2214 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2215 2216 /* Stop translation, this gives other CPUs a chance to run */ 2217 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2218 } 2219 #endif /* defined(TARGET_PPC64) */ 2220 2221 /* or & or. */ 2222 static void gen_or(DisasContext *ctx) 2223 { 2224 int rs, ra, rb; 2225 2226 rs = rS(ctx->opcode); 2227 ra = rA(ctx->opcode); 2228 rb = rB(ctx->opcode); 2229 /* Optimisation for mr. ri case */ 2230 if (rs != ra || rs != rb) { 2231 if (rs != rb) { 2232 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2233 } else { 2234 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2235 } 2236 if (unlikely(Rc(ctx->opcode) != 0)) { 2237 gen_set_Rc0(ctx, cpu_gpr[ra]); 2238 } 2239 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2240 gen_set_Rc0(ctx, cpu_gpr[rs]); 2241 #if defined(TARGET_PPC64) 2242 } else if (rs != 0) { /* 0 is nop */ 2243 int prio = 0; 2244 2245 switch (rs) { 2246 case 1: 2247 /* Set process priority to low */ 2248 prio = 2; 2249 break; 2250 case 6: 2251 /* Set process priority to medium-low */ 2252 prio = 3; 2253 break; 2254 case 2: 2255 /* Set process priority to normal */ 2256 prio = 4; 2257 break; 2258 #if !defined(CONFIG_USER_ONLY) 2259 case 31: 2260 if (!ctx->pr) { 2261 /* Set process priority to very low */ 2262 prio = 1; 2263 } 2264 break; 2265 case 5: 2266 if (!ctx->pr) { 2267 /* Set process priority to medium-hight */ 2268 prio = 5; 2269 } 2270 break; 2271 case 3: 2272 if (!ctx->pr) { 2273 /* Set process priority to high */ 2274 prio = 6; 2275 } 2276 break; 2277 case 7: 2278 if (ctx->hv && !ctx->pr) { 2279 /* Set process priority to very high */ 2280 prio = 7; 2281 } 2282 break; 2283 #endif 2284 default: 2285 break; 2286 } 2287 if (prio) { 2288 TCGv t0 = tcg_temp_new(); 2289 gen_load_spr(t0, SPR_PPR); 2290 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2291 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2292 gen_store_spr(SPR_PPR, t0); 2293 } 2294 #if !defined(CONFIG_USER_ONLY) 2295 /* 2296 * Pause out of TCG otherwise spin loops with smt_low eat too 2297 * much CPU and the kernel hangs. This applies to all 2298 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2299 * mdoio(29), mdoom(30), and all currently undefined. 2300 */ 2301 gen_pause(ctx); 2302 #endif 2303 #endif 2304 } 2305 } 2306 /* orc & orc. */ 2307 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2308 2309 /* xor & xor. */ 2310 static void gen_xor(DisasContext *ctx) 2311 { 2312 /* Optimisation for "set to zero" case */ 2313 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2314 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2315 cpu_gpr[rB(ctx->opcode)]); 2316 } else { 2317 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2318 } 2319 if (unlikely(Rc(ctx->opcode) != 0)) { 2320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2321 } 2322 } 2323 2324 /* ori */ 2325 static void gen_ori(DisasContext *ctx) 2326 { 2327 target_ulong uimm = UIMM(ctx->opcode); 2328 2329 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2330 return; 2331 } 2332 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2333 } 2334 2335 /* oris */ 2336 static void gen_oris(DisasContext *ctx) 2337 { 2338 target_ulong uimm = UIMM(ctx->opcode); 2339 2340 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2341 /* NOP */ 2342 return; 2343 } 2344 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2345 uimm << 16); 2346 } 2347 2348 /* xori */ 2349 static void gen_xori(DisasContext *ctx) 2350 { 2351 target_ulong uimm = UIMM(ctx->opcode); 2352 2353 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2354 /* NOP */ 2355 return; 2356 } 2357 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2358 } 2359 2360 /* xoris */ 2361 static void gen_xoris(DisasContext *ctx) 2362 { 2363 target_ulong uimm = UIMM(ctx->opcode); 2364 2365 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2366 /* NOP */ 2367 return; 2368 } 2369 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2370 uimm << 16); 2371 } 2372 2373 /* popcntb : PowerPC 2.03 specification */ 2374 static void gen_popcntb(DisasContext *ctx) 2375 { 2376 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2377 } 2378 2379 static void gen_popcntw(DisasContext *ctx) 2380 { 2381 #if defined(TARGET_PPC64) 2382 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2383 #else 2384 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2385 #endif 2386 } 2387 2388 #if defined(TARGET_PPC64) 2389 /* popcntd: PowerPC 2.06 specification */ 2390 static void gen_popcntd(DisasContext *ctx) 2391 { 2392 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2393 } 2394 #endif 2395 2396 /* prtyw: PowerPC 2.05 specification */ 2397 static void gen_prtyw(DisasContext *ctx) 2398 { 2399 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2400 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2401 TCGv t0 = tcg_temp_new(); 2402 tcg_gen_shri_tl(t0, rs, 16); 2403 tcg_gen_xor_tl(ra, rs, t0); 2404 tcg_gen_shri_tl(t0, ra, 8); 2405 tcg_gen_xor_tl(ra, ra, t0); 2406 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2407 } 2408 2409 #if defined(TARGET_PPC64) 2410 /* prtyd: PowerPC 2.05 specification */ 2411 static void gen_prtyd(DisasContext *ctx) 2412 { 2413 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2414 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2415 TCGv t0 = tcg_temp_new(); 2416 tcg_gen_shri_tl(t0, rs, 32); 2417 tcg_gen_xor_tl(ra, rs, t0); 2418 tcg_gen_shri_tl(t0, ra, 16); 2419 tcg_gen_xor_tl(ra, ra, t0); 2420 tcg_gen_shri_tl(t0, ra, 8); 2421 tcg_gen_xor_tl(ra, ra, t0); 2422 tcg_gen_andi_tl(ra, ra, 1); 2423 } 2424 #endif 2425 2426 #if defined(TARGET_PPC64) 2427 /* bpermd */ 2428 static void gen_bpermd(DisasContext *ctx) 2429 { 2430 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2431 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2432 } 2433 #endif 2434 2435 #if defined(TARGET_PPC64) 2436 /* extsw & extsw. */ 2437 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2438 2439 /* cntlzd */ 2440 static void gen_cntlzd(DisasContext *ctx) 2441 { 2442 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2443 if (unlikely(Rc(ctx->opcode) != 0)) { 2444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2445 } 2446 } 2447 2448 /* cnttzd */ 2449 static void gen_cnttzd(DisasContext *ctx) 2450 { 2451 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2452 if (unlikely(Rc(ctx->opcode) != 0)) { 2453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2454 } 2455 } 2456 2457 /* darn */ 2458 static void gen_darn(DisasContext *ctx) 2459 { 2460 int l = L(ctx->opcode); 2461 2462 if (l > 2) { 2463 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2464 } else { 2465 translator_io_start(&ctx->base); 2466 if (l == 0) { 2467 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2468 } else { 2469 /* Return 64-bit random for both CRN and RRN */ 2470 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2471 } 2472 } 2473 } 2474 #endif 2475 2476 /*** Integer rotate ***/ 2477 2478 /* rlwimi & rlwimi. */ 2479 static void gen_rlwimi(DisasContext *ctx) 2480 { 2481 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2482 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2483 uint32_t sh = SH(ctx->opcode); 2484 uint32_t mb = MB(ctx->opcode); 2485 uint32_t me = ME(ctx->opcode); 2486 2487 if (sh == (31 - me) && mb <= me) { 2488 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2489 } else { 2490 target_ulong mask; 2491 bool mask_in_32b = true; 2492 TCGv t1; 2493 2494 #if defined(TARGET_PPC64) 2495 mb += 32; 2496 me += 32; 2497 #endif 2498 mask = MASK(mb, me); 2499 2500 #if defined(TARGET_PPC64) 2501 if (mask > 0xffffffffu) { 2502 mask_in_32b = false; 2503 } 2504 #endif 2505 t1 = tcg_temp_new(); 2506 if (mask_in_32b) { 2507 TCGv_i32 t0 = tcg_temp_new_i32(); 2508 tcg_gen_trunc_tl_i32(t0, t_rs); 2509 tcg_gen_rotli_i32(t0, t0, sh); 2510 tcg_gen_extu_i32_tl(t1, t0); 2511 } else { 2512 #if defined(TARGET_PPC64) 2513 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2514 tcg_gen_rotli_i64(t1, t1, sh); 2515 #else 2516 g_assert_not_reached(); 2517 #endif 2518 } 2519 2520 tcg_gen_andi_tl(t1, t1, mask); 2521 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2522 tcg_gen_or_tl(t_ra, t_ra, t1); 2523 } 2524 if (unlikely(Rc(ctx->opcode) != 0)) { 2525 gen_set_Rc0(ctx, t_ra); 2526 } 2527 } 2528 2529 /* rlwinm & rlwinm. */ 2530 static void gen_rlwinm(DisasContext *ctx) 2531 { 2532 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2533 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2534 int sh = SH(ctx->opcode); 2535 int mb = MB(ctx->opcode); 2536 int me = ME(ctx->opcode); 2537 int len = me - mb + 1; 2538 int rsh = (32 - sh) & 31; 2539 2540 if (sh != 0 && len > 0 && me == (31 - sh)) { 2541 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2542 } else if (me == 31 && rsh + len <= 32) { 2543 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2544 } else { 2545 target_ulong mask; 2546 bool mask_in_32b = true; 2547 #if defined(TARGET_PPC64) 2548 mb += 32; 2549 me += 32; 2550 #endif 2551 mask = MASK(mb, me); 2552 #if defined(TARGET_PPC64) 2553 if (mask > 0xffffffffu) { 2554 mask_in_32b = false; 2555 } 2556 #endif 2557 if (mask_in_32b) { 2558 if (sh == 0) { 2559 tcg_gen_andi_tl(t_ra, t_rs, mask); 2560 } else { 2561 TCGv_i32 t0 = tcg_temp_new_i32(); 2562 tcg_gen_trunc_tl_i32(t0, t_rs); 2563 tcg_gen_rotli_i32(t0, t0, sh); 2564 tcg_gen_andi_i32(t0, t0, mask); 2565 tcg_gen_extu_i32_tl(t_ra, t0); 2566 } 2567 } else { 2568 #if defined(TARGET_PPC64) 2569 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2570 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2571 tcg_gen_andi_i64(t_ra, t_ra, mask); 2572 #else 2573 g_assert_not_reached(); 2574 #endif 2575 } 2576 } 2577 if (unlikely(Rc(ctx->opcode) != 0)) { 2578 gen_set_Rc0(ctx, t_ra); 2579 } 2580 } 2581 2582 /* rlwnm & rlwnm. */ 2583 static void gen_rlwnm(DisasContext *ctx) 2584 { 2585 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2586 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2587 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2588 uint32_t mb = MB(ctx->opcode); 2589 uint32_t me = ME(ctx->opcode); 2590 target_ulong mask; 2591 bool mask_in_32b = true; 2592 2593 #if defined(TARGET_PPC64) 2594 mb += 32; 2595 me += 32; 2596 #endif 2597 mask = MASK(mb, me); 2598 2599 #if defined(TARGET_PPC64) 2600 if (mask > 0xffffffffu) { 2601 mask_in_32b = false; 2602 } 2603 #endif 2604 if (mask_in_32b) { 2605 TCGv_i32 t0 = tcg_temp_new_i32(); 2606 TCGv_i32 t1 = tcg_temp_new_i32(); 2607 tcg_gen_trunc_tl_i32(t0, t_rb); 2608 tcg_gen_trunc_tl_i32(t1, t_rs); 2609 tcg_gen_andi_i32(t0, t0, 0x1f); 2610 tcg_gen_rotl_i32(t1, t1, t0); 2611 tcg_gen_extu_i32_tl(t_ra, t1); 2612 } else { 2613 #if defined(TARGET_PPC64) 2614 TCGv_i64 t0 = tcg_temp_new_i64(); 2615 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2616 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2617 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2618 #else 2619 g_assert_not_reached(); 2620 #endif 2621 } 2622 2623 tcg_gen_andi_tl(t_ra, t_ra, mask); 2624 2625 if (unlikely(Rc(ctx->opcode) != 0)) { 2626 gen_set_Rc0(ctx, t_ra); 2627 } 2628 } 2629 2630 #if defined(TARGET_PPC64) 2631 #define GEN_PPC64_R2(name, opc1, opc2) \ 2632 static void glue(gen_, name##0)(DisasContext *ctx) \ 2633 { \ 2634 gen_##name(ctx, 0); \ 2635 } \ 2636 \ 2637 static void glue(gen_, name##1)(DisasContext *ctx) \ 2638 { \ 2639 gen_##name(ctx, 1); \ 2640 } 2641 #define GEN_PPC64_R4(name, opc1, opc2) \ 2642 static void glue(gen_, name##0)(DisasContext *ctx) \ 2643 { \ 2644 gen_##name(ctx, 0, 0); \ 2645 } \ 2646 \ 2647 static void glue(gen_, name##1)(DisasContext *ctx) \ 2648 { \ 2649 gen_##name(ctx, 0, 1); \ 2650 } \ 2651 \ 2652 static void glue(gen_, name##2)(DisasContext *ctx) \ 2653 { \ 2654 gen_##name(ctx, 1, 0); \ 2655 } \ 2656 \ 2657 static void glue(gen_, name##3)(DisasContext *ctx) \ 2658 { \ 2659 gen_##name(ctx, 1, 1); \ 2660 } 2661 2662 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2663 { 2664 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2665 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2666 int len = me - mb + 1; 2667 int rsh = (64 - sh) & 63; 2668 2669 if (sh != 0 && len > 0 && me == (63 - sh)) { 2670 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2671 } else if (me == 63 && rsh + len <= 64) { 2672 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2673 } else { 2674 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2675 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2676 } 2677 if (unlikely(Rc(ctx->opcode) != 0)) { 2678 gen_set_Rc0(ctx, t_ra); 2679 } 2680 } 2681 2682 /* rldicl - rldicl. */ 2683 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2684 { 2685 uint32_t sh, mb; 2686 2687 sh = SH(ctx->opcode) | (shn << 5); 2688 mb = MB(ctx->opcode) | (mbn << 5); 2689 gen_rldinm(ctx, mb, 63, sh); 2690 } 2691 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2692 2693 /* rldicr - rldicr. */ 2694 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2695 { 2696 uint32_t sh, me; 2697 2698 sh = SH(ctx->opcode) | (shn << 5); 2699 me = MB(ctx->opcode) | (men << 5); 2700 gen_rldinm(ctx, 0, me, sh); 2701 } 2702 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2703 2704 /* rldic - rldic. */ 2705 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2706 { 2707 uint32_t sh, mb; 2708 2709 sh = SH(ctx->opcode) | (shn << 5); 2710 mb = MB(ctx->opcode) | (mbn << 5); 2711 gen_rldinm(ctx, mb, 63 - sh, sh); 2712 } 2713 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2714 2715 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2716 { 2717 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2718 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2719 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2720 TCGv t0; 2721 2722 t0 = tcg_temp_new(); 2723 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2724 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2725 2726 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2727 if (unlikely(Rc(ctx->opcode) != 0)) { 2728 gen_set_Rc0(ctx, t_ra); 2729 } 2730 } 2731 2732 /* rldcl - rldcl. */ 2733 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2734 { 2735 uint32_t mb; 2736 2737 mb = MB(ctx->opcode) | (mbn << 5); 2738 gen_rldnm(ctx, mb, 63); 2739 } 2740 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2741 2742 /* rldcr - rldcr. */ 2743 static inline void gen_rldcr(DisasContext *ctx, int men) 2744 { 2745 uint32_t me; 2746 2747 me = MB(ctx->opcode) | (men << 5); 2748 gen_rldnm(ctx, 0, me); 2749 } 2750 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2751 2752 /* rldimi - rldimi. */ 2753 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2754 { 2755 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2756 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2757 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2758 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2759 uint32_t me = 63 - sh; 2760 2761 if (mb <= me) { 2762 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2763 } else { 2764 target_ulong mask = MASK(mb, me); 2765 TCGv t1 = tcg_temp_new(); 2766 2767 tcg_gen_rotli_tl(t1, t_rs, sh); 2768 tcg_gen_andi_tl(t1, t1, mask); 2769 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2770 tcg_gen_or_tl(t_ra, t_ra, t1); 2771 } 2772 if (unlikely(Rc(ctx->opcode) != 0)) { 2773 gen_set_Rc0(ctx, t_ra); 2774 } 2775 } 2776 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2777 #endif 2778 2779 /*** Integer shift ***/ 2780 2781 /* slw & slw. */ 2782 static void gen_slw(DisasContext *ctx) 2783 { 2784 TCGv t0, t1; 2785 2786 t0 = tcg_temp_new(); 2787 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2788 #if defined(TARGET_PPC64) 2789 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2790 tcg_gen_sari_tl(t0, t0, 0x3f); 2791 #else 2792 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2793 tcg_gen_sari_tl(t0, t0, 0x1f); 2794 #endif 2795 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2796 t1 = tcg_temp_new(); 2797 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2798 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2799 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2800 if (unlikely(Rc(ctx->opcode) != 0)) { 2801 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2802 } 2803 } 2804 2805 /* sraw & sraw. */ 2806 static void gen_sraw(DisasContext *ctx) 2807 { 2808 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2809 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2810 if (unlikely(Rc(ctx->opcode) != 0)) { 2811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2812 } 2813 } 2814 2815 /* srawi & srawi. */ 2816 static void gen_srawi(DisasContext *ctx) 2817 { 2818 int sh = SH(ctx->opcode); 2819 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2820 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2821 if (sh == 0) { 2822 tcg_gen_ext32s_tl(dst, src); 2823 tcg_gen_movi_tl(cpu_ca, 0); 2824 if (is_isa300(ctx)) { 2825 tcg_gen_movi_tl(cpu_ca32, 0); 2826 } 2827 } else { 2828 TCGv t0; 2829 tcg_gen_ext32s_tl(dst, src); 2830 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2831 t0 = tcg_temp_new(); 2832 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2833 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2834 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2835 if (is_isa300(ctx)) { 2836 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2837 } 2838 tcg_gen_sari_tl(dst, dst, sh); 2839 } 2840 if (unlikely(Rc(ctx->opcode) != 0)) { 2841 gen_set_Rc0(ctx, dst); 2842 } 2843 } 2844 2845 /* srw & srw. */ 2846 static void gen_srw(DisasContext *ctx) 2847 { 2848 TCGv t0, t1; 2849 2850 t0 = tcg_temp_new(); 2851 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2852 #if defined(TARGET_PPC64) 2853 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2854 tcg_gen_sari_tl(t0, t0, 0x3f); 2855 #else 2856 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2857 tcg_gen_sari_tl(t0, t0, 0x1f); 2858 #endif 2859 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2860 tcg_gen_ext32u_tl(t0, t0); 2861 t1 = tcg_temp_new(); 2862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2863 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2864 if (unlikely(Rc(ctx->opcode) != 0)) { 2865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2866 } 2867 } 2868 2869 #if defined(TARGET_PPC64) 2870 /* sld & sld. */ 2871 static void gen_sld(DisasContext *ctx) 2872 { 2873 TCGv t0, t1; 2874 2875 t0 = tcg_temp_new(); 2876 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2878 tcg_gen_sari_tl(t0, t0, 0x3f); 2879 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2880 t1 = tcg_temp_new(); 2881 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2882 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2883 if (unlikely(Rc(ctx->opcode) != 0)) { 2884 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2885 } 2886 } 2887 2888 /* srad & srad. */ 2889 static void gen_srad(DisasContext *ctx) 2890 { 2891 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2892 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2893 if (unlikely(Rc(ctx->opcode) != 0)) { 2894 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2895 } 2896 } 2897 /* sradi & sradi. */ 2898 static inline void gen_sradi(DisasContext *ctx, int n) 2899 { 2900 int sh = SH(ctx->opcode) + (n << 5); 2901 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2902 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2903 if (sh == 0) { 2904 tcg_gen_mov_tl(dst, src); 2905 tcg_gen_movi_tl(cpu_ca, 0); 2906 if (is_isa300(ctx)) { 2907 tcg_gen_movi_tl(cpu_ca32, 0); 2908 } 2909 } else { 2910 TCGv t0; 2911 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2912 t0 = tcg_temp_new(); 2913 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2914 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2915 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2916 if (is_isa300(ctx)) { 2917 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2918 } 2919 tcg_gen_sari_tl(dst, src, sh); 2920 } 2921 if (unlikely(Rc(ctx->opcode) != 0)) { 2922 gen_set_Rc0(ctx, dst); 2923 } 2924 } 2925 2926 static void gen_sradi0(DisasContext *ctx) 2927 { 2928 gen_sradi(ctx, 0); 2929 } 2930 2931 static void gen_sradi1(DisasContext *ctx) 2932 { 2933 gen_sradi(ctx, 1); 2934 } 2935 2936 /* extswsli & extswsli. */ 2937 static inline void gen_extswsli(DisasContext *ctx, int n) 2938 { 2939 int sh = SH(ctx->opcode) + (n << 5); 2940 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2941 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2942 2943 tcg_gen_ext32s_tl(dst, src); 2944 tcg_gen_shli_tl(dst, dst, sh); 2945 if (unlikely(Rc(ctx->opcode) != 0)) { 2946 gen_set_Rc0(ctx, dst); 2947 } 2948 } 2949 2950 static void gen_extswsli0(DisasContext *ctx) 2951 { 2952 gen_extswsli(ctx, 0); 2953 } 2954 2955 static void gen_extswsli1(DisasContext *ctx) 2956 { 2957 gen_extswsli(ctx, 1); 2958 } 2959 2960 /* srd & srd. */ 2961 static void gen_srd(DisasContext *ctx) 2962 { 2963 TCGv t0, t1; 2964 2965 t0 = tcg_temp_new(); 2966 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2967 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2968 tcg_gen_sari_tl(t0, t0, 0x3f); 2969 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2970 t1 = tcg_temp_new(); 2971 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2972 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2973 if (unlikely(Rc(ctx->opcode) != 0)) { 2974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2975 } 2976 } 2977 #endif 2978 2979 /*** Addressing modes ***/ 2980 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2981 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2982 target_long maskl) 2983 { 2984 target_long simm = SIMM(ctx->opcode); 2985 2986 simm &= ~maskl; 2987 if (rA(ctx->opcode) == 0) { 2988 if (NARROW_MODE(ctx)) { 2989 simm = (uint32_t)simm; 2990 } 2991 tcg_gen_movi_tl(EA, simm); 2992 } else if (likely(simm != 0)) { 2993 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2994 if (NARROW_MODE(ctx)) { 2995 tcg_gen_ext32u_tl(EA, EA); 2996 } 2997 } else { 2998 if (NARROW_MODE(ctx)) { 2999 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3000 } else { 3001 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3002 } 3003 } 3004 } 3005 3006 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3007 { 3008 if (rA(ctx->opcode) == 0) { 3009 if (NARROW_MODE(ctx)) { 3010 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3011 } else { 3012 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3013 } 3014 } else { 3015 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3016 if (NARROW_MODE(ctx)) { 3017 tcg_gen_ext32u_tl(EA, EA); 3018 } 3019 } 3020 } 3021 3022 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3023 { 3024 if (rA(ctx->opcode) == 0) { 3025 tcg_gen_movi_tl(EA, 0); 3026 } else if (NARROW_MODE(ctx)) { 3027 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3028 } else { 3029 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3030 } 3031 } 3032 3033 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3034 target_long val) 3035 { 3036 tcg_gen_addi_tl(ret, arg1, val); 3037 if (NARROW_MODE(ctx)) { 3038 tcg_gen_ext32u_tl(ret, ret); 3039 } 3040 } 3041 3042 static inline void gen_align_no_le(DisasContext *ctx) 3043 { 3044 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3045 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3046 } 3047 3048 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3049 { 3050 TCGv ea = tcg_temp_new(); 3051 if (ra) { 3052 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3053 } else { 3054 tcg_gen_mov_tl(ea, displ); 3055 } 3056 if (NARROW_MODE(ctx)) { 3057 tcg_gen_ext32u_tl(ea, ea); 3058 } 3059 return ea; 3060 } 3061 3062 /*** Integer load ***/ 3063 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3064 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3065 3066 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3067 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3068 TCGv val, \ 3069 TCGv addr) \ 3070 { \ 3071 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3072 } 3073 3074 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3075 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3076 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3077 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3078 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3079 3080 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3081 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3082 3083 #define GEN_QEMU_LOAD_64(ldop, op) \ 3084 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3085 TCGv_i64 val, \ 3086 TCGv addr) \ 3087 { \ 3088 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3089 } 3090 3091 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3092 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3093 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3094 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3095 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3096 3097 #if defined(TARGET_PPC64) 3098 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3099 #endif 3100 3101 #define GEN_QEMU_STORE_TL(stop, op) \ 3102 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3103 TCGv val, \ 3104 TCGv addr) \ 3105 { \ 3106 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3107 } 3108 3109 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3110 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3111 #endif 3112 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3113 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3114 3115 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3116 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3117 3118 #define GEN_QEMU_STORE_64(stop, op) \ 3119 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3120 TCGv_i64 val, \ 3121 TCGv addr) \ 3122 { \ 3123 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3124 } 3125 3126 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3127 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3128 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3129 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3130 3131 #if defined(TARGET_PPC64) 3132 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3133 #endif 3134 3135 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3136 static void glue(gen_, name##x)(DisasContext *ctx) \ 3137 { \ 3138 TCGv EA; \ 3139 chk(ctx); \ 3140 gen_set_access_type(ctx, ACCESS_INT); \ 3141 EA = tcg_temp_new(); \ 3142 gen_addr_reg_index(ctx, EA); \ 3143 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3144 } 3145 3146 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3147 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3148 3149 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3150 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3151 3152 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3153 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3154 { \ 3155 TCGv EA; \ 3156 CHK_SV(ctx); \ 3157 gen_set_access_type(ctx, ACCESS_INT); \ 3158 EA = tcg_temp_new(); \ 3159 gen_addr_reg_index(ctx, EA); \ 3160 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3161 } 3162 3163 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3164 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3165 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3166 #if defined(TARGET_PPC64) 3167 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3168 #endif 3169 3170 #if defined(TARGET_PPC64) 3171 /* CI load/store variants */ 3172 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3173 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3174 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3175 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3176 #endif 3177 3178 /*** Integer store ***/ 3179 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3180 static void glue(gen_, name##x)(DisasContext *ctx) \ 3181 { \ 3182 TCGv EA; \ 3183 chk(ctx); \ 3184 gen_set_access_type(ctx, ACCESS_INT); \ 3185 EA = tcg_temp_new(); \ 3186 gen_addr_reg_index(ctx, EA); \ 3187 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3188 } 3189 #define GEN_STX(name, stop, opc2, opc3, type) \ 3190 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3191 3192 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3193 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3194 3195 #define GEN_STEPX(name, stop, opc2, opc3) \ 3196 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3197 { \ 3198 TCGv EA; \ 3199 CHK_SV(ctx); \ 3200 gen_set_access_type(ctx, ACCESS_INT); \ 3201 EA = tcg_temp_new(); \ 3202 gen_addr_reg_index(ctx, EA); \ 3203 tcg_gen_qemu_st_tl( \ 3204 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3205 } 3206 3207 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3208 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3209 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3210 #if defined(TARGET_PPC64) 3211 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3212 #endif 3213 3214 #if defined(TARGET_PPC64) 3215 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3216 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3217 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3218 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3219 #endif 3220 /*** Integer load and store with byte reverse ***/ 3221 3222 /* lhbrx */ 3223 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3224 3225 /* lwbrx */ 3226 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3227 3228 #if defined(TARGET_PPC64) 3229 /* ldbrx */ 3230 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3231 /* stdbrx */ 3232 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3233 #endif /* TARGET_PPC64 */ 3234 3235 /* sthbrx */ 3236 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3237 /* stwbrx */ 3238 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3239 3240 /*** Integer load and store multiple ***/ 3241 3242 /* lmw */ 3243 static void gen_lmw(DisasContext *ctx) 3244 { 3245 TCGv t0; 3246 TCGv_i32 t1; 3247 3248 if (ctx->le_mode) { 3249 gen_align_no_le(ctx); 3250 return; 3251 } 3252 gen_set_access_type(ctx, ACCESS_INT); 3253 t0 = tcg_temp_new(); 3254 t1 = tcg_constant_i32(rD(ctx->opcode)); 3255 gen_addr_imm_index(ctx, t0, 0); 3256 gen_helper_lmw(cpu_env, t0, t1); 3257 } 3258 3259 /* stmw */ 3260 static void gen_stmw(DisasContext *ctx) 3261 { 3262 TCGv t0; 3263 TCGv_i32 t1; 3264 3265 if (ctx->le_mode) { 3266 gen_align_no_le(ctx); 3267 return; 3268 } 3269 gen_set_access_type(ctx, ACCESS_INT); 3270 t0 = tcg_temp_new(); 3271 t1 = tcg_constant_i32(rS(ctx->opcode)); 3272 gen_addr_imm_index(ctx, t0, 0); 3273 gen_helper_stmw(cpu_env, t0, t1); 3274 } 3275 3276 /*** Integer load and store strings ***/ 3277 3278 /* lswi */ 3279 /* 3280 * PowerPC32 specification says we must generate an exception if rA is 3281 * in the range of registers to be loaded. In an other hand, IBM says 3282 * this is valid, but rA won't be loaded. For now, I'll follow the 3283 * spec... 3284 */ 3285 static void gen_lswi(DisasContext *ctx) 3286 { 3287 TCGv t0; 3288 TCGv_i32 t1, t2; 3289 int nb = NB(ctx->opcode); 3290 int start = rD(ctx->opcode); 3291 int ra = rA(ctx->opcode); 3292 int nr; 3293 3294 if (ctx->le_mode) { 3295 gen_align_no_le(ctx); 3296 return; 3297 } 3298 if (nb == 0) { 3299 nb = 32; 3300 } 3301 nr = DIV_ROUND_UP(nb, 4); 3302 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3304 return; 3305 } 3306 gen_set_access_type(ctx, ACCESS_INT); 3307 t0 = tcg_temp_new(); 3308 gen_addr_register(ctx, t0); 3309 t1 = tcg_constant_i32(nb); 3310 t2 = tcg_constant_i32(start); 3311 gen_helper_lsw(cpu_env, t0, t1, t2); 3312 } 3313 3314 /* lswx */ 3315 static void gen_lswx(DisasContext *ctx) 3316 { 3317 TCGv t0; 3318 TCGv_i32 t1, t2, t3; 3319 3320 if (ctx->le_mode) { 3321 gen_align_no_le(ctx); 3322 return; 3323 } 3324 gen_set_access_type(ctx, ACCESS_INT); 3325 t0 = tcg_temp_new(); 3326 gen_addr_reg_index(ctx, t0); 3327 t1 = tcg_constant_i32(rD(ctx->opcode)); 3328 t2 = tcg_constant_i32(rA(ctx->opcode)); 3329 t3 = tcg_constant_i32(rB(ctx->opcode)); 3330 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3331 } 3332 3333 /* stswi */ 3334 static void gen_stswi(DisasContext *ctx) 3335 { 3336 TCGv t0; 3337 TCGv_i32 t1, t2; 3338 int nb = NB(ctx->opcode); 3339 3340 if (ctx->le_mode) { 3341 gen_align_no_le(ctx); 3342 return; 3343 } 3344 gen_set_access_type(ctx, ACCESS_INT); 3345 t0 = tcg_temp_new(); 3346 gen_addr_register(ctx, t0); 3347 if (nb == 0) { 3348 nb = 32; 3349 } 3350 t1 = tcg_constant_i32(nb); 3351 t2 = tcg_constant_i32(rS(ctx->opcode)); 3352 gen_helper_stsw(cpu_env, t0, t1, t2); 3353 } 3354 3355 /* stswx */ 3356 static void gen_stswx(DisasContext *ctx) 3357 { 3358 TCGv t0; 3359 TCGv_i32 t1, t2; 3360 3361 if (ctx->le_mode) { 3362 gen_align_no_le(ctx); 3363 return; 3364 } 3365 gen_set_access_type(ctx, ACCESS_INT); 3366 t0 = tcg_temp_new(); 3367 gen_addr_reg_index(ctx, t0); 3368 t1 = tcg_temp_new_i32(); 3369 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3370 tcg_gen_andi_i32(t1, t1, 0x7F); 3371 t2 = tcg_constant_i32(rS(ctx->opcode)); 3372 gen_helper_stsw(cpu_env, t0, t1, t2); 3373 } 3374 3375 /*** Memory synchronisation ***/ 3376 /* eieio */ 3377 static void gen_eieio(DisasContext *ctx) 3378 { 3379 TCGBar bar = TCG_MO_ALL; 3380 3381 /* 3382 * eieio has complex semanitcs. It provides memory ordering between 3383 * operations in the set: 3384 * - loads from CI memory. 3385 * - stores to CI memory. 3386 * - stores to WT memory. 3387 * 3388 * It separately also orders memory for operations in the set: 3389 * - stores to cacheble memory. 3390 * 3391 * It also serializes instructions: 3392 * - dcbt and dcbst. 3393 * 3394 * It separately serializes: 3395 * - tlbie and tlbsync. 3396 * 3397 * And separately serializes: 3398 * - slbieg, slbiag, and slbsync. 3399 * 3400 * The end result is that CI memory ordering requires TCG_MO_ALL 3401 * and it is not possible to special-case more relaxed ordering for 3402 * cacheable accesses. TCG_BAR_SC is required to provide this 3403 * serialization. 3404 */ 3405 3406 /* 3407 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3408 * tell the CPU it is a store-forwarding barrier. 3409 */ 3410 if (ctx->opcode & 0x2000000) { 3411 /* 3412 * ISA says that "Reserved fields in instructions are ignored 3413 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3414 * as this is not an instruction software should be using, 3415 * complain to the user. 3416 */ 3417 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3418 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3419 TARGET_FMT_lx "\n", ctx->cia); 3420 } else { 3421 bar = TCG_MO_ST_LD; 3422 } 3423 } 3424 3425 tcg_gen_mb(bar | TCG_BAR_SC); 3426 } 3427 3428 #if !defined(CONFIG_USER_ONLY) 3429 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3430 { 3431 TCGv_i32 t; 3432 TCGLabel *l; 3433 3434 if (!ctx->lazy_tlb_flush) { 3435 return; 3436 } 3437 l = gen_new_label(); 3438 t = tcg_temp_new_i32(); 3439 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3440 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3441 if (global) { 3442 gen_helper_check_tlb_flush_global(cpu_env); 3443 } else { 3444 gen_helper_check_tlb_flush_local(cpu_env); 3445 } 3446 gen_set_label(l); 3447 } 3448 #else 3449 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3450 #endif 3451 3452 /* isync */ 3453 static void gen_isync(DisasContext *ctx) 3454 { 3455 /* 3456 * We need to check for a pending TLB flush. This can only happen in 3457 * kernel mode however so check MSR_PR 3458 */ 3459 if (!ctx->pr) { 3460 gen_check_tlb_flush(ctx, false); 3461 } 3462 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3463 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3464 } 3465 3466 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3467 3468 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3469 { 3470 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3471 TCGv t0 = tcg_temp_new(); 3472 3473 gen_set_access_type(ctx, ACCESS_RES); 3474 gen_addr_reg_index(ctx, t0); 3475 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3476 tcg_gen_mov_tl(cpu_reserve, t0); 3477 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3478 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3479 } 3480 3481 #define LARX(name, memop) \ 3482 static void gen_##name(DisasContext *ctx) \ 3483 { \ 3484 gen_load_locked(ctx, memop); \ 3485 } 3486 3487 /* lwarx */ 3488 LARX(lbarx, DEF_MEMOP(MO_UB)) 3489 LARX(lharx, DEF_MEMOP(MO_UW)) 3490 LARX(lwarx, DEF_MEMOP(MO_UL)) 3491 3492 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3493 TCGv EA, TCGCond cond, int addend) 3494 { 3495 TCGv t = tcg_temp_new(); 3496 TCGv t2 = tcg_temp_new(); 3497 TCGv u = tcg_temp_new(); 3498 3499 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3500 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3501 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3502 tcg_gen_addi_tl(u, t, addend); 3503 3504 /* E.g. for fetch and increment bounded... */ 3505 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3506 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3507 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3508 3509 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3510 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3511 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3512 } 3513 3514 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3515 { 3516 uint32_t gpr_FC = FC(ctx->opcode); 3517 TCGv EA = tcg_temp_new(); 3518 int rt = rD(ctx->opcode); 3519 bool need_serial; 3520 TCGv src, dst; 3521 3522 gen_addr_register(ctx, EA); 3523 dst = cpu_gpr[rt]; 3524 src = cpu_gpr[(rt + 1) & 31]; 3525 3526 need_serial = false; 3527 memop |= MO_ALIGN; 3528 switch (gpr_FC) { 3529 case 0: /* Fetch and add */ 3530 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3531 break; 3532 case 1: /* Fetch and xor */ 3533 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3534 break; 3535 case 2: /* Fetch and or */ 3536 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3537 break; 3538 case 3: /* Fetch and 'and' */ 3539 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3540 break; 3541 case 4: /* Fetch and max unsigned */ 3542 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3543 break; 3544 case 5: /* Fetch and max signed */ 3545 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3546 break; 3547 case 6: /* Fetch and min unsigned */ 3548 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3549 break; 3550 case 7: /* Fetch and min signed */ 3551 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3552 break; 3553 case 8: /* Swap */ 3554 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3555 break; 3556 3557 case 16: /* Compare and swap not equal */ 3558 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3559 need_serial = true; 3560 } else { 3561 TCGv t0 = tcg_temp_new(); 3562 TCGv t1 = tcg_temp_new(); 3563 3564 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3565 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3566 tcg_gen_mov_tl(t1, src); 3567 } else { 3568 tcg_gen_ext32u_tl(t1, src); 3569 } 3570 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3571 cpu_gpr[(rt + 2) & 31], t0); 3572 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3573 tcg_gen_mov_tl(dst, t0); 3574 } 3575 break; 3576 3577 case 24: /* Fetch and increment bounded */ 3578 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3579 need_serial = true; 3580 } else { 3581 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3582 } 3583 break; 3584 case 25: /* Fetch and increment equal */ 3585 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3586 need_serial = true; 3587 } else { 3588 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3589 } 3590 break; 3591 case 28: /* Fetch and decrement bounded */ 3592 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3593 need_serial = true; 3594 } else { 3595 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3596 } 3597 break; 3598 3599 default: 3600 /* invoke data storage error handler */ 3601 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3602 } 3603 3604 if (need_serial) { 3605 /* Restart with exclusive lock. */ 3606 gen_helper_exit_atomic(cpu_env); 3607 ctx->base.is_jmp = DISAS_NORETURN; 3608 } 3609 } 3610 3611 static void gen_lwat(DisasContext *ctx) 3612 { 3613 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3614 } 3615 3616 #ifdef TARGET_PPC64 3617 static void gen_ldat(DisasContext *ctx) 3618 { 3619 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3620 } 3621 #endif 3622 3623 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3624 { 3625 uint32_t gpr_FC = FC(ctx->opcode); 3626 TCGv EA = tcg_temp_new(); 3627 TCGv src, discard; 3628 3629 gen_addr_register(ctx, EA); 3630 src = cpu_gpr[rD(ctx->opcode)]; 3631 discard = tcg_temp_new(); 3632 3633 memop |= MO_ALIGN; 3634 switch (gpr_FC) { 3635 case 0: /* add and Store */ 3636 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3637 break; 3638 case 1: /* xor and Store */ 3639 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3640 break; 3641 case 2: /* Or and Store */ 3642 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3643 break; 3644 case 3: /* 'and' and Store */ 3645 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3646 break; 3647 case 4: /* Store max unsigned */ 3648 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3649 break; 3650 case 5: /* Store max signed */ 3651 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3652 break; 3653 case 6: /* Store min unsigned */ 3654 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3655 break; 3656 case 7: /* Store min signed */ 3657 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3658 break; 3659 case 24: /* Store twin */ 3660 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3661 /* Restart with exclusive lock. */ 3662 gen_helper_exit_atomic(cpu_env); 3663 ctx->base.is_jmp = DISAS_NORETURN; 3664 } else { 3665 TCGv t = tcg_temp_new(); 3666 TCGv t2 = tcg_temp_new(); 3667 TCGv s = tcg_temp_new(); 3668 TCGv s2 = tcg_temp_new(); 3669 TCGv ea_plus_s = tcg_temp_new(); 3670 3671 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3672 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3673 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3674 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3675 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3676 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3677 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3678 } 3679 break; 3680 default: 3681 /* invoke data storage error handler */ 3682 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3683 } 3684 } 3685 3686 static void gen_stwat(DisasContext *ctx) 3687 { 3688 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3689 } 3690 3691 #ifdef TARGET_PPC64 3692 static void gen_stdat(DisasContext *ctx) 3693 { 3694 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3695 } 3696 #endif 3697 3698 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3699 { 3700 TCGLabel *l1 = gen_new_label(); 3701 TCGLabel *l2 = gen_new_label(); 3702 TCGv t0 = tcg_temp_new(); 3703 int reg = rS(ctx->opcode); 3704 3705 gen_set_access_type(ctx, ACCESS_RES); 3706 gen_addr_reg_index(ctx, t0); 3707 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3708 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); 3709 3710 t0 = tcg_temp_new(); 3711 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3712 cpu_gpr[reg], ctx->mem_idx, 3713 DEF_MEMOP(memop) | MO_ALIGN); 3714 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3715 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3716 tcg_gen_or_tl(t0, t0, cpu_so); 3717 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3718 tcg_gen_br(l2); 3719 3720 gen_set_label(l1); 3721 3722 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3723 3724 gen_set_label(l2); 3725 tcg_gen_movi_tl(cpu_reserve, -1); 3726 } 3727 3728 #define STCX(name, memop) \ 3729 static void gen_##name(DisasContext *ctx) \ 3730 { \ 3731 gen_conditional_store(ctx, memop); \ 3732 } 3733 3734 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3735 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3736 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3737 3738 #if defined(TARGET_PPC64) 3739 /* ldarx */ 3740 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3741 /* stdcx. */ 3742 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3743 3744 /* lqarx */ 3745 static void gen_lqarx(DisasContext *ctx) 3746 { 3747 int rd = rD(ctx->opcode); 3748 TCGv EA, hi, lo; 3749 TCGv_i128 t16; 3750 3751 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3752 (rd == rB(ctx->opcode)))) { 3753 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3754 return; 3755 } 3756 3757 gen_set_access_type(ctx, ACCESS_RES); 3758 EA = tcg_temp_new(); 3759 gen_addr_reg_index(ctx, EA); 3760 3761 /* Note that the low part is always in RD+1, even in LE mode. */ 3762 lo = cpu_gpr[rd + 1]; 3763 hi = cpu_gpr[rd]; 3764 3765 t16 = tcg_temp_new_i128(); 3766 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3767 tcg_gen_extr_i128_i64(lo, hi, t16); 3768 3769 tcg_gen_mov_tl(cpu_reserve, EA); 3770 tcg_gen_movi_tl(cpu_reserve_length, 16); 3771 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3772 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3773 } 3774 3775 /* stqcx. */ 3776 static void gen_stqcx_(DisasContext *ctx) 3777 { 3778 TCGLabel *lab_fail, *lab_over; 3779 int rs = rS(ctx->opcode); 3780 TCGv EA, t0, t1; 3781 TCGv_i128 cmp, val; 3782 3783 if (unlikely(rs & 1)) { 3784 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3785 return; 3786 } 3787 3788 lab_fail = gen_new_label(); 3789 lab_over = gen_new_label(); 3790 3791 gen_set_access_type(ctx, ACCESS_RES); 3792 EA = tcg_temp_new(); 3793 gen_addr_reg_index(ctx, EA); 3794 3795 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 3796 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); 3797 3798 cmp = tcg_temp_new_i128(); 3799 val = tcg_temp_new_i128(); 3800 3801 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3802 3803 /* Note that the low part is always in RS+1, even in LE mode. */ 3804 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3805 3806 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3807 DEF_MEMOP(MO_128 | MO_ALIGN)); 3808 3809 t0 = tcg_temp_new(); 3810 t1 = tcg_temp_new(); 3811 tcg_gen_extr_i128_i64(t1, t0, val); 3812 3813 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3814 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3815 tcg_gen_or_tl(t0, t0, t1); 3816 3817 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3818 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3819 tcg_gen_or_tl(t0, t0, cpu_so); 3820 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3821 3822 tcg_gen_br(lab_over); 3823 gen_set_label(lab_fail); 3824 3825 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3826 3827 gen_set_label(lab_over); 3828 tcg_gen_movi_tl(cpu_reserve, -1); 3829 } 3830 #endif /* defined(TARGET_PPC64) */ 3831 3832 /* sync */ 3833 static void gen_sync(DisasContext *ctx) 3834 { 3835 TCGBar bar = TCG_MO_ALL; 3836 uint32_t l = (ctx->opcode >> 21) & 3; 3837 3838 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3839 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3840 } 3841 3842 /* 3843 * We may need to check for a pending TLB flush. 3844 * 3845 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3846 * 3847 * Additionally, this can only happen in kernel mode however so 3848 * check MSR_PR as well. 3849 */ 3850 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3851 gen_check_tlb_flush(ctx, true); 3852 } 3853 3854 tcg_gen_mb(bar | TCG_BAR_SC); 3855 } 3856 3857 /* wait */ 3858 static void gen_wait(DisasContext *ctx) 3859 { 3860 uint32_t wc; 3861 3862 if (ctx->insns_flags & PPC_WAIT) { 3863 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3864 3865 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3866 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3867 wc = WC(ctx->opcode); 3868 } else { 3869 wc = 0; 3870 } 3871 3872 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3873 /* v3.0 defines a new 'wait' encoding. */ 3874 wc = WC(ctx->opcode); 3875 if (ctx->insns_flags2 & PPC2_ISA310) { 3876 uint32_t pl = PL(ctx->opcode); 3877 3878 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3879 if (wc == 3) { 3880 gen_invalid(ctx); 3881 return; 3882 } 3883 3884 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3885 if (pl > 0 && wc != 2) { 3886 gen_invalid(ctx); 3887 return; 3888 } 3889 3890 } else { /* ISA300 */ 3891 /* WC 1-3 are reserved */ 3892 if (wc > 0) { 3893 gen_invalid(ctx); 3894 return; 3895 } 3896 } 3897 3898 } else { 3899 warn_report("wait instruction decoded with wrong ISA flags."); 3900 gen_invalid(ctx); 3901 return; 3902 } 3903 3904 /* 3905 * wait without WC field or with WC=0 waits for an exception / interrupt 3906 * to occur. 3907 */ 3908 if (wc == 0) { 3909 TCGv_i32 t0 = tcg_constant_i32(1); 3910 tcg_gen_st_i32(t0, cpu_env, 3911 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3912 /* Stop translation, as the CPU is supposed to sleep from now */ 3913 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3914 } 3915 3916 /* 3917 * Other wait types must not just wait until an exception occurs because 3918 * ignoring their other wake-up conditions could cause a hang. 3919 * 3920 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3921 * no-ops. 3922 * 3923 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3924 * 3925 * wc=2 waits for an implementation-specific condition, such could be 3926 * always true, so it can be implemented as a no-op. 3927 * 3928 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3929 * 3930 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3931 * Reservation-loss may have implementation-specific conditions, so it 3932 * can be implemented as a no-op. 3933 * 3934 * wc=2 waits for an exception or an amount of time to pass. This 3935 * amount is implementation-specific so it can be implemented as a 3936 * no-op. 3937 * 3938 * ISA v3.1 allows for execution to resume "in the rare case of 3939 * an implementation-dependent event", so in any case software must 3940 * not depend on the architected resumption condition to become 3941 * true, so no-op implementations should be architecturally correct 3942 * (if suboptimal). 3943 */ 3944 } 3945 3946 #if defined(TARGET_PPC64) 3947 static void gen_doze(DisasContext *ctx) 3948 { 3949 #if defined(CONFIG_USER_ONLY) 3950 GEN_PRIV(ctx); 3951 #else 3952 TCGv_i32 t; 3953 3954 CHK_HV(ctx); 3955 t = tcg_constant_i32(PPC_PM_DOZE); 3956 gen_helper_pminsn(cpu_env, t); 3957 /* Stop translation, as the CPU is supposed to sleep from now */ 3958 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3959 #endif /* defined(CONFIG_USER_ONLY) */ 3960 } 3961 3962 static void gen_nap(DisasContext *ctx) 3963 { 3964 #if defined(CONFIG_USER_ONLY) 3965 GEN_PRIV(ctx); 3966 #else 3967 TCGv_i32 t; 3968 3969 CHK_HV(ctx); 3970 t = tcg_constant_i32(PPC_PM_NAP); 3971 gen_helper_pminsn(cpu_env, t); 3972 /* Stop translation, as the CPU is supposed to sleep from now */ 3973 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3974 #endif /* defined(CONFIG_USER_ONLY) */ 3975 } 3976 3977 static void gen_stop(DisasContext *ctx) 3978 { 3979 #if defined(CONFIG_USER_ONLY) 3980 GEN_PRIV(ctx); 3981 #else 3982 TCGv_i32 t; 3983 3984 CHK_HV(ctx); 3985 t = tcg_constant_i32(PPC_PM_STOP); 3986 gen_helper_pminsn(cpu_env, t); 3987 /* Stop translation, as the CPU is supposed to sleep from now */ 3988 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3989 #endif /* defined(CONFIG_USER_ONLY) */ 3990 } 3991 3992 static void gen_sleep(DisasContext *ctx) 3993 { 3994 #if defined(CONFIG_USER_ONLY) 3995 GEN_PRIV(ctx); 3996 #else 3997 TCGv_i32 t; 3998 3999 CHK_HV(ctx); 4000 t = tcg_constant_i32(PPC_PM_SLEEP); 4001 gen_helper_pminsn(cpu_env, t); 4002 /* Stop translation, as the CPU is supposed to sleep from now */ 4003 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4004 #endif /* defined(CONFIG_USER_ONLY) */ 4005 } 4006 4007 static void gen_rvwinkle(DisasContext *ctx) 4008 { 4009 #if defined(CONFIG_USER_ONLY) 4010 GEN_PRIV(ctx); 4011 #else 4012 TCGv_i32 t; 4013 4014 CHK_HV(ctx); 4015 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4016 gen_helper_pminsn(cpu_env, t); 4017 /* Stop translation, as the CPU is supposed to sleep from now */ 4018 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4019 #endif /* defined(CONFIG_USER_ONLY) */ 4020 } 4021 #endif /* #if defined(TARGET_PPC64) */ 4022 4023 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4024 { 4025 #if defined(TARGET_PPC64) 4026 if (ctx->has_cfar) { 4027 tcg_gen_movi_tl(cpu_cfar, nip); 4028 } 4029 #endif 4030 } 4031 4032 #if defined(TARGET_PPC64) 4033 static void pmu_count_insns(DisasContext *ctx) 4034 { 4035 /* 4036 * Do not bother calling the helper if the PMU isn't counting 4037 * instructions. 4038 */ 4039 if (!ctx->pmu_insn_cnt) { 4040 return; 4041 } 4042 4043 #if !defined(CONFIG_USER_ONLY) 4044 TCGLabel *l; 4045 TCGv t0; 4046 4047 /* 4048 * The PMU insns_inc() helper stops the internal PMU timer if a 4049 * counter overflows happens. In that case, if the guest is 4050 * running with icount and we do not handle it beforehand, 4051 * the helper can trigger a 'bad icount read'. 4052 */ 4053 translator_io_start(&ctx->base); 4054 4055 /* Avoid helper calls when only PMC5-6 are enabled. */ 4056 if (!ctx->pmc_other) { 4057 l = gen_new_label(); 4058 t0 = tcg_temp_new(); 4059 4060 gen_load_spr(t0, SPR_POWER_PMC5); 4061 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4062 gen_store_spr(SPR_POWER_PMC5, t0); 4063 /* Check for overflow, if it's enabled */ 4064 if (ctx->mmcr0_pmcjce) { 4065 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4066 gen_helper_handle_pmc5_overflow(cpu_env); 4067 } 4068 4069 gen_set_label(l); 4070 } else { 4071 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4072 } 4073 #else 4074 /* 4075 * User mode can read (but not write) PMC5 and start/stop 4076 * the PMU via MMCR0_FC. In this case just increment 4077 * PMC5 with base.num_insns. 4078 */ 4079 TCGv t0 = tcg_temp_new(); 4080 4081 gen_load_spr(t0, SPR_POWER_PMC5); 4082 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4083 gen_store_spr(SPR_POWER_PMC5, t0); 4084 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4085 } 4086 #else 4087 static void pmu_count_insns(DisasContext *ctx) 4088 { 4089 return; 4090 } 4091 #endif /* #if defined(TARGET_PPC64) */ 4092 4093 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4094 { 4095 return translator_use_goto_tb(&ctx->base, dest); 4096 } 4097 4098 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4099 { 4100 if (unlikely(ctx->singlestep_enabled)) { 4101 gen_debug_exception(ctx); 4102 } else { 4103 /* 4104 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4105 * CF_NO_GOTO_PTR is set. Count insns now. 4106 */ 4107 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4108 pmu_count_insns(ctx); 4109 } 4110 4111 tcg_gen_lookup_and_goto_ptr(); 4112 } 4113 } 4114 4115 /*** Branch ***/ 4116 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4117 { 4118 if (NARROW_MODE(ctx)) { 4119 dest = (uint32_t) dest; 4120 } 4121 if (use_goto_tb(ctx, dest)) { 4122 pmu_count_insns(ctx); 4123 tcg_gen_goto_tb(n); 4124 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4125 tcg_gen_exit_tb(ctx->base.tb, n); 4126 } else { 4127 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4128 gen_lookup_and_goto_ptr(ctx); 4129 } 4130 } 4131 4132 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4133 { 4134 if (NARROW_MODE(ctx)) { 4135 nip = (uint32_t)nip; 4136 } 4137 tcg_gen_movi_tl(cpu_lr, nip); 4138 } 4139 4140 /* b ba bl bla */ 4141 static void gen_b(DisasContext *ctx) 4142 { 4143 target_ulong li, target; 4144 4145 /* sign extend LI */ 4146 li = LI(ctx->opcode); 4147 li = (li ^ 0x02000000) - 0x02000000; 4148 if (likely(AA(ctx->opcode) == 0)) { 4149 target = ctx->cia + li; 4150 } else { 4151 target = li; 4152 } 4153 if (LK(ctx->opcode)) { 4154 gen_setlr(ctx, ctx->base.pc_next); 4155 } 4156 gen_update_cfar(ctx, ctx->cia); 4157 gen_goto_tb(ctx, 0, target); 4158 ctx->base.is_jmp = DISAS_NORETURN; 4159 } 4160 4161 #define BCOND_IM 0 4162 #define BCOND_LR 1 4163 #define BCOND_CTR 2 4164 #define BCOND_TAR 3 4165 4166 static void gen_bcond(DisasContext *ctx, int type) 4167 { 4168 uint32_t bo = BO(ctx->opcode); 4169 TCGLabel *l1; 4170 TCGv target; 4171 4172 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4173 target = tcg_temp_new(); 4174 if (type == BCOND_CTR) { 4175 tcg_gen_mov_tl(target, cpu_ctr); 4176 } else if (type == BCOND_TAR) { 4177 gen_load_spr(target, SPR_TAR); 4178 } else { 4179 tcg_gen_mov_tl(target, cpu_lr); 4180 } 4181 } else { 4182 target = NULL; 4183 } 4184 if (LK(ctx->opcode)) { 4185 gen_setlr(ctx, ctx->base.pc_next); 4186 } 4187 l1 = gen_new_label(); 4188 if ((bo & 0x4) == 0) { 4189 /* Decrement and test CTR */ 4190 TCGv temp = tcg_temp_new(); 4191 4192 if (type == BCOND_CTR) { 4193 /* 4194 * All ISAs up to v3 describe this form of bcctr as invalid but 4195 * some processors, ie. 64-bit server processors compliant with 4196 * arch 2.x, do implement a "test and decrement" logic instead, 4197 * as described in their respective UMs. This logic involves CTR 4198 * to act as both the branch target and a counter, which makes 4199 * it basically useless and thus never used in real code. 4200 * 4201 * This form was hence chosen to trigger extra micro-architectural 4202 * side-effect on real HW needed for the Spectre v2 workaround. 4203 * It is up to guests that implement such workaround, ie. linux, to 4204 * use this form in a way it just triggers the side-effect without 4205 * doing anything else harmful. 4206 */ 4207 if (unlikely(!is_book3s_arch2x(ctx))) { 4208 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4209 return; 4210 } 4211 4212 if (NARROW_MODE(ctx)) { 4213 tcg_gen_ext32u_tl(temp, cpu_ctr); 4214 } else { 4215 tcg_gen_mov_tl(temp, cpu_ctr); 4216 } 4217 if (bo & 0x2) { 4218 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4219 } else { 4220 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4221 } 4222 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4223 } else { 4224 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4225 if (NARROW_MODE(ctx)) { 4226 tcg_gen_ext32u_tl(temp, cpu_ctr); 4227 } else { 4228 tcg_gen_mov_tl(temp, cpu_ctr); 4229 } 4230 if (bo & 0x2) { 4231 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4232 } else { 4233 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4234 } 4235 } 4236 } 4237 if ((bo & 0x10) == 0) { 4238 /* Test CR */ 4239 uint32_t bi = BI(ctx->opcode); 4240 uint32_t mask = 0x08 >> (bi & 0x03); 4241 TCGv_i32 temp = tcg_temp_new_i32(); 4242 4243 if (bo & 0x8) { 4244 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4245 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4246 } else { 4247 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4248 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4249 } 4250 } 4251 gen_update_cfar(ctx, ctx->cia); 4252 if (type == BCOND_IM) { 4253 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4254 if (likely(AA(ctx->opcode) == 0)) { 4255 gen_goto_tb(ctx, 0, ctx->cia + li); 4256 } else { 4257 gen_goto_tb(ctx, 0, li); 4258 } 4259 } else { 4260 if (NARROW_MODE(ctx)) { 4261 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4262 } else { 4263 tcg_gen_andi_tl(cpu_nip, target, ~3); 4264 } 4265 gen_lookup_and_goto_ptr(ctx); 4266 } 4267 if ((bo & 0x14) != 0x14) { 4268 /* fallthrough case */ 4269 gen_set_label(l1); 4270 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4271 } 4272 ctx->base.is_jmp = DISAS_NORETURN; 4273 } 4274 4275 static void gen_bc(DisasContext *ctx) 4276 { 4277 gen_bcond(ctx, BCOND_IM); 4278 } 4279 4280 static void gen_bcctr(DisasContext *ctx) 4281 { 4282 gen_bcond(ctx, BCOND_CTR); 4283 } 4284 4285 static void gen_bclr(DisasContext *ctx) 4286 { 4287 gen_bcond(ctx, BCOND_LR); 4288 } 4289 4290 static void gen_bctar(DisasContext *ctx) 4291 { 4292 gen_bcond(ctx, BCOND_TAR); 4293 } 4294 4295 /*** Condition register logical ***/ 4296 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4297 static void glue(gen_, name)(DisasContext *ctx) \ 4298 { \ 4299 uint8_t bitmask; \ 4300 int sh; \ 4301 TCGv_i32 t0, t1; \ 4302 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4303 t0 = tcg_temp_new_i32(); \ 4304 if (sh > 0) \ 4305 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4306 else if (sh < 0) \ 4307 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4308 else \ 4309 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4310 t1 = tcg_temp_new_i32(); \ 4311 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4312 if (sh > 0) \ 4313 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4314 else if (sh < 0) \ 4315 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4316 else \ 4317 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4318 tcg_op(t0, t0, t1); \ 4319 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4320 tcg_gen_andi_i32(t0, t0, bitmask); \ 4321 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4322 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4323 } 4324 4325 /* crand */ 4326 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4327 /* crandc */ 4328 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4329 /* creqv */ 4330 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4331 /* crnand */ 4332 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4333 /* crnor */ 4334 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4335 /* cror */ 4336 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4337 /* crorc */ 4338 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4339 /* crxor */ 4340 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4341 4342 /* mcrf */ 4343 static void gen_mcrf(DisasContext *ctx) 4344 { 4345 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4346 } 4347 4348 /*** System linkage ***/ 4349 4350 /* rfi (supervisor only) */ 4351 static void gen_rfi(DisasContext *ctx) 4352 { 4353 #if defined(CONFIG_USER_ONLY) 4354 GEN_PRIV(ctx); 4355 #else 4356 /* 4357 * This instruction doesn't exist anymore on 64-bit server 4358 * processors compliant with arch 2.x 4359 */ 4360 if (is_book3s_arch2x(ctx)) { 4361 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4362 return; 4363 } 4364 /* Restore CPU state */ 4365 CHK_SV(ctx); 4366 translator_io_start(&ctx->base); 4367 gen_update_cfar(ctx, ctx->cia); 4368 gen_helper_rfi(cpu_env); 4369 ctx->base.is_jmp = DISAS_EXIT; 4370 #endif 4371 } 4372 4373 #if defined(TARGET_PPC64) 4374 static void gen_rfid(DisasContext *ctx) 4375 { 4376 #if defined(CONFIG_USER_ONLY) 4377 GEN_PRIV(ctx); 4378 #else 4379 /* Restore CPU state */ 4380 CHK_SV(ctx); 4381 translator_io_start(&ctx->base); 4382 gen_update_cfar(ctx, ctx->cia); 4383 gen_helper_rfid(cpu_env); 4384 ctx->base.is_jmp = DISAS_EXIT; 4385 #endif 4386 } 4387 4388 #if !defined(CONFIG_USER_ONLY) 4389 static void gen_rfscv(DisasContext *ctx) 4390 { 4391 #if defined(CONFIG_USER_ONLY) 4392 GEN_PRIV(ctx); 4393 #else 4394 /* Restore CPU state */ 4395 CHK_SV(ctx); 4396 translator_io_start(&ctx->base); 4397 gen_update_cfar(ctx, ctx->cia); 4398 gen_helper_rfscv(cpu_env); 4399 ctx->base.is_jmp = DISAS_EXIT; 4400 #endif 4401 } 4402 #endif 4403 4404 static void gen_hrfid(DisasContext *ctx) 4405 { 4406 #if defined(CONFIG_USER_ONLY) 4407 GEN_PRIV(ctx); 4408 #else 4409 /* Restore CPU state */ 4410 CHK_HV(ctx); 4411 gen_helper_hrfid(cpu_env); 4412 ctx->base.is_jmp = DISAS_EXIT; 4413 #endif 4414 } 4415 #endif 4416 4417 /* sc */ 4418 #if defined(CONFIG_USER_ONLY) 4419 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4420 #else 4421 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4422 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4423 #endif 4424 static void gen_sc(DisasContext *ctx) 4425 { 4426 uint32_t lev; 4427 4428 lev = (ctx->opcode >> 5) & 0x7F; 4429 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4430 } 4431 4432 #if defined(TARGET_PPC64) 4433 #if !defined(CONFIG_USER_ONLY) 4434 static void gen_scv(DisasContext *ctx) 4435 { 4436 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4437 4438 /* Set the PC back to the faulting instruction. */ 4439 gen_update_nip(ctx, ctx->cia); 4440 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4441 4442 ctx->base.is_jmp = DISAS_NORETURN; 4443 } 4444 #endif 4445 #endif 4446 4447 /*** Trap ***/ 4448 4449 /* Check for unconditional traps (always or never) */ 4450 static bool check_unconditional_trap(DisasContext *ctx) 4451 { 4452 /* Trap never */ 4453 if (TO(ctx->opcode) == 0) { 4454 return true; 4455 } 4456 /* Trap always */ 4457 if (TO(ctx->opcode) == 31) { 4458 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4459 return true; 4460 } 4461 return false; 4462 } 4463 4464 /* tw */ 4465 static void gen_tw(DisasContext *ctx) 4466 { 4467 TCGv_i32 t0; 4468 4469 if (check_unconditional_trap(ctx)) { 4470 return; 4471 } 4472 t0 = tcg_constant_i32(TO(ctx->opcode)); 4473 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4474 t0); 4475 } 4476 4477 /* twi */ 4478 static void gen_twi(DisasContext *ctx) 4479 { 4480 TCGv t0; 4481 TCGv_i32 t1; 4482 4483 if (check_unconditional_trap(ctx)) { 4484 return; 4485 } 4486 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4487 t1 = tcg_constant_i32(TO(ctx->opcode)); 4488 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4489 } 4490 4491 #if defined(TARGET_PPC64) 4492 /* td */ 4493 static void gen_td(DisasContext *ctx) 4494 { 4495 TCGv_i32 t0; 4496 4497 if (check_unconditional_trap(ctx)) { 4498 return; 4499 } 4500 t0 = tcg_constant_i32(TO(ctx->opcode)); 4501 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4502 t0); 4503 } 4504 4505 /* tdi */ 4506 static void gen_tdi(DisasContext *ctx) 4507 { 4508 TCGv t0; 4509 TCGv_i32 t1; 4510 4511 if (check_unconditional_trap(ctx)) { 4512 return; 4513 } 4514 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4515 t1 = tcg_constant_i32(TO(ctx->opcode)); 4516 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4517 } 4518 #endif 4519 4520 /*** Processor control ***/ 4521 4522 /* mcrxr */ 4523 static void gen_mcrxr(DisasContext *ctx) 4524 { 4525 TCGv_i32 t0 = tcg_temp_new_i32(); 4526 TCGv_i32 t1 = tcg_temp_new_i32(); 4527 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4528 4529 tcg_gen_trunc_tl_i32(t0, cpu_so); 4530 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4531 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4532 tcg_gen_shli_i32(t0, t0, 3); 4533 tcg_gen_shli_i32(t1, t1, 2); 4534 tcg_gen_shli_i32(dst, dst, 1); 4535 tcg_gen_or_i32(dst, dst, t0); 4536 tcg_gen_or_i32(dst, dst, t1); 4537 4538 tcg_gen_movi_tl(cpu_so, 0); 4539 tcg_gen_movi_tl(cpu_ov, 0); 4540 tcg_gen_movi_tl(cpu_ca, 0); 4541 } 4542 4543 #ifdef TARGET_PPC64 4544 /* mcrxrx */ 4545 static void gen_mcrxrx(DisasContext *ctx) 4546 { 4547 TCGv t0 = tcg_temp_new(); 4548 TCGv t1 = tcg_temp_new(); 4549 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4550 4551 /* copy OV and OV32 */ 4552 tcg_gen_shli_tl(t0, cpu_ov, 1); 4553 tcg_gen_or_tl(t0, t0, cpu_ov32); 4554 tcg_gen_shli_tl(t0, t0, 2); 4555 /* copy CA and CA32 */ 4556 tcg_gen_shli_tl(t1, cpu_ca, 1); 4557 tcg_gen_or_tl(t1, t1, cpu_ca32); 4558 tcg_gen_or_tl(t0, t0, t1); 4559 tcg_gen_trunc_tl_i32(dst, t0); 4560 } 4561 #endif 4562 4563 /* mfcr mfocrf */ 4564 static void gen_mfcr(DisasContext *ctx) 4565 { 4566 uint32_t crm, crn; 4567 4568 if (likely(ctx->opcode & 0x00100000)) { 4569 crm = CRM(ctx->opcode); 4570 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4571 crn = ctz32(crm); 4572 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4573 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4574 cpu_gpr[rD(ctx->opcode)], crn * 4); 4575 } 4576 } else { 4577 TCGv_i32 t0 = tcg_temp_new_i32(); 4578 tcg_gen_mov_i32(t0, cpu_crf[0]); 4579 tcg_gen_shli_i32(t0, t0, 4); 4580 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4581 tcg_gen_shli_i32(t0, t0, 4); 4582 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4583 tcg_gen_shli_i32(t0, t0, 4); 4584 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4585 tcg_gen_shli_i32(t0, t0, 4); 4586 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4587 tcg_gen_shli_i32(t0, t0, 4); 4588 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4589 tcg_gen_shli_i32(t0, t0, 4); 4590 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4591 tcg_gen_shli_i32(t0, t0, 4); 4592 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4593 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4594 } 4595 } 4596 4597 /* mfmsr */ 4598 static void gen_mfmsr(DisasContext *ctx) 4599 { 4600 CHK_SV(ctx); 4601 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4602 } 4603 4604 /* mfspr */ 4605 static inline void gen_op_mfspr(DisasContext *ctx) 4606 { 4607 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4608 uint32_t sprn = SPR(ctx->opcode); 4609 4610 #if defined(CONFIG_USER_ONLY) 4611 read_cb = ctx->spr_cb[sprn].uea_read; 4612 #else 4613 if (ctx->pr) { 4614 read_cb = ctx->spr_cb[sprn].uea_read; 4615 } else if (ctx->hv) { 4616 read_cb = ctx->spr_cb[sprn].hea_read; 4617 } else { 4618 read_cb = ctx->spr_cb[sprn].oea_read; 4619 } 4620 #endif 4621 if (likely(read_cb != NULL)) { 4622 if (likely(read_cb != SPR_NOACCESS)) { 4623 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4624 } else { 4625 /* Privilege exception */ 4626 /* 4627 * This is a hack to avoid warnings when running Linux: 4628 * this OS breaks the PowerPC virtualisation model, 4629 * allowing userland application to read the PVR 4630 */ 4631 if (sprn != SPR_PVR) { 4632 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4633 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4634 ctx->cia); 4635 } 4636 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4637 } 4638 } else { 4639 /* ISA 2.07 defines these as no-ops */ 4640 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4641 (sprn >= 808 && sprn <= 811)) { 4642 /* This is a nop */ 4643 return; 4644 } 4645 /* Not defined */ 4646 qemu_log_mask(LOG_GUEST_ERROR, 4647 "Trying to read invalid spr %d (0x%03x) at " 4648 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4649 4650 /* 4651 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4652 * generate a priv, a hv emu or a no-op 4653 */ 4654 if (sprn & 0x10) { 4655 if (ctx->pr) { 4656 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4657 } 4658 } else { 4659 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4660 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4661 } 4662 } 4663 } 4664 } 4665 4666 static void gen_mfspr(DisasContext *ctx) 4667 { 4668 gen_op_mfspr(ctx); 4669 } 4670 4671 /* mftb */ 4672 static void gen_mftb(DisasContext *ctx) 4673 { 4674 gen_op_mfspr(ctx); 4675 } 4676 4677 /* mtcrf mtocrf*/ 4678 static void gen_mtcrf(DisasContext *ctx) 4679 { 4680 uint32_t crm, crn; 4681 4682 crm = CRM(ctx->opcode); 4683 if (likely((ctx->opcode & 0x00100000))) { 4684 if (crm && ((crm & (crm - 1)) == 0)) { 4685 TCGv_i32 temp = tcg_temp_new_i32(); 4686 crn = ctz32(crm); 4687 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4688 tcg_gen_shri_i32(temp, temp, crn * 4); 4689 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4690 } 4691 } else { 4692 TCGv_i32 temp = tcg_temp_new_i32(); 4693 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4694 for (crn = 0 ; crn < 8 ; crn++) { 4695 if (crm & (1 << crn)) { 4696 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4697 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4698 } 4699 } 4700 } 4701 } 4702 4703 /* mtmsr */ 4704 #if defined(TARGET_PPC64) 4705 static void gen_mtmsrd(DisasContext *ctx) 4706 { 4707 if (unlikely(!is_book3s_arch2x(ctx))) { 4708 gen_invalid(ctx); 4709 return; 4710 } 4711 4712 CHK_SV(ctx); 4713 4714 #if !defined(CONFIG_USER_ONLY) 4715 TCGv t0, t1; 4716 target_ulong mask; 4717 4718 t0 = tcg_temp_new(); 4719 t1 = tcg_temp_new(); 4720 4721 translator_io_start(&ctx->base); 4722 4723 if (ctx->opcode & 0x00010000) { 4724 /* L=1 form only updates EE and RI */ 4725 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4726 } else { 4727 /* mtmsrd does not alter HV, S, ME, or LE */ 4728 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4729 (1ULL << MSR_HV)); 4730 /* 4731 * XXX: we need to update nip before the store if we enter 4732 * power saving mode, we will exit the loop directly from 4733 * ppc_store_msr 4734 */ 4735 gen_update_nip(ctx, ctx->base.pc_next); 4736 } 4737 4738 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4739 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4740 tcg_gen_or_tl(t0, t0, t1); 4741 4742 gen_helper_store_msr(cpu_env, t0); 4743 4744 /* Must stop the translation as machine state (may have) changed */ 4745 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4746 #endif /* !defined(CONFIG_USER_ONLY) */ 4747 } 4748 #endif /* defined(TARGET_PPC64) */ 4749 4750 static void gen_mtmsr(DisasContext *ctx) 4751 { 4752 CHK_SV(ctx); 4753 4754 #if !defined(CONFIG_USER_ONLY) 4755 TCGv t0, t1; 4756 target_ulong mask = 0xFFFFFFFF; 4757 4758 t0 = tcg_temp_new(); 4759 t1 = tcg_temp_new(); 4760 4761 translator_io_start(&ctx->base); 4762 if (ctx->opcode & 0x00010000) { 4763 /* L=1 form only updates EE and RI */ 4764 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4765 } else { 4766 /* mtmsr does not alter S, ME, or LE */ 4767 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4768 4769 /* 4770 * XXX: we need to update nip before the store if we enter 4771 * power saving mode, we will exit the loop directly from 4772 * ppc_store_msr 4773 */ 4774 gen_update_nip(ctx, ctx->base.pc_next); 4775 } 4776 4777 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4778 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4779 tcg_gen_or_tl(t0, t0, t1); 4780 4781 gen_helper_store_msr(cpu_env, t0); 4782 4783 /* Must stop the translation as machine state (may have) changed */ 4784 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4785 #endif 4786 } 4787 4788 /* mtspr */ 4789 static void gen_mtspr(DisasContext *ctx) 4790 { 4791 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4792 uint32_t sprn = SPR(ctx->opcode); 4793 4794 #if defined(CONFIG_USER_ONLY) 4795 write_cb = ctx->spr_cb[sprn].uea_write; 4796 #else 4797 if (ctx->pr) { 4798 write_cb = ctx->spr_cb[sprn].uea_write; 4799 } else if (ctx->hv) { 4800 write_cb = ctx->spr_cb[sprn].hea_write; 4801 } else { 4802 write_cb = ctx->spr_cb[sprn].oea_write; 4803 } 4804 #endif 4805 if (likely(write_cb != NULL)) { 4806 if (likely(write_cb != SPR_NOACCESS)) { 4807 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4808 } else { 4809 /* Privilege exception */ 4810 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4811 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4812 ctx->cia); 4813 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4814 } 4815 } else { 4816 /* ISA 2.07 defines these as no-ops */ 4817 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4818 (sprn >= 808 && sprn <= 811)) { 4819 /* This is a nop */ 4820 return; 4821 } 4822 4823 /* Not defined */ 4824 qemu_log_mask(LOG_GUEST_ERROR, 4825 "Trying to write invalid spr %d (0x%03x) at " 4826 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4827 4828 4829 /* 4830 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4831 * generate a priv, a hv emu or a no-op 4832 */ 4833 if (sprn & 0x10) { 4834 if (ctx->pr) { 4835 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4836 } 4837 } else { 4838 if (ctx->pr || sprn == 0) { 4839 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4840 } 4841 } 4842 } 4843 } 4844 4845 #if defined(TARGET_PPC64) 4846 /* setb */ 4847 static void gen_setb(DisasContext *ctx) 4848 { 4849 TCGv_i32 t0 = tcg_temp_new_i32(); 4850 TCGv_i32 t8 = tcg_constant_i32(8); 4851 TCGv_i32 tm1 = tcg_constant_i32(-1); 4852 int crf = crfS(ctx->opcode); 4853 4854 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4855 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4856 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4857 } 4858 #endif 4859 4860 /*** Cache management ***/ 4861 4862 /* dcbf */ 4863 static void gen_dcbf(DisasContext *ctx) 4864 { 4865 /* XXX: specification says this is treated as a load by the MMU */ 4866 TCGv t0; 4867 gen_set_access_type(ctx, ACCESS_CACHE); 4868 t0 = tcg_temp_new(); 4869 gen_addr_reg_index(ctx, t0); 4870 gen_qemu_ld8u(ctx, t0, t0); 4871 } 4872 4873 /* dcbfep (external PID dcbf) */ 4874 static void gen_dcbfep(DisasContext *ctx) 4875 { 4876 /* XXX: specification says this is treated as a load by the MMU */ 4877 TCGv t0; 4878 CHK_SV(ctx); 4879 gen_set_access_type(ctx, ACCESS_CACHE); 4880 t0 = tcg_temp_new(); 4881 gen_addr_reg_index(ctx, t0); 4882 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4883 } 4884 4885 /* dcbi (Supervisor only) */ 4886 static void gen_dcbi(DisasContext *ctx) 4887 { 4888 #if defined(CONFIG_USER_ONLY) 4889 GEN_PRIV(ctx); 4890 #else 4891 TCGv EA, val; 4892 4893 CHK_SV(ctx); 4894 EA = tcg_temp_new(); 4895 gen_set_access_type(ctx, ACCESS_CACHE); 4896 gen_addr_reg_index(ctx, EA); 4897 val = tcg_temp_new(); 4898 /* XXX: specification says this should be treated as a store by the MMU */ 4899 gen_qemu_ld8u(ctx, val, EA); 4900 gen_qemu_st8(ctx, val, EA); 4901 #endif /* defined(CONFIG_USER_ONLY) */ 4902 } 4903 4904 /* dcdst */ 4905 static void gen_dcbst(DisasContext *ctx) 4906 { 4907 /* XXX: specification say this is treated as a load by the MMU */ 4908 TCGv t0; 4909 gen_set_access_type(ctx, ACCESS_CACHE); 4910 t0 = tcg_temp_new(); 4911 gen_addr_reg_index(ctx, t0); 4912 gen_qemu_ld8u(ctx, t0, t0); 4913 } 4914 4915 /* dcbstep (dcbstep External PID version) */ 4916 static void gen_dcbstep(DisasContext *ctx) 4917 { 4918 /* XXX: specification say this is treated as a load by the MMU */ 4919 TCGv t0; 4920 gen_set_access_type(ctx, ACCESS_CACHE); 4921 t0 = tcg_temp_new(); 4922 gen_addr_reg_index(ctx, t0); 4923 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4924 } 4925 4926 /* dcbt */ 4927 static void gen_dcbt(DisasContext *ctx) 4928 { 4929 /* 4930 * interpreted as no-op 4931 * XXX: specification say this is treated as a load by the MMU but 4932 * does not generate any exception 4933 */ 4934 } 4935 4936 /* dcbtep */ 4937 static void gen_dcbtep(DisasContext *ctx) 4938 { 4939 /* 4940 * interpreted as no-op 4941 * XXX: specification say this is treated as a load by the MMU but 4942 * does not generate any exception 4943 */ 4944 } 4945 4946 /* dcbtst */ 4947 static void gen_dcbtst(DisasContext *ctx) 4948 { 4949 /* 4950 * interpreted as no-op 4951 * XXX: specification say this is treated as a load by the MMU but 4952 * does not generate any exception 4953 */ 4954 } 4955 4956 /* dcbtstep */ 4957 static void gen_dcbtstep(DisasContext *ctx) 4958 { 4959 /* 4960 * interpreted as no-op 4961 * XXX: specification say this is treated as a load by the MMU but 4962 * does not generate any exception 4963 */ 4964 } 4965 4966 /* dcbtls */ 4967 static void gen_dcbtls(DisasContext *ctx) 4968 { 4969 /* Always fails locking the cache */ 4970 TCGv t0 = tcg_temp_new(); 4971 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4972 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4973 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4974 } 4975 4976 /* dcblc */ 4977 static void gen_dcblc(DisasContext *ctx) 4978 { 4979 /* 4980 * interpreted as no-op 4981 */ 4982 } 4983 4984 /* dcbz */ 4985 static void gen_dcbz(DisasContext *ctx) 4986 { 4987 TCGv tcgv_addr; 4988 TCGv_i32 tcgv_op; 4989 4990 gen_set_access_type(ctx, ACCESS_CACHE); 4991 tcgv_addr = tcg_temp_new(); 4992 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 4993 gen_addr_reg_index(ctx, tcgv_addr); 4994 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4995 } 4996 4997 /* dcbzep */ 4998 static void gen_dcbzep(DisasContext *ctx) 4999 { 5000 TCGv tcgv_addr; 5001 TCGv_i32 tcgv_op; 5002 5003 gen_set_access_type(ctx, ACCESS_CACHE); 5004 tcgv_addr = tcg_temp_new(); 5005 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5006 gen_addr_reg_index(ctx, tcgv_addr); 5007 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5008 } 5009 5010 /* dst / dstt */ 5011 static void gen_dst(DisasContext *ctx) 5012 { 5013 if (rA(ctx->opcode) == 0) { 5014 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5015 } else { 5016 /* interpreted as no-op */ 5017 } 5018 } 5019 5020 /* dstst /dststt */ 5021 static void gen_dstst(DisasContext *ctx) 5022 { 5023 if (rA(ctx->opcode) == 0) { 5024 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5025 } else { 5026 /* interpreted as no-op */ 5027 } 5028 5029 } 5030 5031 /* dss / dssall */ 5032 static void gen_dss(DisasContext *ctx) 5033 { 5034 /* interpreted as no-op */ 5035 } 5036 5037 /* icbi */ 5038 static void gen_icbi(DisasContext *ctx) 5039 { 5040 TCGv t0; 5041 gen_set_access_type(ctx, ACCESS_CACHE); 5042 t0 = tcg_temp_new(); 5043 gen_addr_reg_index(ctx, t0); 5044 gen_helper_icbi(cpu_env, t0); 5045 } 5046 5047 /* icbiep */ 5048 static void gen_icbiep(DisasContext *ctx) 5049 { 5050 TCGv t0; 5051 gen_set_access_type(ctx, ACCESS_CACHE); 5052 t0 = tcg_temp_new(); 5053 gen_addr_reg_index(ctx, t0); 5054 gen_helper_icbiep(cpu_env, t0); 5055 } 5056 5057 /* Optional: */ 5058 /* dcba */ 5059 static void gen_dcba(DisasContext *ctx) 5060 { 5061 /* 5062 * interpreted as no-op 5063 * XXX: specification say this is treated as a store by the MMU 5064 * but does not generate any exception 5065 */ 5066 } 5067 5068 /*** Segment register manipulation ***/ 5069 /* Supervisor only: */ 5070 5071 /* mfsr */ 5072 static void gen_mfsr(DisasContext *ctx) 5073 { 5074 #if defined(CONFIG_USER_ONLY) 5075 GEN_PRIV(ctx); 5076 #else 5077 TCGv t0; 5078 5079 CHK_SV(ctx); 5080 t0 = tcg_constant_tl(SR(ctx->opcode)); 5081 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5082 #endif /* defined(CONFIG_USER_ONLY) */ 5083 } 5084 5085 /* mfsrin */ 5086 static void gen_mfsrin(DisasContext *ctx) 5087 { 5088 #if defined(CONFIG_USER_ONLY) 5089 GEN_PRIV(ctx); 5090 #else 5091 TCGv t0; 5092 5093 CHK_SV(ctx); 5094 t0 = tcg_temp_new(); 5095 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5096 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5097 #endif /* defined(CONFIG_USER_ONLY) */ 5098 } 5099 5100 /* mtsr */ 5101 static void gen_mtsr(DisasContext *ctx) 5102 { 5103 #if defined(CONFIG_USER_ONLY) 5104 GEN_PRIV(ctx); 5105 #else 5106 TCGv t0; 5107 5108 CHK_SV(ctx); 5109 t0 = tcg_constant_tl(SR(ctx->opcode)); 5110 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5111 #endif /* defined(CONFIG_USER_ONLY) */ 5112 } 5113 5114 /* mtsrin */ 5115 static void gen_mtsrin(DisasContext *ctx) 5116 { 5117 #if defined(CONFIG_USER_ONLY) 5118 GEN_PRIV(ctx); 5119 #else 5120 TCGv t0; 5121 CHK_SV(ctx); 5122 5123 t0 = tcg_temp_new(); 5124 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5125 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5126 #endif /* defined(CONFIG_USER_ONLY) */ 5127 } 5128 5129 #if defined(TARGET_PPC64) 5130 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5131 5132 /* mfsr */ 5133 static void gen_mfsr_64b(DisasContext *ctx) 5134 { 5135 #if defined(CONFIG_USER_ONLY) 5136 GEN_PRIV(ctx); 5137 #else 5138 TCGv t0; 5139 5140 CHK_SV(ctx); 5141 t0 = tcg_constant_tl(SR(ctx->opcode)); 5142 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5143 #endif /* defined(CONFIG_USER_ONLY) */ 5144 } 5145 5146 /* mfsrin */ 5147 static void gen_mfsrin_64b(DisasContext *ctx) 5148 { 5149 #if defined(CONFIG_USER_ONLY) 5150 GEN_PRIV(ctx); 5151 #else 5152 TCGv t0; 5153 5154 CHK_SV(ctx); 5155 t0 = tcg_temp_new(); 5156 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5157 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5158 #endif /* defined(CONFIG_USER_ONLY) */ 5159 } 5160 5161 /* mtsr */ 5162 static void gen_mtsr_64b(DisasContext *ctx) 5163 { 5164 #if defined(CONFIG_USER_ONLY) 5165 GEN_PRIV(ctx); 5166 #else 5167 TCGv t0; 5168 5169 CHK_SV(ctx); 5170 t0 = tcg_constant_tl(SR(ctx->opcode)); 5171 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5172 #endif /* defined(CONFIG_USER_ONLY) */ 5173 } 5174 5175 /* mtsrin */ 5176 static void gen_mtsrin_64b(DisasContext *ctx) 5177 { 5178 #if defined(CONFIG_USER_ONLY) 5179 GEN_PRIV(ctx); 5180 #else 5181 TCGv t0; 5182 5183 CHK_SV(ctx); 5184 t0 = tcg_temp_new(); 5185 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5186 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5187 #endif /* defined(CONFIG_USER_ONLY) */ 5188 } 5189 5190 #endif /* defined(TARGET_PPC64) */ 5191 5192 /*** Lookaside buffer management ***/ 5193 /* Optional & supervisor only: */ 5194 5195 /* tlbia */ 5196 static void gen_tlbia(DisasContext *ctx) 5197 { 5198 #if defined(CONFIG_USER_ONLY) 5199 GEN_PRIV(ctx); 5200 #else 5201 CHK_HV(ctx); 5202 5203 gen_helper_tlbia(cpu_env); 5204 #endif /* defined(CONFIG_USER_ONLY) */ 5205 } 5206 5207 /* tlbsync */ 5208 static void gen_tlbsync(DisasContext *ctx) 5209 { 5210 #if defined(CONFIG_USER_ONLY) 5211 GEN_PRIV(ctx); 5212 #else 5213 5214 if (ctx->gtse) { 5215 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5216 } else { 5217 CHK_HV(ctx); /* Else hypervisor privileged */ 5218 } 5219 5220 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5221 if (ctx->insns_flags & PPC_BOOKE) { 5222 gen_check_tlb_flush(ctx, true); 5223 } 5224 #endif /* defined(CONFIG_USER_ONLY) */ 5225 } 5226 5227 /*** External control ***/ 5228 /* Optional: */ 5229 5230 /* eciwx */ 5231 static void gen_eciwx(DisasContext *ctx) 5232 { 5233 TCGv t0; 5234 /* Should check EAR[E] ! */ 5235 gen_set_access_type(ctx, ACCESS_EXT); 5236 t0 = tcg_temp_new(); 5237 gen_addr_reg_index(ctx, t0); 5238 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5239 DEF_MEMOP(MO_UL | MO_ALIGN)); 5240 } 5241 5242 /* ecowx */ 5243 static void gen_ecowx(DisasContext *ctx) 5244 { 5245 TCGv t0; 5246 /* Should check EAR[E] ! */ 5247 gen_set_access_type(ctx, ACCESS_EXT); 5248 t0 = tcg_temp_new(); 5249 gen_addr_reg_index(ctx, t0); 5250 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5251 DEF_MEMOP(MO_UL | MO_ALIGN)); 5252 } 5253 5254 /* 602 - 603 - G2 TLB management */ 5255 5256 /* tlbld */ 5257 static void gen_tlbld_6xx(DisasContext *ctx) 5258 { 5259 #if defined(CONFIG_USER_ONLY) 5260 GEN_PRIV(ctx); 5261 #else 5262 CHK_SV(ctx); 5263 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5264 #endif /* defined(CONFIG_USER_ONLY) */ 5265 } 5266 5267 /* tlbli */ 5268 static void gen_tlbli_6xx(DisasContext *ctx) 5269 { 5270 #if defined(CONFIG_USER_ONLY) 5271 GEN_PRIV(ctx); 5272 #else 5273 CHK_SV(ctx); 5274 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5275 #endif /* defined(CONFIG_USER_ONLY) */ 5276 } 5277 5278 /* BookE specific instructions */ 5279 5280 /* XXX: not implemented on 440 ? */ 5281 static void gen_mfapidi(DisasContext *ctx) 5282 { 5283 /* XXX: TODO */ 5284 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5285 } 5286 5287 /* XXX: not implemented on 440 ? */ 5288 static void gen_tlbiva(DisasContext *ctx) 5289 { 5290 #if defined(CONFIG_USER_ONLY) 5291 GEN_PRIV(ctx); 5292 #else 5293 TCGv t0; 5294 5295 CHK_SV(ctx); 5296 t0 = tcg_temp_new(); 5297 gen_addr_reg_index(ctx, t0); 5298 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5299 #endif /* defined(CONFIG_USER_ONLY) */ 5300 } 5301 5302 /* All 405 MAC instructions are translated here */ 5303 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5304 int ra, int rb, int rt, int Rc) 5305 { 5306 TCGv t0, t1; 5307 5308 t0 = tcg_temp_new(); 5309 t1 = tcg_temp_new(); 5310 5311 switch (opc3 & 0x0D) { 5312 case 0x05: 5313 /* macchw - macchw. - macchwo - macchwo. */ 5314 /* macchws - macchws. - macchwso - macchwso. */ 5315 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5316 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5317 /* mulchw - mulchw. */ 5318 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5319 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5320 tcg_gen_ext16s_tl(t1, t1); 5321 break; 5322 case 0x04: 5323 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5324 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5325 /* mulchwu - mulchwu. */ 5326 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5327 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5328 tcg_gen_ext16u_tl(t1, t1); 5329 break; 5330 case 0x01: 5331 /* machhw - machhw. - machhwo - machhwo. */ 5332 /* machhws - machhws. - machhwso - machhwso. */ 5333 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5334 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5335 /* mulhhw - mulhhw. */ 5336 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5337 tcg_gen_ext16s_tl(t0, t0); 5338 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5339 tcg_gen_ext16s_tl(t1, t1); 5340 break; 5341 case 0x00: 5342 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5343 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5344 /* mulhhwu - mulhhwu. */ 5345 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5346 tcg_gen_ext16u_tl(t0, t0); 5347 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5348 tcg_gen_ext16u_tl(t1, t1); 5349 break; 5350 case 0x0D: 5351 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5352 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5353 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5354 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5355 /* mullhw - mullhw. */ 5356 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5357 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5358 break; 5359 case 0x0C: 5360 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5361 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5362 /* mullhwu - mullhwu. */ 5363 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5364 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5365 break; 5366 } 5367 if (opc2 & 0x04) { 5368 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5369 tcg_gen_mul_tl(t1, t0, t1); 5370 if (opc2 & 0x02) { 5371 /* nmultiply-and-accumulate (0x0E) */ 5372 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5373 } else { 5374 /* multiply-and-accumulate (0x0C) */ 5375 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5376 } 5377 5378 if (opc3 & 0x12) { 5379 /* Check overflow and/or saturate */ 5380 TCGLabel *l1 = gen_new_label(); 5381 5382 if (opc3 & 0x10) { 5383 /* Start with XER OV disabled, the most likely case */ 5384 tcg_gen_movi_tl(cpu_ov, 0); 5385 } 5386 if (opc3 & 0x01) { 5387 /* Signed */ 5388 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5389 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5390 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5391 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5392 if (opc3 & 0x02) { 5393 /* Saturate */ 5394 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5395 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5396 } 5397 } else { 5398 /* Unsigned */ 5399 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5400 if (opc3 & 0x02) { 5401 /* Saturate */ 5402 tcg_gen_movi_tl(t0, UINT32_MAX); 5403 } 5404 } 5405 if (opc3 & 0x10) { 5406 /* Check overflow */ 5407 tcg_gen_movi_tl(cpu_ov, 1); 5408 tcg_gen_movi_tl(cpu_so, 1); 5409 } 5410 gen_set_label(l1); 5411 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5412 } 5413 } else { 5414 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5415 } 5416 if (unlikely(Rc) != 0) { 5417 /* Update Rc0 */ 5418 gen_set_Rc0(ctx, cpu_gpr[rt]); 5419 } 5420 } 5421 5422 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5423 static void glue(gen_, name)(DisasContext *ctx) \ 5424 { \ 5425 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5426 rD(ctx->opcode), Rc(ctx->opcode)); \ 5427 } 5428 5429 /* macchw - macchw. */ 5430 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5431 /* macchwo - macchwo. */ 5432 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5433 /* macchws - macchws. */ 5434 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5435 /* macchwso - macchwso. */ 5436 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5437 /* macchwsu - macchwsu. */ 5438 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5439 /* macchwsuo - macchwsuo. */ 5440 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5441 /* macchwu - macchwu. */ 5442 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5443 /* macchwuo - macchwuo. */ 5444 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5445 /* machhw - machhw. */ 5446 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5447 /* machhwo - machhwo. */ 5448 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5449 /* machhws - machhws. */ 5450 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5451 /* machhwso - machhwso. */ 5452 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5453 /* machhwsu - machhwsu. */ 5454 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5455 /* machhwsuo - machhwsuo. */ 5456 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5457 /* machhwu - machhwu. */ 5458 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5459 /* machhwuo - machhwuo. */ 5460 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5461 /* maclhw - maclhw. */ 5462 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5463 /* maclhwo - maclhwo. */ 5464 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5465 /* maclhws - maclhws. */ 5466 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5467 /* maclhwso - maclhwso. */ 5468 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5469 /* maclhwu - maclhwu. */ 5470 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5471 /* maclhwuo - maclhwuo. */ 5472 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5473 /* maclhwsu - maclhwsu. */ 5474 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5475 /* maclhwsuo - maclhwsuo. */ 5476 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5477 /* nmacchw - nmacchw. */ 5478 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5479 /* nmacchwo - nmacchwo. */ 5480 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5481 /* nmacchws - nmacchws. */ 5482 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5483 /* nmacchwso - nmacchwso. */ 5484 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5485 /* nmachhw - nmachhw. */ 5486 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5487 /* nmachhwo - nmachhwo. */ 5488 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5489 /* nmachhws - nmachhws. */ 5490 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5491 /* nmachhwso - nmachhwso. */ 5492 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5493 /* nmaclhw - nmaclhw. */ 5494 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5495 /* nmaclhwo - nmaclhwo. */ 5496 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5497 /* nmaclhws - nmaclhws. */ 5498 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5499 /* nmaclhwso - nmaclhwso. */ 5500 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5501 5502 /* mulchw - mulchw. */ 5503 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5504 /* mulchwu - mulchwu. */ 5505 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5506 /* mulhhw - mulhhw. */ 5507 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5508 /* mulhhwu - mulhhwu. */ 5509 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5510 /* mullhw - mullhw. */ 5511 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5512 /* mullhwu - mullhwu. */ 5513 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5514 5515 /* mfdcr */ 5516 static void gen_mfdcr(DisasContext *ctx) 5517 { 5518 #if defined(CONFIG_USER_ONLY) 5519 GEN_PRIV(ctx); 5520 #else 5521 TCGv dcrn; 5522 5523 CHK_SV(ctx); 5524 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5525 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5526 #endif /* defined(CONFIG_USER_ONLY) */ 5527 } 5528 5529 /* mtdcr */ 5530 static void gen_mtdcr(DisasContext *ctx) 5531 { 5532 #if defined(CONFIG_USER_ONLY) 5533 GEN_PRIV(ctx); 5534 #else 5535 TCGv dcrn; 5536 5537 CHK_SV(ctx); 5538 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5539 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5540 #endif /* defined(CONFIG_USER_ONLY) */ 5541 } 5542 5543 /* mfdcrx */ 5544 /* XXX: not implemented on 440 ? */ 5545 static void gen_mfdcrx(DisasContext *ctx) 5546 { 5547 #if defined(CONFIG_USER_ONLY) 5548 GEN_PRIV(ctx); 5549 #else 5550 CHK_SV(ctx); 5551 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5552 cpu_gpr[rA(ctx->opcode)]); 5553 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5554 #endif /* defined(CONFIG_USER_ONLY) */ 5555 } 5556 5557 /* mtdcrx */ 5558 /* XXX: not implemented on 440 ? */ 5559 static void gen_mtdcrx(DisasContext *ctx) 5560 { 5561 #if defined(CONFIG_USER_ONLY) 5562 GEN_PRIV(ctx); 5563 #else 5564 CHK_SV(ctx); 5565 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5566 cpu_gpr[rS(ctx->opcode)]); 5567 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5568 #endif /* defined(CONFIG_USER_ONLY) */ 5569 } 5570 5571 /* dccci */ 5572 static void gen_dccci(DisasContext *ctx) 5573 { 5574 CHK_SV(ctx); 5575 /* interpreted as no-op */ 5576 } 5577 5578 /* dcread */ 5579 static void gen_dcread(DisasContext *ctx) 5580 { 5581 #if defined(CONFIG_USER_ONLY) 5582 GEN_PRIV(ctx); 5583 #else 5584 TCGv EA, val; 5585 5586 CHK_SV(ctx); 5587 gen_set_access_type(ctx, ACCESS_CACHE); 5588 EA = tcg_temp_new(); 5589 gen_addr_reg_index(ctx, EA); 5590 val = tcg_temp_new(); 5591 gen_qemu_ld32u(ctx, val, EA); 5592 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5593 #endif /* defined(CONFIG_USER_ONLY) */ 5594 } 5595 5596 /* icbt */ 5597 static void gen_icbt_40x(DisasContext *ctx) 5598 { 5599 /* 5600 * interpreted as no-op 5601 * XXX: specification say this is treated as a load by the MMU but 5602 * does not generate any exception 5603 */ 5604 } 5605 5606 /* iccci */ 5607 static void gen_iccci(DisasContext *ctx) 5608 { 5609 CHK_SV(ctx); 5610 /* interpreted as no-op */ 5611 } 5612 5613 /* icread */ 5614 static void gen_icread(DisasContext *ctx) 5615 { 5616 CHK_SV(ctx); 5617 /* interpreted as no-op */ 5618 } 5619 5620 /* rfci (supervisor only) */ 5621 static void gen_rfci_40x(DisasContext *ctx) 5622 { 5623 #if defined(CONFIG_USER_ONLY) 5624 GEN_PRIV(ctx); 5625 #else 5626 CHK_SV(ctx); 5627 /* Restore CPU state */ 5628 gen_helper_40x_rfci(cpu_env); 5629 ctx->base.is_jmp = DISAS_EXIT; 5630 #endif /* defined(CONFIG_USER_ONLY) */ 5631 } 5632 5633 static void gen_rfci(DisasContext *ctx) 5634 { 5635 #if defined(CONFIG_USER_ONLY) 5636 GEN_PRIV(ctx); 5637 #else 5638 CHK_SV(ctx); 5639 /* Restore CPU state */ 5640 gen_helper_rfci(cpu_env); 5641 ctx->base.is_jmp = DISAS_EXIT; 5642 #endif /* defined(CONFIG_USER_ONLY) */ 5643 } 5644 5645 /* BookE specific */ 5646 5647 /* XXX: not implemented on 440 ? */ 5648 static void gen_rfdi(DisasContext *ctx) 5649 { 5650 #if defined(CONFIG_USER_ONLY) 5651 GEN_PRIV(ctx); 5652 #else 5653 CHK_SV(ctx); 5654 /* Restore CPU state */ 5655 gen_helper_rfdi(cpu_env); 5656 ctx->base.is_jmp = DISAS_EXIT; 5657 #endif /* defined(CONFIG_USER_ONLY) */ 5658 } 5659 5660 /* XXX: not implemented on 440 ? */ 5661 static void gen_rfmci(DisasContext *ctx) 5662 { 5663 #if defined(CONFIG_USER_ONLY) 5664 GEN_PRIV(ctx); 5665 #else 5666 CHK_SV(ctx); 5667 /* Restore CPU state */ 5668 gen_helper_rfmci(cpu_env); 5669 ctx->base.is_jmp = DISAS_EXIT; 5670 #endif /* defined(CONFIG_USER_ONLY) */ 5671 } 5672 5673 /* TLB management - PowerPC 405 implementation */ 5674 5675 /* tlbre */ 5676 static void gen_tlbre_40x(DisasContext *ctx) 5677 { 5678 #if defined(CONFIG_USER_ONLY) 5679 GEN_PRIV(ctx); 5680 #else 5681 CHK_SV(ctx); 5682 switch (rB(ctx->opcode)) { 5683 case 0: 5684 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5685 cpu_gpr[rA(ctx->opcode)]); 5686 break; 5687 case 1: 5688 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5689 cpu_gpr[rA(ctx->opcode)]); 5690 break; 5691 default: 5692 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5693 break; 5694 } 5695 #endif /* defined(CONFIG_USER_ONLY) */ 5696 } 5697 5698 /* tlbsx - tlbsx. */ 5699 static void gen_tlbsx_40x(DisasContext *ctx) 5700 { 5701 #if defined(CONFIG_USER_ONLY) 5702 GEN_PRIV(ctx); 5703 #else 5704 TCGv t0; 5705 5706 CHK_SV(ctx); 5707 t0 = tcg_temp_new(); 5708 gen_addr_reg_index(ctx, t0); 5709 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5710 if (Rc(ctx->opcode)) { 5711 TCGLabel *l1 = gen_new_label(); 5712 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5713 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5714 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5715 gen_set_label(l1); 5716 } 5717 #endif /* defined(CONFIG_USER_ONLY) */ 5718 } 5719 5720 /* tlbwe */ 5721 static void gen_tlbwe_40x(DisasContext *ctx) 5722 { 5723 #if defined(CONFIG_USER_ONLY) 5724 GEN_PRIV(ctx); 5725 #else 5726 CHK_SV(ctx); 5727 5728 switch (rB(ctx->opcode)) { 5729 case 0: 5730 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5731 cpu_gpr[rS(ctx->opcode)]); 5732 break; 5733 case 1: 5734 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5735 cpu_gpr[rS(ctx->opcode)]); 5736 break; 5737 default: 5738 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5739 break; 5740 } 5741 #endif /* defined(CONFIG_USER_ONLY) */ 5742 } 5743 5744 /* TLB management - PowerPC 440 implementation */ 5745 5746 /* tlbre */ 5747 static void gen_tlbre_440(DisasContext *ctx) 5748 { 5749 #if defined(CONFIG_USER_ONLY) 5750 GEN_PRIV(ctx); 5751 #else 5752 CHK_SV(ctx); 5753 5754 switch (rB(ctx->opcode)) { 5755 case 0: 5756 case 1: 5757 case 2: 5758 { 5759 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5760 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5761 t0, cpu_gpr[rA(ctx->opcode)]); 5762 } 5763 break; 5764 default: 5765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5766 break; 5767 } 5768 #endif /* defined(CONFIG_USER_ONLY) */ 5769 } 5770 5771 /* tlbsx - tlbsx. */ 5772 static void gen_tlbsx_440(DisasContext *ctx) 5773 { 5774 #if defined(CONFIG_USER_ONLY) 5775 GEN_PRIV(ctx); 5776 #else 5777 TCGv t0; 5778 5779 CHK_SV(ctx); 5780 t0 = tcg_temp_new(); 5781 gen_addr_reg_index(ctx, t0); 5782 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5783 if (Rc(ctx->opcode)) { 5784 TCGLabel *l1 = gen_new_label(); 5785 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5786 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5787 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5788 gen_set_label(l1); 5789 } 5790 #endif /* defined(CONFIG_USER_ONLY) */ 5791 } 5792 5793 /* tlbwe */ 5794 static void gen_tlbwe_440(DisasContext *ctx) 5795 { 5796 #if defined(CONFIG_USER_ONLY) 5797 GEN_PRIV(ctx); 5798 #else 5799 CHK_SV(ctx); 5800 switch (rB(ctx->opcode)) { 5801 case 0: 5802 case 1: 5803 case 2: 5804 { 5805 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5806 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5807 cpu_gpr[rS(ctx->opcode)]); 5808 } 5809 break; 5810 default: 5811 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5812 break; 5813 } 5814 #endif /* defined(CONFIG_USER_ONLY) */ 5815 } 5816 5817 /* TLB management - PowerPC BookE 2.06 implementation */ 5818 5819 /* tlbre */ 5820 static void gen_tlbre_booke206(DisasContext *ctx) 5821 { 5822 #if defined(CONFIG_USER_ONLY) 5823 GEN_PRIV(ctx); 5824 #else 5825 CHK_SV(ctx); 5826 gen_helper_booke206_tlbre(cpu_env); 5827 #endif /* defined(CONFIG_USER_ONLY) */ 5828 } 5829 5830 /* tlbsx - tlbsx. */ 5831 static void gen_tlbsx_booke206(DisasContext *ctx) 5832 { 5833 #if defined(CONFIG_USER_ONLY) 5834 GEN_PRIV(ctx); 5835 #else 5836 TCGv t0; 5837 5838 CHK_SV(ctx); 5839 if (rA(ctx->opcode)) { 5840 t0 = tcg_temp_new(); 5841 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5842 } else { 5843 t0 = cpu_gpr[rB(ctx->opcode)]; 5844 } 5845 gen_helper_booke206_tlbsx(cpu_env, t0); 5846 #endif /* defined(CONFIG_USER_ONLY) */ 5847 } 5848 5849 /* tlbwe */ 5850 static void gen_tlbwe_booke206(DisasContext *ctx) 5851 { 5852 #if defined(CONFIG_USER_ONLY) 5853 GEN_PRIV(ctx); 5854 #else 5855 CHK_SV(ctx); 5856 gen_helper_booke206_tlbwe(cpu_env); 5857 #endif /* defined(CONFIG_USER_ONLY) */ 5858 } 5859 5860 static void gen_tlbivax_booke206(DisasContext *ctx) 5861 { 5862 #if defined(CONFIG_USER_ONLY) 5863 GEN_PRIV(ctx); 5864 #else 5865 TCGv t0; 5866 5867 CHK_SV(ctx); 5868 t0 = tcg_temp_new(); 5869 gen_addr_reg_index(ctx, t0); 5870 gen_helper_booke206_tlbivax(cpu_env, t0); 5871 #endif /* defined(CONFIG_USER_ONLY) */ 5872 } 5873 5874 static void gen_tlbilx_booke206(DisasContext *ctx) 5875 { 5876 #if defined(CONFIG_USER_ONLY) 5877 GEN_PRIV(ctx); 5878 #else 5879 TCGv t0; 5880 5881 CHK_SV(ctx); 5882 t0 = tcg_temp_new(); 5883 gen_addr_reg_index(ctx, t0); 5884 5885 switch ((ctx->opcode >> 21) & 0x3) { 5886 case 0: 5887 gen_helper_booke206_tlbilx0(cpu_env, t0); 5888 break; 5889 case 1: 5890 gen_helper_booke206_tlbilx1(cpu_env, t0); 5891 break; 5892 case 3: 5893 gen_helper_booke206_tlbilx3(cpu_env, t0); 5894 break; 5895 default: 5896 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5897 break; 5898 } 5899 #endif /* defined(CONFIG_USER_ONLY) */ 5900 } 5901 5902 /* wrtee */ 5903 static void gen_wrtee(DisasContext *ctx) 5904 { 5905 #if defined(CONFIG_USER_ONLY) 5906 GEN_PRIV(ctx); 5907 #else 5908 TCGv t0; 5909 5910 CHK_SV(ctx); 5911 t0 = tcg_temp_new(); 5912 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5913 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5914 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5915 gen_ppc_maybe_interrupt(ctx); 5916 /* 5917 * Stop translation to have a chance to raise an exception if we 5918 * just set msr_ee to 1 5919 */ 5920 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5921 #endif /* defined(CONFIG_USER_ONLY) */ 5922 } 5923 5924 /* wrteei */ 5925 static void gen_wrteei(DisasContext *ctx) 5926 { 5927 #if defined(CONFIG_USER_ONLY) 5928 GEN_PRIV(ctx); 5929 #else 5930 CHK_SV(ctx); 5931 if (ctx->opcode & 0x00008000) { 5932 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5933 gen_ppc_maybe_interrupt(ctx); 5934 /* Stop translation to have a chance to raise an exception */ 5935 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5936 } else { 5937 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5938 } 5939 #endif /* defined(CONFIG_USER_ONLY) */ 5940 } 5941 5942 /* PowerPC 440 specific instructions */ 5943 5944 /* dlmzb */ 5945 static void gen_dlmzb(DisasContext *ctx) 5946 { 5947 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5948 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 5949 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5950 } 5951 5952 /* mbar replaces eieio on 440 */ 5953 static void gen_mbar(DisasContext *ctx) 5954 { 5955 /* interpreted as no-op */ 5956 } 5957 5958 /* msync replaces sync on 440 */ 5959 static void gen_msync_4xx(DisasContext *ctx) 5960 { 5961 /* Only e500 seems to treat reserved bits as invalid */ 5962 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 5963 (ctx->opcode & 0x03FFF801)) { 5964 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5965 } 5966 /* otherwise interpreted as no-op */ 5967 } 5968 5969 /* icbt */ 5970 static void gen_icbt_440(DisasContext *ctx) 5971 { 5972 /* 5973 * interpreted as no-op 5974 * XXX: specification say this is treated as a load by the MMU but 5975 * does not generate any exception 5976 */ 5977 } 5978 5979 #if defined(TARGET_PPC64) 5980 static void gen_maddld(DisasContext *ctx) 5981 { 5982 TCGv_i64 t1 = tcg_temp_new_i64(); 5983 5984 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5985 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 5986 } 5987 5988 /* maddhd maddhdu */ 5989 static void gen_maddhd_maddhdu(DisasContext *ctx) 5990 { 5991 TCGv_i64 lo = tcg_temp_new_i64(); 5992 TCGv_i64 hi = tcg_temp_new_i64(); 5993 TCGv_i64 t1 = tcg_temp_new_i64(); 5994 5995 if (Rc(ctx->opcode)) { 5996 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 5997 cpu_gpr[rB(ctx->opcode)]); 5998 tcg_gen_movi_i64(t1, 0); 5999 } else { 6000 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6001 cpu_gpr[rB(ctx->opcode)]); 6002 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6003 } 6004 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6005 cpu_gpr[rC(ctx->opcode)], t1); 6006 } 6007 #endif /* defined(TARGET_PPC64) */ 6008 6009 static void gen_tbegin(DisasContext *ctx) 6010 { 6011 if (unlikely(!ctx->tm_enabled)) { 6012 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6013 return; 6014 } 6015 gen_helper_tbegin(cpu_env); 6016 } 6017 6018 #define GEN_TM_NOOP(name) \ 6019 static inline void gen_##name(DisasContext *ctx) \ 6020 { \ 6021 if (unlikely(!ctx->tm_enabled)) { \ 6022 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6023 return; \ 6024 } \ 6025 /* \ 6026 * Because tbegin always fails in QEMU, these user \ 6027 * space instructions all have a simple implementation: \ 6028 * \ 6029 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6030 * = 0b0 || 0b00 || 0b0 \ 6031 */ \ 6032 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6033 } 6034 6035 GEN_TM_NOOP(tend); 6036 GEN_TM_NOOP(tabort); 6037 GEN_TM_NOOP(tabortwc); 6038 GEN_TM_NOOP(tabortwci); 6039 GEN_TM_NOOP(tabortdc); 6040 GEN_TM_NOOP(tabortdci); 6041 GEN_TM_NOOP(tsr); 6042 6043 static inline void gen_cp_abort(DisasContext *ctx) 6044 { 6045 /* Do Nothing */ 6046 } 6047 6048 #define GEN_CP_PASTE_NOOP(name) \ 6049 static inline void gen_##name(DisasContext *ctx) \ 6050 { \ 6051 /* \ 6052 * Generate invalid exception until we have an \ 6053 * implementation of the copy paste facility \ 6054 */ \ 6055 gen_invalid(ctx); \ 6056 } 6057 6058 GEN_CP_PASTE_NOOP(copy) 6059 GEN_CP_PASTE_NOOP(paste) 6060 6061 static void gen_tcheck(DisasContext *ctx) 6062 { 6063 if (unlikely(!ctx->tm_enabled)) { 6064 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6065 return; 6066 } 6067 /* 6068 * Because tbegin always fails, the tcheck implementation is 6069 * simple: 6070 * 6071 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6072 * = 0b1 || 0b00 || 0b0 6073 */ 6074 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6075 } 6076 6077 #if defined(CONFIG_USER_ONLY) 6078 #define GEN_TM_PRIV_NOOP(name) \ 6079 static inline void gen_##name(DisasContext *ctx) \ 6080 { \ 6081 gen_priv_opc(ctx); \ 6082 } 6083 6084 #else 6085 6086 #define GEN_TM_PRIV_NOOP(name) \ 6087 static inline void gen_##name(DisasContext *ctx) \ 6088 { \ 6089 CHK_SV(ctx); \ 6090 if (unlikely(!ctx->tm_enabled)) { \ 6091 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6092 return; \ 6093 } \ 6094 /* \ 6095 * Because tbegin always fails, the implementation is \ 6096 * simple: \ 6097 * \ 6098 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6099 * = 0b0 || 0b00 | 0b0 \ 6100 */ \ 6101 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6102 } 6103 6104 #endif 6105 6106 GEN_TM_PRIV_NOOP(treclaim); 6107 GEN_TM_PRIV_NOOP(trechkpt); 6108 6109 static inline void get_fpr(TCGv_i64 dst, int regno) 6110 { 6111 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6112 } 6113 6114 static inline void set_fpr(int regno, TCGv_i64 src) 6115 { 6116 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6117 /* 6118 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6119 * corresponding to the target FPR was undefined. However, 6120 * most (if not all) real hardware were setting the result to 0. 6121 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6122 * to be 0. 6123 */ 6124 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6125 } 6126 6127 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6128 { 6129 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6130 } 6131 6132 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6133 { 6134 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6135 } 6136 6137 /* 6138 * Helpers for decodetree used by !function for decoding arguments. 6139 */ 6140 static int times_2(DisasContext *ctx, int x) 6141 { 6142 return x * 2; 6143 } 6144 6145 static int times_4(DisasContext *ctx, int x) 6146 { 6147 return x * 4; 6148 } 6149 6150 static int times_16(DisasContext *ctx, int x) 6151 { 6152 return x * 16; 6153 } 6154 6155 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6156 { 6157 return deposit64(0xfffffffffffffe00, 3, 6, x); 6158 } 6159 6160 /* 6161 * Helpers for trans_* functions to check for specific insns flags. 6162 * Use token pasting to ensure that we use the proper flag with the 6163 * proper variable. 6164 */ 6165 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6166 do { \ 6167 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6168 return false; \ 6169 } \ 6170 } while (0) 6171 6172 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6173 do { \ 6174 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6175 return false; \ 6176 } \ 6177 } while (0) 6178 6179 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6180 #if TARGET_LONG_BITS == 32 6181 # define REQUIRE_64BIT(CTX) return false 6182 #else 6183 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6184 #endif 6185 6186 #define REQUIRE_VECTOR(CTX) \ 6187 do { \ 6188 if (unlikely(!(CTX)->altivec_enabled)) { \ 6189 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6190 return true; \ 6191 } \ 6192 } while (0) 6193 6194 #define REQUIRE_VSX(CTX) \ 6195 do { \ 6196 if (unlikely(!(CTX)->vsx_enabled)) { \ 6197 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6198 return true; \ 6199 } \ 6200 } while (0) 6201 6202 #define REQUIRE_FPU(ctx) \ 6203 do { \ 6204 if (unlikely(!(ctx)->fpu_enabled)) { \ 6205 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6206 return true; \ 6207 } \ 6208 } while (0) 6209 6210 #if !defined(CONFIG_USER_ONLY) 6211 #define REQUIRE_SV(CTX) \ 6212 do { \ 6213 if (unlikely((CTX)->pr)) { \ 6214 gen_priv_opc(CTX); \ 6215 return true; \ 6216 } \ 6217 } while (0) 6218 6219 #define REQUIRE_HV(CTX) \ 6220 do { \ 6221 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6222 gen_priv_opc(CTX); \ 6223 return true; \ 6224 } \ 6225 } while (0) 6226 #else 6227 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6228 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6229 #endif 6230 6231 /* 6232 * Helpers for implementing sets of trans_* functions. 6233 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6234 */ 6235 #define TRANS(NAME, FUNC, ...) \ 6236 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6237 { return FUNC(ctx, a, __VA_ARGS__); } 6238 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6239 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6240 { \ 6241 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6242 return FUNC(ctx, a, __VA_ARGS__); \ 6243 } 6244 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6245 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6246 { \ 6247 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6248 return FUNC(ctx, a, __VA_ARGS__); \ 6249 } 6250 6251 #define TRANS64(NAME, FUNC, ...) \ 6252 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6253 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6254 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6255 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6256 { \ 6257 REQUIRE_64BIT(ctx); \ 6258 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6259 return FUNC(ctx, a, __VA_ARGS__); \ 6260 } 6261 6262 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6263 6264 6265 #include "decode-insn32.c.inc" 6266 #include "decode-insn64.c.inc" 6267 #include "power8-pmu-regs.c.inc" 6268 6269 /* 6270 * Incorporate CIA into the constant when R=1. 6271 * Validate that when R=1, RA=0. 6272 */ 6273 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6274 { 6275 d->rt = a->rt; 6276 d->ra = a->ra; 6277 d->si = a->si; 6278 if (a->r) { 6279 if (unlikely(a->ra != 0)) { 6280 gen_invalid(ctx); 6281 return false; 6282 } 6283 d->si += ctx->cia; 6284 } 6285 return true; 6286 } 6287 6288 #include "translate/fixedpoint-impl.c.inc" 6289 6290 #include "translate/fp-impl.c.inc" 6291 6292 #include "translate/vmx-impl.c.inc" 6293 6294 #include "translate/vsx-impl.c.inc" 6295 6296 #include "translate/dfp-impl.c.inc" 6297 6298 #include "translate/spe-impl.c.inc" 6299 6300 #include "translate/branch-impl.c.inc" 6301 6302 #include "translate/processor-ctrl-impl.c.inc" 6303 6304 #include "translate/storage-ctrl-impl.c.inc" 6305 6306 /* Handles lfdp */ 6307 static void gen_dform39(DisasContext *ctx) 6308 { 6309 if ((ctx->opcode & 0x3) == 0) { 6310 if (ctx->insns_flags2 & PPC2_ISA205) { 6311 return gen_lfdp(ctx); 6312 } 6313 } 6314 return gen_invalid(ctx); 6315 } 6316 6317 /* Handles stfdp */ 6318 static void gen_dform3D(DisasContext *ctx) 6319 { 6320 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6321 /* stfdp */ 6322 if (ctx->insns_flags2 & PPC2_ISA205) { 6323 return gen_stfdp(ctx); 6324 } 6325 } 6326 return gen_invalid(ctx); 6327 } 6328 6329 #if defined(TARGET_PPC64) 6330 /* brd */ 6331 static void gen_brd(DisasContext *ctx) 6332 { 6333 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6334 } 6335 6336 /* brw */ 6337 static void gen_brw(DisasContext *ctx) 6338 { 6339 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6340 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6341 6342 } 6343 6344 /* brh */ 6345 static void gen_brh(DisasContext *ctx) 6346 { 6347 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6348 TCGv_i64 t1 = tcg_temp_new_i64(); 6349 TCGv_i64 t2 = tcg_temp_new_i64(); 6350 6351 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6352 tcg_gen_and_i64(t2, t1, mask); 6353 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6354 tcg_gen_shli_i64(t1, t1, 8); 6355 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6356 } 6357 #endif 6358 6359 static opcode_t opcodes[] = { 6360 #if defined(TARGET_PPC64) 6361 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6362 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6363 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6364 #endif 6365 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6366 #if defined(TARGET_PPC64) 6367 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6368 #endif 6369 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6370 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6371 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6372 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6373 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6374 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6375 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6376 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6377 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6378 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6379 #if defined(TARGET_PPC64) 6380 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6381 #endif 6382 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6383 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6384 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6385 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6386 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6387 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6388 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6389 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6390 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6391 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6392 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6393 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6394 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6395 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6396 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6397 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6398 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6399 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6400 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6401 #if defined(TARGET_PPC64) 6402 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6403 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6404 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6405 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6406 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6407 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6408 #endif 6409 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6410 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6411 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6412 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6413 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6414 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6415 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6416 #if defined(TARGET_PPC64) 6417 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6418 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6419 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6420 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6421 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6422 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6423 PPC_NONE, PPC2_ISA300), 6424 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6425 PPC_NONE, PPC2_ISA300), 6426 #endif 6427 /* handles lfdp, lxsd, lxssp */ 6428 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6429 /* handles stfdp, stxsd, stxssp */ 6430 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6431 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6432 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6433 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6434 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6435 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6436 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6437 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6438 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6439 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6440 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6441 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6442 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6443 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6444 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6445 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6446 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6447 #if defined(TARGET_PPC64) 6448 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6449 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6450 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6451 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6452 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6453 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6454 #endif 6455 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6456 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6457 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6458 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6459 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6460 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6461 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6462 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6463 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6464 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6465 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6466 #if defined(TARGET_PPC64) 6467 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6468 #if !defined(CONFIG_USER_ONLY) 6469 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6470 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6471 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6472 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6473 #endif 6474 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6475 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6476 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6477 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6478 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6479 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6480 #endif 6481 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6482 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6483 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6484 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6485 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6486 #if defined(TARGET_PPC64) 6487 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6488 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6489 #endif 6490 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6491 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6492 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6493 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6494 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6495 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6496 #if defined(TARGET_PPC64) 6497 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6498 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6499 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6500 #endif 6501 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6502 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6503 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6504 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6505 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6506 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6507 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6508 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6509 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6510 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6511 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6512 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6513 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6514 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6515 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6516 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6517 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6518 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6519 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6520 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6521 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6522 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6523 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6524 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6525 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6526 #if defined(TARGET_PPC64) 6527 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6528 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6529 PPC_SEGMENT_64B), 6530 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6531 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6532 PPC_SEGMENT_64B), 6533 #endif 6534 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6535 /* 6536 * XXX Those instructions will need to be handled differently for 6537 * different ISA versions 6538 */ 6539 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6540 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6541 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6542 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6543 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6544 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6545 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6546 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6547 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6548 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6549 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6550 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6551 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6552 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6553 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6554 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6555 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6556 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6557 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6558 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6559 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6560 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6561 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6562 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6563 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6564 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6565 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6566 PPC_NONE, PPC2_BOOKE206), 6567 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6568 PPC_NONE, PPC2_BOOKE206), 6569 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6570 PPC_NONE, PPC2_BOOKE206), 6571 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6572 PPC_NONE, PPC2_BOOKE206), 6573 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6574 PPC_NONE, PPC2_BOOKE206), 6575 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6576 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6577 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6578 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6579 PPC_BOOKE, PPC2_BOOKE206), 6580 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6581 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6582 PPC_BOOKE, PPC2_BOOKE206), 6583 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6584 PPC_440_SPEC), 6585 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6586 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6587 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6588 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6589 #if defined(TARGET_PPC64) 6590 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6591 PPC2_ISA300), 6592 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6593 #endif 6594 6595 #undef GEN_INT_ARITH_ADD 6596 #undef GEN_INT_ARITH_ADD_CONST 6597 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6598 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6599 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6600 add_ca, compute_ca, compute_ov) \ 6601 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6602 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6603 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6604 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6605 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6606 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6607 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6608 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6609 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6610 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6611 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6612 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6613 6614 #undef GEN_INT_ARITH_DIVW 6615 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6616 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6617 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6618 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6619 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6620 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6621 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6622 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6623 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6624 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6625 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6626 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6627 6628 #if defined(TARGET_PPC64) 6629 #undef GEN_INT_ARITH_DIVD 6630 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6631 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6632 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6633 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6634 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6635 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6636 6637 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6638 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6639 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6640 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6641 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6642 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6643 6644 #undef GEN_INT_ARITH_MUL_HELPER 6645 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6646 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6647 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6648 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6649 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6650 #endif 6651 6652 #undef GEN_INT_ARITH_SUBF 6653 #undef GEN_INT_ARITH_SUBF_CONST 6654 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6655 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6656 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6657 add_ca, compute_ca, compute_ov) \ 6658 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6659 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6660 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6661 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6662 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6663 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6664 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6665 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6666 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6667 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6668 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6669 6670 #undef GEN_LOGICAL1 6671 #undef GEN_LOGICAL2 6672 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6673 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6674 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6675 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6676 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6677 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6678 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6679 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6680 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6681 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6682 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6683 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6684 #if defined(TARGET_PPC64) 6685 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6686 #endif 6687 6688 #if defined(TARGET_PPC64) 6689 #undef GEN_PPC64_R2 6690 #undef GEN_PPC64_R4 6691 #define GEN_PPC64_R2(name, opc1, opc2) \ 6692 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6693 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6694 PPC_64B) 6695 #define GEN_PPC64_R4(name, opc1, opc2) \ 6696 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6697 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6698 PPC_64B), \ 6699 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6700 PPC_64B), \ 6701 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6702 PPC_64B) 6703 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6704 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6705 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6706 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6707 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6708 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6709 #endif 6710 6711 #undef GEN_LDX_E 6712 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6713 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6714 6715 #if defined(TARGET_PPC64) 6716 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6717 6718 /* HV/P7 and later only */ 6719 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6720 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6721 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6722 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6723 #endif 6724 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6725 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6726 6727 /* External PID based load */ 6728 #undef GEN_LDEPX 6729 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6730 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6731 0x00000001, PPC_NONE, PPC2_BOOKE206), 6732 6733 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6734 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6735 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6736 #if defined(TARGET_PPC64) 6737 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6738 #endif 6739 6740 #undef GEN_STX_E 6741 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6742 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6743 6744 #if defined(TARGET_PPC64) 6745 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6746 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6747 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6748 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6749 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6750 #endif 6751 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6752 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6753 6754 #undef GEN_STEPX 6755 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6756 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6757 0x00000001, PPC_NONE, PPC2_BOOKE206), 6758 6759 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6760 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6761 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6762 #if defined(TARGET_PPC64) 6763 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6764 #endif 6765 6766 #undef GEN_CRLOGIC 6767 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6768 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6769 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6770 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6771 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6772 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6773 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6774 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6775 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6776 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6777 6778 #undef GEN_MAC_HANDLER 6779 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6780 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6781 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6782 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6783 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6784 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6785 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6786 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6787 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6788 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6789 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6790 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6791 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6792 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6793 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6794 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6795 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6796 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6797 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6798 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6799 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6800 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6801 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6802 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6803 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6804 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6805 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6806 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6807 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6808 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6809 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6810 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6811 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6812 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6813 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6814 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6815 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6816 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6817 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6818 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6819 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6820 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6821 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6822 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6823 6824 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6825 PPC_NONE, PPC2_TM), 6826 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6827 PPC_NONE, PPC2_TM), 6828 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6829 PPC_NONE, PPC2_TM), 6830 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6831 PPC_NONE, PPC2_TM), 6832 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6833 PPC_NONE, PPC2_TM), 6834 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6835 PPC_NONE, PPC2_TM), 6836 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6837 PPC_NONE, PPC2_TM), 6838 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6839 PPC_NONE, PPC2_TM), 6840 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6841 PPC_NONE, PPC2_TM), 6842 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6843 PPC_NONE, PPC2_TM), 6844 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6845 PPC_NONE, PPC2_TM), 6846 6847 #include "translate/fp-ops.c.inc" 6848 6849 #include "translate/vmx-ops.c.inc" 6850 6851 #include "translate/vsx-ops.c.inc" 6852 6853 #include "translate/spe-ops.c.inc" 6854 }; 6855 6856 /*****************************************************************************/ 6857 /* Opcode types */ 6858 enum { 6859 PPC_DIRECT = 0, /* Opcode routine */ 6860 PPC_INDIRECT = 1, /* Indirect opcode table */ 6861 }; 6862 6863 #define PPC_OPCODE_MASK 0x3 6864 6865 static inline int is_indirect_opcode(void *handler) 6866 { 6867 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6868 } 6869 6870 static inline opc_handler_t **ind_table(void *handler) 6871 { 6872 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6873 } 6874 6875 /* Instruction table creation */ 6876 /* Opcodes tables creation */ 6877 static void fill_new_table(opc_handler_t **table, int len) 6878 { 6879 int i; 6880 6881 for (i = 0; i < len; i++) { 6882 table[i] = &invalid_handler; 6883 } 6884 } 6885 6886 static int create_new_table(opc_handler_t **table, unsigned char idx) 6887 { 6888 opc_handler_t **tmp; 6889 6890 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6891 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6892 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6893 6894 return 0; 6895 } 6896 6897 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6898 opc_handler_t *handler) 6899 { 6900 if (table[idx] != &invalid_handler) { 6901 return -1; 6902 } 6903 table[idx] = handler; 6904 6905 return 0; 6906 } 6907 6908 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6909 unsigned char idx, opc_handler_t *handler) 6910 { 6911 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6912 printf("*** ERROR: opcode %02x already assigned in main " 6913 "opcode table\n", idx); 6914 return -1; 6915 } 6916 6917 return 0; 6918 } 6919 6920 static int register_ind_in_table(opc_handler_t **table, 6921 unsigned char idx1, unsigned char idx2, 6922 opc_handler_t *handler) 6923 { 6924 if (table[idx1] == &invalid_handler) { 6925 if (create_new_table(table, idx1) < 0) { 6926 printf("*** ERROR: unable to create indirect table " 6927 "idx=%02x\n", idx1); 6928 return -1; 6929 } 6930 } else { 6931 if (!is_indirect_opcode(table[idx1])) { 6932 printf("*** ERROR: idx %02x already assigned to a direct " 6933 "opcode\n", idx1); 6934 return -1; 6935 } 6936 } 6937 if (handler != NULL && 6938 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6939 printf("*** ERROR: opcode %02x already assigned in " 6940 "opcode table %02x\n", idx2, idx1); 6941 return -1; 6942 } 6943 6944 return 0; 6945 } 6946 6947 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6948 unsigned char idx1, unsigned char idx2, 6949 opc_handler_t *handler) 6950 { 6951 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6952 } 6953 6954 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6955 unsigned char idx1, unsigned char idx2, 6956 unsigned char idx3, opc_handler_t *handler) 6957 { 6958 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6959 printf("*** ERROR: unable to join indirect table idx " 6960 "[%02x-%02x]\n", idx1, idx2); 6961 return -1; 6962 } 6963 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6964 handler) < 0) { 6965 printf("*** ERROR: unable to insert opcode " 6966 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6967 return -1; 6968 } 6969 6970 return 0; 6971 } 6972 6973 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6974 unsigned char idx1, unsigned char idx2, 6975 unsigned char idx3, unsigned char idx4, 6976 opc_handler_t *handler) 6977 { 6978 opc_handler_t **table; 6979 6980 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6981 printf("*** ERROR: unable to join indirect table idx " 6982 "[%02x-%02x]\n", idx1, idx2); 6983 return -1; 6984 } 6985 table = ind_table(ppc_opcodes[idx1]); 6986 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 6987 printf("*** ERROR: unable to join 2nd-level indirect table idx " 6988 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6989 return -1; 6990 } 6991 table = ind_table(table[idx2]); 6992 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 6993 printf("*** ERROR: unable to insert opcode " 6994 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 6995 return -1; 6996 } 6997 return 0; 6998 } 6999 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7000 { 7001 if (insn->opc2 != 0xFF) { 7002 if (insn->opc3 != 0xFF) { 7003 if (insn->opc4 != 0xFF) { 7004 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7005 insn->opc3, insn->opc4, 7006 &insn->handler) < 0) { 7007 return -1; 7008 } 7009 } else { 7010 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7011 insn->opc3, &insn->handler) < 0) { 7012 return -1; 7013 } 7014 } 7015 } else { 7016 if (register_ind_insn(ppc_opcodes, insn->opc1, 7017 insn->opc2, &insn->handler) < 0) { 7018 return -1; 7019 } 7020 } 7021 } else { 7022 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7023 return -1; 7024 } 7025 } 7026 7027 return 0; 7028 } 7029 7030 static int test_opcode_table(opc_handler_t **table, int len) 7031 { 7032 int i, count, tmp; 7033 7034 for (i = 0, count = 0; i < len; i++) { 7035 /* Consistency fixup */ 7036 if (table[i] == NULL) { 7037 table[i] = &invalid_handler; 7038 } 7039 if (table[i] != &invalid_handler) { 7040 if (is_indirect_opcode(table[i])) { 7041 tmp = test_opcode_table(ind_table(table[i]), 7042 PPC_CPU_INDIRECT_OPCODES_LEN); 7043 if (tmp == 0) { 7044 free(table[i]); 7045 table[i] = &invalid_handler; 7046 } else { 7047 count++; 7048 } 7049 } else { 7050 count++; 7051 } 7052 } 7053 } 7054 7055 return count; 7056 } 7057 7058 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7059 { 7060 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7061 printf("*** WARNING: no opcode defined !\n"); 7062 } 7063 } 7064 7065 /*****************************************************************************/ 7066 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7067 { 7068 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7069 opcode_t *opc; 7070 7071 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7072 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7073 if (((opc->handler.type & pcc->insns_flags) != 0) || 7074 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7075 if (register_insn(cpu->opcodes, opc) < 0) { 7076 error_setg(errp, "ERROR initializing PowerPC instruction " 7077 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7078 opc->opc3); 7079 return; 7080 } 7081 } 7082 } 7083 fix_opcode_tables(cpu->opcodes); 7084 fflush(stdout); 7085 fflush(stderr); 7086 } 7087 7088 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7089 { 7090 opc_handler_t **table, **table_2; 7091 int i, j, k; 7092 7093 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7094 if (cpu->opcodes[i] == &invalid_handler) { 7095 continue; 7096 } 7097 if (is_indirect_opcode(cpu->opcodes[i])) { 7098 table = ind_table(cpu->opcodes[i]); 7099 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7100 if (table[j] == &invalid_handler) { 7101 continue; 7102 } 7103 if (is_indirect_opcode(table[j])) { 7104 table_2 = ind_table(table[j]); 7105 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7106 if (table_2[k] != &invalid_handler && 7107 is_indirect_opcode(table_2[k])) { 7108 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7109 ~PPC_INDIRECT)); 7110 } 7111 } 7112 g_free((opc_handler_t *)((uintptr_t)table[j] & 7113 ~PPC_INDIRECT)); 7114 } 7115 } 7116 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7117 ~PPC_INDIRECT)); 7118 } 7119 } 7120 } 7121 7122 int ppc_fixup_cpu(PowerPCCPU *cpu) 7123 { 7124 CPUPPCState *env = &cpu->env; 7125 7126 /* 7127 * TCG doesn't (yet) emulate some groups of instructions that are 7128 * implemented on some otherwise supported CPUs (e.g. VSX and 7129 * decimal floating point instructions on POWER7). We remove 7130 * unsupported instruction groups from the cpu state's instruction 7131 * masks and hope the guest can cope. For at least the pseries 7132 * machine, the unavailability of these instructions can be 7133 * advertised to the guest via the device tree. 7134 */ 7135 if ((env->insns_flags & ~PPC_TCG_INSNS) 7136 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7137 warn_report("Disabling some instructions which are not " 7138 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7139 env->insns_flags & ~PPC_TCG_INSNS, 7140 env->insns_flags2 & ~PPC_TCG_INSNS2); 7141 } 7142 env->insns_flags &= PPC_TCG_INSNS; 7143 env->insns_flags2 &= PPC_TCG_INSNS2; 7144 return 0; 7145 } 7146 7147 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7148 { 7149 opc_handler_t **table, *handler; 7150 uint32_t inval; 7151 7152 ctx->opcode = insn; 7153 7154 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7155 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7156 ctx->le_mode ? "little" : "big"); 7157 7158 table = cpu->opcodes; 7159 handler = table[opc1(insn)]; 7160 if (is_indirect_opcode(handler)) { 7161 table = ind_table(handler); 7162 handler = table[opc2(insn)]; 7163 if (is_indirect_opcode(handler)) { 7164 table = ind_table(handler); 7165 handler = table[opc3(insn)]; 7166 if (is_indirect_opcode(handler)) { 7167 table = ind_table(handler); 7168 handler = table[opc4(insn)]; 7169 } 7170 } 7171 } 7172 7173 /* Is opcode *REALLY* valid ? */ 7174 if (unlikely(handler->handler == &gen_invalid)) { 7175 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7176 "%02x - %02x - %02x - %02x (%08x) " 7177 TARGET_FMT_lx "\n", 7178 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7179 insn, ctx->cia); 7180 return false; 7181 } 7182 7183 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7184 && Rc(insn))) { 7185 inval = handler->inval2; 7186 } else { 7187 inval = handler->inval1; 7188 } 7189 7190 if (unlikely((insn & inval) != 0)) { 7191 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7192 "%02x - %02x - %02x - %02x (%08x) " 7193 TARGET_FMT_lx "\n", insn & inval, 7194 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7195 insn, ctx->cia); 7196 return false; 7197 } 7198 7199 handler->handler(ctx); 7200 return true; 7201 } 7202 7203 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7204 { 7205 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7206 CPUPPCState *env = cs->env_ptr; 7207 uint32_t hflags = ctx->base.tb->flags; 7208 7209 ctx->spr_cb = env->spr_cb; 7210 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7211 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7212 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7213 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7214 ctx->insns_flags = env->insns_flags; 7215 ctx->insns_flags2 = env->insns_flags2; 7216 ctx->access_type = -1; 7217 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7218 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7219 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7220 ctx->flags = env->flags; 7221 #if defined(TARGET_PPC64) 7222 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7223 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7224 #endif 7225 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7226 || env->mmu_model & POWERPC_MMU_64; 7227 7228 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7229 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7230 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7231 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7232 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7233 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7234 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7235 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7236 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7237 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7238 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7239 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7240 7241 ctx->singlestep_enabled = 0; 7242 if ((hflags >> HFLAGS_SE) & 1) { 7243 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7244 ctx->base.max_insns = 1; 7245 } 7246 if ((hflags >> HFLAGS_BE) & 1) { 7247 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7248 } 7249 } 7250 7251 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7252 { 7253 } 7254 7255 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7256 { 7257 tcg_gen_insn_start(dcbase->pc_next); 7258 } 7259 7260 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7261 { 7262 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7263 return opc1(insn) == 1; 7264 } 7265 7266 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7267 { 7268 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7269 PowerPCCPU *cpu = POWERPC_CPU(cs); 7270 CPUPPCState *env = cs->env_ptr; 7271 target_ulong pc; 7272 uint32_t insn; 7273 bool ok; 7274 7275 LOG_DISAS("----------------\n"); 7276 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7277 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7278 7279 ctx->cia = pc = ctx->base.pc_next; 7280 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7281 ctx->base.pc_next = pc += 4; 7282 7283 if (!is_prefix_insn(ctx, insn)) { 7284 ok = (decode_insn32(ctx, insn) || 7285 decode_legacy(cpu, ctx, insn)); 7286 } else if ((pc & 63) == 0) { 7287 /* 7288 * Power v3.1, section 1.9 Exceptions: 7289 * attempt to execute a prefixed instruction that crosses a 7290 * 64-byte address boundary (system alignment error). 7291 */ 7292 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7293 ok = true; 7294 } else { 7295 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7296 need_byteswap(ctx)); 7297 ctx->base.pc_next = pc += 4; 7298 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7299 } 7300 if (!ok) { 7301 gen_invalid(ctx); 7302 } 7303 7304 /* End the TB when crossing a page boundary. */ 7305 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7306 ctx->base.is_jmp = DISAS_TOO_MANY; 7307 } 7308 } 7309 7310 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7311 { 7312 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7313 DisasJumpType is_jmp = ctx->base.is_jmp; 7314 target_ulong nip = ctx->base.pc_next; 7315 7316 if (is_jmp == DISAS_NORETURN) { 7317 /* We have already exited the TB. */ 7318 return; 7319 } 7320 7321 /* Honor single stepping. */ 7322 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7323 && (nip <= 0x100 || nip > 0xf00)) { 7324 switch (is_jmp) { 7325 case DISAS_TOO_MANY: 7326 case DISAS_EXIT_UPDATE: 7327 case DISAS_CHAIN_UPDATE: 7328 gen_update_nip(ctx, nip); 7329 break; 7330 case DISAS_EXIT: 7331 case DISAS_CHAIN: 7332 break; 7333 default: 7334 g_assert_not_reached(); 7335 } 7336 7337 gen_debug_exception(ctx); 7338 return; 7339 } 7340 7341 switch (is_jmp) { 7342 case DISAS_TOO_MANY: 7343 if (use_goto_tb(ctx, nip)) { 7344 pmu_count_insns(ctx); 7345 tcg_gen_goto_tb(0); 7346 gen_update_nip(ctx, nip); 7347 tcg_gen_exit_tb(ctx->base.tb, 0); 7348 break; 7349 } 7350 /* fall through */ 7351 case DISAS_CHAIN_UPDATE: 7352 gen_update_nip(ctx, nip); 7353 /* fall through */ 7354 case DISAS_CHAIN: 7355 /* 7356 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7357 * CF_NO_GOTO_PTR is set. Count insns now. 7358 */ 7359 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7360 pmu_count_insns(ctx); 7361 } 7362 7363 tcg_gen_lookup_and_goto_ptr(); 7364 break; 7365 7366 case DISAS_EXIT_UPDATE: 7367 gen_update_nip(ctx, nip); 7368 /* fall through */ 7369 case DISAS_EXIT: 7370 pmu_count_insns(ctx); 7371 tcg_gen_exit_tb(NULL, 0); 7372 break; 7373 7374 default: 7375 g_assert_not_reached(); 7376 } 7377 } 7378 7379 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7380 CPUState *cs, FILE *logfile) 7381 { 7382 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7383 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7384 } 7385 7386 static const TranslatorOps ppc_tr_ops = { 7387 .init_disas_context = ppc_tr_init_disas_context, 7388 .tb_start = ppc_tr_tb_start, 7389 .insn_start = ppc_tr_insn_start, 7390 .translate_insn = ppc_tr_translate_insn, 7391 .tb_stop = ppc_tr_tb_stop, 7392 .disas_log = ppc_tr_disas_log, 7393 }; 7394 7395 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7396 target_ulong pc, void *host_pc) 7397 { 7398 DisasContext ctx; 7399 7400 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7401 } 7402