1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 #include "qemu/atomic128.h" 36 #include "spr_common.h" 37 #include "power8-pmu.h" 38 39 #include "qemu/qemu-print.h" 40 #include "qapi/error.h" 41 42 #define HELPER_H "helper.h" 43 #include "exec/helper-info.c.inc" 44 #undef HELPER_H 45 46 #define CPU_SINGLE_STEP 0x1 47 #define CPU_BRANCH_STEP 0x2 48 49 /* Include definitions for instructions classes and implementations flags */ 50 /* #define PPC_DEBUG_DISAS */ 51 52 #ifdef PPC_DEBUG_DISAS 53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54 #else 55 # define LOG_DISAS(...) do { } while (0) 56 #endif 57 /*****************************************************************************/ 58 /* Code translation helpers */ 59 60 /* global register indexes */ 61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62 + 10 * 4 + 22 * 5 /* SPE GPRh */ 63 + 8 * 5 /* CRF */]; 64 static TCGv cpu_gpr[32]; 65 static TCGv cpu_gprh[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75 static TCGv cpu_reserve; 76 static TCGv cpu_reserve_length; 77 static TCGv cpu_reserve_val; 78 static TCGv cpu_reserve_val2; 79 static TCGv cpu_fpscr; 80 static TCGv_i32 cpu_access_type; 81 82 void ppc_translate_init(void) 83 { 84 int i; 85 char *p; 86 size_t cpu_reg_names_size; 87 88 p = cpu_reg_names; 89 cpu_reg_names_size = sizeof(cpu_reg_names); 90 91 for (i = 0; i < 8; i++) { 92 snprintf(p, cpu_reg_names_size, "crf%d", i); 93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94 offsetof(CPUPPCState, crf[i]), p); 95 p += 5; 96 cpu_reg_names_size -= 5; 97 } 98 99 for (i = 0; i < 32; i++) { 100 snprintf(p, cpu_reg_names_size, "r%d", i); 101 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102 offsetof(CPUPPCState, gpr[i]), p); 103 p += (i < 10) ? 3 : 4; 104 cpu_reg_names_size -= (i < 10) ? 3 : 4; 105 snprintf(p, cpu_reg_names_size, "r%dH", i); 106 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107 offsetof(CPUPPCState, gprh[i]), p); 108 p += (i < 10) ? 4 : 5; 109 cpu_reg_names_size -= (i < 10) ? 4 : 5; 110 } 111 112 cpu_nip = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, nip), "nip"); 114 115 cpu_msr = tcg_global_mem_new(cpu_env, 116 offsetof(CPUPPCState, msr), "msr"); 117 118 cpu_ctr = tcg_global_mem_new(cpu_env, 119 offsetof(CPUPPCState, ctr), "ctr"); 120 121 cpu_lr = tcg_global_mem_new(cpu_env, 122 offsetof(CPUPPCState, lr), "lr"); 123 124 #if defined(TARGET_PPC64) 125 cpu_cfar = tcg_global_mem_new(cpu_env, 126 offsetof(CPUPPCState, cfar), "cfar"); 127 #endif 128 129 cpu_xer = tcg_global_mem_new(cpu_env, 130 offsetof(CPUPPCState, xer), "xer"); 131 cpu_so = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, so), "SO"); 133 cpu_ov = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, ov), "OV"); 135 cpu_ca = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ca), "CA"); 137 cpu_ov32 = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ov32), "OV32"); 139 cpu_ca32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ca32), "CA32"); 141 142 cpu_reserve = tcg_global_mem_new(cpu_env, 143 offsetof(CPUPPCState, reserve_addr), 144 "reserve_addr"); 145 cpu_reserve_length = tcg_global_mem_new(cpu_env, 146 offsetof(CPUPPCState, 147 reserve_length), 148 "reserve_length"); 149 cpu_reserve_val = tcg_global_mem_new(cpu_env, 150 offsetof(CPUPPCState, reserve_val), 151 "reserve_val"); 152 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 153 offsetof(CPUPPCState, reserve_val2), 154 "reserve_val2"); 155 156 cpu_fpscr = tcg_global_mem_new(cpu_env, 157 offsetof(CPUPPCState, fpscr), "fpscr"); 158 159 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 160 offsetof(CPUPPCState, access_type), 161 "access_type"); 162 } 163 164 /* internal defines */ 165 struct DisasContext { 166 DisasContextBase base; 167 target_ulong cia; /* current instruction address */ 168 uint32_t opcode; 169 /* Routine used to access memory */ 170 bool pr, hv, dr, le_mode; 171 bool lazy_tlb_flush; 172 bool need_access_type; 173 int mem_idx; 174 int access_type; 175 /* Translation flags */ 176 MemOp default_tcg_memop_mask; 177 #if defined(TARGET_PPC64) 178 bool sf_mode; 179 bool has_cfar; 180 #endif 181 bool fpu_enabled; 182 bool altivec_enabled; 183 bool vsx_enabled; 184 bool spe_enabled; 185 bool tm_enabled; 186 bool gtse; 187 bool hr; 188 bool mmcr0_pmcc0; 189 bool mmcr0_pmcc1; 190 bool mmcr0_pmcjce; 191 bool pmc_other; 192 bool pmu_insn_cnt; 193 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 194 int singlestep_enabled; 195 uint32_t flags; 196 uint64_t insns_flags; 197 uint64_t insns_flags2; 198 }; 199 200 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 201 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 202 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 203 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 204 205 /* Return true iff byteswap is needed in a scalar memop */ 206 static inline bool need_byteswap(const DisasContext *ctx) 207 { 208 #if TARGET_BIG_ENDIAN 209 return ctx->le_mode; 210 #else 211 return !ctx->le_mode; 212 #endif 213 } 214 215 /* True when active word size < size of target_long. */ 216 #ifdef TARGET_PPC64 217 # define NARROW_MODE(C) (!(C)->sf_mode) 218 #else 219 # define NARROW_MODE(C) 0 220 #endif 221 222 struct opc_handler_t { 223 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 224 uint32_t inval1; 225 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 226 uint32_t inval2; 227 /* instruction type */ 228 uint64_t type; 229 /* extended instruction type */ 230 uint64_t type2; 231 /* handler */ 232 void (*handler)(DisasContext *ctx); 233 }; 234 235 static inline bool gen_serialize(DisasContext *ctx) 236 { 237 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 238 /* Restart with exclusive lock. */ 239 gen_helper_exit_atomic(cpu_env); 240 ctx->base.is_jmp = DISAS_NORETURN; 241 return false; 242 } 243 return true; 244 } 245 246 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 247 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 248 { 249 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 250 return gen_serialize(ctx); 251 } 252 253 return true; 254 } 255 #endif 256 257 /* SPR load/store helpers */ 258 static inline void gen_load_spr(TCGv t, int reg) 259 { 260 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 261 } 262 263 static inline void gen_store_spr(int reg, TCGv t) 264 { 265 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 266 } 267 268 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 269 { 270 if (ctx->need_access_type && ctx->access_type != access_type) { 271 tcg_gen_movi_i32(cpu_access_type, access_type); 272 ctx->access_type = access_type; 273 } 274 } 275 276 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 277 { 278 if (NARROW_MODE(ctx)) { 279 nip = (uint32_t)nip; 280 } 281 tcg_gen_movi_tl(cpu_nip, nip); 282 } 283 284 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 285 { 286 TCGv_i32 t0, t1; 287 288 /* 289 * These are all synchronous exceptions, we set the PC back to the 290 * faulting instruction 291 */ 292 gen_update_nip(ctx, ctx->cia); 293 t0 = tcg_constant_i32(excp); 294 t1 = tcg_constant_i32(error); 295 gen_helper_raise_exception_err(cpu_env, t0, t1); 296 ctx->base.is_jmp = DISAS_NORETURN; 297 } 298 299 static void gen_exception(DisasContext *ctx, uint32_t excp) 300 { 301 TCGv_i32 t0; 302 303 /* 304 * These are all synchronous exceptions, we set the PC back to the 305 * faulting instruction 306 */ 307 gen_update_nip(ctx, ctx->cia); 308 t0 = tcg_constant_i32(excp); 309 gen_helper_raise_exception(cpu_env, t0); 310 ctx->base.is_jmp = DISAS_NORETURN; 311 } 312 313 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 314 target_ulong nip) 315 { 316 TCGv_i32 t0; 317 318 gen_update_nip(ctx, nip); 319 t0 = tcg_constant_i32(excp); 320 gen_helper_raise_exception(cpu_env, t0); 321 ctx->base.is_jmp = DISAS_NORETURN; 322 } 323 324 #if !defined(CONFIG_USER_ONLY) 325 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 326 { 327 translator_io_start(&ctx->base); 328 gen_helper_ppc_maybe_interrupt(cpu_env); 329 } 330 #endif 331 332 /* 333 * Tells the caller what is the appropriate exception to generate and prepares 334 * SPR registers for this exception. 335 * 336 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 337 * POWERPC_EXCP_DEBUG (on BookE). 338 */ 339 static void gen_debug_exception(DisasContext *ctx) 340 { 341 #if !defined(CONFIG_USER_ONLY) 342 if (ctx->flags & POWERPC_FLAG_DE) { 343 target_ulong dbsr = 0; 344 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 345 dbsr = DBCR0_ICMP; 346 } else { 347 /* Must have been branch */ 348 dbsr = DBCR0_BRT; 349 } 350 TCGv t0 = tcg_temp_new(); 351 gen_load_spr(t0, SPR_BOOKE_DBSR); 352 tcg_gen_ori_tl(t0, t0, dbsr); 353 gen_store_spr(SPR_BOOKE_DBSR, t0); 354 gen_helper_raise_exception(cpu_env, 355 tcg_constant_i32(POWERPC_EXCP_DEBUG)); 356 ctx->base.is_jmp = DISAS_NORETURN; 357 } else { 358 TCGv t0 = tcg_temp_new(); 359 tcg_gen_movi_tl(t0, ctx->cia); 360 gen_helper_book3s_trace(cpu_env, t0); 361 ctx->base.is_jmp = DISAS_NORETURN; 362 } 363 #endif 364 } 365 366 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 367 { 368 /* Will be converted to program check if needed */ 369 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 370 } 371 372 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 373 { 374 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 375 } 376 377 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 378 { 379 /* Will be converted to program check if needed */ 380 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 381 } 382 383 /*****************************************************************************/ 384 /* SPR READ/WRITE CALLBACKS */ 385 386 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 387 { 388 #if 0 389 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 390 printf("ERROR: try to access SPR %d !\n", sprn); 391 #endif 392 } 393 394 /* #define PPC_DUMP_SPR_ACCESSES */ 395 396 /* 397 * Generic callbacks: 398 * do nothing but store/retrieve spr value 399 */ 400 static void spr_load_dump_spr(int sprn) 401 { 402 #ifdef PPC_DUMP_SPR_ACCESSES 403 TCGv_i32 t0 = tcg_constant_i32(sprn); 404 gen_helper_load_dump_spr(cpu_env, t0); 405 #endif 406 } 407 408 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 409 { 410 gen_load_spr(cpu_gpr[gprn], sprn); 411 spr_load_dump_spr(sprn); 412 } 413 414 static void spr_store_dump_spr(int sprn) 415 { 416 #ifdef PPC_DUMP_SPR_ACCESSES 417 TCGv_i32 t0 = tcg_constant_i32(sprn); 418 gen_helper_store_dump_spr(cpu_env, t0); 419 #endif 420 } 421 422 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 423 { 424 gen_store_spr(sprn, cpu_gpr[gprn]); 425 spr_store_dump_spr(sprn); 426 } 427 428 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 429 { 430 #ifdef TARGET_PPC64 431 TCGv t0 = tcg_temp_new(); 432 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 433 gen_store_spr(sprn, t0); 434 spr_store_dump_spr(sprn); 435 #else 436 spr_write_generic(ctx, sprn, gprn); 437 #endif 438 } 439 440 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 441 { 442 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 443 spr_write_generic(ctx, sprn, gprn); 444 return; 445 } 446 447 if (!gen_serialize(ctx)) { 448 return; 449 } 450 451 gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), 452 cpu_gpr[gprn]); 453 spr_store_dump_spr(sprn); 454 } 455 456 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 457 { 458 /* This does not implement >1 thread */ 459 TCGv t0 = tcg_temp_new(); 460 TCGv t1 = tcg_temp_new(); 461 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 462 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 463 tcg_gen_or_tl(t1, t1, t0); 464 gen_store_spr(sprn, t1); 465 } 466 467 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 468 { 469 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 470 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 471 spr_write_CTRL_ST(ctx, sprn, gprn); 472 goto out; 473 } 474 475 if (!gen_serialize(ctx)) { 476 return; 477 } 478 479 gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 480 cpu_gpr[gprn]); 481 out: 482 spr_store_dump_spr(sprn); 483 484 /* 485 * SPR_CTRL writes must force a new translation block, 486 * allowing the PMU to calculate the run latch events with 487 * more accuracy. 488 */ 489 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 490 } 491 492 #if !defined(CONFIG_USER_ONLY) 493 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 494 { 495 TCGv t0 = tcg_temp_new(); 496 TCGv t1 = tcg_temp_new(); 497 gen_load_spr(t0, sprn); 498 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 499 tcg_gen_and_tl(t0, t0, t1); 500 gen_store_spr(sprn, t0); 501 } 502 503 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 504 { 505 } 506 507 #endif 508 509 /* SPR common to all PowerPC */ 510 /* XER */ 511 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 512 { 513 TCGv dst = cpu_gpr[gprn]; 514 TCGv t0 = tcg_temp_new(); 515 TCGv t1 = tcg_temp_new(); 516 TCGv t2 = tcg_temp_new(); 517 tcg_gen_mov_tl(dst, cpu_xer); 518 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 519 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 520 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 521 tcg_gen_or_tl(t0, t0, t1); 522 tcg_gen_or_tl(dst, dst, t2); 523 tcg_gen_or_tl(dst, dst, t0); 524 if (is_isa300(ctx)) { 525 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 526 tcg_gen_or_tl(dst, dst, t0); 527 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 528 tcg_gen_or_tl(dst, dst, t0); 529 } 530 } 531 532 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 533 { 534 TCGv src = cpu_gpr[gprn]; 535 /* Write all flags, while reading back check for isa300 */ 536 tcg_gen_andi_tl(cpu_xer, src, 537 ~((1u << XER_SO) | 538 (1u << XER_OV) | (1u << XER_OV32) | 539 (1u << XER_CA) | (1u << XER_CA32))); 540 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 541 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 542 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 543 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 544 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 545 } 546 547 /* LR */ 548 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 549 { 550 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 551 } 552 553 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 554 { 555 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 556 } 557 558 /* CFAR */ 559 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 560 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 561 { 562 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 563 } 564 565 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 566 { 567 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 568 } 569 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 570 571 /* CTR */ 572 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 573 { 574 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 575 } 576 577 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 578 { 579 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 580 } 581 582 /* User read access to SPR */ 583 /* USPRx */ 584 /* UMMCRx */ 585 /* UPMCx */ 586 /* USIA */ 587 /* UDECR */ 588 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 589 { 590 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 591 } 592 593 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 594 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 595 { 596 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 597 } 598 #endif 599 600 /* SPR common to all non-embedded PowerPC */ 601 /* DECR */ 602 #if !defined(CONFIG_USER_ONLY) 603 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 604 { 605 translator_io_start(&ctx->base); 606 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 607 } 608 609 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 610 { 611 translator_io_start(&ctx->base); 612 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 613 } 614 #endif 615 616 /* SPR common to all non-embedded PowerPC, except 601 */ 617 /* Time base */ 618 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 619 { 620 translator_io_start(&ctx->base); 621 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 622 } 623 624 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 625 { 626 translator_io_start(&ctx->base); 627 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 628 } 629 630 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 631 { 632 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 633 } 634 635 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 636 { 637 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 638 } 639 640 #if !defined(CONFIG_USER_ONLY) 641 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 642 { 643 translator_io_start(&ctx->base); 644 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 645 } 646 647 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 648 { 649 translator_io_start(&ctx->base); 650 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 651 } 652 653 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 654 { 655 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 656 } 657 658 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 659 { 660 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 661 } 662 663 #if defined(TARGET_PPC64) 664 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 665 { 666 translator_io_start(&ctx->base); 667 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 668 } 669 670 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 671 { 672 translator_io_start(&ctx->base); 673 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 674 } 675 676 /* HDECR */ 677 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 678 { 679 translator_io_start(&ctx->base); 680 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 681 } 682 683 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 684 { 685 translator_io_start(&ctx->base); 686 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 687 } 688 689 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 690 { 691 translator_io_start(&ctx->base); 692 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 693 } 694 695 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 696 { 697 translator_io_start(&ctx->base); 698 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 699 } 700 701 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 702 { 703 translator_io_start(&ctx->base); 704 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 705 } 706 707 #endif 708 #endif 709 710 #if !defined(CONFIG_USER_ONLY) 711 /* IBAT0U...IBAT0U */ 712 /* IBAT0L...IBAT7L */ 713 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 714 { 715 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 716 offsetof(CPUPPCState, 717 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 718 } 719 720 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 721 { 722 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 723 offsetof(CPUPPCState, 724 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 725 } 726 727 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 728 { 729 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 730 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 731 } 732 733 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 734 { 735 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 736 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 737 } 738 739 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 740 { 741 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 742 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 743 } 744 745 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 746 { 747 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 748 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 749 } 750 751 /* DBAT0U...DBAT7U */ 752 /* DBAT0L...DBAT7L */ 753 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 754 { 755 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 756 offsetof(CPUPPCState, 757 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 758 } 759 760 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 761 { 762 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 763 offsetof(CPUPPCState, 764 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 765 } 766 767 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 768 { 769 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 770 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 771 } 772 773 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 774 { 775 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 776 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 777 } 778 779 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 780 { 781 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 782 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 783 } 784 785 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 786 { 787 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 788 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 789 } 790 791 /* SDR1 */ 792 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 793 { 794 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 795 } 796 797 #if defined(TARGET_PPC64) 798 /* 64 bits PowerPC specific SPRs */ 799 /* PIDR */ 800 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 801 { 802 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 803 } 804 805 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 806 { 807 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 808 } 809 810 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 811 { 812 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 813 } 814 815 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 816 { 817 TCGv t0 = tcg_temp_new(); 818 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 819 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 820 } 821 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 822 { 823 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 824 } 825 826 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 827 { 828 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 829 } 830 831 /* DPDES */ 832 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 833 { 834 if (!gen_serialize_core_lpar(ctx)) { 835 return; 836 } 837 838 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 839 } 840 841 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 842 { 843 if (!gen_serialize_core_lpar(ctx)) { 844 return; 845 } 846 847 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 848 } 849 #endif 850 #endif 851 852 /* PowerPC 40x specific registers */ 853 #if !defined(CONFIG_USER_ONLY) 854 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 855 { 856 translator_io_start(&ctx->base); 857 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 858 } 859 860 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 861 { 862 translator_io_start(&ctx->base); 863 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 864 } 865 866 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 867 { 868 translator_io_start(&ctx->base); 869 gen_store_spr(sprn, cpu_gpr[gprn]); 870 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 871 /* We must stop translation as we may have rebooted */ 872 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 873 } 874 875 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 876 { 877 translator_io_start(&ctx->base); 878 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 879 } 880 881 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 882 { 883 translator_io_start(&ctx->base); 884 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 885 } 886 887 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 888 { 889 translator_io_start(&ctx->base); 890 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 891 } 892 893 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 894 { 895 TCGv t0 = tcg_temp_new(); 896 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 897 gen_helper_store_40x_pid(cpu_env, t0); 898 } 899 900 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 901 { 902 translator_io_start(&ctx->base); 903 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 904 } 905 906 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 907 { 908 translator_io_start(&ctx->base); 909 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 910 } 911 #endif 912 913 /* PIR */ 914 #if !defined(CONFIG_USER_ONLY) 915 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 916 { 917 TCGv t0 = tcg_temp_new(); 918 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 919 gen_store_spr(SPR_PIR, t0); 920 } 921 #endif 922 923 /* SPE specific registers */ 924 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 925 { 926 TCGv_i32 t0 = tcg_temp_new_i32(); 927 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 928 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 929 } 930 931 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 932 { 933 TCGv_i32 t0 = tcg_temp_new_i32(); 934 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 935 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 936 } 937 938 #if !defined(CONFIG_USER_ONLY) 939 /* Callback used to write the exception vector base */ 940 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 941 { 942 TCGv t0 = tcg_temp_new(); 943 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 944 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 945 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 946 gen_store_spr(sprn, t0); 947 } 948 949 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 950 { 951 int sprn_offs; 952 953 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 954 sprn_offs = sprn - SPR_BOOKE_IVOR0; 955 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 956 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 957 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 958 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 959 } else { 960 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 961 " vector 0x%03x\n", sprn); 962 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 963 return; 964 } 965 966 TCGv t0 = tcg_temp_new(); 967 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 968 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 969 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 970 gen_store_spr(sprn, t0); 971 } 972 #endif 973 974 #ifdef TARGET_PPC64 975 #ifndef CONFIG_USER_ONLY 976 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 977 { 978 TCGv t0 = tcg_temp_new(); 979 TCGv t1 = tcg_temp_new(); 980 TCGv t2 = tcg_temp_new(); 981 982 /* 983 * Note, the HV=1 PR=0 case is handled earlier by simply using 984 * spr_write_generic for HV mode in the SPR table 985 */ 986 987 /* Build insertion mask into t1 based on context */ 988 if (ctx->pr) { 989 gen_load_spr(t1, SPR_UAMOR); 990 } else { 991 gen_load_spr(t1, SPR_AMOR); 992 } 993 994 /* Mask new bits into t2 */ 995 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 996 997 /* Load AMR and clear new bits in t0 */ 998 gen_load_spr(t0, SPR_AMR); 999 tcg_gen_andc_tl(t0, t0, t1); 1000 1001 /* Or'in new bits and write it out */ 1002 tcg_gen_or_tl(t0, t0, t2); 1003 gen_store_spr(SPR_AMR, t0); 1004 spr_store_dump_spr(SPR_AMR); 1005 } 1006 1007 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1008 { 1009 TCGv t0 = tcg_temp_new(); 1010 TCGv t1 = tcg_temp_new(); 1011 TCGv t2 = tcg_temp_new(); 1012 1013 /* 1014 * Note, the HV=1 case is handled earlier by simply using 1015 * spr_write_generic for HV mode in the SPR table 1016 */ 1017 1018 /* Build insertion mask into t1 based on context */ 1019 gen_load_spr(t1, SPR_AMOR); 1020 1021 /* Mask new bits into t2 */ 1022 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1023 1024 /* Load AMR and clear new bits in t0 */ 1025 gen_load_spr(t0, SPR_UAMOR); 1026 tcg_gen_andc_tl(t0, t0, t1); 1027 1028 /* Or'in new bits and write it out */ 1029 tcg_gen_or_tl(t0, t0, t2); 1030 gen_store_spr(SPR_UAMOR, t0); 1031 spr_store_dump_spr(SPR_UAMOR); 1032 } 1033 1034 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1035 { 1036 TCGv t0 = tcg_temp_new(); 1037 TCGv t1 = tcg_temp_new(); 1038 TCGv t2 = tcg_temp_new(); 1039 1040 /* 1041 * Note, the HV=1 case is handled earlier by simply using 1042 * spr_write_generic for HV mode in the SPR table 1043 */ 1044 1045 /* Build insertion mask into t1 based on context */ 1046 gen_load_spr(t1, SPR_AMOR); 1047 1048 /* Mask new bits into t2 */ 1049 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1050 1051 /* Load AMR and clear new bits in t0 */ 1052 gen_load_spr(t0, SPR_IAMR); 1053 tcg_gen_andc_tl(t0, t0, t1); 1054 1055 /* Or'in new bits and write it out */ 1056 tcg_gen_or_tl(t0, t0, t2); 1057 gen_store_spr(SPR_IAMR, t0); 1058 spr_store_dump_spr(SPR_IAMR); 1059 } 1060 #endif 1061 #endif 1062 1063 #ifndef CONFIG_USER_ONLY 1064 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1065 { 1066 gen_helper_fixup_thrm(cpu_env); 1067 gen_load_spr(cpu_gpr[gprn], sprn); 1068 spr_load_dump_spr(sprn); 1069 } 1070 #endif /* !CONFIG_USER_ONLY */ 1071 1072 #if !defined(CONFIG_USER_ONLY) 1073 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1074 { 1075 TCGv t0 = tcg_temp_new(); 1076 1077 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1078 gen_store_spr(sprn, t0); 1079 } 1080 1081 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1082 { 1083 TCGv t0 = tcg_temp_new(); 1084 1085 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1086 gen_store_spr(sprn, t0); 1087 } 1088 1089 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1090 { 1091 TCGv t0 = tcg_temp_new(); 1092 1093 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1094 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1095 gen_store_spr(sprn, t0); 1096 } 1097 1098 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1099 { 1100 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1101 } 1102 1103 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1104 { 1105 TCGv_i32 t0 = tcg_constant_i32(sprn); 1106 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1107 } 1108 1109 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1110 { 1111 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1112 } 1113 1114 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1115 { 1116 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1117 } 1118 1119 #endif 1120 1121 #if !defined(CONFIG_USER_ONLY) 1122 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1123 { 1124 TCGv val = tcg_temp_new(); 1125 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1126 gen_store_spr(SPR_BOOKE_MAS3, val); 1127 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1128 gen_store_spr(SPR_BOOKE_MAS7, val); 1129 } 1130 1131 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1132 { 1133 TCGv mas7 = tcg_temp_new(); 1134 TCGv mas3 = tcg_temp_new(); 1135 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1136 tcg_gen_shli_tl(mas7, mas7, 32); 1137 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1138 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1139 } 1140 1141 #endif 1142 1143 #ifdef TARGET_PPC64 1144 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1145 int bit, int sprn, int cause) 1146 { 1147 TCGv_i32 t1 = tcg_constant_i32(bit); 1148 TCGv_i32 t2 = tcg_constant_i32(sprn); 1149 TCGv_i32 t3 = tcg_constant_i32(cause); 1150 1151 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1152 } 1153 1154 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1155 int bit, int sprn, int cause) 1156 { 1157 TCGv_i32 t1 = tcg_constant_i32(bit); 1158 TCGv_i32 t2 = tcg_constant_i32(sprn); 1159 TCGv_i32 t3 = tcg_constant_i32(cause); 1160 1161 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1162 } 1163 1164 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1165 { 1166 TCGv spr_up = tcg_temp_new(); 1167 TCGv spr = tcg_temp_new(); 1168 1169 gen_load_spr(spr, sprn - 1); 1170 tcg_gen_shri_tl(spr_up, spr, 32); 1171 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1172 } 1173 1174 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1175 { 1176 TCGv spr = tcg_temp_new(); 1177 1178 gen_load_spr(spr, sprn - 1); 1179 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1180 gen_store_spr(sprn - 1, spr); 1181 } 1182 1183 #if !defined(CONFIG_USER_ONLY) 1184 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1185 { 1186 TCGv hmer = tcg_temp_new(); 1187 1188 gen_load_spr(hmer, sprn); 1189 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1190 gen_store_spr(sprn, hmer); 1191 spr_store_dump_spr(sprn); 1192 } 1193 1194 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1195 { 1196 gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1197 } 1198 1199 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1200 { 1201 gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1202 } 1203 1204 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1205 { 1206 translator_io_start(&ctx->base); 1207 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1208 } 1209 #endif /* !defined(CONFIG_USER_ONLY) */ 1210 1211 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1212 { 1213 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1214 spr_read_generic(ctx, gprn, sprn); 1215 } 1216 1217 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1218 { 1219 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1220 spr_write_generic(ctx, sprn, gprn); 1221 } 1222 1223 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1224 { 1225 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1226 spr_read_generic(ctx, gprn, sprn); 1227 } 1228 1229 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1230 { 1231 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1232 spr_write_generic(ctx, sprn, gprn); 1233 } 1234 1235 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1236 { 1237 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1238 spr_read_prev_upper32(ctx, gprn, sprn); 1239 } 1240 1241 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1242 { 1243 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1244 spr_write_prev_upper32(ctx, sprn, gprn); 1245 } 1246 1247 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1248 { 1249 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1250 spr_read_generic(ctx, gprn, sprn); 1251 } 1252 1253 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1254 { 1255 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1256 spr_write_generic(ctx, sprn, gprn); 1257 } 1258 1259 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1260 { 1261 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1262 spr_read_prev_upper32(ctx, gprn, sprn); 1263 } 1264 1265 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1266 { 1267 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1268 spr_write_prev_upper32(ctx, sprn, gprn); 1269 } 1270 1271 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1272 { 1273 TCGv t0 = tcg_temp_new(); 1274 1275 /* 1276 * Access to the (H)DEXCR in problem state is done using separated 1277 * SPR indexes which are 16 below the SPR indexes which have full 1278 * access to the (H)DEXCR in privileged state. Problem state can 1279 * only read bits 32:63, bits 0:31 return 0. 1280 * 1281 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1282 */ 1283 1284 gen_load_spr(t0, sprn + 16); 1285 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1286 } 1287 #endif 1288 1289 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1290 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1291 1292 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1293 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1294 1295 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1296 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1297 1298 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1299 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1300 1301 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1302 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1303 1304 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1305 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1306 1307 typedef struct opcode_t { 1308 unsigned char opc1, opc2, opc3, opc4; 1309 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1310 unsigned char pad[4]; 1311 #endif 1312 opc_handler_t handler; 1313 const char *oname; 1314 } opcode_t; 1315 1316 static void gen_priv_opc(DisasContext *ctx) 1317 { 1318 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1319 } 1320 1321 /* Helpers for priv. check */ 1322 #define GEN_PRIV(CTX) \ 1323 do { \ 1324 gen_priv_opc(CTX); return; \ 1325 } while (0) 1326 1327 #if defined(CONFIG_USER_ONLY) 1328 #define CHK_HV(CTX) GEN_PRIV(CTX) 1329 #define CHK_SV(CTX) GEN_PRIV(CTX) 1330 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1331 #else 1332 #define CHK_HV(CTX) \ 1333 do { \ 1334 if (unlikely(ctx->pr || !ctx->hv)) {\ 1335 GEN_PRIV(CTX); \ 1336 } \ 1337 } while (0) 1338 #define CHK_SV(CTX) \ 1339 do { \ 1340 if (unlikely(ctx->pr)) { \ 1341 GEN_PRIV(CTX); \ 1342 } \ 1343 } while (0) 1344 #define CHK_HVRM(CTX) \ 1345 do { \ 1346 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1347 GEN_PRIV(CTX); \ 1348 } \ 1349 } while (0) 1350 #endif 1351 1352 #define CHK_NONE(CTX) 1353 1354 /*****************************************************************************/ 1355 /* PowerPC instructions table */ 1356 1357 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1358 { \ 1359 .opc1 = op1, \ 1360 .opc2 = op2, \ 1361 .opc3 = op3, \ 1362 .opc4 = 0xff, \ 1363 .handler = { \ 1364 .inval1 = invl, \ 1365 .type = _typ, \ 1366 .type2 = _typ2, \ 1367 .handler = &gen_##name, \ 1368 }, \ 1369 .oname = stringify(name), \ 1370 } 1371 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1372 { \ 1373 .opc1 = op1, \ 1374 .opc2 = op2, \ 1375 .opc3 = op3, \ 1376 .opc4 = 0xff, \ 1377 .handler = { \ 1378 .inval1 = invl1, \ 1379 .inval2 = invl2, \ 1380 .type = _typ, \ 1381 .type2 = _typ2, \ 1382 .handler = &gen_##name, \ 1383 }, \ 1384 .oname = stringify(name), \ 1385 } 1386 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1387 { \ 1388 .opc1 = op1, \ 1389 .opc2 = op2, \ 1390 .opc3 = op3, \ 1391 .opc4 = 0xff, \ 1392 .handler = { \ 1393 .inval1 = invl, \ 1394 .type = _typ, \ 1395 .type2 = _typ2, \ 1396 .handler = &gen_##name, \ 1397 }, \ 1398 .oname = onam, \ 1399 } 1400 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1401 { \ 1402 .opc1 = op1, \ 1403 .opc2 = op2, \ 1404 .opc3 = op3, \ 1405 .opc4 = op4, \ 1406 .handler = { \ 1407 .inval1 = invl, \ 1408 .type = _typ, \ 1409 .type2 = _typ2, \ 1410 .handler = &gen_##name, \ 1411 }, \ 1412 .oname = stringify(name), \ 1413 } 1414 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1415 { \ 1416 .opc1 = op1, \ 1417 .opc2 = op2, \ 1418 .opc3 = op3, \ 1419 .opc4 = op4, \ 1420 .handler = { \ 1421 .inval1 = invl, \ 1422 .type = _typ, \ 1423 .type2 = _typ2, \ 1424 .handler = &gen_##name, \ 1425 }, \ 1426 .oname = onam, \ 1427 } 1428 1429 /* Invalid instruction */ 1430 static void gen_invalid(DisasContext *ctx) 1431 { 1432 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1433 } 1434 1435 static opc_handler_t invalid_handler = { 1436 .inval1 = 0xFFFFFFFF, 1437 .inval2 = 0xFFFFFFFF, 1438 .type = PPC_NONE, 1439 .type2 = PPC_NONE, 1440 .handler = gen_invalid, 1441 }; 1442 1443 /*** Integer comparison ***/ 1444 1445 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1446 { 1447 TCGv t0 = tcg_temp_new(); 1448 TCGv t1 = tcg_temp_new(); 1449 TCGv_i32 t = tcg_temp_new_i32(); 1450 1451 tcg_gen_movi_tl(t0, CRF_EQ); 1452 tcg_gen_movi_tl(t1, CRF_LT); 1453 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1454 t0, arg0, arg1, t1, t0); 1455 tcg_gen_movi_tl(t1, CRF_GT); 1456 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1457 t0, arg0, arg1, t1, t0); 1458 1459 tcg_gen_trunc_tl_i32(t, t0); 1460 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1461 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1462 } 1463 1464 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1465 { 1466 TCGv t0 = tcg_constant_tl(arg1); 1467 gen_op_cmp(arg0, t0, s, crf); 1468 } 1469 1470 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1471 { 1472 TCGv t0, t1; 1473 t0 = tcg_temp_new(); 1474 t1 = tcg_temp_new(); 1475 if (s) { 1476 tcg_gen_ext32s_tl(t0, arg0); 1477 tcg_gen_ext32s_tl(t1, arg1); 1478 } else { 1479 tcg_gen_ext32u_tl(t0, arg0); 1480 tcg_gen_ext32u_tl(t1, arg1); 1481 } 1482 gen_op_cmp(t0, t1, s, crf); 1483 } 1484 1485 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1486 { 1487 TCGv t0 = tcg_constant_tl(arg1); 1488 gen_op_cmp32(arg0, t0, s, crf); 1489 } 1490 1491 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1492 { 1493 if (NARROW_MODE(ctx)) { 1494 gen_op_cmpi32(reg, 0, 1, 0); 1495 } else { 1496 gen_op_cmpi(reg, 0, 1, 0); 1497 } 1498 } 1499 1500 /* cmprb - range comparison: isupper, isaplha, islower*/ 1501 static void gen_cmprb(DisasContext *ctx) 1502 { 1503 TCGv_i32 src1 = tcg_temp_new_i32(); 1504 TCGv_i32 src2 = tcg_temp_new_i32(); 1505 TCGv_i32 src2lo = tcg_temp_new_i32(); 1506 TCGv_i32 src2hi = tcg_temp_new_i32(); 1507 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1508 1509 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1510 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1511 1512 tcg_gen_andi_i32(src1, src1, 0xFF); 1513 tcg_gen_ext8u_i32(src2lo, src2); 1514 tcg_gen_shri_i32(src2, src2, 8); 1515 tcg_gen_ext8u_i32(src2hi, src2); 1516 1517 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1518 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1519 tcg_gen_and_i32(crf, src2lo, src2hi); 1520 1521 if (ctx->opcode & 0x00200000) { 1522 tcg_gen_shri_i32(src2, src2, 8); 1523 tcg_gen_ext8u_i32(src2lo, src2); 1524 tcg_gen_shri_i32(src2, src2, 8); 1525 tcg_gen_ext8u_i32(src2hi, src2); 1526 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1527 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1528 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1529 tcg_gen_or_i32(crf, crf, src2lo); 1530 } 1531 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1532 } 1533 1534 #if defined(TARGET_PPC64) 1535 /* cmpeqb */ 1536 static void gen_cmpeqb(DisasContext *ctx) 1537 { 1538 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1539 cpu_gpr[rB(ctx->opcode)]); 1540 } 1541 #endif 1542 1543 /* isel (PowerPC 2.03 specification) */ 1544 static void gen_isel(DisasContext *ctx) 1545 { 1546 uint32_t bi = rC(ctx->opcode); 1547 uint32_t mask = 0x08 >> (bi & 0x03); 1548 TCGv t0 = tcg_temp_new(); 1549 TCGv zr; 1550 1551 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1552 tcg_gen_andi_tl(t0, t0, mask); 1553 1554 zr = tcg_constant_tl(0); 1555 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1556 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1557 cpu_gpr[rB(ctx->opcode)]); 1558 } 1559 1560 /* cmpb: PowerPC 2.05 specification */ 1561 static void gen_cmpb(DisasContext *ctx) 1562 { 1563 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1564 cpu_gpr[rB(ctx->opcode)]); 1565 } 1566 1567 /*** Integer arithmetic ***/ 1568 1569 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1570 TCGv arg1, TCGv arg2, int sub) 1571 { 1572 TCGv t0 = tcg_temp_new(); 1573 1574 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1575 tcg_gen_xor_tl(t0, arg1, arg2); 1576 if (sub) { 1577 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1578 } else { 1579 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1580 } 1581 if (NARROW_MODE(ctx)) { 1582 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1583 if (is_isa300(ctx)) { 1584 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1585 } 1586 } else { 1587 if (is_isa300(ctx)) { 1588 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1589 } 1590 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1591 } 1592 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1593 } 1594 1595 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1596 TCGv res, TCGv arg0, TCGv arg1, 1597 TCGv ca32, int sub) 1598 { 1599 TCGv t0; 1600 1601 if (!is_isa300(ctx)) { 1602 return; 1603 } 1604 1605 t0 = tcg_temp_new(); 1606 if (sub) { 1607 tcg_gen_eqv_tl(t0, arg0, arg1); 1608 } else { 1609 tcg_gen_xor_tl(t0, arg0, arg1); 1610 } 1611 tcg_gen_xor_tl(t0, t0, res); 1612 tcg_gen_extract_tl(ca32, t0, 32, 1); 1613 } 1614 1615 /* Common add function */ 1616 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1617 TCGv arg2, TCGv ca, TCGv ca32, 1618 bool add_ca, bool compute_ca, 1619 bool compute_ov, bool compute_rc0) 1620 { 1621 TCGv t0 = ret; 1622 1623 if (compute_ca || compute_ov) { 1624 t0 = tcg_temp_new(); 1625 } 1626 1627 if (compute_ca) { 1628 if (NARROW_MODE(ctx)) { 1629 /* 1630 * Caution: a non-obvious corner case of the spec is that 1631 * we must produce the *entire* 64-bit addition, but 1632 * produce the carry into bit 32. 1633 */ 1634 TCGv t1 = tcg_temp_new(); 1635 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1636 tcg_gen_add_tl(t0, arg1, arg2); 1637 if (add_ca) { 1638 tcg_gen_add_tl(t0, t0, ca); 1639 } 1640 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1641 tcg_gen_extract_tl(ca, ca, 32, 1); 1642 if (is_isa300(ctx)) { 1643 tcg_gen_mov_tl(ca32, ca); 1644 } 1645 } else { 1646 TCGv zero = tcg_constant_tl(0); 1647 if (add_ca) { 1648 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1649 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1650 } else { 1651 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1652 } 1653 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1654 } 1655 } else { 1656 tcg_gen_add_tl(t0, arg1, arg2); 1657 if (add_ca) { 1658 tcg_gen_add_tl(t0, t0, ca); 1659 } 1660 } 1661 1662 if (compute_ov) { 1663 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1664 } 1665 if (unlikely(compute_rc0)) { 1666 gen_set_Rc0(ctx, t0); 1667 } 1668 1669 if (t0 != ret) { 1670 tcg_gen_mov_tl(ret, t0); 1671 } 1672 } 1673 /* Add functions with two operands */ 1674 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1675 static void glue(gen_, name)(DisasContext *ctx) \ 1676 { \ 1677 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1678 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1679 ca, glue(ca, 32), \ 1680 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1681 } 1682 /* Add functions with one operand and one immediate */ 1683 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1684 add_ca, compute_ca, compute_ov) \ 1685 static void glue(gen_, name)(DisasContext *ctx) \ 1686 { \ 1687 TCGv t0 = tcg_constant_tl(const_val); \ 1688 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1689 cpu_gpr[rA(ctx->opcode)], t0, \ 1690 ca, glue(ca, 32), \ 1691 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1692 } 1693 1694 /* add add. addo addo. */ 1695 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1696 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1697 /* addc addc. addco addco. */ 1698 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1699 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1700 /* adde adde. addeo addeo. */ 1701 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1702 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1703 /* addme addme. addmeo addmeo. */ 1704 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1705 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1706 /* addex */ 1707 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1708 /* addze addze. addzeo addzeo.*/ 1709 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1710 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1711 /* addic addic.*/ 1712 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1713 { 1714 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1715 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1716 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1717 } 1718 1719 static void gen_addic(DisasContext *ctx) 1720 { 1721 gen_op_addic(ctx, 0); 1722 } 1723 1724 static void gen_addic_(DisasContext *ctx) 1725 { 1726 gen_op_addic(ctx, 1); 1727 } 1728 1729 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1730 TCGv arg2, int sign, int compute_ov) 1731 { 1732 TCGv_i32 t0 = tcg_temp_new_i32(); 1733 TCGv_i32 t1 = tcg_temp_new_i32(); 1734 TCGv_i32 t2 = tcg_temp_new_i32(); 1735 TCGv_i32 t3 = tcg_temp_new_i32(); 1736 1737 tcg_gen_trunc_tl_i32(t0, arg1); 1738 tcg_gen_trunc_tl_i32(t1, arg2); 1739 if (sign) { 1740 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1741 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1742 tcg_gen_and_i32(t2, t2, t3); 1743 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1744 tcg_gen_or_i32(t2, t2, t3); 1745 tcg_gen_movi_i32(t3, 0); 1746 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1747 tcg_gen_div_i32(t3, t0, t1); 1748 tcg_gen_extu_i32_tl(ret, t3); 1749 } else { 1750 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1751 tcg_gen_movi_i32(t3, 0); 1752 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1753 tcg_gen_divu_i32(t3, t0, t1); 1754 tcg_gen_extu_i32_tl(ret, t3); 1755 } 1756 if (compute_ov) { 1757 tcg_gen_extu_i32_tl(cpu_ov, t2); 1758 if (is_isa300(ctx)) { 1759 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1760 } 1761 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1762 } 1763 1764 if (unlikely(Rc(ctx->opcode) != 0)) { 1765 gen_set_Rc0(ctx, ret); 1766 } 1767 } 1768 /* Div functions */ 1769 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1770 static void glue(gen_, name)(DisasContext *ctx) \ 1771 { \ 1772 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1773 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1774 sign, compute_ov); \ 1775 } 1776 /* divwu divwu. divwuo divwuo. */ 1777 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1778 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1779 /* divw divw. divwo divwo. */ 1780 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1781 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1782 1783 /* div[wd]eu[o][.] */ 1784 #define GEN_DIVE(name, hlpr, compute_ov) \ 1785 static void gen_##name(DisasContext *ctx) \ 1786 { \ 1787 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1788 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1789 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1790 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1791 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1792 } \ 1793 } 1794 1795 GEN_DIVE(divweu, divweu, 0); 1796 GEN_DIVE(divweuo, divweu, 1); 1797 GEN_DIVE(divwe, divwe, 0); 1798 GEN_DIVE(divweo, divwe, 1); 1799 1800 #if defined(TARGET_PPC64) 1801 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1802 TCGv arg2, int sign, int compute_ov) 1803 { 1804 TCGv_i64 t0 = tcg_temp_new_i64(); 1805 TCGv_i64 t1 = tcg_temp_new_i64(); 1806 TCGv_i64 t2 = tcg_temp_new_i64(); 1807 TCGv_i64 t3 = tcg_temp_new_i64(); 1808 1809 tcg_gen_mov_i64(t0, arg1); 1810 tcg_gen_mov_i64(t1, arg2); 1811 if (sign) { 1812 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1813 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1814 tcg_gen_and_i64(t2, t2, t3); 1815 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1816 tcg_gen_or_i64(t2, t2, t3); 1817 tcg_gen_movi_i64(t3, 0); 1818 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1819 tcg_gen_div_i64(ret, t0, t1); 1820 } else { 1821 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1822 tcg_gen_movi_i64(t3, 0); 1823 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1824 tcg_gen_divu_i64(ret, t0, t1); 1825 } 1826 if (compute_ov) { 1827 tcg_gen_mov_tl(cpu_ov, t2); 1828 if (is_isa300(ctx)) { 1829 tcg_gen_mov_tl(cpu_ov32, t2); 1830 } 1831 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1832 } 1833 1834 if (unlikely(Rc(ctx->opcode) != 0)) { 1835 gen_set_Rc0(ctx, ret); 1836 } 1837 } 1838 1839 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1840 static void glue(gen_, name)(DisasContext *ctx) \ 1841 { \ 1842 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1843 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1844 sign, compute_ov); \ 1845 } 1846 /* divdu divdu. divduo divduo. */ 1847 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1848 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1849 /* divd divd. divdo divdo. */ 1850 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1851 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1852 1853 GEN_DIVE(divdeu, divdeu, 0); 1854 GEN_DIVE(divdeuo, divdeu, 1); 1855 GEN_DIVE(divde, divde, 0); 1856 GEN_DIVE(divdeo, divde, 1); 1857 #endif 1858 1859 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1860 TCGv arg2, int sign) 1861 { 1862 TCGv_i32 t0 = tcg_temp_new_i32(); 1863 TCGv_i32 t1 = tcg_temp_new_i32(); 1864 1865 tcg_gen_trunc_tl_i32(t0, arg1); 1866 tcg_gen_trunc_tl_i32(t1, arg2); 1867 if (sign) { 1868 TCGv_i32 t2 = tcg_temp_new_i32(); 1869 TCGv_i32 t3 = tcg_temp_new_i32(); 1870 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1871 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1872 tcg_gen_and_i32(t2, t2, t3); 1873 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1874 tcg_gen_or_i32(t2, t2, t3); 1875 tcg_gen_movi_i32(t3, 0); 1876 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1877 tcg_gen_rem_i32(t3, t0, t1); 1878 tcg_gen_ext_i32_tl(ret, t3); 1879 } else { 1880 TCGv_i32 t2 = tcg_constant_i32(1); 1881 TCGv_i32 t3 = tcg_constant_i32(0); 1882 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1883 tcg_gen_remu_i32(t0, t0, t1); 1884 tcg_gen_extu_i32_tl(ret, t0); 1885 } 1886 } 1887 1888 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1889 static void glue(gen_, name)(DisasContext *ctx) \ 1890 { \ 1891 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1892 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1893 sign); \ 1894 } 1895 1896 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1897 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1898 1899 #if defined(TARGET_PPC64) 1900 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1901 TCGv arg2, int sign) 1902 { 1903 TCGv_i64 t0 = tcg_temp_new_i64(); 1904 TCGv_i64 t1 = tcg_temp_new_i64(); 1905 1906 tcg_gen_mov_i64(t0, arg1); 1907 tcg_gen_mov_i64(t1, arg2); 1908 if (sign) { 1909 TCGv_i64 t2 = tcg_temp_new_i64(); 1910 TCGv_i64 t3 = tcg_temp_new_i64(); 1911 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1912 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1913 tcg_gen_and_i64(t2, t2, t3); 1914 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1915 tcg_gen_or_i64(t2, t2, t3); 1916 tcg_gen_movi_i64(t3, 0); 1917 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1918 tcg_gen_rem_i64(ret, t0, t1); 1919 } else { 1920 TCGv_i64 t2 = tcg_constant_i64(1); 1921 TCGv_i64 t3 = tcg_constant_i64(0); 1922 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1923 tcg_gen_remu_i64(ret, t0, t1); 1924 } 1925 } 1926 1927 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1928 static void glue(gen_, name)(DisasContext *ctx) \ 1929 { \ 1930 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1931 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1932 sign); \ 1933 } 1934 1935 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1936 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1937 #endif 1938 1939 /* mulhw mulhw. */ 1940 static void gen_mulhw(DisasContext *ctx) 1941 { 1942 TCGv_i32 t0 = tcg_temp_new_i32(); 1943 TCGv_i32 t1 = tcg_temp_new_i32(); 1944 1945 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1946 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1947 tcg_gen_muls2_i32(t0, t1, t0, t1); 1948 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1949 if (unlikely(Rc(ctx->opcode) != 0)) { 1950 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1951 } 1952 } 1953 1954 /* mulhwu mulhwu. */ 1955 static void gen_mulhwu(DisasContext *ctx) 1956 { 1957 TCGv_i32 t0 = tcg_temp_new_i32(); 1958 TCGv_i32 t1 = tcg_temp_new_i32(); 1959 1960 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1961 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1962 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1963 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1964 if (unlikely(Rc(ctx->opcode) != 0)) { 1965 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1966 } 1967 } 1968 1969 /* mullw mullw. */ 1970 static void gen_mullw(DisasContext *ctx) 1971 { 1972 #if defined(TARGET_PPC64) 1973 TCGv_i64 t0, t1; 1974 t0 = tcg_temp_new_i64(); 1975 t1 = tcg_temp_new_i64(); 1976 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1977 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1978 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1979 #else 1980 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1981 cpu_gpr[rB(ctx->opcode)]); 1982 #endif 1983 if (unlikely(Rc(ctx->opcode) != 0)) { 1984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1985 } 1986 } 1987 1988 /* mullwo mullwo. */ 1989 static void gen_mullwo(DisasContext *ctx) 1990 { 1991 TCGv_i32 t0 = tcg_temp_new_i32(); 1992 TCGv_i32 t1 = tcg_temp_new_i32(); 1993 1994 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1995 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1996 tcg_gen_muls2_i32(t0, t1, t0, t1); 1997 #if defined(TARGET_PPC64) 1998 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1999 #else 2000 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2001 #endif 2002 2003 tcg_gen_sari_i32(t0, t0, 31); 2004 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2005 tcg_gen_extu_i32_tl(cpu_ov, t0); 2006 if (is_isa300(ctx)) { 2007 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2008 } 2009 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2010 2011 if (unlikely(Rc(ctx->opcode) != 0)) { 2012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2013 } 2014 } 2015 2016 /* mulli */ 2017 static void gen_mulli(DisasContext *ctx) 2018 { 2019 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2020 SIMM(ctx->opcode)); 2021 } 2022 2023 #if defined(TARGET_PPC64) 2024 /* mulhd mulhd. */ 2025 static void gen_mulhd(DisasContext *ctx) 2026 { 2027 TCGv lo = tcg_temp_new(); 2028 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2030 if (unlikely(Rc(ctx->opcode) != 0)) { 2031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2032 } 2033 } 2034 2035 /* mulhdu mulhdu. */ 2036 static void gen_mulhdu(DisasContext *ctx) 2037 { 2038 TCGv lo = tcg_temp_new(); 2039 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2040 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2041 if (unlikely(Rc(ctx->opcode) != 0)) { 2042 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2043 } 2044 } 2045 2046 /* mulld mulld. */ 2047 static void gen_mulld(DisasContext *ctx) 2048 { 2049 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2050 cpu_gpr[rB(ctx->opcode)]); 2051 if (unlikely(Rc(ctx->opcode) != 0)) { 2052 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2053 } 2054 } 2055 2056 /* mulldo mulldo. */ 2057 static void gen_mulldo(DisasContext *ctx) 2058 { 2059 TCGv_i64 t0 = tcg_temp_new_i64(); 2060 TCGv_i64 t1 = tcg_temp_new_i64(); 2061 2062 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2063 cpu_gpr[rB(ctx->opcode)]); 2064 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2065 2066 tcg_gen_sari_i64(t0, t0, 63); 2067 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2068 if (is_isa300(ctx)) { 2069 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2070 } 2071 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2072 2073 if (unlikely(Rc(ctx->opcode) != 0)) { 2074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2075 } 2076 } 2077 #endif 2078 2079 /* Common subf function */ 2080 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2081 TCGv arg2, bool add_ca, bool compute_ca, 2082 bool compute_ov, bool compute_rc0) 2083 { 2084 TCGv t0 = ret; 2085 2086 if (compute_ca || compute_ov) { 2087 t0 = tcg_temp_new(); 2088 } 2089 2090 if (compute_ca) { 2091 /* dest = ~arg1 + arg2 [+ ca]. */ 2092 if (NARROW_MODE(ctx)) { 2093 /* 2094 * Caution: a non-obvious corner case of the spec is that 2095 * we must produce the *entire* 64-bit addition, but 2096 * produce the carry into bit 32. 2097 */ 2098 TCGv inv1 = tcg_temp_new(); 2099 TCGv t1 = tcg_temp_new(); 2100 tcg_gen_not_tl(inv1, arg1); 2101 if (add_ca) { 2102 tcg_gen_add_tl(t0, arg2, cpu_ca); 2103 } else { 2104 tcg_gen_addi_tl(t0, arg2, 1); 2105 } 2106 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2107 tcg_gen_add_tl(t0, t0, inv1); 2108 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2109 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2110 if (is_isa300(ctx)) { 2111 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2112 } 2113 } else if (add_ca) { 2114 TCGv zero, inv1 = tcg_temp_new(); 2115 tcg_gen_not_tl(inv1, arg1); 2116 zero = tcg_constant_tl(0); 2117 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2118 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2119 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2120 } else { 2121 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2122 tcg_gen_sub_tl(t0, arg2, arg1); 2123 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2124 } 2125 } else if (add_ca) { 2126 /* 2127 * Since we're ignoring carry-out, we can simplify the 2128 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2129 */ 2130 tcg_gen_sub_tl(t0, arg2, arg1); 2131 tcg_gen_add_tl(t0, t0, cpu_ca); 2132 tcg_gen_subi_tl(t0, t0, 1); 2133 } else { 2134 tcg_gen_sub_tl(t0, arg2, arg1); 2135 } 2136 2137 if (compute_ov) { 2138 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2139 } 2140 if (unlikely(compute_rc0)) { 2141 gen_set_Rc0(ctx, t0); 2142 } 2143 2144 if (t0 != ret) { 2145 tcg_gen_mov_tl(ret, t0); 2146 } 2147 } 2148 /* Sub functions with Two operands functions */ 2149 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2150 static void glue(gen_, name)(DisasContext *ctx) \ 2151 { \ 2152 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2153 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2154 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2155 } 2156 /* Sub functions with one operand and one immediate */ 2157 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2158 add_ca, compute_ca, compute_ov) \ 2159 static void glue(gen_, name)(DisasContext *ctx) \ 2160 { \ 2161 TCGv t0 = tcg_constant_tl(const_val); \ 2162 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2163 cpu_gpr[rA(ctx->opcode)], t0, \ 2164 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2165 } 2166 /* subf subf. subfo subfo. */ 2167 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2168 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2169 /* subfc subfc. subfco subfco. */ 2170 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2171 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2172 /* subfe subfe. subfeo subfo. */ 2173 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2174 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2175 /* subfme subfme. subfmeo subfmeo. */ 2176 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2177 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2178 /* subfze subfze. subfzeo subfzeo.*/ 2179 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2180 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2181 2182 /* subfic */ 2183 static void gen_subfic(DisasContext *ctx) 2184 { 2185 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2186 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2187 c, 0, 1, 0, 0); 2188 } 2189 2190 /* neg neg. nego nego. */ 2191 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2192 { 2193 TCGv zero = tcg_constant_tl(0); 2194 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2195 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2196 } 2197 2198 static void gen_neg(DisasContext *ctx) 2199 { 2200 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2201 if (unlikely(Rc(ctx->opcode))) { 2202 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2203 } 2204 } 2205 2206 static void gen_nego(DisasContext *ctx) 2207 { 2208 gen_op_arith_neg(ctx, 1); 2209 } 2210 2211 /*** Integer logical ***/ 2212 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2213 static void glue(gen_, name)(DisasContext *ctx) \ 2214 { \ 2215 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2216 cpu_gpr[rB(ctx->opcode)]); \ 2217 if (unlikely(Rc(ctx->opcode) != 0)) \ 2218 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2219 } 2220 2221 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2222 static void glue(gen_, name)(DisasContext *ctx) \ 2223 { \ 2224 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2225 if (unlikely(Rc(ctx->opcode) != 0)) \ 2226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2227 } 2228 2229 /* and & and. */ 2230 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2231 /* andc & andc. */ 2232 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2233 2234 /* andi. */ 2235 static void gen_andi_(DisasContext *ctx) 2236 { 2237 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2238 UIMM(ctx->opcode)); 2239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2240 } 2241 2242 /* andis. */ 2243 static void gen_andis_(DisasContext *ctx) 2244 { 2245 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2246 UIMM(ctx->opcode) << 16); 2247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2248 } 2249 2250 /* cntlzw */ 2251 static void gen_cntlzw(DisasContext *ctx) 2252 { 2253 TCGv_i32 t = tcg_temp_new_i32(); 2254 2255 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2256 tcg_gen_clzi_i32(t, t, 32); 2257 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2258 2259 if (unlikely(Rc(ctx->opcode) != 0)) { 2260 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2261 } 2262 } 2263 2264 /* cnttzw */ 2265 static void gen_cnttzw(DisasContext *ctx) 2266 { 2267 TCGv_i32 t = tcg_temp_new_i32(); 2268 2269 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2270 tcg_gen_ctzi_i32(t, t, 32); 2271 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2272 2273 if (unlikely(Rc(ctx->opcode) != 0)) { 2274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2275 } 2276 } 2277 2278 /* eqv & eqv. */ 2279 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2280 /* extsb & extsb. */ 2281 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2282 /* extsh & extsh. */ 2283 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2284 /* nand & nand. */ 2285 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2286 /* nor & nor. */ 2287 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2288 2289 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2290 static void gen_pause(DisasContext *ctx) 2291 { 2292 TCGv_i32 t0 = tcg_constant_i32(0); 2293 tcg_gen_st_i32(t0, cpu_env, 2294 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2295 2296 /* Stop translation, this gives other CPUs a chance to run */ 2297 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2298 } 2299 #endif /* defined(TARGET_PPC64) */ 2300 2301 /* or & or. */ 2302 static void gen_or(DisasContext *ctx) 2303 { 2304 int rs, ra, rb; 2305 2306 rs = rS(ctx->opcode); 2307 ra = rA(ctx->opcode); 2308 rb = rB(ctx->opcode); 2309 /* Optimisation for mr. ri case */ 2310 if (rs != ra || rs != rb) { 2311 if (rs != rb) { 2312 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2313 } else { 2314 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2315 } 2316 if (unlikely(Rc(ctx->opcode) != 0)) { 2317 gen_set_Rc0(ctx, cpu_gpr[ra]); 2318 } 2319 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2320 gen_set_Rc0(ctx, cpu_gpr[rs]); 2321 #if defined(TARGET_PPC64) 2322 } else if (rs != 0) { /* 0 is nop */ 2323 int prio = 0; 2324 2325 switch (rs) { 2326 case 1: 2327 /* Set process priority to low */ 2328 prio = 2; 2329 break; 2330 case 6: 2331 /* Set process priority to medium-low */ 2332 prio = 3; 2333 break; 2334 case 2: 2335 /* Set process priority to normal */ 2336 prio = 4; 2337 break; 2338 #if !defined(CONFIG_USER_ONLY) 2339 case 31: 2340 if (!ctx->pr) { 2341 /* Set process priority to very low */ 2342 prio = 1; 2343 } 2344 break; 2345 case 5: 2346 if (!ctx->pr) { 2347 /* Set process priority to medium-hight */ 2348 prio = 5; 2349 } 2350 break; 2351 case 3: 2352 if (!ctx->pr) { 2353 /* Set process priority to high */ 2354 prio = 6; 2355 } 2356 break; 2357 case 7: 2358 if (ctx->hv && !ctx->pr) { 2359 /* Set process priority to very high */ 2360 prio = 7; 2361 } 2362 break; 2363 #endif 2364 default: 2365 break; 2366 } 2367 if (prio) { 2368 TCGv t0 = tcg_temp_new(); 2369 gen_load_spr(t0, SPR_PPR); 2370 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2371 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2372 gen_store_spr(SPR_PPR, t0); 2373 } 2374 #if !defined(CONFIG_USER_ONLY) 2375 /* 2376 * Pause out of TCG otherwise spin loops with smt_low eat too 2377 * much CPU and the kernel hangs. This applies to all 2378 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2379 * mdoio(29), mdoom(30), and all currently undefined. 2380 */ 2381 gen_pause(ctx); 2382 #endif 2383 #endif 2384 } 2385 } 2386 /* orc & orc. */ 2387 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2388 2389 /* xor & xor. */ 2390 static void gen_xor(DisasContext *ctx) 2391 { 2392 /* Optimisation for "set to zero" case */ 2393 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2394 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2395 cpu_gpr[rB(ctx->opcode)]); 2396 } else { 2397 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2398 } 2399 if (unlikely(Rc(ctx->opcode) != 0)) { 2400 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2401 } 2402 } 2403 2404 /* ori */ 2405 static void gen_ori(DisasContext *ctx) 2406 { 2407 target_ulong uimm = UIMM(ctx->opcode); 2408 2409 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2410 return; 2411 } 2412 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2413 } 2414 2415 /* oris */ 2416 static void gen_oris(DisasContext *ctx) 2417 { 2418 target_ulong uimm = UIMM(ctx->opcode); 2419 2420 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2421 /* NOP */ 2422 return; 2423 } 2424 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2425 uimm << 16); 2426 } 2427 2428 /* xori */ 2429 static void gen_xori(DisasContext *ctx) 2430 { 2431 target_ulong uimm = UIMM(ctx->opcode); 2432 2433 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2434 /* NOP */ 2435 return; 2436 } 2437 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2438 } 2439 2440 /* xoris */ 2441 static void gen_xoris(DisasContext *ctx) 2442 { 2443 target_ulong uimm = UIMM(ctx->opcode); 2444 2445 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2446 /* NOP */ 2447 return; 2448 } 2449 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2450 uimm << 16); 2451 } 2452 2453 /* popcntb : PowerPC 2.03 specification */ 2454 static void gen_popcntb(DisasContext *ctx) 2455 { 2456 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2457 } 2458 2459 static void gen_popcntw(DisasContext *ctx) 2460 { 2461 #if defined(TARGET_PPC64) 2462 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2463 #else 2464 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2465 #endif 2466 } 2467 2468 #if defined(TARGET_PPC64) 2469 /* popcntd: PowerPC 2.06 specification */ 2470 static void gen_popcntd(DisasContext *ctx) 2471 { 2472 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2473 } 2474 #endif 2475 2476 /* prtyw: PowerPC 2.05 specification */ 2477 static void gen_prtyw(DisasContext *ctx) 2478 { 2479 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2480 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2481 TCGv t0 = tcg_temp_new(); 2482 tcg_gen_shri_tl(t0, rs, 16); 2483 tcg_gen_xor_tl(ra, rs, t0); 2484 tcg_gen_shri_tl(t0, ra, 8); 2485 tcg_gen_xor_tl(ra, ra, t0); 2486 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2487 } 2488 2489 #if defined(TARGET_PPC64) 2490 /* prtyd: PowerPC 2.05 specification */ 2491 static void gen_prtyd(DisasContext *ctx) 2492 { 2493 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2494 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2495 TCGv t0 = tcg_temp_new(); 2496 tcg_gen_shri_tl(t0, rs, 32); 2497 tcg_gen_xor_tl(ra, rs, t0); 2498 tcg_gen_shri_tl(t0, ra, 16); 2499 tcg_gen_xor_tl(ra, ra, t0); 2500 tcg_gen_shri_tl(t0, ra, 8); 2501 tcg_gen_xor_tl(ra, ra, t0); 2502 tcg_gen_andi_tl(ra, ra, 1); 2503 } 2504 #endif 2505 2506 #if defined(TARGET_PPC64) 2507 /* bpermd */ 2508 static void gen_bpermd(DisasContext *ctx) 2509 { 2510 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2511 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2512 } 2513 #endif 2514 2515 #if defined(TARGET_PPC64) 2516 /* extsw & extsw. */ 2517 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2518 2519 /* cntlzd */ 2520 static void gen_cntlzd(DisasContext *ctx) 2521 { 2522 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2523 if (unlikely(Rc(ctx->opcode) != 0)) { 2524 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2525 } 2526 } 2527 2528 /* cnttzd */ 2529 static void gen_cnttzd(DisasContext *ctx) 2530 { 2531 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2532 if (unlikely(Rc(ctx->opcode) != 0)) { 2533 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2534 } 2535 } 2536 2537 /* darn */ 2538 static void gen_darn(DisasContext *ctx) 2539 { 2540 int l = L(ctx->opcode); 2541 2542 if (l > 2) { 2543 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2544 } else { 2545 translator_io_start(&ctx->base); 2546 if (l == 0) { 2547 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2548 } else { 2549 /* Return 64-bit random for both CRN and RRN */ 2550 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2551 } 2552 } 2553 } 2554 #endif 2555 2556 /*** Integer rotate ***/ 2557 2558 /* rlwimi & rlwimi. */ 2559 static void gen_rlwimi(DisasContext *ctx) 2560 { 2561 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2562 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2563 uint32_t sh = SH(ctx->opcode); 2564 uint32_t mb = MB(ctx->opcode); 2565 uint32_t me = ME(ctx->opcode); 2566 2567 if (sh == (31 - me) && mb <= me) { 2568 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2569 } else { 2570 target_ulong mask; 2571 bool mask_in_32b = true; 2572 TCGv t1; 2573 2574 #if defined(TARGET_PPC64) 2575 mb += 32; 2576 me += 32; 2577 #endif 2578 mask = MASK(mb, me); 2579 2580 #if defined(TARGET_PPC64) 2581 if (mask > 0xffffffffu) { 2582 mask_in_32b = false; 2583 } 2584 #endif 2585 t1 = tcg_temp_new(); 2586 if (mask_in_32b) { 2587 TCGv_i32 t0 = tcg_temp_new_i32(); 2588 tcg_gen_trunc_tl_i32(t0, t_rs); 2589 tcg_gen_rotli_i32(t0, t0, sh); 2590 tcg_gen_extu_i32_tl(t1, t0); 2591 } else { 2592 #if defined(TARGET_PPC64) 2593 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2594 tcg_gen_rotli_i64(t1, t1, sh); 2595 #else 2596 g_assert_not_reached(); 2597 #endif 2598 } 2599 2600 tcg_gen_andi_tl(t1, t1, mask); 2601 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2602 tcg_gen_or_tl(t_ra, t_ra, t1); 2603 } 2604 if (unlikely(Rc(ctx->opcode) != 0)) { 2605 gen_set_Rc0(ctx, t_ra); 2606 } 2607 } 2608 2609 /* rlwinm & rlwinm. */ 2610 static void gen_rlwinm(DisasContext *ctx) 2611 { 2612 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2613 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2614 int sh = SH(ctx->opcode); 2615 int mb = MB(ctx->opcode); 2616 int me = ME(ctx->opcode); 2617 int len = me - mb + 1; 2618 int rsh = (32 - sh) & 31; 2619 2620 if (sh != 0 && len > 0 && me == (31 - sh)) { 2621 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2622 } else if (me == 31 && rsh + len <= 32) { 2623 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2624 } else { 2625 target_ulong mask; 2626 bool mask_in_32b = true; 2627 #if defined(TARGET_PPC64) 2628 mb += 32; 2629 me += 32; 2630 #endif 2631 mask = MASK(mb, me); 2632 #if defined(TARGET_PPC64) 2633 if (mask > 0xffffffffu) { 2634 mask_in_32b = false; 2635 } 2636 #endif 2637 if (mask_in_32b) { 2638 if (sh == 0) { 2639 tcg_gen_andi_tl(t_ra, t_rs, mask); 2640 } else { 2641 TCGv_i32 t0 = tcg_temp_new_i32(); 2642 tcg_gen_trunc_tl_i32(t0, t_rs); 2643 tcg_gen_rotli_i32(t0, t0, sh); 2644 tcg_gen_andi_i32(t0, t0, mask); 2645 tcg_gen_extu_i32_tl(t_ra, t0); 2646 } 2647 } else { 2648 #if defined(TARGET_PPC64) 2649 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2650 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2651 tcg_gen_andi_i64(t_ra, t_ra, mask); 2652 #else 2653 g_assert_not_reached(); 2654 #endif 2655 } 2656 } 2657 if (unlikely(Rc(ctx->opcode) != 0)) { 2658 gen_set_Rc0(ctx, t_ra); 2659 } 2660 } 2661 2662 /* rlwnm & rlwnm. */ 2663 static void gen_rlwnm(DisasContext *ctx) 2664 { 2665 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2666 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2667 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2668 uint32_t mb = MB(ctx->opcode); 2669 uint32_t me = ME(ctx->opcode); 2670 target_ulong mask; 2671 bool mask_in_32b = true; 2672 2673 #if defined(TARGET_PPC64) 2674 mb += 32; 2675 me += 32; 2676 #endif 2677 mask = MASK(mb, me); 2678 2679 #if defined(TARGET_PPC64) 2680 if (mask > 0xffffffffu) { 2681 mask_in_32b = false; 2682 } 2683 #endif 2684 if (mask_in_32b) { 2685 TCGv_i32 t0 = tcg_temp_new_i32(); 2686 TCGv_i32 t1 = tcg_temp_new_i32(); 2687 tcg_gen_trunc_tl_i32(t0, t_rb); 2688 tcg_gen_trunc_tl_i32(t1, t_rs); 2689 tcg_gen_andi_i32(t0, t0, 0x1f); 2690 tcg_gen_rotl_i32(t1, t1, t0); 2691 tcg_gen_extu_i32_tl(t_ra, t1); 2692 } else { 2693 #if defined(TARGET_PPC64) 2694 TCGv_i64 t0 = tcg_temp_new_i64(); 2695 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2696 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2697 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2698 #else 2699 g_assert_not_reached(); 2700 #endif 2701 } 2702 2703 tcg_gen_andi_tl(t_ra, t_ra, mask); 2704 2705 if (unlikely(Rc(ctx->opcode) != 0)) { 2706 gen_set_Rc0(ctx, t_ra); 2707 } 2708 } 2709 2710 #if defined(TARGET_PPC64) 2711 #define GEN_PPC64_R2(name, opc1, opc2) \ 2712 static void glue(gen_, name##0)(DisasContext *ctx) \ 2713 { \ 2714 gen_##name(ctx, 0); \ 2715 } \ 2716 \ 2717 static void glue(gen_, name##1)(DisasContext *ctx) \ 2718 { \ 2719 gen_##name(ctx, 1); \ 2720 } 2721 #define GEN_PPC64_R4(name, opc1, opc2) \ 2722 static void glue(gen_, name##0)(DisasContext *ctx) \ 2723 { \ 2724 gen_##name(ctx, 0, 0); \ 2725 } \ 2726 \ 2727 static void glue(gen_, name##1)(DisasContext *ctx) \ 2728 { \ 2729 gen_##name(ctx, 0, 1); \ 2730 } \ 2731 \ 2732 static void glue(gen_, name##2)(DisasContext *ctx) \ 2733 { \ 2734 gen_##name(ctx, 1, 0); \ 2735 } \ 2736 \ 2737 static void glue(gen_, name##3)(DisasContext *ctx) \ 2738 { \ 2739 gen_##name(ctx, 1, 1); \ 2740 } 2741 2742 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2743 { 2744 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2745 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2746 int len = me - mb + 1; 2747 int rsh = (64 - sh) & 63; 2748 2749 if (sh != 0 && len > 0 && me == (63 - sh)) { 2750 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2751 } else if (me == 63 && rsh + len <= 64) { 2752 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2753 } else { 2754 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2755 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2756 } 2757 if (unlikely(Rc(ctx->opcode) != 0)) { 2758 gen_set_Rc0(ctx, t_ra); 2759 } 2760 } 2761 2762 /* rldicl - rldicl. */ 2763 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2764 { 2765 uint32_t sh, mb; 2766 2767 sh = SH(ctx->opcode) | (shn << 5); 2768 mb = MB(ctx->opcode) | (mbn << 5); 2769 gen_rldinm(ctx, mb, 63, sh); 2770 } 2771 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2772 2773 /* rldicr - rldicr. */ 2774 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2775 { 2776 uint32_t sh, me; 2777 2778 sh = SH(ctx->opcode) | (shn << 5); 2779 me = MB(ctx->opcode) | (men << 5); 2780 gen_rldinm(ctx, 0, me, sh); 2781 } 2782 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2783 2784 /* rldic - rldic. */ 2785 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2786 { 2787 uint32_t sh, mb; 2788 2789 sh = SH(ctx->opcode) | (shn << 5); 2790 mb = MB(ctx->opcode) | (mbn << 5); 2791 gen_rldinm(ctx, mb, 63 - sh, sh); 2792 } 2793 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2794 2795 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2796 { 2797 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2798 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2799 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2800 TCGv t0; 2801 2802 t0 = tcg_temp_new(); 2803 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2804 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2805 2806 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2807 if (unlikely(Rc(ctx->opcode) != 0)) { 2808 gen_set_Rc0(ctx, t_ra); 2809 } 2810 } 2811 2812 /* rldcl - rldcl. */ 2813 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2814 { 2815 uint32_t mb; 2816 2817 mb = MB(ctx->opcode) | (mbn << 5); 2818 gen_rldnm(ctx, mb, 63); 2819 } 2820 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2821 2822 /* rldcr - rldcr. */ 2823 static inline void gen_rldcr(DisasContext *ctx, int men) 2824 { 2825 uint32_t me; 2826 2827 me = MB(ctx->opcode) | (men << 5); 2828 gen_rldnm(ctx, 0, me); 2829 } 2830 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2831 2832 /* rldimi - rldimi. */ 2833 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2834 { 2835 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2836 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2837 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2838 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2839 uint32_t me = 63 - sh; 2840 2841 if (mb <= me) { 2842 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2843 } else { 2844 target_ulong mask = MASK(mb, me); 2845 TCGv t1 = tcg_temp_new(); 2846 2847 tcg_gen_rotli_tl(t1, t_rs, sh); 2848 tcg_gen_andi_tl(t1, t1, mask); 2849 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2850 tcg_gen_or_tl(t_ra, t_ra, t1); 2851 } 2852 if (unlikely(Rc(ctx->opcode) != 0)) { 2853 gen_set_Rc0(ctx, t_ra); 2854 } 2855 } 2856 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2857 #endif 2858 2859 /*** Integer shift ***/ 2860 2861 /* slw & slw. */ 2862 static void gen_slw(DisasContext *ctx) 2863 { 2864 TCGv t0, t1; 2865 2866 t0 = tcg_temp_new(); 2867 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2868 #if defined(TARGET_PPC64) 2869 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2870 tcg_gen_sari_tl(t0, t0, 0x3f); 2871 #else 2872 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2873 tcg_gen_sari_tl(t0, t0, 0x1f); 2874 #endif 2875 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2876 t1 = tcg_temp_new(); 2877 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2878 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2879 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2880 if (unlikely(Rc(ctx->opcode) != 0)) { 2881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2882 } 2883 } 2884 2885 /* sraw & sraw. */ 2886 static void gen_sraw(DisasContext *ctx) 2887 { 2888 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2889 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2890 if (unlikely(Rc(ctx->opcode) != 0)) { 2891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2892 } 2893 } 2894 2895 /* srawi & srawi. */ 2896 static void gen_srawi(DisasContext *ctx) 2897 { 2898 int sh = SH(ctx->opcode); 2899 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2900 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2901 if (sh == 0) { 2902 tcg_gen_ext32s_tl(dst, src); 2903 tcg_gen_movi_tl(cpu_ca, 0); 2904 if (is_isa300(ctx)) { 2905 tcg_gen_movi_tl(cpu_ca32, 0); 2906 } 2907 } else { 2908 TCGv t0; 2909 tcg_gen_ext32s_tl(dst, src); 2910 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2911 t0 = tcg_temp_new(); 2912 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2913 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2914 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2915 if (is_isa300(ctx)) { 2916 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2917 } 2918 tcg_gen_sari_tl(dst, dst, sh); 2919 } 2920 if (unlikely(Rc(ctx->opcode) != 0)) { 2921 gen_set_Rc0(ctx, dst); 2922 } 2923 } 2924 2925 /* srw & srw. */ 2926 static void gen_srw(DisasContext *ctx) 2927 { 2928 TCGv t0, t1; 2929 2930 t0 = tcg_temp_new(); 2931 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2932 #if defined(TARGET_PPC64) 2933 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2934 tcg_gen_sari_tl(t0, t0, 0x3f); 2935 #else 2936 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2937 tcg_gen_sari_tl(t0, t0, 0x1f); 2938 #endif 2939 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2940 tcg_gen_ext32u_tl(t0, t0); 2941 t1 = tcg_temp_new(); 2942 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2943 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2944 if (unlikely(Rc(ctx->opcode) != 0)) { 2945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2946 } 2947 } 2948 2949 #if defined(TARGET_PPC64) 2950 /* sld & sld. */ 2951 static void gen_sld(DisasContext *ctx) 2952 { 2953 TCGv t0, t1; 2954 2955 t0 = tcg_temp_new(); 2956 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2957 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2958 tcg_gen_sari_tl(t0, t0, 0x3f); 2959 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2960 t1 = tcg_temp_new(); 2961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2962 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2963 if (unlikely(Rc(ctx->opcode) != 0)) { 2964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2965 } 2966 } 2967 2968 /* srad & srad. */ 2969 static void gen_srad(DisasContext *ctx) 2970 { 2971 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2972 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2973 if (unlikely(Rc(ctx->opcode) != 0)) { 2974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2975 } 2976 } 2977 /* sradi & sradi. */ 2978 static inline void gen_sradi(DisasContext *ctx, int n) 2979 { 2980 int sh = SH(ctx->opcode) + (n << 5); 2981 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2982 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2983 if (sh == 0) { 2984 tcg_gen_mov_tl(dst, src); 2985 tcg_gen_movi_tl(cpu_ca, 0); 2986 if (is_isa300(ctx)) { 2987 tcg_gen_movi_tl(cpu_ca32, 0); 2988 } 2989 } else { 2990 TCGv t0; 2991 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2992 t0 = tcg_temp_new(); 2993 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2994 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2995 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2996 if (is_isa300(ctx)) { 2997 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2998 } 2999 tcg_gen_sari_tl(dst, src, sh); 3000 } 3001 if (unlikely(Rc(ctx->opcode) != 0)) { 3002 gen_set_Rc0(ctx, dst); 3003 } 3004 } 3005 3006 static void gen_sradi0(DisasContext *ctx) 3007 { 3008 gen_sradi(ctx, 0); 3009 } 3010 3011 static void gen_sradi1(DisasContext *ctx) 3012 { 3013 gen_sradi(ctx, 1); 3014 } 3015 3016 /* extswsli & extswsli. */ 3017 static inline void gen_extswsli(DisasContext *ctx, int n) 3018 { 3019 int sh = SH(ctx->opcode) + (n << 5); 3020 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3021 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3022 3023 tcg_gen_ext32s_tl(dst, src); 3024 tcg_gen_shli_tl(dst, dst, sh); 3025 if (unlikely(Rc(ctx->opcode) != 0)) { 3026 gen_set_Rc0(ctx, dst); 3027 } 3028 } 3029 3030 static void gen_extswsli0(DisasContext *ctx) 3031 { 3032 gen_extswsli(ctx, 0); 3033 } 3034 3035 static void gen_extswsli1(DisasContext *ctx) 3036 { 3037 gen_extswsli(ctx, 1); 3038 } 3039 3040 /* srd & srd. */ 3041 static void gen_srd(DisasContext *ctx) 3042 { 3043 TCGv t0, t1; 3044 3045 t0 = tcg_temp_new(); 3046 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3047 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3048 tcg_gen_sari_tl(t0, t0, 0x3f); 3049 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3050 t1 = tcg_temp_new(); 3051 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3052 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3053 if (unlikely(Rc(ctx->opcode) != 0)) { 3054 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3055 } 3056 } 3057 #endif 3058 3059 /*** Addressing modes ***/ 3060 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3061 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3062 target_long maskl) 3063 { 3064 target_long simm = SIMM(ctx->opcode); 3065 3066 simm &= ~maskl; 3067 if (rA(ctx->opcode) == 0) { 3068 if (NARROW_MODE(ctx)) { 3069 simm = (uint32_t)simm; 3070 } 3071 tcg_gen_movi_tl(EA, simm); 3072 } else if (likely(simm != 0)) { 3073 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3074 if (NARROW_MODE(ctx)) { 3075 tcg_gen_ext32u_tl(EA, EA); 3076 } 3077 } else { 3078 if (NARROW_MODE(ctx)) { 3079 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3080 } else { 3081 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3082 } 3083 } 3084 } 3085 3086 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3087 { 3088 if (rA(ctx->opcode) == 0) { 3089 if (NARROW_MODE(ctx)) { 3090 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3091 } else { 3092 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3093 } 3094 } else { 3095 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3096 if (NARROW_MODE(ctx)) { 3097 tcg_gen_ext32u_tl(EA, EA); 3098 } 3099 } 3100 } 3101 3102 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3103 { 3104 if (rA(ctx->opcode) == 0) { 3105 tcg_gen_movi_tl(EA, 0); 3106 } else if (NARROW_MODE(ctx)) { 3107 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3108 } else { 3109 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3110 } 3111 } 3112 3113 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3114 target_long val) 3115 { 3116 tcg_gen_addi_tl(ret, arg1, val); 3117 if (NARROW_MODE(ctx)) { 3118 tcg_gen_ext32u_tl(ret, ret); 3119 } 3120 } 3121 3122 static inline void gen_align_no_le(DisasContext *ctx) 3123 { 3124 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3125 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3126 } 3127 3128 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3129 { 3130 TCGv ea = tcg_temp_new(); 3131 if (ra) { 3132 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3133 } else { 3134 tcg_gen_mov_tl(ea, displ); 3135 } 3136 if (NARROW_MODE(ctx)) { 3137 tcg_gen_ext32u_tl(ea, ea); 3138 } 3139 return ea; 3140 } 3141 3142 /*** Integer load ***/ 3143 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3144 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3145 3146 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3147 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3148 TCGv val, \ 3149 TCGv addr) \ 3150 { \ 3151 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3152 } 3153 3154 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3155 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3156 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3157 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3158 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3159 3160 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3161 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3162 3163 #define GEN_QEMU_LOAD_64(ldop, op) \ 3164 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3165 TCGv_i64 val, \ 3166 TCGv addr) \ 3167 { \ 3168 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3169 } 3170 3171 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3172 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3173 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3174 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3175 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3176 3177 #if defined(TARGET_PPC64) 3178 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3179 #endif 3180 3181 #define GEN_QEMU_STORE_TL(stop, op) \ 3182 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3183 TCGv val, \ 3184 TCGv addr) \ 3185 { \ 3186 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3187 } 3188 3189 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3190 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3191 #endif 3192 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3193 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3194 3195 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3196 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3197 3198 #define GEN_QEMU_STORE_64(stop, op) \ 3199 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3200 TCGv_i64 val, \ 3201 TCGv addr) \ 3202 { \ 3203 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3204 } 3205 3206 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3207 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3208 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3209 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3210 3211 #if defined(TARGET_PPC64) 3212 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3213 #endif 3214 3215 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3216 static void glue(gen_, name##x)(DisasContext *ctx) \ 3217 { \ 3218 TCGv EA; \ 3219 chk(ctx); \ 3220 gen_set_access_type(ctx, ACCESS_INT); \ 3221 EA = tcg_temp_new(); \ 3222 gen_addr_reg_index(ctx, EA); \ 3223 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3224 } 3225 3226 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3227 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3228 3229 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3230 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3231 3232 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3233 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3234 { \ 3235 TCGv EA; \ 3236 CHK_SV(ctx); \ 3237 gen_set_access_type(ctx, ACCESS_INT); \ 3238 EA = tcg_temp_new(); \ 3239 gen_addr_reg_index(ctx, EA); \ 3240 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3241 } 3242 3243 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3244 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3245 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3246 #if defined(TARGET_PPC64) 3247 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3248 #endif 3249 3250 #if defined(TARGET_PPC64) 3251 /* CI load/store variants */ 3252 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3253 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3254 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3255 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3256 #endif 3257 3258 /*** Integer store ***/ 3259 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3260 static void glue(gen_, name##x)(DisasContext *ctx) \ 3261 { \ 3262 TCGv EA; \ 3263 chk(ctx); \ 3264 gen_set_access_type(ctx, ACCESS_INT); \ 3265 EA = tcg_temp_new(); \ 3266 gen_addr_reg_index(ctx, EA); \ 3267 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3268 } 3269 #define GEN_STX(name, stop, opc2, opc3, type) \ 3270 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3271 3272 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3273 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3274 3275 #define GEN_STEPX(name, stop, opc2, opc3) \ 3276 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3277 { \ 3278 TCGv EA; \ 3279 CHK_SV(ctx); \ 3280 gen_set_access_type(ctx, ACCESS_INT); \ 3281 EA = tcg_temp_new(); \ 3282 gen_addr_reg_index(ctx, EA); \ 3283 tcg_gen_qemu_st_tl( \ 3284 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3285 } 3286 3287 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3288 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3289 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3290 #if defined(TARGET_PPC64) 3291 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3292 #endif 3293 3294 #if defined(TARGET_PPC64) 3295 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3296 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3297 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3298 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3299 #endif 3300 /*** Integer load and store with byte reverse ***/ 3301 3302 /* lhbrx */ 3303 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3304 3305 /* lwbrx */ 3306 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3307 3308 #if defined(TARGET_PPC64) 3309 /* ldbrx */ 3310 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3311 /* stdbrx */ 3312 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3313 #endif /* TARGET_PPC64 */ 3314 3315 /* sthbrx */ 3316 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3317 /* stwbrx */ 3318 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3319 3320 /*** Integer load and store multiple ***/ 3321 3322 /* lmw */ 3323 static void gen_lmw(DisasContext *ctx) 3324 { 3325 TCGv t0; 3326 TCGv_i32 t1; 3327 3328 if (ctx->le_mode) { 3329 gen_align_no_le(ctx); 3330 return; 3331 } 3332 gen_set_access_type(ctx, ACCESS_INT); 3333 t0 = tcg_temp_new(); 3334 t1 = tcg_constant_i32(rD(ctx->opcode)); 3335 gen_addr_imm_index(ctx, t0, 0); 3336 gen_helper_lmw(cpu_env, t0, t1); 3337 } 3338 3339 /* stmw */ 3340 static void gen_stmw(DisasContext *ctx) 3341 { 3342 TCGv t0; 3343 TCGv_i32 t1; 3344 3345 if (ctx->le_mode) { 3346 gen_align_no_le(ctx); 3347 return; 3348 } 3349 gen_set_access_type(ctx, ACCESS_INT); 3350 t0 = tcg_temp_new(); 3351 t1 = tcg_constant_i32(rS(ctx->opcode)); 3352 gen_addr_imm_index(ctx, t0, 0); 3353 gen_helper_stmw(cpu_env, t0, t1); 3354 } 3355 3356 /*** Integer load and store strings ***/ 3357 3358 /* lswi */ 3359 /* 3360 * PowerPC32 specification says we must generate an exception if rA is 3361 * in the range of registers to be loaded. In an other hand, IBM says 3362 * this is valid, but rA won't be loaded. For now, I'll follow the 3363 * spec... 3364 */ 3365 static void gen_lswi(DisasContext *ctx) 3366 { 3367 TCGv t0; 3368 TCGv_i32 t1, t2; 3369 int nb = NB(ctx->opcode); 3370 int start = rD(ctx->opcode); 3371 int ra = rA(ctx->opcode); 3372 int nr; 3373 3374 if (ctx->le_mode) { 3375 gen_align_no_le(ctx); 3376 return; 3377 } 3378 if (nb == 0) { 3379 nb = 32; 3380 } 3381 nr = DIV_ROUND_UP(nb, 4); 3382 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3383 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3384 return; 3385 } 3386 gen_set_access_type(ctx, ACCESS_INT); 3387 t0 = tcg_temp_new(); 3388 gen_addr_register(ctx, t0); 3389 t1 = tcg_constant_i32(nb); 3390 t2 = tcg_constant_i32(start); 3391 gen_helper_lsw(cpu_env, t0, t1, t2); 3392 } 3393 3394 /* lswx */ 3395 static void gen_lswx(DisasContext *ctx) 3396 { 3397 TCGv t0; 3398 TCGv_i32 t1, t2, t3; 3399 3400 if (ctx->le_mode) { 3401 gen_align_no_le(ctx); 3402 return; 3403 } 3404 gen_set_access_type(ctx, ACCESS_INT); 3405 t0 = tcg_temp_new(); 3406 gen_addr_reg_index(ctx, t0); 3407 t1 = tcg_constant_i32(rD(ctx->opcode)); 3408 t2 = tcg_constant_i32(rA(ctx->opcode)); 3409 t3 = tcg_constant_i32(rB(ctx->opcode)); 3410 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3411 } 3412 3413 /* stswi */ 3414 static void gen_stswi(DisasContext *ctx) 3415 { 3416 TCGv t0; 3417 TCGv_i32 t1, t2; 3418 int nb = NB(ctx->opcode); 3419 3420 if (ctx->le_mode) { 3421 gen_align_no_le(ctx); 3422 return; 3423 } 3424 gen_set_access_type(ctx, ACCESS_INT); 3425 t0 = tcg_temp_new(); 3426 gen_addr_register(ctx, t0); 3427 if (nb == 0) { 3428 nb = 32; 3429 } 3430 t1 = tcg_constant_i32(nb); 3431 t2 = tcg_constant_i32(rS(ctx->opcode)); 3432 gen_helper_stsw(cpu_env, t0, t1, t2); 3433 } 3434 3435 /* stswx */ 3436 static void gen_stswx(DisasContext *ctx) 3437 { 3438 TCGv t0; 3439 TCGv_i32 t1, t2; 3440 3441 if (ctx->le_mode) { 3442 gen_align_no_le(ctx); 3443 return; 3444 } 3445 gen_set_access_type(ctx, ACCESS_INT); 3446 t0 = tcg_temp_new(); 3447 gen_addr_reg_index(ctx, t0); 3448 t1 = tcg_temp_new_i32(); 3449 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3450 tcg_gen_andi_i32(t1, t1, 0x7F); 3451 t2 = tcg_constant_i32(rS(ctx->opcode)); 3452 gen_helper_stsw(cpu_env, t0, t1, t2); 3453 } 3454 3455 /*** Memory synchronisation ***/ 3456 /* eieio */ 3457 static void gen_eieio(DisasContext *ctx) 3458 { 3459 TCGBar bar = TCG_MO_ALL; 3460 3461 /* 3462 * eieio has complex semanitcs. It provides memory ordering between 3463 * operations in the set: 3464 * - loads from CI memory. 3465 * - stores to CI memory. 3466 * - stores to WT memory. 3467 * 3468 * It separately also orders memory for operations in the set: 3469 * - stores to cacheble memory. 3470 * 3471 * It also serializes instructions: 3472 * - dcbt and dcbst. 3473 * 3474 * It separately serializes: 3475 * - tlbie and tlbsync. 3476 * 3477 * And separately serializes: 3478 * - slbieg, slbiag, and slbsync. 3479 * 3480 * The end result is that CI memory ordering requires TCG_MO_ALL 3481 * and it is not possible to special-case more relaxed ordering for 3482 * cacheable accesses. TCG_BAR_SC is required to provide this 3483 * serialization. 3484 */ 3485 3486 /* 3487 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3488 * tell the CPU it is a store-forwarding barrier. 3489 */ 3490 if (ctx->opcode & 0x2000000) { 3491 /* 3492 * ISA says that "Reserved fields in instructions are ignored 3493 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3494 * as this is not an instruction software should be using, 3495 * complain to the user. 3496 */ 3497 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3498 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3499 TARGET_FMT_lx "\n", ctx->cia); 3500 } else { 3501 bar = TCG_MO_ST_LD; 3502 } 3503 } 3504 3505 tcg_gen_mb(bar | TCG_BAR_SC); 3506 } 3507 3508 #if !defined(CONFIG_USER_ONLY) 3509 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3510 { 3511 TCGv_i32 t; 3512 TCGLabel *l; 3513 3514 if (!ctx->lazy_tlb_flush) { 3515 return; 3516 } 3517 l = gen_new_label(); 3518 t = tcg_temp_new_i32(); 3519 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3520 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3521 if (global) { 3522 gen_helper_check_tlb_flush_global(cpu_env); 3523 } else { 3524 gen_helper_check_tlb_flush_local(cpu_env); 3525 } 3526 gen_set_label(l); 3527 } 3528 #else 3529 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3530 #endif 3531 3532 /* isync */ 3533 static void gen_isync(DisasContext *ctx) 3534 { 3535 /* 3536 * We need to check for a pending TLB flush. This can only happen in 3537 * kernel mode however so check MSR_PR 3538 */ 3539 if (!ctx->pr) { 3540 gen_check_tlb_flush(ctx, false); 3541 } 3542 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3543 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3544 } 3545 3546 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3547 3548 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3549 { 3550 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3551 TCGv t0 = tcg_temp_new(); 3552 3553 gen_set_access_type(ctx, ACCESS_RES); 3554 gen_addr_reg_index(ctx, t0); 3555 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3556 tcg_gen_mov_tl(cpu_reserve, t0); 3557 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3558 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3559 } 3560 3561 #define LARX(name, memop) \ 3562 static void gen_##name(DisasContext *ctx) \ 3563 { \ 3564 gen_load_locked(ctx, memop); \ 3565 } 3566 3567 /* lwarx */ 3568 LARX(lbarx, DEF_MEMOP(MO_UB)) 3569 LARX(lharx, DEF_MEMOP(MO_UW)) 3570 LARX(lwarx, DEF_MEMOP(MO_UL)) 3571 3572 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3573 TCGv EA, TCGCond cond, int addend) 3574 { 3575 TCGv t = tcg_temp_new(); 3576 TCGv t2 = tcg_temp_new(); 3577 TCGv u = tcg_temp_new(); 3578 3579 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3580 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3581 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3582 tcg_gen_addi_tl(u, t, addend); 3583 3584 /* E.g. for fetch and increment bounded... */ 3585 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3586 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3587 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3588 3589 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3590 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3591 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3592 } 3593 3594 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3595 { 3596 uint32_t gpr_FC = FC(ctx->opcode); 3597 TCGv EA = tcg_temp_new(); 3598 int rt = rD(ctx->opcode); 3599 bool need_serial; 3600 TCGv src, dst; 3601 3602 gen_addr_register(ctx, EA); 3603 dst = cpu_gpr[rt]; 3604 src = cpu_gpr[(rt + 1) & 31]; 3605 3606 need_serial = false; 3607 memop |= MO_ALIGN; 3608 switch (gpr_FC) { 3609 case 0: /* Fetch and add */ 3610 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3611 break; 3612 case 1: /* Fetch and xor */ 3613 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3614 break; 3615 case 2: /* Fetch and or */ 3616 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3617 break; 3618 case 3: /* Fetch and 'and' */ 3619 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3620 break; 3621 case 4: /* Fetch and max unsigned */ 3622 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3623 break; 3624 case 5: /* Fetch and max signed */ 3625 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3626 break; 3627 case 6: /* Fetch and min unsigned */ 3628 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3629 break; 3630 case 7: /* Fetch and min signed */ 3631 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3632 break; 3633 case 8: /* Swap */ 3634 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3635 break; 3636 3637 case 16: /* Compare and swap not equal */ 3638 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3639 need_serial = true; 3640 } else { 3641 TCGv t0 = tcg_temp_new(); 3642 TCGv t1 = tcg_temp_new(); 3643 3644 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3645 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3646 tcg_gen_mov_tl(t1, src); 3647 } else { 3648 tcg_gen_ext32u_tl(t1, src); 3649 } 3650 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3651 cpu_gpr[(rt + 2) & 31], t0); 3652 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3653 tcg_gen_mov_tl(dst, t0); 3654 } 3655 break; 3656 3657 case 24: /* Fetch and increment bounded */ 3658 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3659 need_serial = true; 3660 } else { 3661 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3662 } 3663 break; 3664 case 25: /* Fetch and increment equal */ 3665 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3666 need_serial = true; 3667 } else { 3668 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3669 } 3670 break; 3671 case 28: /* Fetch and decrement bounded */ 3672 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3673 need_serial = true; 3674 } else { 3675 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3676 } 3677 break; 3678 3679 default: 3680 /* invoke data storage error handler */ 3681 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3682 } 3683 3684 if (need_serial) { 3685 /* Restart with exclusive lock. */ 3686 gen_helper_exit_atomic(cpu_env); 3687 ctx->base.is_jmp = DISAS_NORETURN; 3688 } 3689 } 3690 3691 static void gen_lwat(DisasContext *ctx) 3692 { 3693 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3694 } 3695 3696 #ifdef TARGET_PPC64 3697 static void gen_ldat(DisasContext *ctx) 3698 { 3699 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3700 } 3701 #endif 3702 3703 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3704 { 3705 uint32_t gpr_FC = FC(ctx->opcode); 3706 TCGv EA = tcg_temp_new(); 3707 TCGv src, discard; 3708 3709 gen_addr_register(ctx, EA); 3710 src = cpu_gpr[rD(ctx->opcode)]; 3711 discard = tcg_temp_new(); 3712 3713 memop |= MO_ALIGN; 3714 switch (gpr_FC) { 3715 case 0: /* add and Store */ 3716 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3717 break; 3718 case 1: /* xor and Store */ 3719 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3720 break; 3721 case 2: /* Or and Store */ 3722 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3723 break; 3724 case 3: /* 'and' and Store */ 3725 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3726 break; 3727 case 4: /* Store max unsigned */ 3728 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3729 break; 3730 case 5: /* Store max signed */ 3731 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3732 break; 3733 case 6: /* Store min unsigned */ 3734 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3735 break; 3736 case 7: /* Store min signed */ 3737 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3738 break; 3739 case 24: /* Store twin */ 3740 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3741 /* Restart with exclusive lock. */ 3742 gen_helper_exit_atomic(cpu_env); 3743 ctx->base.is_jmp = DISAS_NORETURN; 3744 } else { 3745 TCGv t = tcg_temp_new(); 3746 TCGv t2 = tcg_temp_new(); 3747 TCGv s = tcg_temp_new(); 3748 TCGv s2 = tcg_temp_new(); 3749 TCGv ea_plus_s = tcg_temp_new(); 3750 3751 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3752 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3753 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3754 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3755 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3756 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3757 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3758 } 3759 break; 3760 default: 3761 /* invoke data storage error handler */ 3762 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3763 } 3764 } 3765 3766 static void gen_stwat(DisasContext *ctx) 3767 { 3768 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3769 } 3770 3771 #ifdef TARGET_PPC64 3772 static void gen_stdat(DisasContext *ctx) 3773 { 3774 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3775 } 3776 #endif 3777 3778 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3779 { 3780 TCGLabel *lfail; 3781 TCGv EA; 3782 TCGv cr0; 3783 TCGv t0; 3784 int rs = rS(ctx->opcode); 3785 3786 lfail = gen_new_label(); 3787 EA = tcg_temp_new(); 3788 cr0 = tcg_temp_new(); 3789 t0 = tcg_temp_new(); 3790 3791 tcg_gen_mov_tl(cr0, cpu_so); 3792 gen_set_access_type(ctx, ACCESS_RES); 3793 gen_addr_reg_index(ctx, EA); 3794 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3795 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3796 3797 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3798 cpu_gpr[rs], ctx->mem_idx, 3799 DEF_MEMOP(memop) | MO_ALIGN); 3800 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3801 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3802 tcg_gen_or_tl(cr0, cr0, t0); 3803 3804 gen_set_label(lfail); 3805 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3806 tcg_gen_movi_tl(cpu_reserve, -1); 3807 } 3808 3809 #define STCX(name, memop) \ 3810 static void gen_##name(DisasContext *ctx) \ 3811 { \ 3812 gen_conditional_store(ctx, memop); \ 3813 } 3814 3815 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3816 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3817 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3818 3819 #if defined(TARGET_PPC64) 3820 /* ldarx */ 3821 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3822 /* stdcx. */ 3823 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3824 3825 /* lqarx */ 3826 static void gen_lqarx(DisasContext *ctx) 3827 { 3828 int rd = rD(ctx->opcode); 3829 TCGv EA, hi, lo; 3830 TCGv_i128 t16; 3831 3832 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3833 (rd == rB(ctx->opcode)))) { 3834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3835 return; 3836 } 3837 3838 gen_set_access_type(ctx, ACCESS_RES); 3839 EA = tcg_temp_new(); 3840 gen_addr_reg_index(ctx, EA); 3841 3842 /* Note that the low part is always in RD+1, even in LE mode. */ 3843 lo = cpu_gpr[rd + 1]; 3844 hi = cpu_gpr[rd]; 3845 3846 t16 = tcg_temp_new_i128(); 3847 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3848 tcg_gen_extr_i128_i64(lo, hi, t16); 3849 3850 tcg_gen_mov_tl(cpu_reserve, EA); 3851 tcg_gen_movi_tl(cpu_reserve_length, 16); 3852 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3853 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3854 } 3855 3856 /* stqcx. */ 3857 static void gen_stqcx_(DisasContext *ctx) 3858 { 3859 TCGLabel *lfail; 3860 TCGv EA, t0, t1; 3861 TCGv cr0; 3862 TCGv_i128 cmp, val; 3863 int rs = rS(ctx->opcode); 3864 3865 if (unlikely(rs & 1)) { 3866 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3867 return; 3868 } 3869 3870 lfail = gen_new_label(); 3871 EA = tcg_temp_new(); 3872 cr0 = tcg_temp_new(); 3873 3874 tcg_gen_mov_tl(cr0, cpu_so); 3875 gen_set_access_type(ctx, ACCESS_RES); 3876 gen_addr_reg_index(ctx, EA); 3877 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3878 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3879 3880 cmp = tcg_temp_new_i128(); 3881 val = tcg_temp_new_i128(); 3882 3883 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3884 3885 /* Note that the low part is always in RS+1, even in LE mode. */ 3886 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3887 3888 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3889 DEF_MEMOP(MO_128 | MO_ALIGN)); 3890 3891 t0 = tcg_temp_new(); 3892 t1 = tcg_temp_new(); 3893 tcg_gen_extr_i128_i64(t1, t0, val); 3894 3895 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3896 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3897 tcg_gen_or_tl(t0, t0, t1); 3898 3899 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3900 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3901 tcg_gen_or_tl(cr0, cr0, t0); 3902 3903 gen_set_label(lfail); 3904 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3905 tcg_gen_movi_tl(cpu_reserve, -1); 3906 } 3907 #endif /* defined(TARGET_PPC64) */ 3908 3909 /* sync */ 3910 static void gen_sync(DisasContext *ctx) 3911 { 3912 TCGBar bar = TCG_MO_ALL; 3913 uint32_t l = (ctx->opcode >> 21) & 3; 3914 3915 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3916 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3917 } 3918 3919 /* 3920 * We may need to check for a pending TLB flush. 3921 * 3922 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3923 * 3924 * Additionally, this can only happen in kernel mode however so 3925 * check MSR_PR as well. 3926 */ 3927 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3928 gen_check_tlb_flush(ctx, true); 3929 } 3930 3931 tcg_gen_mb(bar | TCG_BAR_SC); 3932 } 3933 3934 /* wait */ 3935 static void gen_wait(DisasContext *ctx) 3936 { 3937 uint32_t wc; 3938 3939 if (ctx->insns_flags & PPC_WAIT) { 3940 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3941 3942 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3943 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3944 wc = WC(ctx->opcode); 3945 } else { 3946 wc = 0; 3947 } 3948 3949 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3950 /* v3.0 defines a new 'wait' encoding. */ 3951 wc = WC(ctx->opcode); 3952 if (ctx->insns_flags2 & PPC2_ISA310) { 3953 uint32_t pl = PL(ctx->opcode); 3954 3955 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3956 if (wc == 3) { 3957 gen_invalid(ctx); 3958 return; 3959 } 3960 3961 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3962 if (pl > 0 && wc != 2) { 3963 gen_invalid(ctx); 3964 return; 3965 } 3966 3967 } else { /* ISA300 */ 3968 /* WC 1-3 are reserved */ 3969 if (wc > 0) { 3970 gen_invalid(ctx); 3971 return; 3972 } 3973 } 3974 3975 } else { 3976 warn_report("wait instruction decoded with wrong ISA flags."); 3977 gen_invalid(ctx); 3978 return; 3979 } 3980 3981 /* 3982 * wait without WC field or with WC=0 waits for an exception / interrupt 3983 * to occur. 3984 */ 3985 if (wc == 0) { 3986 TCGv_i32 t0 = tcg_constant_i32(1); 3987 tcg_gen_st_i32(t0, cpu_env, 3988 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3989 /* Stop translation, as the CPU is supposed to sleep from now */ 3990 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3991 } 3992 3993 /* 3994 * Other wait types must not just wait until an exception occurs because 3995 * ignoring their other wake-up conditions could cause a hang. 3996 * 3997 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3998 * no-ops. 3999 * 4000 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 4001 * 4002 * wc=2 waits for an implementation-specific condition, such could be 4003 * always true, so it can be implemented as a no-op. 4004 * 4005 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 4006 * 4007 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 4008 * Reservation-loss may have implementation-specific conditions, so it 4009 * can be implemented as a no-op. 4010 * 4011 * wc=2 waits for an exception or an amount of time to pass. This 4012 * amount is implementation-specific so it can be implemented as a 4013 * no-op. 4014 * 4015 * ISA v3.1 allows for execution to resume "in the rare case of 4016 * an implementation-dependent event", so in any case software must 4017 * not depend on the architected resumption condition to become 4018 * true, so no-op implementations should be architecturally correct 4019 * (if suboptimal). 4020 */ 4021 } 4022 4023 #if defined(TARGET_PPC64) 4024 static void gen_doze(DisasContext *ctx) 4025 { 4026 #if defined(CONFIG_USER_ONLY) 4027 GEN_PRIV(ctx); 4028 #else 4029 TCGv_i32 t; 4030 4031 CHK_HV(ctx); 4032 translator_io_start(&ctx->base); 4033 t = tcg_constant_i32(PPC_PM_DOZE); 4034 gen_helper_pminsn(cpu_env, t); 4035 /* Stop translation, as the CPU is supposed to sleep from now */ 4036 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4037 #endif /* defined(CONFIG_USER_ONLY) */ 4038 } 4039 4040 static void gen_nap(DisasContext *ctx) 4041 { 4042 #if defined(CONFIG_USER_ONLY) 4043 GEN_PRIV(ctx); 4044 #else 4045 TCGv_i32 t; 4046 4047 CHK_HV(ctx); 4048 translator_io_start(&ctx->base); 4049 t = tcg_constant_i32(PPC_PM_NAP); 4050 gen_helper_pminsn(cpu_env, t); 4051 /* Stop translation, as the CPU is supposed to sleep from now */ 4052 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4053 #endif /* defined(CONFIG_USER_ONLY) */ 4054 } 4055 4056 static void gen_stop(DisasContext *ctx) 4057 { 4058 #if defined(CONFIG_USER_ONLY) 4059 GEN_PRIV(ctx); 4060 #else 4061 TCGv_i32 t; 4062 4063 CHK_HV(ctx); 4064 translator_io_start(&ctx->base); 4065 t = tcg_constant_i32(PPC_PM_STOP); 4066 gen_helper_pminsn(cpu_env, t); 4067 /* Stop translation, as the CPU is supposed to sleep from now */ 4068 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4069 #endif /* defined(CONFIG_USER_ONLY) */ 4070 } 4071 4072 static void gen_sleep(DisasContext *ctx) 4073 { 4074 #if defined(CONFIG_USER_ONLY) 4075 GEN_PRIV(ctx); 4076 #else 4077 TCGv_i32 t; 4078 4079 CHK_HV(ctx); 4080 translator_io_start(&ctx->base); 4081 t = tcg_constant_i32(PPC_PM_SLEEP); 4082 gen_helper_pminsn(cpu_env, t); 4083 /* Stop translation, as the CPU is supposed to sleep from now */ 4084 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4085 #endif /* defined(CONFIG_USER_ONLY) */ 4086 } 4087 4088 static void gen_rvwinkle(DisasContext *ctx) 4089 { 4090 #if defined(CONFIG_USER_ONLY) 4091 GEN_PRIV(ctx); 4092 #else 4093 TCGv_i32 t; 4094 4095 CHK_HV(ctx); 4096 translator_io_start(&ctx->base); 4097 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4098 gen_helper_pminsn(cpu_env, t); 4099 /* Stop translation, as the CPU is supposed to sleep from now */ 4100 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4101 #endif /* defined(CONFIG_USER_ONLY) */ 4102 } 4103 #endif /* #if defined(TARGET_PPC64) */ 4104 4105 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4106 { 4107 #if defined(TARGET_PPC64) 4108 if (ctx->has_cfar) { 4109 tcg_gen_movi_tl(cpu_cfar, nip); 4110 } 4111 #endif 4112 } 4113 4114 #if defined(TARGET_PPC64) 4115 static void pmu_count_insns(DisasContext *ctx) 4116 { 4117 /* 4118 * Do not bother calling the helper if the PMU isn't counting 4119 * instructions. 4120 */ 4121 if (!ctx->pmu_insn_cnt) { 4122 return; 4123 } 4124 4125 #if !defined(CONFIG_USER_ONLY) 4126 TCGLabel *l; 4127 TCGv t0; 4128 4129 /* 4130 * The PMU insns_inc() helper stops the internal PMU timer if a 4131 * counter overflows happens. In that case, if the guest is 4132 * running with icount and we do not handle it beforehand, 4133 * the helper can trigger a 'bad icount read'. 4134 */ 4135 translator_io_start(&ctx->base); 4136 4137 /* Avoid helper calls when only PMC5-6 are enabled. */ 4138 if (!ctx->pmc_other) { 4139 l = gen_new_label(); 4140 t0 = tcg_temp_new(); 4141 4142 gen_load_spr(t0, SPR_POWER_PMC5); 4143 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4144 gen_store_spr(SPR_POWER_PMC5, t0); 4145 /* Check for overflow, if it's enabled */ 4146 if (ctx->mmcr0_pmcjce) { 4147 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4148 gen_helper_handle_pmc5_overflow(cpu_env); 4149 } 4150 4151 gen_set_label(l); 4152 } else { 4153 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4154 } 4155 #else 4156 /* 4157 * User mode can read (but not write) PMC5 and start/stop 4158 * the PMU via MMCR0_FC. In this case just increment 4159 * PMC5 with base.num_insns. 4160 */ 4161 TCGv t0 = tcg_temp_new(); 4162 4163 gen_load_spr(t0, SPR_POWER_PMC5); 4164 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4165 gen_store_spr(SPR_POWER_PMC5, t0); 4166 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4167 } 4168 #else 4169 static void pmu_count_insns(DisasContext *ctx) 4170 { 4171 return; 4172 } 4173 #endif /* #if defined(TARGET_PPC64) */ 4174 4175 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4176 { 4177 if (unlikely(ctx->singlestep_enabled)) { 4178 return false; 4179 } 4180 return translator_use_goto_tb(&ctx->base, dest); 4181 } 4182 4183 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4184 { 4185 if (unlikely(ctx->singlestep_enabled)) { 4186 gen_debug_exception(ctx, false); 4187 } else { 4188 /* 4189 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4190 * CF_NO_GOTO_PTR is set. Count insns now. 4191 */ 4192 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4193 pmu_count_insns(ctx); 4194 } 4195 4196 tcg_gen_lookup_and_goto_ptr(); 4197 } 4198 } 4199 4200 /*** Branch ***/ 4201 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4202 { 4203 if (NARROW_MODE(ctx)) { 4204 dest = (uint32_t) dest; 4205 } 4206 if (use_goto_tb(ctx, dest)) { 4207 pmu_count_insns(ctx); 4208 tcg_gen_goto_tb(n); 4209 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4210 tcg_gen_exit_tb(ctx->base.tb, n); 4211 } else { 4212 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4213 gen_lookup_and_goto_ptr(ctx); 4214 } 4215 } 4216 4217 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4218 { 4219 if (NARROW_MODE(ctx)) { 4220 nip = (uint32_t)nip; 4221 } 4222 tcg_gen_movi_tl(cpu_lr, nip); 4223 } 4224 4225 /* b ba bl bla */ 4226 static void gen_b(DisasContext *ctx) 4227 { 4228 target_ulong li, target; 4229 4230 /* sign extend LI */ 4231 li = LI(ctx->opcode); 4232 li = (li ^ 0x02000000) - 0x02000000; 4233 if (likely(AA(ctx->opcode) == 0)) { 4234 target = ctx->cia + li; 4235 } else { 4236 target = li; 4237 } 4238 if (LK(ctx->opcode)) { 4239 gen_setlr(ctx, ctx->base.pc_next); 4240 } 4241 gen_update_cfar(ctx, ctx->cia); 4242 gen_goto_tb(ctx, 0, target); 4243 ctx->base.is_jmp = DISAS_NORETURN; 4244 } 4245 4246 #define BCOND_IM 0 4247 #define BCOND_LR 1 4248 #define BCOND_CTR 2 4249 #define BCOND_TAR 3 4250 4251 static void gen_bcond(DisasContext *ctx, int type) 4252 { 4253 uint32_t bo = BO(ctx->opcode); 4254 TCGLabel *l1; 4255 TCGv target; 4256 4257 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4258 target = tcg_temp_new(); 4259 if (type == BCOND_CTR) { 4260 tcg_gen_mov_tl(target, cpu_ctr); 4261 } else if (type == BCOND_TAR) { 4262 gen_load_spr(target, SPR_TAR); 4263 } else { 4264 tcg_gen_mov_tl(target, cpu_lr); 4265 } 4266 } else { 4267 target = NULL; 4268 } 4269 if (LK(ctx->opcode)) { 4270 gen_setlr(ctx, ctx->base.pc_next); 4271 } 4272 l1 = gen_new_label(); 4273 if ((bo & 0x4) == 0) { 4274 /* Decrement and test CTR */ 4275 TCGv temp = tcg_temp_new(); 4276 4277 if (type == BCOND_CTR) { 4278 /* 4279 * All ISAs up to v3 describe this form of bcctr as invalid but 4280 * some processors, ie. 64-bit server processors compliant with 4281 * arch 2.x, do implement a "test and decrement" logic instead, 4282 * as described in their respective UMs. This logic involves CTR 4283 * to act as both the branch target and a counter, which makes 4284 * it basically useless and thus never used in real code. 4285 * 4286 * This form was hence chosen to trigger extra micro-architectural 4287 * side-effect on real HW needed for the Spectre v2 workaround. 4288 * It is up to guests that implement such workaround, ie. linux, to 4289 * use this form in a way it just triggers the side-effect without 4290 * doing anything else harmful. 4291 */ 4292 if (unlikely(!is_book3s_arch2x(ctx))) { 4293 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4294 return; 4295 } 4296 4297 if (NARROW_MODE(ctx)) { 4298 tcg_gen_ext32u_tl(temp, cpu_ctr); 4299 } else { 4300 tcg_gen_mov_tl(temp, cpu_ctr); 4301 } 4302 if (bo & 0x2) { 4303 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4304 } else { 4305 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4306 } 4307 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4308 } else { 4309 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4310 if (NARROW_MODE(ctx)) { 4311 tcg_gen_ext32u_tl(temp, cpu_ctr); 4312 } else { 4313 tcg_gen_mov_tl(temp, cpu_ctr); 4314 } 4315 if (bo & 0x2) { 4316 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4317 } else { 4318 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4319 } 4320 } 4321 } 4322 if ((bo & 0x10) == 0) { 4323 /* Test CR */ 4324 uint32_t bi = BI(ctx->opcode); 4325 uint32_t mask = 0x08 >> (bi & 0x03); 4326 TCGv_i32 temp = tcg_temp_new_i32(); 4327 4328 if (bo & 0x8) { 4329 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4330 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4331 } else { 4332 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4333 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4334 } 4335 } 4336 gen_update_cfar(ctx, ctx->cia); 4337 if (type == BCOND_IM) { 4338 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4339 if (likely(AA(ctx->opcode) == 0)) { 4340 gen_goto_tb(ctx, 0, ctx->cia + li); 4341 } else { 4342 gen_goto_tb(ctx, 0, li); 4343 } 4344 } else { 4345 if (NARROW_MODE(ctx)) { 4346 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4347 } else { 4348 tcg_gen_andi_tl(cpu_nip, target, ~3); 4349 } 4350 gen_lookup_and_goto_ptr(ctx); 4351 } 4352 if ((bo & 0x14) != 0x14) { 4353 /* fallthrough case */ 4354 gen_set_label(l1); 4355 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4356 } 4357 ctx->base.is_jmp = DISAS_NORETURN; 4358 } 4359 4360 static void gen_bc(DisasContext *ctx) 4361 { 4362 gen_bcond(ctx, BCOND_IM); 4363 } 4364 4365 static void gen_bcctr(DisasContext *ctx) 4366 { 4367 gen_bcond(ctx, BCOND_CTR); 4368 } 4369 4370 static void gen_bclr(DisasContext *ctx) 4371 { 4372 gen_bcond(ctx, BCOND_LR); 4373 } 4374 4375 static void gen_bctar(DisasContext *ctx) 4376 { 4377 gen_bcond(ctx, BCOND_TAR); 4378 } 4379 4380 /*** Condition register logical ***/ 4381 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4382 static void glue(gen_, name)(DisasContext *ctx) \ 4383 { \ 4384 uint8_t bitmask; \ 4385 int sh; \ 4386 TCGv_i32 t0, t1; \ 4387 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4388 t0 = tcg_temp_new_i32(); \ 4389 if (sh > 0) \ 4390 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4391 else if (sh < 0) \ 4392 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4393 else \ 4394 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4395 t1 = tcg_temp_new_i32(); \ 4396 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4397 if (sh > 0) \ 4398 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4399 else if (sh < 0) \ 4400 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4401 else \ 4402 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4403 tcg_op(t0, t0, t1); \ 4404 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4405 tcg_gen_andi_i32(t0, t0, bitmask); \ 4406 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4407 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4408 } 4409 4410 /* crand */ 4411 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4412 /* crandc */ 4413 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4414 /* creqv */ 4415 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4416 /* crnand */ 4417 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4418 /* crnor */ 4419 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4420 /* cror */ 4421 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4422 /* crorc */ 4423 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4424 /* crxor */ 4425 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4426 4427 /* mcrf */ 4428 static void gen_mcrf(DisasContext *ctx) 4429 { 4430 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4431 } 4432 4433 /*** System linkage ***/ 4434 4435 /* rfi (supervisor only) */ 4436 static void gen_rfi(DisasContext *ctx) 4437 { 4438 #if defined(CONFIG_USER_ONLY) 4439 GEN_PRIV(ctx); 4440 #else 4441 /* 4442 * This instruction doesn't exist anymore on 64-bit server 4443 * processors compliant with arch 2.x 4444 */ 4445 if (is_book3s_arch2x(ctx)) { 4446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4447 return; 4448 } 4449 /* Restore CPU state */ 4450 CHK_SV(ctx); 4451 translator_io_start(&ctx->base); 4452 gen_update_cfar(ctx, ctx->cia); 4453 gen_helper_rfi(cpu_env); 4454 ctx->base.is_jmp = DISAS_EXIT; 4455 #endif 4456 } 4457 4458 #if defined(TARGET_PPC64) 4459 static void gen_rfid(DisasContext *ctx) 4460 { 4461 #if defined(CONFIG_USER_ONLY) 4462 GEN_PRIV(ctx); 4463 #else 4464 /* Restore CPU state */ 4465 CHK_SV(ctx); 4466 translator_io_start(&ctx->base); 4467 gen_update_cfar(ctx, ctx->cia); 4468 gen_helper_rfid(cpu_env); 4469 ctx->base.is_jmp = DISAS_EXIT; 4470 #endif 4471 } 4472 4473 #if !defined(CONFIG_USER_ONLY) 4474 static void gen_rfscv(DisasContext *ctx) 4475 { 4476 #if defined(CONFIG_USER_ONLY) 4477 GEN_PRIV(ctx); 4478 #else 4479 /* Restore CPU state */ 4480 CHK_SV(ctx); 4481 translator_io_start(&ctx->base); 4482 gen_update_cfar(ctx, ctx->cia); 4483 gen_helper_rfscv(cpu_env); 4484 ctx->base.is_jmp = DISAS_EXIT; 4485 #endif 4486 } 4487 #endif 4488 4489 static void gen_hrfid(DisasContext *ctx) 4490 { 4491 #if defined(CONFIG_USER_ONLY) 4492 GEN_PRIV(ctx); 4493 #else 4494 /* Restore CPU state */ 4495 CHK_HV(ctx); 4496 translator_io_start(&ctx->base); 4497 gen_helper_hrfid(cpu_env); 4498 ctx->base.is_jmp = DISAS_EXIT; 4499 #endif 4500 } 4501 #endif 4502 4503 /* sc */ 4504 #if defined(CONFIG_USER_ONLY) 4505 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4506 #else 4507 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4508 #endif 4509 static void gen_sc(DisasContext *ctx) 4510 { 4511 uint32_t lev; 4512 4513 /* 4514 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4515 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4516 * for Ultravisor which TCG does not support, so just ignore the top 6. 4517 */ 4518 lev = (ctx->opcode >> 5) & 0x1; 4519 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4520 } 4521 4522 #if defined(TARGET_PPC64) 4523 #if !defined(CONFIG_USER_ONLY) 4524 static void gen_scv(DisasContext *ctx) 4525 { 4526 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4527 4528 /* Set the PC back to the faulting instruction. */ 4529 gen_update_nip(ctx, ctx->cia); 4530 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4531 4532 ctx->base.is_jmp = DISAS_NORETURN; 4533 } 4534 #endif 4535 #endif 4536 4537 /*** Trap ***/ 4538 4539 /* Check for unconditional traps (always or never) */ 4540 static bool check_unconditional_trap(DisasContext *ctx) 4541 { 4542 /* Trap never */ 4543 if (TO(ctx->opcode) == 0) { 4544 return true; 4545 } 4546 /* Trap always */ 4547 if (TO(ctx->opcode) == 31) { 4548 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4549 return true; 4550 } 4551 return false; 4552 } 4553 4554 /* tw */ 4555 static void gen_tw(DisasContext *ctx) 4556 { 4557 TCGv_i32 t0; 4558 4559 if (check_unconditional_trap(ctx)) { 4560 return; 4561 } 4562 t0 = tcg_constant_i32(TO(ctx->opcode)); 4563 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4564 t0); 4565 } 4566 4567 /* twi */ 4568 static void gen_twi(DisasContext *ctx) 4569 { 4570 TCGv t0; 4571 TCGv_i32 t1; 4572 4573 if (check_unconditional_trap(ctx)) { 4574 return; 4575 } 4576 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4577 t1 = tcg_constant_i32(TO(ctx->opcode)); 4578 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4579 } 4580 4581 #if defined(TARGET_PPC64) 4582 /* td */ 4583 static void gen_td(DisasContext *ctx) 4584 { 4585 TCGv_i32 t0; 4586 4587 if (check_unconditional_trap(ctx)) { 4588 return; 4589 } 4590 t0 = tcg_constant_i32(TO(ctx->opcode)); 4591 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4592 t0); 4593 } 4594 4595 /* tdi */ 4596 static void gen_tdi(DisasContext *ctx) 4597 { 4598 TCGv t0; 4599 TCGv_i32 t1; 4600 4601 if (check_unconditional_trap(ctx)) { 4602 return; 4603 } 4604 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4605 t1 = tcg_constant_i32(TO(ctx->opcode)); 4606 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4607 } 4608 #endif 4609 4610 /*** Processor control ***/ 4611 4612 /* mcrxr */ 4613 static void gen_mcrxr(DisasContext *ctx) 4614 { 4615 TCGv_i32 t0 = tcg_temp_new_i32(); 4616 TCGv_i32 t1 = tcg_temp_new_i32(); 4617 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4618 4619 tcg_gen_trunc_tl_i32(t0, cpu_so); 4620 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4621 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4622 tcg_gen_shli_i32(t0, t0, 3); 4623 tcg_gen_shli_i32(t1, t1, 2); 4624 tcg_gen_shli_i32(dst, dst, 1); 4625 tcg_gen_or_i32(dst, dst, t0); 4626 tcg_gen_or_i32(dst, dst, t1); 4627 4628 tcg_gen_movi_tl(cpu_so, 0); 4629 tcg_gen_movi_tl(cpu_ov, 0); 4630 tcg_gen_movi_tl(cpu_ca, 0); 4631 } 4632 4633 #ifdef TARGET_PPC64 4634 /* mcrxrx */ 4635 static void gen_mcrxrx(DisasContext *ctx) 4636 { 4637 TCGv t0 = tcg_temp_new(); 4638 TCGv t1 = tcg_temp_new(); 4639 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4640 4641 /* copy OV and OV32 */ 4642 tcg_gen_shli_tl(t0, cpu_ov, 1); 4643 tcg_gen_or_tl(t0, t0, cpu_ov32); 4644 tcg_gen_shli_tl(t0, t0, 2); 4645 /* copy CA and CA32 */ 4646 tcg_gen_shli_tl(t1, cpu_ca, 1); 4647 tcg_gen_or_tl(t1, t1, cpu_ca32); 4648 tcg_gen_or_tl(t0, t0, t1); 4649 tcg_gen_trunc_tl_i32(dst, t0); 4650 } 4651 #endif 4652 4653 /* mfcr mfocrf */ 4654 static void gen_mfcr(DisasContext *ctx) 4655 { 4656 uint32_t crm, crn; 4657 4658 if (likely(ctx->opcode & 0x00100000)) { 4659 crm = CRM(ctx->opcode); 4660 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4661 crn = ctz32(crm); 4662 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4663 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4664 cpu_gpr[rD(ctx->opcode)], crn * 4); 4665 } 4666 } else { 4667 TCGv_i32 t0 = tcg_temp_new_i32(); 4668 tcg_gen_mov_i32(t0, cpu_crf[0]); 4669 tcg_gen_shli_i32(t0, t0, 4); 4670 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4671 tcg_gen_shli_i32(t0, t0, 4); 4672 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4673 tcg_gen_shli_i32(t0, t0, 4); 4674 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4675 tcg_gen_shli_i32(t0, t0, 4); 4676 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4677 tcg_gen_shli_i32(t0, t0, 4); 4678 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4679 tcg_gen_shli_i32(t0, t0, 4); 4680 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4681 tcg_gen_shli_i32(t0, t0, 4); 4682 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4683 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4684 } 4685 } 4686 4687 /* mfmsr */ 4688 static void gen_mfmsr(DisasContext *ctx) 4689 { 4690 CHK_SV(ctx); 4691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4692 } 4693 4694 /* mfspr */ 4695 static inline void gen_op_mfspr(DisasContext *ctx) 4696 { 4697 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4698 uint32_t sprn = SPR(ctx->opcode); 4699 4700 #if defined(CONFIG_USER_ONLY) 4701 read_cb = ctx->spr_cb[sprn].uea_read; 4702 #else 4703 if (ctx->pr) { 4704 read_cb = ctx->spr_cb[sprn].uea_read; 4705 } else if (ctx->hv) { 4706 read_cb = ctx->spr_cb[sprn].hea_read; 4707 } else { 4708 read_cb = ctx->spr_cb[sprn].oea_read; 4709 } 4710 #endif 4711 if (likely(read_cb != NULL)) { 4712 if (likely(read_cb != SPR_NOACCESS)) { 4713 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4714 } else { 4715 /* Privilege exception */ 4716 /* 4717 * This is a hack to avoid warnings when running Linux: 4718 * this OS breaks the PowerPC virtualisation model, 4719 * allowing userland application to read the PVR 4720 */ 4721 if (sprn != SPR_PVR) { 4722 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4723 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4724 ctx->cia); 4725 } 4726 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4727 } 4728 } else { 4729 /* ISA 2.07 defines these as no-ops */ 4730 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4731 (sprn >= 808 && sprn <= 811)) { 4732 /* This is a nop */ 4733 return; 4734 } 4735 /* Not defined */ 4736 qemu_log_mask(LOG_GUEST_ERROR, 4737 "Trying to read invalid spr %d (0x%03x) at " 4738 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4739 4740 /* 4741 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4742 * generate a priv, a hv emu or a no-op 4743 */ 4744 if (sprn & 0x10) { 4745 if (ctx->pr) { 4746 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4747 } 4748 } else { 4749 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4750 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4751 } 4752 } 4753 } 4754 } 4755 4756 static void gen_mfspr(DisasContext *ctx) 4757 { 4758 gen_op_mfspr(ctx); 4759 } 4760 4761 /* mftb */ 4762 static void gen_mftb(DisasContext *ctx) 4763 { 4764 gen_op_mfspr(ctx); 4765 } 4766 4767 /* mtcrf mtocrf*/ 4768 static void gen_mtcrf(DisasContext *ctx) 4769 { 4770 uint32_t crm, crn; 4771 4772 crm = CRM(ctx->opcode); 4773 if (likely((ctx->opcode & 0x00100000))) { 4774 if (crm && ((crm & (crm - 1)) == 0)) { 4775 TCGv_i32 temp = tcg_temp_new_i32(); 4776 crn = ctz32(crm); 4777 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4778 tcg_gen_shri_i32(temp, temp, crn * 4); 4779 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4780 } 4781 } else { 4782 TCGv_i32 temp = tcg_temp_new_i32(); 4783 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4784 for (crn = 0 ; crn < 8 ; crn++) { 4785 if (crm & (1 << crn)) { 4786 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4787 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4788 } 4789 } 4790 } 4791 } 4792 4793 /* mtmsr */ 4794 #if defined(TARGET_PPC64) 4795 static void gen_mtmsrd(DisasContext *ctx) 4796 { 4797 if (unlikely(!is_book3s_arch2x(ctx))) { 4798 gen_invalid(ctx); 4799 return; 4800 } 4801 4802 CHK_SV(ctx); 4803 4804 #if !defined(CONFIG_USER_ONLY) 4805 TCGv t0, t1; 4806 target_ulong mask; 4807 4808 t0 = tcg_temp_new(); 4809 t1 = tcg_temp_new(); 4810 4811 translator_io_start(&ctx->base); 4812 4813 if (ctx->opcode & 0x00010000) { 4814 /* L=1 form only updates EE and RI */ 4815 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4816 } else { 4817 /* mtmsrd does not alter HV, S, ME, or LE */ 4818 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4819 (1ULL << MSR_HV)); 4820 /* 4821 * XXX: we need to update nip before the store if we enter 4822 * power saving mode, we will exit the loop directly from 4823 * ppc_store_msr 4824 */ 4825 gen_update_nip(ctx, ctx->base.pc_next); 4826 } 4827 4828 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4829 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4830 tcg_gen_or_tl(t0, t0, t1); 4831 4832 gen_helper_store_msr(cpu_env, t0); 4833 4834 /* Must stop the translation as machine state (may have) changed */ 4835 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4836 #endif /* !defined(CONFIG_USER_ONLY) */ 4837 } 4838 #endif /* defined(TARGET_PPC64) */ 4839 4840 static void gen_mtmsr(DisasContext *ctx) 4841 { 4842 CHK_SV(ctx); 4843 4844 #if !defined(CONFIG_USER_ONLY) 4845 TCGv t0, t1; 4846 target_ulong mask = 0xFFFFFFFF; 4847 4848 t0 = tcg_temp_new(); 4849 t1 = tcg_temp_new(); 4850 4851 translator_io_start(&ctx->base); 4852 if (ctx->opcode & 0x00010000) { 4853 /* L=1 form only updates EE and RI */ 4854 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4855 } else { 4856 /* mtmsr does not alter S, ME, or LE */ 4857 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4858 4859 /* 4860 * XXX: we need to update nip before the store if we enter 4861 * power saving mode, we will exit the loop directly from 4862 * ppc_store_msr 4863 */ 4864 gen_update_nip(ctx, ctx->base.pc_next); 4865 } 4866 4867 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4868 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4869 tcg_gen_or_tl(t0, t0, t1); 4870 4871 gen_helper_store_msr(cpu_env, t0); 4872 4873 /* Must stop the translation as machine state (may have) changed */ 4874 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4875 #endif 4876 } 4877 4878 /* mtspr */ 4879 static void gen_mtspr(DisasContext *ctx) 4880 { 4881 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4882 uint32_t sprn = SPR(ctx->opcode); 4883 4884 #if defined(CONFIG_USER_ONLY) 4885 write_cb = ctx->spr_cb[sprn].uea_write; 4886 #else 4887 if (ctx->pr) { 4888 write_cb = ctx->spr_cb[sprn].uea_write; 4889 } else if (ctx->hv) { 4890 write_cb = ctx->spr_cb[sprn].hea_write; 4891 } else { 4892 write_cb = ctx->spr_cb[sprn].oea_write; 4893 } 4894 #endif 4895 if (likely(write_cb != NULL)) { 4896 if (likely(write_cb != SPR_NOACCESS)) { 4897 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4898 } else { 4899 /* Privilege exception */ 4900 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4901 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4902 ctx->cia); 4903 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4904 } 4905 } else { 4906 /* ISA 2.07 defines these as no-ops */ 4907 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4908 (sprn >= 808 && sprn <= 811)) { 4909 /* This is a nop */ 4910 return; 4911 } 4912 4913 /* Not defined */ 4914 qemu_log_mask(LOG_GUEST_ERROR, 4915 "Trying to write invalid spr %d (0x%03x) at " 4916 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4917 4918 4919 /* 4920 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4921 * generate a priv, a hv emu or a no-op 4922 */ 4923 if (sprn & 0x10) { 4924 if (ctx->pr) { 4925 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4926 } 4927 } else { 4928 if (ctx->pr || sprn == 0) { 4929 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4930 } 4931 } 4932 } 4933 } 4934 4935 #if defined(TARGET_PPC64) 4936 /* setb */ 4937 static void gen_setb(DisasContext *ctx) 4938 { 4939 TCGv_i32 t0 = tcg_temp_new_i32(); 4940 TCGv_i32 t8 = tcg_constant_i32(8); 4941 TCGv_i32 tm1 = tcg_constant_i32(-1); 4942 int crf = crfS(ctx->opcode); 4943 4944 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4945 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4946 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4947 } 4948 #endif 4949 4950 /*** Cache management ***/ 4951 4952 /* dcbf */ 4953 static void gen_dcbf(DisasContext *ctx) 4954 { 4955 /* XXX: specification says this is treated as a load by the MMU */ 4956 TCGv t0; 4957 gen_set_access_type(ctx, ACCESS_CACHE); 4958 t0 = tcg_temp_new(); 4959 gen_addr_reg_index(ctx, t0); 4960 gen_qemu_ld8u(ctx, t0, t0); 4961 } 4962 4963 /* dcbfep (external PID dcbf) */ 4964 static void gen_dcbfep(DisasContext *ctx) 4965 { 4966 /* XXX: specification says this is treated as a load by the MMU */ 4967 TCGv t0; 4968 CHK_SV(ctx); 4969 gen_set_access_type(ctx, ACCESS_CACHE); 4970 t0 = tcg_temp_new(); 4971 gen_addr_reg_index(ctx, t0); 4972 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4973 } 4974 4975 /* dcbi (Supervisor only) */ 4976 static void gen_dcbi(DisasContext *ctx) 4977 { 4978 #if defined(CONFIG_USER_ONLY) 4979 GEN_PRIV(ctx); 4980 #else 4981 TCGv EA, val; 4982 4983 CHK_SV(ctx); 4984 EA = tcg_temp_new(); 4985 gen_set_access_type(ctx, ACCESS_CACHE); 4986 gen_addr_reg_index(ctx, EA); 4987 val = tcg_temp_new(); 4988 /* XXX: specification says this should be treated as a store by the MMU */ 4989 gen_qemu_ld8u(ctx, val, EA); 4990 gen_qemu_st8(ctx, val, EA); 4991 #endif /* defined(CONFIG_USER_ONLY) */ 4992 } 4993 4994 /* dcdst */ 4995 static void gen_dcbst(DisasContext *ctx) 4996 { 4997 /* XXX: specification say this is treated as a load by the MMU */ 4998 TCGv t0; 4999 gen_set_access_type(ctx, ACCESS_CACHE); 5000 t0 = tcg_temp_new(); 5001 gen_addr_reg_index(ctx, t0); 5002 gen_qemu_ld8u(ctx, t0, t0); 5003 } 5004 5005 /* dcbstep (dcbstep External PID version) */ 5006 static void gen_dcbstep(DisasContext *ctx) 5007 { 5008 /* XXX: specification say this is treated as a load by the MMU */ 5009 TCGv t0; 5010 gen_set_access_type(ctx, ACCESS_CACHE); 5011 t0 = tcg_temp_new(); 5012 gen_addr_reg_index(ctx, t0); 5013 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 5014 } 5015 5016 /* dcbt */ 5017 static void gen_dcbt(DisasContext *ctx) 5018 { 5019 /* 5020 * interpreted as no-op 5021 * XXX: specification say this is treated as a load by the MMU but 5022 * does not generate any exception 5023 */ 5024 } 5025 5026 /* dcbtep */ 5027 static void gen_dcbtep(DisasContext *ctx) 5028 { 5029 /* 5030 * interpreted as no-op 5031 * XXX: specification say this is treated as a load by the MMU but 5032 * does not generate any exception 5033 */ 5034 } 5035 5036 /* dcbtst */ 5037 static void gen_dcbtst(DisasContext *ctx) 5038 { 5039 /* 5040 * interpreted as no-op 5041 * XXX: specification say this is treated as a load by the MMU but 5042 * does not generate any exception 5043 */ 5044 } 5045 5046 /* dcbtstep */ 5047 static void gen_dcbtstep(DisasContext *ctx) 5048 { 5049 /* 5050 * interpreted as no-op 5051 * XXX: specification say this is treated as a load by the MMU but 5052 * does not generate any exception 5053 */ 5054 } 5055 5056 /* dcbtls */ 5057 static void gen_dcbtls(DisasContext *ctx) 5058 { 5059 /* Always fails locking the cache */ 5060 TCGv t0 = tcg_temp_new(); 5061 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5062 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5063 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5064 } 5065 5066 /* dcblc */ 5067 static void gen_dcblc(DisasContext *ctx) 5068 { 5069 /* 5070 * interpreted as no-op 5071 */ 5072 } 5073 5074 /* dcbz */ 5075 static void gen_dcbz(DisasContext *ctx) 5076 { 5077 TCGv tcgv_addr; 5078 TCGv_i32 tcgv_op; 5079 5080 gen_set_access_type(ctx, ACCESS_CACHE); 5081 tcgv_addr = tcg_temp_new(); 5082 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5083 gen_addr_reg_index(ctx, tcgv_addr); 5084 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5085 } 5086 5087 /* dcbzep */ 5088 static void gen_dcbzep(DisasContext *ctx) 5089 { 5090 TCGv tcgv_addr; 5091 TCGv_i32 tcgv_op; 5092 5093 gen_set_access_type(ctx, ACCESS_CACHE); 5094 tcgv_addr = tcg_temp_new(); 5095 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5096 gen_addr_reg_index(ctx, tcgv_addr); 5097 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5098 } 5099 5100 /* dst / dstt */ 5101 static void gen_dst(DisasContext *ctx) 5102 { 5103 if (rA(ctx->opcode) == 0) { 5104 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5105 } else { 5106 /* interpreted as no-op */ 5107 } 5108 } 5109 5110 /* dstst /dststt */ 5111 static void gen_dstst(DisasContext *ctx) 5112 { 5113 if (rA(ctx->opcode) == 0) { 5114 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5115 } else { 5116 /* interpreted as no-op */ 5117 } 5118 5119 } 5120 5121 /* dss / dssall */ 5122 static void gen_dss(DisasContext *ctx) 5123 { 5124 /* interpreted as no-op */ 5125 } 5126 5127 /* icbi */ 5128 static void gen_icbi(DisasContext *ctx) 5129 { 5130 TCGv t0; 5131 gen_set_access_type(ctx, ACCESS_CACHE); 5132 t0 = tcg_temp_new(); 5133 gen_addr_reg_index(ctx, t0); 5134 gen_helper_icbi(cpu_env, t0); 5135 } 5136 5137 /* icbiep */ 5138 static void gen_icbiep(DisasContext *ctx) 5139 { 5140 TCGv t0; 5141 gen_set_access_type(ctx, ACCESS_CACHE); 5142 t0 = tcg_temp_new(); 5143 gen_addr_reg_index(ctx, t0); 5144 gen_helper_icbiep(cpu_env, t0); 5145 } 5146 5147 /* Optional: */ 5148 /* dcba */ 5149 static void gen_dcba(DisasContext *ctx) 5150 { 5151 /* 5152 * interpreted as no-op 5153 * XXX: specification say this is treated as a store by the MMU 5154 * but does not generate any exception 5155 */ 5156 } 5157 5158 /*** Segment register manipulation ***/ 5159 /* Supervisor only: */ 5160 5161 /* mfsr */ 5162 static void gen_mfsr(DisasContext *ctx) 5163 { 5164 #if defined(CONFIG_USER_ONLY) 5165 GEN_PRIV(ctx); 5166 #else 5167 TCGv t0; 5168 5169 CHK_SV(ctx); 5170 t0 = tcg_constant_tl(SR(ctx->opcode)); 5171 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5172 #endif /* defined(CONFIG_USER_ONLY) */ 5173 } 5174 5175 /* mfsrin */ 5176 static void gen_mfsrin(DisasContext *ctx) 5177 { 5178 #if defined(CONFIG_USER_ONLY) 5179 GEN_PRIV(ctx); 5180 #else 5181 TCGv t0; 5182 5183 CHK_SV(ctx); 5184 t0 = tcg_temp_new(); 5185 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5186 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5187 #endif /* defined(CONFIG_USER_ONLY) */ 5188 } 5189 5190 /* mtsr */ 5191 static void gen_mtsr(DisasContext *ctx) 5192 { 5193 #if defined(CONFIG_USER_ONLY) 5194 GEN_PRIV(ctx); 5195 #else 5196 TCGv t0; 5197 5198 CHK_SV(ctx); 5199 t0 = tcg_constant_tl(SR(ctx->opcode)); 5200 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5201 #endif /* defined(CONFIG_USER_ONLY) */ 5202 } 5203 5204 /* mtsrin */ 5205 static void gen_mtsrin(DisasContext *ctx) 5206 { 5207 #if defined(CONFIG_USER_ONLY) 5208 GEN_PRIV(ctx); 5209 #else 5210 TCGv t0; 5211 CHK_SV(ctx); 5212 5213 t0 = tcg_temp_new(); 5214 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5215 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5216 #endif /* defined(CONFIG_USER_ONLY) */ 5217 } 5218 5219 #if defined(TARGET_PPC64) 5220 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5221 5222 /* mfsr */ 5223 static void gen_mfsr_64b(DisasContext *ctx) 5224 { 5225 #if defined(CONFIG_USER_ONLY) 5226 GEN_PRIV(ctx); 5227 #else 5228 TCGv t0; 5229 5230 CHK_SV(ctx); 5231 t0 = tcg_constant_tl(SR(ctx->opcode)); 5232 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5233 #endif /* defined(CONFIG_USER_ONLY) */ 5234 } 5235 5236 /* mfsrin */ 5237 static void gen_mfsrin_64b(DisasContext *ctx) 5238 { 5239 #if defined(CONFIG_USER_ONLY) 5240 GEN_PRIV(ctx); 5241 #else 5242 TCGv t0; 5243 5244 CHK_SV(ctx); 5245 t0 = tcg_temp_new(); 5246 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5247 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5248 #endif /* defined(CONFIG_USER_ONLY) */ 5249 } 5250 5251 /* mtsr */ 5252 static void gen_mtsr_64b(DisasContext *ctx) 5253 { 5254 #if defined(CONFIG_USER_ONLY) 5255 GEN_PRIV(ctx); 5256 #else 5257 TCGv t0; 5258 5259 CHK_SV(ctx); 5260 t0 = tcg_constant_tl(SR(ctx->opcode)); 5261 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5262 #endif /* defined(CONFIG_USER_ONLY) */ 5263 } 5264 5265 /* mtsrin */ 5266 static void gen_mtsrin_64b(DisasContext *ctx) 5267 { 5268 #if defined(CONFIG_USER_ONLY) 5269 GEN_PRIV(ctx); 5270 #else 5271 TCGv t0; 5272 5273 CHK_SV(ctx); 5274 t0 = tcg_temp_new(); 5275 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5276 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5277 #endif /* defined(CONFIG_USER_ONLY) */ 5278 } 5279 5280 #endif /* defined(TARGET_PPC64) */ 5281 5282 /*** Lookaside buffer management ***/ 5283 /* Optional & supervisor only: */ 5284 5285 /* tlbia */ 5286 static void gen_tlbia(DisasContext *ctx) 5287 { 5288 #if defined(CONFIG_USER_ONLY) 5289 GEN_PRIV(ctx); 5290 #else 5291 CHK_HV(ctx); 5292 5293 gen_helper_tlbia(cpu_env); 5294 #endif /* defined(CONFIG_USER_ONLY) */ 5295 } 5296 5297 /* tlbsync */ 5298 static void gen_tlbsync(DisasContext *ctx) 5299 { 5300 #if defined(CONFIG_USER_ONLY) 5301 GEN_PRIV(ctx); 5302 #else 5303 5304 if (ctx->gtse) { 5305 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5306 } else { 5307 CHK_HV(ctx); /* Else hypervisor privileged */ 5308 } 5309 5310 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5311 if (ctx->insns_flags & PPC_BOOKE) { 5312 gen_check_tlb_flush(ctx, true); 5313 } 5314 #endif /* defined(CONFIG_USER_ONLY) */ 5315 } 5316 5317 /*** External control ***/ 5318 /* Optional: */ 5319 5320 /* eciwx */ 5321 static void gen_eciwx(DisasContext *ctx) 5322 { 5323 TCGv t0; 5324 /* Should check EAR[E] ! */ 5325 gen_set_access_type(ctx, ACCESS_EXT); 5326 t0 = tcg_temp_new(); 5327 gen_addr_reg_index(ctx, t0); 5328 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5329 DEF_MEMOP(MO_UL | MO_ALIGN)); 5330 } 5331 5332 /* ecowx */ 5333 static void gen_ecowx(DisasContext *ctx) 5334 { 5335 TCGv t0; 5336 /* Should check EAR[E] ! */ 5337 gen_set_access_type(ctx, ACCESS_EXT); 5338 t0 = tcg_temp_new(); 5339 gen_addr_reg_index(ctx, t0); 5340 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5341 DEF_MEMOP(MO_UL | MO_ALIGN)); 5342 } 5343 5344 /* 602 - 603 - G2 TLB management */ 5345 5346 /* tlbld */ 5347 static void gen_tlbld_6xx(DisasContext *ctx) 5348 { 5349 #if defined(CONFIG_USER_ONLY) 5350 GEN_PRIV(ctx); 5351 #else 5352 CHK_SV(ctx); 5353 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5354 #endif /* defined(CONFIG_USER_ONLY) */ 5355 } 5356 5357 /* tlbli */ 5358 static void gen_tlbli_6xx(DisasContext *ctx) 5359 { 5360 #if defined(CONFIG_USER_ONLY) 5361 GEN_PRIV(ctx); 5362 #else 5363 CHK_SV(ctx); 5364 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5365 #endif /* defined(CONFIG_USER_ONLY) */ 5366 } 5367 5368 /* BookE specific instructions */ 5369 5370 /* XXX: not implemented on 440 ? */ 5371 static void gen_mfapidi(DisasContext *ctx) 5372 { 5373 /* XXX: TODO */ 5374 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5375 } 5376 5377 /* XXX: not implemented on 440 ? */ 5378 static void gen_tlbiva(DisasContext *ctx) 5379 { 5380 #if defined(CONFIG_USER_ONLY) 5381 GEN_PRIV(ctx); 5382 #else 5383 TCGv t0; 5384 5385 CHK_SV(ctx); 5386 t0 = tcg_temp_new(); 5387 gen_addr_reg_index(ctx, t0); 5388 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5389 #endif /* defined(CONFIG_USER_ONLY) */ 5390 } 5391 5392 /* All 405 MAC instructions are translated here */ 5393 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5394 int ra, int rb, int rt, int Rc) 5395 { 5396 TCGv t0, t1; 5397 5398 t0 = tcg_temp_new(); 5399 t1 = tcg_temp_new(); 5400 5401 switch (opc3 & 0x0D) { 5402 case 0x05: 5403 /* macchw - macchw. - macchwo - macchwo. */ 5404 /* macchws - macchws. - macchwso - macchwso. */ 5405 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5406 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5407 /* mulchw - mulchw. */ 5408 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5409 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5410 tcg_gen_ext16s_tl(t1, t1); 5411 break; 5412 case 0x04: 5413 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5414 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5415 /* mulchwu - mulchwu. */ 5416 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5417 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5418 tcg_gen_ext16u_tl(t1, t1); 5419 break; 5420 case 0x01: 5421 /* machhw - machhw. - machhwo - machhwo. */ 5422 /* machhws - machhws. - machhwso - machhwso. */ 5423 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5424 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5425 /* mulhhw - mulhhw. */ 5426 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5427 tcg_gen_ext16s_tl(t0, t0); 5428 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5429 tcg_gen_ext16s_tl(t1, t1); 5430 break; 5431 case 0x00: 5432 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5433 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5434 /* mulhhwu - mulhhwu. */ 5435 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5436 tcg_gen_ext16u_tl(t0, t0); 5437 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5438 tcg_gen_ext16u_tl(t1, t1); 5439 break; 5440 case 0x0D: 5441 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5442 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5443 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5444 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5445 /* mullhw - mullhw. */ 5446 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5447 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5448 break; 5449 case 0x0C: 5450 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5451 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5452 /* mullhwu - mullhwu. */ 5453 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5454 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5455 break; 5456 } 5457 if (opc2 & 0x04) { 5458 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5459 tcg_gen_mul_tl(t1, t0, t1); 5460 if (opc2 & 0x02) { 5461 /* nmultiply-and-accumulate (0x0E) */ 5462 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5463 } else { 5464 /* multiply-and-accumulate (0x0C) */ 5465 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5466 } 5467 5468 if (opc3 & 0x12) { 5469 /* Check overflow and/or saturate */ 5470 TCGLabel *l1 = gen_new_label(); 5471 5472 if (opc3 & 0x10) { 5473 /* Start with XER OV disabled, the most likely case */ 5474 tcg_gen_movi_tl(cpu_ov, 0); 5475 } 5476 if (opc3 & 0x01) { 5477 /* Signed */ 5478 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5479 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5480 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5481 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5482 if (opc3 & 0x02) { 5483 /* Saturate */ 5484 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5485 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5486 } 5487 } else { 5488 /* Unsigned */ 5489 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5490 if (opc3 & 0x02) { 5491 /* Saturate */ 5492 tcg_gen_movi_tl(t0, UINT32_MAX); 5493 } 5494 } 5495 if (opc3 & 0x10) { 5496 /* Check overflow */ 5497 tcg_gen_movi_tl(cpu_ov, 1); 5498 tcg_gen_movi_tl(cpu_so, 1); 5499 } 5500 gen_set_label(l1); 5501 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5502 } 5503 } else { 5504 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5505 } 5506 if (unlikely(Rc) != 0) { 5507 /* Update Rc0 */ 5508 gen_set_Rc0(ctx, cpu_gpr[rt]); 5509 } 5510 } 5511 5512 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5513 static void glue(gen_, name)(DisasContext *ctx) \ 5514 { \ 5515 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5516 rD(ctx->opcode), Rc(ctx->opcode)); \ 5517 } 5518 5519 /* macchw - macchw. */ 5520 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5521 /* macchwo - macchwo. */ 5522 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5523 /* macchws - macchws. */ 5524 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5525 /* macchwso - macchwso. */ 5526 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5527 /* macchwsu - macchwsu. */ 5528 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5529 /* macchwsuo - macchwsuo. */ 5530 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5531 /* macchwu - macchwu. */ 5532 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5533 /* macchwuo - macchwuo. */ 5534 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5535 /* machhw - machhw. */ 5536 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5537 /* machhwo - machhwo. */ 5538 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5539 /* machhws - machhws. */ 5540 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5541 /* machhwso - machhwso. */ 5542 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5543 /* machhwsu - machhwsu. */ 5544 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5545 /* machhwsuo - machhwsuo. */ 5546 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5547 /* machhwu - machhwu. */ 5548 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5549 /* machhwuo - machhwuo. */ 5550 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5551 /* maclhw - maclhw. */ 5552 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5553 /* maclhwo - maclhwo. */ 5554 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5555 /* maclhws - maclhws. */ 5556 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5557 /* maclhwso - maclhwso. */ 5558 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5559 /* maclhwu - maclhwu. */ 5560 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5561 /* maclhwuo - maclhwuo. */ 5562 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5563 /* maclhwsu - maclhwsu. */ 5564 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5565 /* maclhwsuo - maclhwsuo. */ 5566 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5567 /* nmacchw - nmacchw. */ 5568 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5569 /* nmacchwo - nmacchwo. */ 5570 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5571 /* nmacchws - nmacchws. */ 5572 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5573 /* nmacchwso - nmacchwso. */ 5574 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5575 /* nmachhw - nmachhw. */ 5576 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5577 /* nmachhwo - nmachhwo. */ 5578 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5579 /* nmachhws - nmachhws. */ 5580 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5581 /* nmachhwso - nmachhwso. */ 5582 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5583 /* nmaclhw - nmaclhw. */ 5584 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5585 /* nmaclhwo - nmaclhwo. */ 5586 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5587 /* nmaclhws - nmaclhws. */ 5588 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5589 /* nmaclhwso - nmaclhwso. */ 5590 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5591 5592 /* mulchw - mulchw. */ 5593 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5594 /* mulchwu - mulchwu. */ 5595 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5596 /* mulhhw - mulhhw. */ 5597 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5598 /* mulhhwu - mulhhwu. */ 5599 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5600 /* mullhw - mullhw. */ 5601 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5602 /* mullhwu - mullhwu. */ 5603 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5604 5605 /* mfdcr */ 5606 static void gen_mfdcr(DisasContext *ctx) 5607 { 5608 #if defined(CONFIG_USER_ONLY) 5609 GEN_PRIV(ctx); 5610 #else 5611 TCGv dcrn; 5612 5613 CHK_SV(ctx); 5614 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5615 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5616 #endif /* defined(CONFIG_USER_ONLY) */ 5617 } 5618 5619 /* mtdcr */ 5620 static void gen_mtdcr(DisasContext *ctx) 5621 { 5622 #if defined(CONFIG_USER_ONLY) 5623 GEN_PRIV(ctx); 5624 #else 5625 TCGv dcrn; 5626 5627 CHK_SV(ctx); 5628 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5629 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5630 #endif /* defined(CONFIG_USER_ONLY) */ 5631 } 5632 5633 /* mfdcrx */ 5634 /* XXX: not implemented on 440 ? */ 5635 static void gen_mfdcrx(DisasContext *ctx) 5636 { 5637 #if defined(CONFIG_USER_ONLY) 5638 GEN_PRIV(ctx); 5639 #else 5640 CHK_SV(ctx); 5641 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5642 cpu_gpr[rA(ctx->opcode)]); 5643 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5644 #endif /* defined(CONFIG_USER_ONLY) */ 5645 } 5646 5647 /* mtdcrx */ 5648 /* XXX: not implemented on 440 ? */ 5649 static void gen_mtdcrx(DisasContext *ctx) 5650 { 5651 #if defined(CONFIG_USER_ONLY) 5652 GEN_PRIV(ctx); 5653 #else 5654 CHK_SV(ctx); 5655 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5656 cpu_gpr[rS(ctx->opcode)]); 5657 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5658 #endif /* defined(CONFIG_USER_ONLY) */ 5659 } 5660 5661 /* dccci */ 5662 static void gen_dccci(DisasContext *ctx) 5663 { 5664 CHK_SV(ctx); 5665 /* interpreted as no-op */ 5666 } 5667 5668 /* dcread */ 5669 static void gen_dcread(DisasContext *ctx) 5670 { 5671 #if defined(CONFIG_USER_ONLY) 5672 GEN_PRIV(ctx); 5673 #else 5674 TCGv EA, val; 5675 5676 CHK_SV(ctx); 5677 gen_set_access_type(ctx, ACCESS_CACHE); 5678 EA = tcg_temp_new(); 5679 gen_addr_reg_index(ctx, EA); 5680 val = tcg_temp_new(); 5681 gen_qemu_ld32u(ctx, val, EA); 5682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5683 #endif /* defined(CONFIG_USER_ONLY) */ 5684 } 5685 5686 /* icbt */ 5687 static void gen_icbt_40x(DisasContext *ctx) 5688 { 5689 /* 5690 * interpreted as no-op 5691 * XXX: specification say this is treated as a load by the MMU but 5692 * does not generate any exception 5693 */ 5694 } 5695 5696 /* iccci */ 5697 static void gen_iccci(DisasContext *ctx) 5698 { 5699 CHK_SV(ctx); 5700 /* interpreted as no-op */ 5701 } 5702 5703 /* icread */ 5704 static void gen_icread(DisasContext *ctx) 5705 { 5706 CHK_SV(ctx); 5707 /* interpreted as no-op */ 5708 } 5709 5710 /* rfci (supervisor only) */ 5711 static void gen_rfci_40x(DisasContext *ctx) 5712 { 5713 #if defined(CONFIG_USER_ONLY) 5714 GEN_PRIV(ctx); 5715 #else 5716 CHK_SV(ctx); 5717 /* Restore CPU state */ 5718 gen_helper_40x_rfci(cpu_env); 5719 ctx->base.is_jmp = DISAS_EXIT; 5720 #endif /* defined(CONFIG_USER_ONLY) */ 5721 } 5722 5723 static void gen_rfci(DisasContext *ctx) 5724 { 5725 #if defined(CONFIG_USER_ONLY) 5726 GEN_PRIV(ctx); 5727 #else 5728 CHK_SV(ctx); 5729 /* Restore CPU state */ 5730 gen_helper_rfci(cpu_env); 5731 ctx->base.is_jmp = DISAS_EXIT; 5732 #endif /* defined(CONFIG_USER_ONLY) */ 5733 } 5734 5735 /* BookE specific */ 5736 5737 /* XXX: not implemented on 440 ? */ 5738 static void gen_rfdi(DisasContext *ctx) 5739 { 5740 #if defined(CONFIG_USER_ONLY) 5741 GEN_PRIV(ctx); 5742 #else 5743 CHK_SV(ctx); 5744 /* Restore CPU state */ 5745 gen_helper_rfdi(cpu_env); 5746 ctx->base.is_jmp = DISAS_EXIT; 5747 #endif /* defined(CONFIG_USER_ONLY) */ 5748 } 5749 5750 /* XXX: not implemented on 440 ? */ 5751 static void gen_rfmci(DisasContext *ctx) 5752 { 5753 #if defined(CONFIG_USER_ONLY) 5754 GEN_PRIV(ctx); 5755 #else 5756 CHK_SV(ctx); 5757 /* Restore CPU state */ 5758 gen_helper_rfmci(cpu_env); 5759 ctx->base.is_jmp = DISAS_EXIT; 5760 #endif /* defined(CONFIG_USER_ONLY) */ 5761 } 5762 5763 /* TLB management - PowerPC 405 implementation */ 5764 5765 /* tlbre */ 5766 static void gen_tlbre_40x(DisasContext *ctx) 5767 { 5768 #if defined(CONFIG_USER_ONLY) 5769 GEN_PRIV(ctx); 5770 #else 5771 CHK_SV(ctx); 5772 switch (rB(ctx->opcode)) { 5773 case 0: 5774 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5775 cpu_gpr[rA(ctx->opcode)]); 5776 break; 5777 case 1: 5778 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5779 cpu_gpr[rA(ctx->opcode)]); 5780 break; 5781 default: 5782 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5783 break; 5784 } 5785 #endif /* defined(CONFIG_USER_ONLY) */ 5786 } 5787 5788 /* tlbsx - tlbsx. */ 5789 static void gen_tlbsx_40x(DisasContext *ctx) 5790 { 5791 #if defined(CONFIG_USER_ONLY) 5792 GEN_PRIV(ctx); 5793 #else 5794 TCGv t0; 5795 5796 CHK_SV(ctx); 5797 t0 = tcg_temp_new(); 5798 gen_addr_reg_index(ctx, t0); 5799 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5800 if (Rc(ctx->opcode)) { 5801 TCGLabel *l1 = gen_new_label(); 5802 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5803 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5804 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5805 gen_set_label(l1); 5806 } 5807 #endif /* defined(CONFIG_USER_ONLY) */ 5808 } 5809 5810 /* tlbwe */ 5811 static void gen_tlbwe_40x(DisasContext *ctx) 5812 { 5813 #if defined(CONFIG_USER_ONLY) 5814 GEN_PRIV(ctx); 5815 #else 5816 CHK_SV(ctx); 5817 5818 switch (rB(ctx->opcode)) { 5819 case 0: 5820 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5821 cpu_gpr[rS(ctx->opcode)]); 5822 break; 5823 case 1: 5824 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5825 cpu_gpr[rS(ctx->opcode)]); 5826 break; 5827 default: 5828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5829 break; 5830 } 5831 #endif /* defined(CONFIG_USER_ONLY) */ 5832 } 5833 5834 /* TLB management - PowerPC 440 implementation */ 5835 5836 /* tlbre */ 5837 static void gen_tlbre_440(DisasContext *ctx) 5838 { 5839 #if defined(CONFIG_USER_ONLY) 5840 GEN_PRIV(ctx); 5841 #else 5842 CHK_SV(ctx); 5843 5844 switch (rB(ctx->opcode)) { 5845 case 0: 5846 case 1: 5847 case 2: 5848 { 5849 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5850 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5851 t0, cpu_gpr[rA(ctx->opcode)]); 5852 } 5853 break; 5854 default: 5855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5856 break; 5857 } 5858 #endif /* defined(CONFIG_USER_ONLY) */ 5859 } 5860 5861 /* tlbsx - tlbsx. */ 5862 static void gen_tlbsx_440(DisasContext *ctx) 5863 { 5864 #if defined(CONFIG_USER_ONLY) 5865 GEN_PRIV(ctx); 5866 #else 5867 TCGv t0; 5868 5869 CHK_SV(ctx); 5870 t0 = tcg_temp_new(); 5871 gen_addr_reg_index(ctx, t0); 5872 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5873 if (Rc(ctx->opcode)) { 5874 TCGLabel *l1 = gen_new_label(); 5875 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5876 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5877 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5878 gen_set_label(l1); 5879 } 5880 #endif /* defined(CONFIG_USER_ONLY) */ 5881 } 5882 5883 /* tlbwe */ 5884 static void gen_tlbwe_440(DisasContext *ctx) 5885 { 5886 #if defined(CONFIG_USER_ONLY) 5887 GEN_PRIV(ctx); 5888 #else 5889 CHK_SV(ctx); 5890 switch (rB(ctx->opcode)) { 5891 case 0: 5892 case 1: 5893 case 2: 5894 { 5895 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5896 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5897 cpu_gpr[rS(ctx->opcode)]); 5898 } 5899 break; 5900 default: 5901 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5902 break; 5903 } 5904 #endif /* defined(CONFIG_USER_ONLY) */ 5905 } 5906 5907 /* TLB management - PowerPC BookE 2.06 implementation */ 5908 5909 /* tlbre */ 5910 static void gen_tlbre_booke206(DisasContext *ctx) 5911 { 5912 #if defined(CONFIG_USER_ONLY) 5913 GEN_PRIV(ctx); 5914 #else 5915 CHK_SV(ctx); 5916 gen_helper_booke206_tlbre(cpu_env); 5917 #endif /* defined(CONFIG_USER_ONLY) */ 5918 } 5919 5920 /* tlbsx - tlbsx. */ 5921 static void gen_tlbsx_booke206(DisasContext *ctx) 5922 { 5923 #if defined(CONFIG_USER_ONLY) 5924 GEN_PRIV(ctx); 5925 #else 5926 TCGv t0; 5927 5928 CHK_SV(ctx); 5929 if (rA(ctx->opcode)) { 5930 t0 = tcg_temp_new(); 5931 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5932 } else { 5933 t0 = cpu_gpr[rB(ctx->opcode)]; 5934 } 5935 gen_helper_booke206_tlbsx(cpu_env, t0); 5936 #endif /* defined(CONFIG_USER_ONLY) */ 5937 } 5938 5939 /* tlbwe */ 5940 static void gen_tlbwe_booke206(DisasContext *ctx) 5941 { 5942 #if defined(CONFIG_USER_ONLY) 5943 GEN_PRIV(ctx); 5944 #else 5945 CHK_SV(ctx); 5946 gen_helper_booke206_tlbwe(cpu_env); 5947 #endif /* defined(CONFIG_USER_ONLY) */ 5948 } 5949 5950 static void gen_tlbivax_booke206(DisasContext *ctx) 5951 { 5952 #if defined(CONFIG_USER_ONLY) 5953 GEN_PRIV(ctx); 5954 #else 5955 TCGv t0; 5956 5957 CHK_SV(ctx); 5958 t0 = tcg_temp_new(); 5959 gen_addr_reg_index(ctx, t0); 5960 gen_helper_booke206_tlbivax(cpu_env, t0); 5961 #endif /* defined(CONFIG_USER_ONLY) */ 5962 } 5963 5964 static void gen_tlbilx_booke206(DisasContext *ctx) 5965 { 5966 #if defined(CONFIG_USER_ONLY) 5967 GEN_PRIV(ctx); 5968 #else 5969 TCGv t0; 5970 5971 CHK_SV(ctx); 5972 t0 = tcg_temp_new(); 5973 gen_addr_reg_index(ctx, t0); 5974 5975 switch ((ctx->opcode >> 21) & 0x3) { 5976 case 0: 5977 gen_helper_booke206_tlbilx0(cpu_env, t0); 5978 break; 5979 case 1: 5980 gen_helper_booke206_tlbilx1(cpu_env, t0); 5981 break; 5982 case 3: 5983 gen_helper_booke206_tlbilx3(cpu_env, t0); 5984 break; 5985 default: 5986 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5987 break; 5988 } 5989 #endif /* defined(CONFIG_USER_ONLY) */ 5990 } 5991 5992 /* wrtee */ 5993 static void gen_wrtee(DisasContext *ctx) 5994 { 5995 #if defined(CONFIG_USER_ONLY) 5996 GEN_PRIV(ctx); 5997 #else 5998 TCGv t0; 5999 6000 CHK_SV(ctx); 6001 t0 = tcg_temp_new(); 6002 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6003 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6004 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6005 gen_ppc_maybe_interrupt(ctx); 6006 /* 6007 * Stop translation to have a chance to raise an exception if we 6008 * just set msr_ee to 1 6009 */ 6010 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6011 #endif /* defined(CONFIG_USER_ONLY) */ 6012 } 6013 6014 /* wrteei */ 6015 static void gen_wrteei(DisasContext *ctx) 6016 { 6017 #if defined(CONFIG_USER_ONLY) 6018 GEN_PRIV(ctx); 6019 #else 6020 CHK_SV(ctx); 6021 if (ctx->opcode & 0x00008000) { 6022 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6023 gen_ppc_maybe_interrupt(ctx); 6024 /* Stop translation to have a chance to raise an exception */ 6025 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6026 } else { 6027 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6028 } 6029 #endif /* defined(CONFIG_USER_ONLY) */ 6030 } 6031 6032 /* PowerPC 440 specific instructions */ 6033 6034 /* dlmzb */ 6035 static void gen_dlmzb(DisasContext *ctx) 6036 { 6037 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6038 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6039 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6040 } 6041 6042 /* mbar replaces eieio on 440 */ 6043 static void gen_mbar(DisasContext *ctx) 6044 { 6045 /* interpreted as no-op */ 6046 } 6047 6048 /* msync replaces sync on 440 */ 6049 static void gen_msync_4xx(DisasContext *ctx) 6050 { 6051 /* Only e500 seems to treat reserved bits as invalid */ 6052 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6053 (ctx->opcode & 0x03FFF801)) { 6054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6055 } 6056 /* otherwise interpreted as no-op */ 6057 } 6058 6059 /* icbt */ 6060 static void gen_icbt_440(DisasContext *ctx) 6061 { 6062 /* 6063 * interpreted as no-op 6064 * XXX: specification say this is treated as a load by the MMU but 6065 * does not generate any exception 6066 */ 6067 } 6068 6069 #if defined(TARGET_PPC64) 6070 static void gen_maddld(DisasContext *ctx) 6071 { 6072 TCGv_i64 t1 = tcg_temp_new_i64(); 6073 6074 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6075 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6076 } 6077 6078 /* maddhd maddhdu */ 6079 static void gen_maddhd_maddhdu(DisasContext *ctx) 6080 { 6081 TCGv_i64 lo = tcg_temp_new_i64(); 6082 TCGv_i64 hi = tcg_temp_new_i64(); 6083 TCGv_i64 t1 = tcg_temp_new_i64(); 6084 6085 if (Rc(ctx->opcode)) { 6086 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6087 cpu_gpr[rB(ctx->opcode)]); 6088 tcg_gen_movi_i64(t1, 0); 6089 } else { 6090 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6091 cpu_gpr[rB(ctx->opcode)]); 6092 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6093 } 6094 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6095 cpu_gpr[rC(ctx->opcode)], t1); 6096 } 6097 #endif /* defined(TARGET_PPC64) */ 6098 6099 static void gen_tbegin(DisasContext *ctx) 6100 { 6101 if (unlikely(!ctx->tm_enabled)) { 6102 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6103 return; 6104 } 6105 gen_helper_tbegin(cpu_env); 6106 } 6107 6108 #define GEN_TM_NOOP(name) \ 6109 static inline void gen_##name(DisasContext *ctx) \ 6110 { \ 6111 if (unlikely(!ctx->tm_enabled)) { \ 6112 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6113 return; \ 6114 } \ 6115 /* \ 6116 * Because tbegin always fails in QEMU, these user \ 6117 * space instructions all have a simple implementation: \ 6118 * \ 6119 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6120 * = 0b0 || 0b00 || 0b0 \ 6121 */ \ 6122 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6123 } 6124 6125 GEN_TM_NOOP(tend); 6126 GEN_TM_NOOP(tabort); 6127 GEN_TM_NOOP(tabortwc); 6128 GEN_TM_NOOP(tabortwci); 6129 GEN_TM_NOOP(tabortdc); 6130 GEN_TM_NOOP(tabortdci); 6131 GEN_TM_NOOP(tsr); 6132 6133 static inline void gen_cp_abort(DisasContext *ctx) 6134 { 6135 /* Do Nothing */ 6136 } 6137 6138 #define GEN_CP_PASTE_NOOP(name) \ 6139 static inline void gen_##name(DisasContext *ctx) \ 6140 { \ 6141 /* \ 6142 * Generate invalid exception until we have an \ 6143 * implementation of the copy paste facility \ 6144 */ \ 6145 gen_invalid(ctx); \ 6146 } 6147 6148 GEN_CP_PASTE_NOOP(copy) 6149 GEN_CP_PASTE_NOOP(paste) 6150 6151 static void gen_tcheck(DisasContext *ctx) 6152 { 6153 if (unlikely(!ctx->tm_enabled)) { 6154 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6155 return; 6156 } 6157 /* 6158 * Because tbegin always fails, the tcheck implementation is 6159 * simple: 6160 * 6161 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6162 * = 0b1 || 0b00 || 0b0 6163 */ 6164 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6165 } 6166 6167 #if defined(CONFIG_USER_ONLY) 6168 #define GEN_TM_PRIV_NOOP(name) \ 6169 static inline void gen_##name(DisasContext *ctx) \ 6170 { \ 6171 gen_priv_opc(ctx); \ 6172 } 6173 6174 #else 6175 6176 #define GEN_TM_PRIV_NOOP(name) \ 6177 static inline void gen_##name(DisasContext *ctx) \ 6178 { \ 6179 CHK_SV(ctx); \ 6180 if (unlikely(!ctx->tm_enabled)) { \ 6181 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6182 return; \ 6183 } \ 6184 /* \ 6185 * Because tbegin always fails, the implementation is \ 6186 * simple: \ 6187 * \ 6188 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6189 * = 0b0 || 0b00 | 0b0 \ 6190 */ \ 6191 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6192 } 6193 6194 #endif 6195 6196 GEN_TM_PRIV_NOOP(treclaim); 6197 GEN_TM_PRIV_NOOP(trechkpt); 6198 6199 static inline void get_fpr(TCGv_i64 dst, int regno) 6200 { 6201 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6202 } 6203 6204 static inline void set_fpr(int regno, TCGv_i64 src) 6205 { 6206 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6207 /* 6208 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6209 * corresponding to the target FPR was undefined. However, 6210 * most (if not all) real hardware were setting the result to 0. 6211 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6212 * to be 0. 6213 */ 6214 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6215 } 6216 6217 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6218 { 6219 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6220 } 6221 6222 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6223 { 6224 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6225 } 6226 6227 /* 6228 * Helpers for decodetree used by !function for decoding arguments. 6229 */ 6230 static int times_2(DisasContext *ctx, int x) 6231 { 6232 return x * 2; 6233 } 6234 6235 static int times_4(DisasContext *ctx, int x) 6236 { 6237 return x * 4; 6238 } 6239 6240 static int times_16(DisasContext *ctx, int x) 6241 { 6242 return x * 16; 6243 } 6244 6245 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6246 { 6247 return deposit64(0xfffffffffffffe00, 3, 6, x); 6248 } 6249 6250 /* 6251 * Helpers for trans_* functions to check for specific insns flags. 6252 * Use token pasting to ensure that we use the proper flag with the 6253 * proper variable. 6254 */ 6255 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6256 do { \ 6257 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6258 return false; \ 6259 } \ 6260 } while (0) 6261 6262 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6263 do { \ 6264 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6265 return false; \ 6266 } \ 6267 } while (0) 6268 6269 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6270 #if TARGET_LONG_BITS == 32 6271 # define REQUIRE_64BIT(CTX) return false 6272 #else 6273 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6274 #endif 6275 6276 #define REQUIRE_VECTOR(CTX) \ 6277 do { \ 6278 if (unlikely(!(CTX)->altivec_enabled)) { \ 6279 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6280 return true; \ 6281 } \ 6282 } while (0) 6283 6284 #define REQUIRE_VSX(CTX) \ 6285 do { \ 6286 if (unlikely(!(CTX)->vsx_enabled)) { \ 6287 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6288 return true; \ 6289 } \ 6290 } while (0) 6291 6292 #define REQUIRE_FPU(ctx) \ 6293 do { \ 6294 if (unlikely(!(ctx)->fpu_enabled)) { \ 6295 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6296 return true; \ 6297 } \ 6298 } while (0) 6299 6300 #if !defined(CONFIG_USER_ONLY) 6301 #define REQUIRE_SV(CTX) \ 6302 do { \ 6303 if (unlikely((CTX)->pr)) { \ 6304 gen_priv_opc(CTX); \ 6305 return true; \ 6306 } \ 6307 } while (0) 6308 6309 #define REQUIRE_HV(CTX) \ 6310 do { \ 6311 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6312 gen_priv_opc(CTX); \ 6313 return true; \ 6314 } \ 6315 } while (0) 6316 #else 6317 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6318 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6319 #endif 6320 6321 /* 6322 * Helpers for implementing sets of trans_* functions. 6323 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6324 */ 6325 #define TRANS(NAME, FUNC, ...) \ 6326 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6327 { return FUNC(ctx, a, __VA_ARGS__); } 6328 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6329 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6330 { \ 6331 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6332 return FUNC(ctx, a, __VA_ARGS__); \ 6333 } 6334 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6335 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6336 { \ 6337 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6338 return FUNC(ctx, a, __VA_ARGS__); \ 6339 } 6340 6341 #define TRANS64(NAME, FUNC, ...) \ 6342 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6343 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6344 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6345 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6346 { \ 6347 REQUIRE_64BIT(ctx); \ 6348 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6349 return FUNC(ctx, a, __VA_ARGS__); \ 6350 } 6351 6352 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6353 6354 6355 #include "decode-insn32.c.inc" 6356 #include "decode-insn64.c.inc" 6357 #include "power8-pmu-regs.c.inc" 6358 6359 /* 6360 * Incorporate CIA into the constant when R=1. 6361 * Validate that when R=1, RA=0. 6362 */ 6363 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6364 { 6365 d->rt = a->rt; 6366 d->ra = a->ra; 6367 d->si = a->si; 6368 if (a->r) { 6369 if (unlikely(a->ra != 0)) { 6370 gen_invalid(ctx); 6371 return false; 6372 } 6373 d->si += ctx->cia; 6374 } 6375 return true; 6376 } 6377 6378 #include "translate/fixedpoint-impl.c.inc" 6379 6380 #include "translate/fp-impl.c.inc" 6381 6382 #include "translate/vmx-impl.c.inc" 6383 6384 #include "translate/vsx-impl.c.inc" 6385 6386 #include "translate/dfp-impl.c.inc" 6387 6388 #include "translate/spe-impl.c.inc" 6389 6390 #include "translate/branch-impl.c.inc" 6391 6392 #include "translate/processor-ctrl-impl.c.inc" 6393 6394 #include "translate/storage-ctrl-impl.c.inc" 6395 6396 /* Handles lfdp */ 6397 static void gen_dform39(DisasContext *ctx) 6398 { 6399 if ((ctx->opcode & 0x3) == 0) { 6400 if (ctx->insns_flags2 & PPC2_ISA205) { 6401 return gen_lfdp(ctx); 6402 } 6403 } 6404 return gen_invalid(ctx); 6405 } 6406 6407 /* Handles stfdp */ 6408 static void gen_dform3D(DisasContext *ctx) 6409 { 6410 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6411 /* stfdp */ 6412 if (ctx->insns_flags2 & PPC2_ISA205) { 6413 return gen_stfdp(ctx); 6414 } 6415 } 6416 return gen_invalid(ctx); 6417 } 6418 6419 #if defined(TARGET_PPC64) 6420 /* brd */ 6421 static void gen_brd(DisasContext *ctx) 6422 { 6423 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6424 } 6425 6426 /* brw */ 6427 static void gen_brw(DisasContext *ctx) 6428 { 6429 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6430 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6431 6432 } 6433 6434 /* brh */ 6435 static void gen_brh(DisasContext *ctx) 6436 { 6437 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6438 TCGv_i64 t1 = tcg_temp_new_i64(); 6439 TCGv_i64 t2 = tcg_temp_new_i64(); 6440 6441 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6442 tcg_gen_and_i64(t2, t1, mask); 6443 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6444 tcg_gen_shli_i64(t1, t1, 8); 6445 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6446 } 6447 #endif 6448 6449 static opcode_t opcodes[] = { 6450 #if defined(TARGET_PPC64) 6451 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6452 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6453 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6454 #endif 6455 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6456 #if defined(TARGET_PPC64) 6457 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6458 #endif 6459 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6460 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6461 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6462 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6464 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6465 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6466 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6467 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6468 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6469 #if defined(TARGET_PPC64) 6470 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6471 #endif 6472 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6473 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6474 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6477 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6478 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6479 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6480 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6481 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6482 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6483 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6484 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6485 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6486 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6487 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6488 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6489 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6490 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6491 #if defined(TARGET_PPC64) 6492 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6493 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6494 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6495 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6496 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6497 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6498 #endif 6499 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6500 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6501 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6502 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6503 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6504 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6505 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6506 #if defined(TARGET_PPC64) 6507 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6508 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6509 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6510 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6511 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6512 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6513 PPC_NONE, PPC2_ISA300), 6514 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6515 PPC_NONE, PPC2_ISA300), 6516 #endif 6517 /* handles lfdp, lxsd, lxssp */ 6518 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6519 /* handles stfdp, stxsd, stxssp */ 6520 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6521 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6522 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6523 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6524 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6525 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6526 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6527 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6528 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6529 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6530 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6531 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6532 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6533 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6534 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6535 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6536 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6537 #if defined(TARGET_PPC64) 6538 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6539 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6540 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6541 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6542 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6543 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6544 #endif 6545 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6546 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6547 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6548 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6549 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6550 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6551 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6552 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6553 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6554 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6555 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6556 #if defined(TARGET_PPC64) 6557 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6558 #if !defined(CONFIG_USER_ONLY) 6559 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6560 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6561 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6562 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6563 #endif 6564 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6565 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6566 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6567 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6568 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6569 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6570 #endif 6571 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6572 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6573 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6574 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6575 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6576 #if defined(TARGET_PPC64) 6577 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6578 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6579 #endif 6580 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6581 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6582 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6583 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6584 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6585 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6586 #if defined(TARGET_PPC64) 6587 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6588 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6589 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6590 #endif 6591 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6592 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6593 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6594 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6595 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6596 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6597 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6598 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6599 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6600 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6601 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6602 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6603 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6604 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6605 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6606 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6607 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6608 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6609 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6610 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6611 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6612 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6613 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6614 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6615 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6616 #if defined(TARGET_PPC64) 6617 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6618 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6619 PPC_SEGMENT_64B), 6620 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6621 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6622 PPC_SEGMENT_64B), 6623 #endif 6624 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6625 /* 6626 * XXX Those instructions will need to be handled differently for 6627 * different ISA versions 6628 */ 6629 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6630 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6631 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6632 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6633 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6634 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6635 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6636 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6637 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6638 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6639 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6640 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6641 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6642 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6643 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6644 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6645 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6646 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6647 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6648 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6649 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6650 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6651 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6652 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6653 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6654 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6655 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6656 PPC_NONE, PPC2_BOOKE206), 6657 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6658 PPC_NONE, PPC2_BOOKE206), 6659 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6660 PPC_NONE, PPC2_BOOKE206), 6661 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6662 PPC_NONE, PPC2_BOOKE206), 6663 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6664 PPC_NONE, PPC2_BOOKE206), 6665 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6666 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6667 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6668 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6669 PPC_BOOKE, PPC2_BOOKE206), 6670 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6671 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6672 PPC_BOOKE, PPC2_BOOKE206), 6673 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6674 PPC_440_SPEC), 6675 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6676 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6677 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6678 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6679 #if defined(TARGET_PPC64) 6680 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6681 PPC2_ISA300), 6682 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6683 #endif 6684 6685 #undef GEN_INT_ARITH_ADD 6686 #undef GEN_INT_ARITH_ADD_CONST 6687 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6688 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6689 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6690 add_ca, compute_ca, compute_ov) \ 6691 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6692 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6693 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6694 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6695 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6696 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6697 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6698 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6699 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6700 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6701 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6702 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6703 6704 #undef GEN_INT_ARITH_DIVW 6705 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6706 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6707 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6708 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6709 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6710 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6711 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6713 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6714 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6715 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6716 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6717 6718 #if defined(TARGET_PPC64) 6719 #undef GEN_INT_ARITH_DIVD 6720 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6721 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6722 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6723 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6724 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6725 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6726 6727 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6728 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6729 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6730 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6731 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6732 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6733 6734 #undef GEN_INT_ARITH_MUL_HELPER 6735 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6736 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6737 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6738 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6739 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6740 #endif 6741 6742 #undef GEN_INT_ARITH_SUBF 6743 #undef GEN_INT_ARITH_SUBF_CONST 6744 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6745 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6746 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6747 add_ca, compute_ca, compute_ov) \ 6748 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6749 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6750 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6751 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6752 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6753 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6754 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6755 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6756 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6757 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6758 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6759 6760 #undef GEN_LOGICAL1 6761 #undef GEN_LOGICAL2 6762 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6763 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6764 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6765 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6766 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6767 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6768 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6769 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6770 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6771 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6772 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6773 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6774 #if defined(TARGET_PPC64) 6775 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6776 #endif 6777 6778 #if defined(TARGET_PPC64) 6779 #undef GEN_PPC64_R2 6780 #undef GEN_PPC64_R4 6781 #define GEN_PPC64_R2(name, opc1, opc2) \ 6782 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6783 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6784 PPC_64B) 6785 #define GEN_PPC64_R4(name, opc1, opc2) \ 6786 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6787 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6788 PPC_64B), \ 6789 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6790 PPC_64B), \ 6791 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6792 PPC_64B) 6793 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6794 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6795 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6796 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6797 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6798 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6799 #endif 6800 6801 #undef GEN_LDX_E 6802 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6803 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6804 6805 #if defined(TARGET_PPC64) 6806 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6807 6808 /* HV/P7 and later only */ 6809 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6810 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6811 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6812 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6813 #endif 6814 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6815 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6816 6817 /* External PID based load */ 6818 #undef GEN_LDEPX 6819 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6820 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6821 0x00000001, PPC_NONE, PPC2_BOOKE206), 6822 6823 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6824 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6825 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6826 #if defined(TARGET_PPC64) 6827 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6828 #endif 6829 6830 #undef GEN_STX_E 6831 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6832 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6833 6834 #if defined(TARGET_PPC64) 6835 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6836 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6837 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6838 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6839 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6840 #endif 6841 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6842 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6843 6844 #undef GEN_STEPX 6845 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6846 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6847 0x00000001, PPC_NONE, PPC2_BOOKE206), 6848 6849 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6850 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6851 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6852 #if defined(TARGET_PPC64) 6853 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6854 #endif 6855 6856 #undef GEN_CRLOGIC 6857 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6858 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6859 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6860 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6861 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6862 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6863 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6864 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6865 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6866 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6867 6868 #undef GEN_MAC_HANDLER 6869 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6870 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6871 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6872 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6873 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6874 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6875 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6876 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6877 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6878 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6879 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6880 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6881 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6882 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6883 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6884 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6885 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6886 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6887 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6888 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6889 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6890 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6891 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6892 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6893 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6894 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6895 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6896 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6897 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6898 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6899 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6900 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6901 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6902 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6903 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6904 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6905 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6906 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6907 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6908 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6909 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6910 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6911 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6912 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6913 6914 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6915 PPC_NONE, PPC2_TM), 6916 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6917 PPC_NONE, PPC2_TM), 6918 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6919 PPC_NONE, PPC2_TM), 6920 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6921 PPC_NONE, PPC2_TM), 6922 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6923 PPC_NONE, PPC2_TM), 6924 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6925 PPC_NONE, PPC2_TM), 6926 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6927 PPC_NONE, PPC2_TM), 6928 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6929 PPC_NONE, PPC2_TM), 6930 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6931 PPC_NONE, PPC2_TM), 6932 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6933 PPC_NONE, PPC2_TM), 6934 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6935 PPC_NONE, PPC2_TM), 6936 6937 #include "translate/fp-ops.c.inc" 6938 6939 #include "translate/vmx-ops.c.inc" 6940 6941 #include "translate/vsx-ops.c.inc" 6942 6943 #include "translate/spe-ops.c.inc" 6944 }; 6945 6946 /*****************************************************************************/ 6947 /* Opcode types */ 6948 enum { 6949 PPC_DIRECT = 0, /* Opcode routine */ 6950 PPC_INDIRECT = 1, /* Indirect opcode table */ 6951 }; 6952 6953 #define PPC_OPCODE_MASK 0x3 6954 6955 static inline int is_indirect_opcode(void *handler) 6956 { 6957 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6958 } 6959 6960 static inline opc_handler_t **ind_table(void *handler) 6961 { 6962 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6963 } 6964 6965 /* Instruction table creation */ 6966 /* Opcodes tables creation */ 6967 static void fill_new_table(opc_handler_t **table, int len) 6968 { 6969 int i; 6970 6971 for (i = 0; i < len; i++) { 6972 table[i] = &invalid_handler; 6973 } 6974 } 6975 6976 static int create_new_table(opc_handler_t **table, unsigned char idx) 6977 { 6978 opc_handler_t **tmp; 6979 6980 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6981 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6982 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6983 6984 return 0; 6985 } 6986 6987 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6988 opc_handler_t *handler) 6989 { 6990 if (table[idx] != &invalid_handler) { 6991 return -1; 6992 } 6993 table[idx] = handler; 6994 6995 return 0; 6996 } 6997 6998 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6999 unsigned char idx, opc_handler_t *handler) 7000 { 7001 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 7002 printf("*** ERROR: opcode %02x already assigned in main " 7003 "opcode table\n", idx); 7004 return -1; 7005 } 7006 7007 return 0; 7008 } 7009 7010 static int register_ind_in_table(opc_handler_t **table, 7011 unsigned char idx1, unsigned char idx2, 7012 opc_handler_t *handler) 7013 { 7014 if (table[idx1] == &invalid_handler) { 7015 if (create_new_table(table, idx1) < 0) { 7016 printf("*** ERROR: unable to create indirect table " 7017 "idx=%02x\n", idx1); 7018 return -1; 7019 } 7020 } else { 7021 if (!is_indirect_opcode(table[idx1])) { 7022 printf("*** ERROR: idx %02x already assigned to a direct " 7023 "opcode\n", idx1); 7024 return -1; 7025 } 7026 } 7027 if (handler != NULL && 7028 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7029 printf("*** ERROR: opcode %02x already assigned in " 7030 "opcode table %02x\n", idx2, idx1); 7031 return -1; 7032 } 7033 7034 return 0; 7035 } 7036 7037 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7038 unsigned char idx1, unsigned char idx2, 7039 opc_handler_t *handler) 7040 { 7041 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7042 } 7043 7044 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7045 unsigned char idx1, unsigned char idx2, 7046 unsigned char idx3, opc_handler_t *handler) 7047 { 7048 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7049 printf("*** ERROR: unable to join indirect table idx " 7050 "[%02x-%02x]\n", idx1, idx2); 7051 return -1; 7052 } 7053 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7054 handler) < 0) { 7055 printf("*** ERROR: unable to insert opcode " 7056 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7057 return -1; 7058 } 7059 7060 return 0; 7061 } 7062 7063 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7064 unsigned char idx1, unsigned char idx2, 7065 unsigned char idx3, unsigned char idx4, 7066 opc_handler_t *handler) 7067 { 7068 opc_handler_t **table; 7069 7070 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7071 printf("*** ERROR: unable to join indirect table idx " 7072 "[%02x-%02x]\n", idx1, idx2); 7073 return -1; 7074 } 7075 table = ind_table(ppc_opcodes[idx1]); 7076 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7077 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7078 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7079 return -1; 7080 } 7081 table = ind_table(table[idx2]); 7082 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7083 printf("*** ERROR: unable to insert opcode " 7084 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7085 return -1; 7086 } 7087 return 0; 7088 } 7089 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7090 { 7091 if (insn->opc2 != 0xFF) { 7092 if (insn->opc3 != 0xFF) { 7093 if (insn->opc4 != 0xFF) { 7094 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7095 insn->opc3, insn->opc4, 7096 &insn->handler) < 0) { 7097 return -1; 7098 } 7099 } else { 7100 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7101 insn->opc3, &insn->handler) < 0) { 7102 return -1; 7103 } 7104 } 7105 } else { 7106 if (register_ind_insn(ppc_opcodes, insn->opc1, 7107 insn->opc2, &insn->handler) < 0) { 7108 return -1; 7109 } 7110 } 7111 } else { 7112 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7113 return -1; 7114 } 7115 } 7116 7117 return 0; 7118 } 7119 7120 static int test_opcode_table(opc_handler_t **table, int len) 7121 { 7122 int i, count, tmp; 7123 7124 for (i = 0, count = 0; i < len; i++) { 7125 /* Consistency fixup */ 7126 if (table[i] == NULL) { 7127 table[i] = &invalid_handler; 7128 } 7129 if (table[i] != &invalid_handler) { 7130 if (is_indirect_opcode(table[i])) { 7131 tmp = test_opcode_table(ind_table(table[i]), 7132 PPC_CPU_INDIRECT_OPCODES_LEN); 7133 if (tmp == 0) { 7134 free(table[i]); 7135 table[i] = &invalid_handler; 7136 } else { 7137 count++; 7138 } 7139 } else { 7140 count++; 7141 } 7142 } 7143 } 7144 7145 return count; 7146 } 7147 7148 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7149 { 7150 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7151 printf("*** WARNING: no opcode defined !\n"); 7152 } 7153 } 7154 7155 /*****************************************************************************/ 7156 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7157 { 7158 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7159 opcode_t *opc; 7160 7161 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7162 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7163 if (((opc->handler.type & pcc->insns_flags) != 0) || 7164 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7165 if (register_insn(cpu->opcodes, opc) < 0) { 7166 error_setg(errp, "ERROR initializing PowerPC instruction " 7167 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7168 opc->opc3); 7169 return; 7170 } 7171 } 7172 } 7173 fix_opcode_tables(cpu->opcodes); 7174 fflush(stdout); 7175 fflush(stderr); 7176 } 7177 7178 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7179 { 7180 opc_handler_t **table, **table_2; 7181 int i, j, k; 7182 7183 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7184 if (cpu->opcodes[i] == &invalid_handler) { 7185 continue; 7186 } 7187 if (is_indirect_opcode(cpu->opcodes[i])) { 7188 table = ind_table(cpu->opcodes[i]); 7189 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7190 if (table[j] == &invalid_handler) { 7191 continue; 7192 } 7193 if (is_indirect_opcode(table[j])) { 7194 table_2 = ind_table(table[j]); 7195 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7196 if (table_2[k] != &invalid_handler && 7197 is_indirect_opcode(table_2[k])) { 7198 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7199 ~PPC_INDIRECT)); 7200 } 7201 } 7202 g_free((opc_handler_t *)((uintptr_t)table[j] & 7203 ~PPC_INDIRECT)); 7204 } 7205 } 7206 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7207 ~PPC_INDIRECT)); 7208 } 7209 } 7210 } 7211 7212 int ppc_fixup_cpu(PowerPCCPU *cpu) 7213 { 7214 CPUPPCState *env = &cpu->env; 7215 7216 /* 7217 * TCG doesn't (yet) emulate some groups of instructions that are 7218 * implemented on some otherwise supported CPUs (e.g. VSX and 7219 * decimal floating point instructions on POWER7). We remove 7220 * unsupported instruction groups from the cpu state's instruction 7221 * masks and hope the guest can cope. For at least the pseries 7222 * machine, the unavailability of these instructions can be 7223 * advertised to the guest via the device tree. 7224 */ 7225 if ((env->insns_flags & ~PPC_TCG_INSNS) 7226 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7227 warn_report("Disabling some instructions which are not " 7228 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7229 env->insns_flags & ~PPC_TCG_INSNS, 7230 env->insns_flags2 & ~PPC_TCG_INSNS2); 7231 } 7232 env->insns_flags &= PPC_TCG_INSNS; 7233 env->insns_flags2 &= PPC_TCG_INSNS2; 7234 return 0; 7235 } 7236 7237 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7238 { 7239 opc_handler_t **table, *handler; 7240 uint32_t inval; 7241 7242 ctx->opcode = insn; 7243 7244 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7245 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7246 ctx->le_mode ? "little" : "big"); 7247 7248 table = cpu->opcodes; 7249 handler = table[opc1(insn)]; 7250 if (is_indirect_opcode(handler)) { 7251 table = ind_table(handler); 7252 handler = table[opc2(insn)]; 7253 if (is_indirect_opcode(handler)) { 7254 table = ind_table(handler); 7255 handler = table[opc3(insn)]; 7256 if (is_indirect_opcode(handler)) { 7257 table = ind_table(handler); 7258 handler = table[opc4(insn)]; 7259 } 7260 } 7261 } 7262 7263 /* Is opcode *REALLY* valid ? */ 7264 if (unlikely(handler->handler == &gen_invalid)) { 7265 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7266 "%02x - %02x - %02x - %02x (%08x) " 7267 TARGET_FMT_lx "\n", 7268 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7269 insn, ctx->cia); 7270 return false; 7271 } 7272 7273 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7274 && Rc(insn))) { 7275 inval = handler->inval2; 7276 } else { 7277 inval = handler->inval1; 7278 } 7279 7280 if (unlikely((insn & inval) != 0)) { 7281 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7282 "%02x - %02x - %02x - %02x (%08x) " 7283 TARGET_FMT_lx "\n", insn & inval, 7284 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7285 insn, ctx->cia); 7286 return false; 7287 } 7288 7289 handler->handler(ctx); 7290 return true; 7291 } 7292 7293 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7294 { 7295 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7296 CPUPPCState *env = cs->env_ptr; 7297 uint32_t hflags = ctx->base.tb->flags; 7298 7299 ctx->spr_cb = env->spr_cb; 7300 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7301 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7302 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7303 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7304 ctx->insns_flags = env->insns_flags; 7305 ctx->insns_flags2 = env->insns_flags2; 7306 ctx->access_type = -1; 7307 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7308 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7309 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7310 ctx->flags = env->flags; 7311 #if defined(TARGET_PPC64) 7312 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7313 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7314 #endif 7315 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7316 || env->mmu_model & POWERPC_MMU_64; 7317 7318 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7319 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7320 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7321 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7322 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7323 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7324 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7325 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7326 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7327 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7328 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7329 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7330 7331 ctx->singlestep_enabled = 0; 7332 if ((hflags >> HFLAGS_SE) & 1) { 7333 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7334 ctx->base.max_insns = 1; 7335 } 7336 if ((hflags >> HFLAGS_BE) & 1) { 7337 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7338 } 7339 } 7340 7341 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7342 { 7343 } 7344 7345 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7346 { 7347 tcg_gen_insn_start(dcbase->pc_next); 7348 } 7349 7350 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7351 { 7352 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7353 return opc1(insn) == 1; 7354 } 7355 7356 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7357 { 7358 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7359 PowerPCCPU *cpu = POWERPC_CPU(cs); 7360 CPUPPCState *env = cs->env_ptr; 7361 target_ulong pc; 7362 uint32_t insn; 7363 bool ok; 7364 7365 LOG_DISAS("----------------\n"); 7366 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7367 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7368 7369 ctx->cia = pc = ctx->base.pc_next; 7370 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7371 ctx->base.pc_next = pc += 4; 7372 7373 if (!is_prefix_insn(ctx, insn)) { 7374 ok = (decode_insn32(ctx, insn) || 7375 decode_legacy(cpu, ctx, insn)); 7376 } else if ((pc & 63) == 0) { 7377 /* 7378 * Power v3.1, section 1.9 Exceptions: 7379 * attempt to execute a prefixed instruction that crosses a 7380 * 64-byte address boundary (system alignment error). 7381 */ 7382 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7383 ok = true; 7384 } else { 7385 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7386 need_byteswap(ctx)); 7387 ctx->base.pc_next = pc += 4; 7388 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7389 } 7390 if (!ok) { 7391 gen_invalid(ctx); 7392 } 7393 7394 /* End the TB when crossing a page boundary. */ 7395 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7396 ctx->base.is_jmp = DISAS_TOO_MANY; 7397 } 7398 } 7399 7400 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7401 { 7402 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7403 DisasJumpType is_jmp = ctx->base.is_jmp; 7404 target_ulong nip = ctx->base.pc_next; 7405 7406 if (is_jmp == DISAS_NORETURN) { 7407 /* We have already exited the TB. */ 7408 return; 7409 } 7410 7411 /* Honor single stepping. */ 7412 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7413 switch (is_jmp) { 7414 case DISAS_TOO_MANY: 7415 case DISAS_EXIT_UPDATE: 7416 case DISAS_CHAIN_UPDATE: 7417 gen_update_nip(ctx, nip); 7418 break; 7419 case DISAS_EXIT: 7420 case DISAS_CHAIN: 7421 break; 7422 default: 7423 g_assert_not_reached(); 7424 } 7425 7426 gen_debug_exception(ctx); 7427 return; 7428 } 7429 7430 switch (is_jmp) { 7431 case DISAS_TOO_MANY: 7432 if (use_goto_tb(ctx, nip)) { 7433 pmu_count_insns(ctx); 7434 tcg_gen_goto_tb(0); 7435 gen_update_nip(ctx, nip); 7436 tcg_gen_exit_tb(ctx->base.tb, 0); 7437 break; 7438 } 7439 /* fall through */ 7440 case DISAS_CHAIN_UPDATE: 7441 gen_update_nip(ctx, nip); 7442 /* fall through */ 7443 case DISAS_CHAIN: 7444 /* 7445 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7446 * CF_NO_GOTO_PTR is set. Count insns now. 7447 */ 7448 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7449 pmu_count_insns(ctx); 7450 } 7451 7452 tcg_gen_lookup_and_goto_ptr(); 7453 break; 7454 7455 case DISAS_EXIT_UPDATE: 7456 gen_update_nip(ctx, nip); 7457 /* fall through */ 7458 case DISAS_EXIT: 7459 pmu_count_insns(ctx); 7460 tcg_gen_exit_tb(NULL, 0); 7461 break; 7462 7463 default: 7464 g_assert_not_reached(); 7465 } 7466 } 7467 7468 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7469 CPUState *cs, FILE *logfile) 7470 { 7471 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7472 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7473 } 7474 7475 static const TranslatorOps ppc_tr_ops = { 7476 .init_disas_context = ppc_tr_init_disas_context, 7477 .tb_start = ppc_tr_tb_start, 7478 .insn_start = ppc_tr_insn_start, 7479 .translate_insn = ppc_tr_translate_insn, 7480 .tb_stop = ppc_tr_tb_stop, 7481 .disas_log = ppc_tr_disas_log, 7482 }; 7483 7484 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7485 target_ulong pc, void *host_pc) 7486 { 7487 DisasContext ctx; 7488 7489 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7490 } 7491