1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 33 #include "exec/translator.h" 34 #include "exec/log.h" 35 #include "qemu/atomic128.h" 36 #include "spr_common.h" 37 #include "power8-pmu.h" 38 39 #include "qemu/qemu-print.h" 40 #include "qapi/error.h" 41 42 #define HELPER_H "helper.h" 43 #include "exec/helper-info.c.inc" 44 #undef HELPER_H 45 46 #define CPU_SINGLE_STEP 0x1 47 #define CPU_BRANCH_STEP 0x2 48 49 /* Include definitions for instructions classes and implementations flags */ 50 /* #define PPC_DEBUG_DISAS */ 51 52 #ifdef PPC_DEBUG_DISAS 53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54 #else 55 # define LOG_DISAS(...) do { } while (0) 56 #endif 57 /*****************************************************************************/ 58 /* Code translation helpers */ 59 60 /* global register indexes */ 61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62 + 10 * 4 + 22 * 5 /* SPE GPRh */ 63 + 8 * 5 /* CRF */]; 64 static TCGv cpu_gpr[32]; 65 static TCGv cpu_gprh[32]; 66 static TCGv_i32 cpu_crf[8]; 67 static TCGv cpu_nip; 68 static TCGv cpu_msr; 69 static TCGv cpu_ctr; 70 static TCGv cpu_lr; 71 #if defined(TARGET_PPC64) 72 static TCGv cpu_cfar; 73 #endif 74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75 static TCGv cpu_reserve; 76 static TCGv cpu_reserve_length; 77 static TCGv cpu_reserve_val; 78 static TCGv cpu_reserve_val2; 79 static TCGv cpu_fpscr; 80 static TCGv_i32 cpu_access_type; 81 82 void ppc_translate_init(void) 83 { 84 int i; 85 char *p; 86 size_t cpu_reg_names_size; 87 88 p = cpu_reg_names; 89 cpu_reg_names_size = sizeof(cpu_reg_names); 90 91 for (i = 0; i < 8; i++) { 92 snprintf(p, cpu_reg_names_size, "crf%d", i); 93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94 offsetof(CPUPPCState, crf[i]), p); 95 p += 5; 96 cpu_reg_names_size -= 5; 97 } 98 99 for (i = 0; i < 32; i++) { 100 snprintf(p, cpu_reg_names_size, "r%d", i); 101 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102 offsetof(CPUPPCState, gpr[i]), p); 103 p += (i < 10) ? 3 : 4; 104 cpu_reg_names_size -= (i < 10) ? 3 : 4; 105 snprintf(p, cpu_reg_names_size, "r%dH", i); 106 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107 offsetof(CPUPPCState, gprh[i]), p); 108 p += (i < 10) ? 4 : 5; 109 cpu_reg_names_size -= (i < 10) ? 4 : 5; 110 } 111 112 cpu_nip = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, nip), "nip"); 114 115 cpu_msr = tcg_global_mem_new(cpu_env, 116 offsetof(CPUPPCState, msr), "msr"); 117 118 cpu_ctr = tcg_global_mem_new(cpu_env, 119 offsetof(CPUPPCState, ctr), "ctr"); 120 121 cpu_lr = tcg_global_mem_new(cpu_env, 122 offsetof(CPUPPCState, lr), "lr"); 123 124 #if defined(TARGET_PPC64) 125 cpu_cfar = tcg_global_mem_new(cpu_env, 126 offsetof(CPUPPCState, cfar), "cfar"); 127 #endif 128 129 cpu_xer = tcg_global_mem_new(cpu_env, 130 offsetof(CPUPPCState, xer), "xer"); 131 cpu_so = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, so), "SO"); 133 cpu_ov = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, ov), "OV"); 135 cpu_ca = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ca), "CA"); 137 cpu_ov32 = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ov32), "OV32"); 139 cpu_ca32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ca32), "CA32"); 141 142 cpu_reserve = tcg_global_mem_new(cpu_env, 143 offsetof(CPUPPCState, reserve_addr), 144 "reserve_addr"); 145 cpu_reserve_length = tcg_global_mem_new(cpu_env, 146 offsetof(CPUPPCState, 147 reserve_length), 148 "reserve_length"); 149 cpu_reserve_val = tcg_global_mem_new(cpu_env, 150 offsetof(CPUPPCState, reserve_val), 151 "reserve_val"); 152 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 153 offsetof(CPUPPCState, reserve_val2), 154 "reserve_val2"); 155 156 cpu_fpscr = tcg_global_mem_new(cpu_env, 157 offsetof(CPUPPCState, fpscr), "fpscr"); 158 159 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 160 offsetof(CPUPPCState, access_type), 161 "access_type"); 162 } 163 164 /* internal defines */ 165 struct DisasContext { 166 DisasContextBase base; 167 target_ulong cia; /* current instruction address */ 168 uint32_t opcode; 169 /* Routine used to access memory */ 170 bool pr, hv, dr, le_mode; 171 bool lazy_tlb_flush; 172 bool need_access_type; 173 int mem_idx; 174 int access_type; 175 /* Translation flags */ 176 MemOp default_tcg_memop_mask; 177 #if defined(TARGET_PPC64) 178 bool sf_mode; 179 bool has_cfar; 180 #endif 181 bool fpu_enabled; 182 bool altivec_enabled; 183 bool vsx_enabled; 184 bool spe_enabled; 185 bool tm_enabled; 186 bool gtse; 187 bool hr; 188 bool mmcr0_pmcc0; 189 bool mmcr0_pmcc1; 190 bool mmcr0_pmcjce; 191 bool pmc_other; 192 bool pmu_insn_cnt; 193 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 194 int singlestep_enabled; 195 uint32_t flags; 196 uint64_t insns_flags; 197 uint64_t insns_flags2; 198 }; 199 200 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 201 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 202 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 203 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 204 205 /* Return true iff byteswap is needed in a scalar memop */ 206 static inline bool need_byteswap(const DisasContext *ctx) 207 { 208 #if TARGET_BIG_ENDIAN 209 return ctx->le_mode; 210 #else 211 return !ctx->le_mode; 212 #endif 213 } 214 215 /* True when active word size < size of target_long. */ 216 #ifdef TARGET_PPC64 217 # define NARROW_MODE(C) (!(C)->sf_mode) 218 #else 219 # define NARROW_MODE(C) 0 220 #endif 221 222 struct opc_handler_t { 223 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 224 uint32_t inval1; 225 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 226 uint32_t inval2; 227 /* instruction type */ 228 uint64_t type; 229 /* extended instruction type */ 230 uint64_t type2; 231 /* handler */ 232 void (*handler)(DisasContext *ctx); 233 }; 234 235 static inline bool gen_serialize(DisasContext *ctx) 236 { 237 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 238 /* Restart with exclusive lock. */ 239 gen_helper_exit_atomic(cpu_env); 240 ctx->base.is_jmp = DISAS_NORETURN; 241 return false; 242 } 243 return true; 244 } 245 246 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 247 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 248 { 249 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 250 return gen_serialize(ctx); 251 } 252 253 return true; 254 } 255 #endif 256 257 /* SPR load/store helpers */ 258 static inline void gen_load_spr(TCGv t, int reg) 259 { 260 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 261 } 262 263 static inline void gen_store_spr(int reg, TCGv t) 264 { 265 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 266 } 267 268 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 269 { 270 if (ctx->need_access_type && ctx->access_type != access_type) { 271 tcg_gen_movi_i32(cpu_access_type, access_type); 272 ctx->access_type = access_type; 273 } 274 } 275 276 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 277 { 278 if (NARROW_MODE(ctx)) { 279 nip = (uint32_t)nip; 280 } 281 tcg_gen_movi_tl(cpu_nip, nip); 282 } 283 284 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 285 { 286 TCGv_i32 t0, t1; 287 288 /* 289 * These are all synchronous exceptions, we set the PC back to the 290 * faulting instruction 291 */ 292 gen_update_nip(ctx, ctx->cia); 293 t0 = tcg_constant_i32(excp); 294 t1 = tcg_constant_i32(error); 295 gen_helper_raise_exception_err(cpu_env, t0, t1); 296 ctx->base.is_jmp = DISAS_NORETURN; 297 } 298 299 static void gen_exception(DisasContext *ctx, uint32_t excp) 300 { 301 TCGv_i32 t0; 302 303 /* 304 * These are all synchronous exceptions, we set the PC back to the 305 * faulting instruction 306 */ 307 gen_update_nip(ctx, ctx->cia); 308 t0 = tcg_constant_i32(excp); 309 gen_helper_raise_exception(cpu_env, t0); 310 ctx->base.is_jmp = DISAS_NORETURN; 311 } 312 313 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 314 target_ulong nip) 315 { 316 TCGv_i32 t0; 317 318 gen_update_nip(ctx, nip); 319 t0 = tcg_constant_i32(excp); 320 gen_helper_raise_exception(cpu_env, t0); 321 ctx->base.is_jmp = DISAS_NORETURN; 322 } 323 324 #if !defined(CONFIG_USER_ONLY) 325 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 326 { 327 translator_io_start(&ctx->base); 328 gen_helper_ppc_maybe_interrupt(cpu_env); 329 } 330 #endif 331 332 /* 333 * Tells the caller what is the appropriate exception to generate and prepares 334 * SPR registers for this exception. 335 * 336 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 337 * POWERPC_EXCP_DEBUG (on BookE). 338 */ 339 static uint32_t gen_prep_dbgex(DisasContext *ctx) 340 { 341 if (ctx->flags & POWERPC_FLAG_DE) { 342 target_ulong dbsr = 0; 343 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 344 dbsr = DBCR0_ICMP; 345 } else { 346 /* Must have been branch */ 347 dbsr = DBCR0_BRT; 348 } 349 TCGv t0 = tcg_temp_new(); 350 gen_load_spr(t0, SPR_BOOKE_DBSR); 351 tcg_gen_ori_tl(t0, t0, dbsr); 352 gen_store_spr(SPR_BOOKE_DBSR, t0); 353 return POWERPC_EXCP_DEBUG; 354 } else { 355 return POWERPC_EXCP_TRACE; 356 } 357 } 358 359 static void gen_debug_exception(DisasContext *ctx) 360 { 361 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 362 ctx->base.is_jmp = DISAS_NORETURN; 363 } 364 365 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 366 { 367 /* Will be converted to program check if needed */ 368 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 369 } 370 371 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 372 { 373 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 374 } 375 376 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 377 { 378 /* Will be converted to program check if needed */ 379 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 380 } 381 382 /*****************************************************************************/ 383 /* SPR READ/WRITE CALLBACKS */ 384 385 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 386 { 387 #if 0 388 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 389 printf("ERROR: try to access SPR %d !\n", sprn); 390 #endif 391 } 392 393 /* #define PPC_DUMP_SPR_ACCESSES */ 394 395 /* 396 * Generic callbacks: 397 * do nothing but store/retrieve spr value 398 */ 399 static void spr_load_dump_spr(int sprn) 400 { 401 #ifdef PPC_DUMP_SPR_ACCESSES 402 TCGv_i32 t0 = tcg_constant_i32(sprn); 403 gen_helper_load_dump_spr(cpu_env, t0); 404 #endif 405 } 406 407 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 408 { 409 gen_load_spr(cpu_gpr[gprn], sprn); 410 spr_load_dump_spr(sprn); 411 } 412 413 static void spr_store_dump_spr(int sprn) 414 { 415 #ifdef PPC_DUMP_SPR_ACCESSES 416 TCGv_i32 t0 = tcg_constant_i32(sprn); 417 gen_helper_store_dump_spr(cpu_env, t0); 418 #endif 419 } 420 421 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 422 { 423 gen_store_spr(sprn, cpu_gpr[gprn]); 424 spr_store_dump_spr(sprn); 425 } 426 427 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 428 { 429 #ifdef TARGET_PPC64 430 TCGv t0 = tcg_temp_new(); 431 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 432 gen_store_spr(sprn, t0); 433 spr_store_dump_spr(sprn); 434 #else 435 spr_write_generic(ctx, sprn, gprn); 436 #endif 437 } 438 439 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 440 { 441 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 442 spr_write_generic(ctx, sprn, gprn); 443 return; 444 } 445 446 if (!gen_serialize(ctx)) { 447 return; 448 } 449 450 gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), 451 cpu_gpr[gprn]); 452 spr_store_dump_spr(sprn); 453 } 454 455 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 456 { 457 /* This does not implement >1 thread */ 458 TCGv t0 = tcg_temp_new(); 459 TCGv t1 = tcg_temp_new(); 460 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 461 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 462 tcg_gen_or_tl(t1, t1, t0); 463 gen_store_spr(sprn, t1); 464 } 465 466 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 467 { 468 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 469 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 470 spr_write_CTRL_ST(ctx, sprn, gprn); 471 goto out; 472 } 473 474 if (!gen_serialize(ctx)) { 475 return; 476 } 477 478 gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 479 cpu_gpr[gprn]); 480 out: 481 spr_store_dump_spr(sprn); 482 483 /* 484 * SPR_CTRL writes must force a new translation block, 485 * allowing the PMU to calculate the run latch events with 486 * more accuracy. 487 */ 488 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 489 } 490 491 #if !defined(CONFIG_USER_ONLY) 492 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 493 { 494 TCGv t0 = tcg_temp_new(); 495 TCGv t1 = tcg_temp_new(); 496 gen_load_spr(t0, sprn); 497 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 498 tcg_gen_and_tl(t0, t0, t1); 499 gen_store_spr(sprn, t0); 500 } 501 502 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 503 { 504 } 505 506 #endif 507 508 /* SPR common to all PowerPC */ 509 /* XER */ 510 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 511 { 512 TCGv dst = cpu_gpr[gprn]; 513 TCGv t0 = tcg_temp_new(); 514 TCGv t1 = tcg_temp_new(); 515 TCGv t2 = tcg_temp_new(); 516 tcg_gen_mov_tl(dst, cpu_xer); 517 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 518 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 519 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 520 tcg_gen_or_tl(t0, t0, t1); 521 tcg_gen_or_tl(dst, dst, t2); 522 tcg_gen_or_tl(dst, dst, t0); 523 if (is_isa300(ctx)) { 524 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 525 tcg_gen_or_tl(dst, dst, t0); 526 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 527 tcg_gen_or_tl(dst, dst, t0); 528 } 529 } 530 531 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 532 { 533 TCGv src = cpu_gpr[gprn]; 534 /* Write all flags, while reading back check for isa300 */ 535 tcg_gen_andi_tl(cpu_xer, src, 536 ~((1u << XER_SO) | 537 (1u << XER_OV) | (1u << XER_OV32) | 538 (1u << XER_CA) | (1u << XER_CA32))); 539 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 540 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 541 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 542 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 543 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 544 } 545 546 /* LR */ 547 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 548 { 549 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 550 } 551 552 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 553 { 554 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 555 } 556 557 /* CFAR */ 558 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 559 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 560 { 561 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 562 } 563 564 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 565 { 566 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 567 } 568 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 569 570 /* CTR */ 571 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 572 { 573 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 574 } 575 576 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 577 { 578 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 579 } 580 581 /* User read access to SPR */ 582 /* USPRx */ 583 /* UMMCRx */ 584 /* UPMCx */ 585 /* USIA */ 586 /* UDECR */ 587 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 588 { 589 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 590 } 591 592 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 593 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 594 { 595 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 596 } 597 #endif 598 599 /* SPR common to all non-embedded PowerPC */ 600 /* DECR */ 601 #if !defined(CONFIG_USER_ONLY) 602 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 603 { 604 translator_io_start(&ctx->base); 605 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 606 } 607 608 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 609 { 610 translator_io_start(&ctx->base); 611 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 612 } 613 #endif 614 615 /* SPR common to all non-embedded PowerPC, except 601 */ 616 /* Time base */ 617 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 618 { 619 translator_io_start(&ctx->base); 620 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 621 } 622 623 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 624 { 625 translator_io_start(&ctx->base); 626 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 627 } 628 629 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 630 { 631 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 632 } 633 634 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 635 { 636 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 637 } 638 639 #if !defined(CONFIG_USER_ONLY) 640 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 641 { 642 translator_io_start(&ctx->base); 643 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 644 } 645 646 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 647 { 648 translator_io_start(&ctx->base); 649 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 650 } 651 652 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 653 { 654 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 655 } 656 657 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 658 { 659 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 660 } 661 662 #if defined(TARGET_PPC64) 663 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 664 { 665 translator_io_start(&ctx->base); 666 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 667 } 668 669 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 670 { 671 translator_io_start(&ctx->base); 672 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 673 } 674 675 /* HDECR */ 676 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 677 { 678 translator_io_start(&ctx->base); 679 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 680 } 681 682 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 683 { 684 translator_io_start(&ctx->base); 685 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 686 } 687 688 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 689 { 690 translator_io_start(&ctx->base); 691 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 692 } 693 694 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 695 { 696 translator_io_start(&ctx->base); 697 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 698 } 699 700 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 701 { 702 translator_io_start(&ctx->base); 703 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 704 } 705 706 #endif 707 #endif 708 709 #if !defined(CONFIG_USER_ONLY) 710 /* IBAT0U...IBAT0U */ 711 /* IBAT0L...IBAT7L */ 712 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 713 { 714 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 715 offsetof(CPUPPCState, 716 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 717 } 718 719 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 720 { 721 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 722 offsetof(CPUPPCState, 723 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 724 } 725 726 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 727 { 728 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 729 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 730 } 731 732 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 733 { 734 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 735 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 736 } 737 738 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 739 { 740 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 741 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 742 } 743 744 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 745 { 746 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 747 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 748 } 749 750 /* DBAT0U...DBAT7U */ 751 /* DBAT0L...DBAT7L */ 752 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 753 { 754 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 755 offsetof(CPUPPCState, 756 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 757 } 758 759 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 760 { 761 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 762 offsetof(CPUPPCState, 763 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 764 } 765 766 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 767 { 768 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 769 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 770 } 771 772 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 773 { 774 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 775 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 776 } 777 778 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 779 { 780 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 781 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 782 } 783 784 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 785 { 786 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 787 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 788 } 789 790 /* SDR1 */ 791 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 792 { 793 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 794 } 795 796 #if defined(TARGET_PPC64) 797 /* 64 bits PowerPC specific SPRs */ 798 /* PIDR */ 799 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 800 { 801 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 802 } 803 804 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 805 { 806 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 807 } 808 809 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 810 { 811 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 812 } 813 814 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 815 { 816 TCGv t0 = tcg_temp_new(); 817 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 818 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 819 } 820 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 821 { 822 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 823 } 824 825 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 826 { 827 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 828 } 829 830 /* DPDES */ 831 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 832 { 833 if (!gen_serialize_core_lpar(ctx)) { 834 return; 835 } 836 837 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 838 } 839 840 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 841 { 842 if (!gen_serialize_core_lpar(ctx)) { 843 return; 844 } 845 846 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 847 } 848 #endif 849 #endif 850 851 /* PowerPC 40x specific registers */ 852 #if !defined(CONFIG_USER_ONLY) 853 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 854 { 855 translator_io_start(&ctx->base); 856 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 857 } 858 859 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 860 { 861 translator_io_start(&ctx->base); 862 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 863 } 864 865 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 866 { 867 translator_io_start(&ctx->base); 868 gen_store_spr(sprn, cpu_gpr[gprn]); 869 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 870 /* We must stop translation as we may have rebooted */ 871 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 872 } 873 874 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 875 { 876 translator_io_start(&ctx->base); 877 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 878 } 879 880 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 881 { 882 translator_io_start(&ctx->base); 883 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 884 } 885 886 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 887 { 888 translator_io_start(&ctx->base); 889 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 890 } 891 892 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 893 { 894 TCGv t0 = tcg_temp_new(); 895 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 896 gen_helper_store_40x_pid(cpu_env, t0); 897 } 898 899 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 900 { 901 translator_io_start(&ctx->base); 902 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 903 } 904 905 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 906 { 907 translator_io_start(&ctx->base); 908 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 909 } 910 #endif 911 912 /* PIR */ 913 #if !defined(CONFIG_USER_ONLY) 914 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 915 { 916 TCGv t0 = tcg_temp_new(); 917 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 918 gen_store_spr(SPR_PIR, t0); 919 } 920 #endif 921 922 /* SPE specific registers */ 923 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 924 { 925 TCGv_i32 t0 = tcg_temp_new_i32(); 926 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 927 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 928 } 929 930 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 931 { 932 TCGv_i32 t0 = tcg_temp_new_i32(); 933 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 934 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 935 } 936 937 #if !defined(CONFIG_USER_ONLY) 938 /* Callback used to write the exception vector base */ 939 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 940 { 941 TCGv t0 = tcg_temp_new(); 942 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 943 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 944 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 945 gen_store_spr(sprn, t0); 946 } 947 948 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 949 { 950 int sprn_offs; 951 952 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 953 sprn_offs = sprn - SPR_BOOKE_IVOR0; 954 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 955 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 956 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 957 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 958 } else { 959 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 960 " vector 0x%03x\n", sprn); 961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 962 return; 963 } 964 965 TCGv t0 = tcg_temp_new(); 966 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 967 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 968 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 969 gen_store_spr(sprn, t0); 970 } 971 #endif 972 973 #ifdef TARGET_PPC64 974 #ifndef CONFIG_USER_ONLY 975 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 976 { 977 TCGv t0 = tcg_temp_new(); 978 TCGv t1 = tcg_temp_new(); 979 TCGv t2 = tcg_temp_new(); 980 981 /* 982 * Note, the HV=1 PR=0 case is handled earlier by simply using 983 * spr_write_generic for HV mode in the SPR table 984 */ 985 986 /* Build insertion mask into t1 based on context */ 987 if (ctx->pr) { 988 gen_load_spr(t1, SPR_UAMOR); 989 } else { 990 gen_load_spr(t1, SPR_AMOR); 991 } 992 993 /* Mask new bits into t2 */ 994 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 995 996 /* Load AMR and clear new bits in t0 */ 997 gen_load_spr(t0, SPR_AMR); 998 tcg_gen_andc_tl(t0, t0, t1); 999 1000 /* Or'in new bits and write it out */ 1001 tcg_gen_or_tl(t0, t0, t2); 1002 gen_store_spr(SPR_AMR, t0); 1003 spr_store_dump_spr(SPR_AMR); 1004 } 1005 1006 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1007 { 1008 TCGv t0 = tcg_temp_new(); 1009 TCGv t1 = tcg_temp_new(); 1010 TCGv t2 = tcg_temp_new(); 1011 1012 /* 1013 * Note, the HV=1 case is handled earlier by simply using 1014 * spr_write_generic for HV mode in the SPR table 1015 */ 1016 1017 /* Build insertion mask into t1 based on context */ 1018 gen_load_spr(t1, SPR_AMOR); 1019 1020 /* Mask new bits into t2 */ 1021 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1022 1023 /* Load AMR and clear new bits in t0 */ 1024 gen_load_spr(t0, SPR_UAMOR); 1025 tcg_gen_andc_tl(t0, t0, t1); 1026 1027 /* Or'in new bits and write it out */ 1028 tcg_gen_or_tl(t0, t0, t2); 1029 gen_store_spr(SPR_UAMOR, t0); 1030 spr_store_dump_spr(SPR_UAMOR); 1031 } 1032 1033 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1034 { 1035 TCGv t0 = tcg_temp_new(); 1036 TCGv t1 = tcg_temp_new(); 1037 TCGv t2 = tcg_temp_new(); 1038 1039 /* 1040 * Note, the HV=1 case is handled earlier by simply using 1041 * spr_write_generic for HV mode in the SPR table 1042 */ 1043 1044 /* Build insertion mask into t1 based on context */ 1045 gen_load_spr(t1, SPR_AMOR); 1046 1047 /* Mask new bits into t2 */ 1048 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1049 1050 /* Load AMR and clear new bits in t0 */ 1051 gen_load_spr(t0, SPR_IAMR); 1052 tcg_gen_andc_tl(t0, t0, t1); 1053 1054 /* Or'in new bits and write it out */ 1055 tcg_gen_or_tl(t0, t0, t2); 1056 gen_store_spr(SPR_IAMR, t0); 1057 spr_store_dump_spr(SPR_IAMR); 1058 } 1059 #endif 1060 #endif 1061 1062 #ifndef CONFIG_USER_ONLY 1063 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1064 { 1065 gen_helper_fixup_thrm(cpu_env); 1066 gen_load_spr(cpu_gpr[gprn], sprn); 1067 spr_load_dump_spr(sprn); 1068 } 1069 #endif /* !CONFIG_USER_ONLY */ 1070 1071 #if !defined(CONFIG_USER_ONLY) 1072 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1073 { 1074 TCGv t0 = tcg_temp_new(); 1075 1076 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1077 gen_store_spr(sprn, t0); 1078 } 1079 1080 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1081 { 1082 TCGv t0 = tcg_temp_new(); 1083 1084 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1085 gen_store_spr(sprn, t0); 1086 } 1087 1088 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1089 { 1090 TCGv t0 = tcg_temp_new(); 1091 1092 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1093 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1094 gen_store_spr(sprn, t0); 1095 } 1096 1097 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1098 { 1099 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1100 } 1101 1102 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1103 { 1104 TCGv_i32 t0 = tcg_constant_i32(sprn); 1105 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1106 } 1107 1108 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1109 { 1110 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1111 } 1112 1113 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1114 { 1115 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1116 } 1117 1118 #endif 1119 1120 #if !defined(CONFIG_USER_ONLY) 1121 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1122 { 1123 TCGv val = tcg_temp_new(); 1124 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1125 gen_store_spr(SPR_BOOKE_MAS3, val); 1126 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1127 gen_store_spr(SPR_BOOKE_MAS7, val); 1128 } 1129 1130 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1131 { 1132 TCGv mas7 = tcg_temp_new(); 1133 TCGv mas3 = tcg_temp_new(); 1134 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1135 tcg_gen_shli_tl(mas7, mas7, 32); 1136 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1137 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1138 } 1139 1140 #endif 1141 1142 #ifdef TARGET_PPC64 1143 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1144 int bit, int sprn, int cause) 1145 { 1146 TCGv_i32 t1 = tcg_constant_i32(bit); 1147 TCGv_i32 t2 = tcg_constant_i32(sprn); 1148 TCGv_i32 t3 = tcg_constant_i32(cause); 1149 1150 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1151 } 1152 1153 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1154 int bit, int sprn, int cause) 1155 { 1156 TCGv_i32 t1 = tcg_constant_i32(bit); 1157 TCGv_i32 t2 = tcg_constant_i32(sprn); 1158 TCGv_i32 t3 = tcg_constant_i32(cause); 1159 1160 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1161 } 1162 1163 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1164 { 1165 TCGv spr_up = tcg_temp_new(); 1166 TCGv spr = tcg_temp_new(); 1167 1168 gen_load_spr(spr, sprn - 1); 1169 tcg_gen_shri_tl(spr_up, spr, 32); 1170 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1171 } 1172 1173 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1174 { 1175 TCGv spr = tcg_temp_new(); 1176 1177 gen_load_spr(spr, sprn - 1); 1178 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1179 gen_store_spr(sprn - 1, spr); 1180 } 1181 1182 #if !defined(CONFIG_USER_ONLY) 1183 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1184 { 1185 TCGv hmer = tcg_temp_new(); 1186 1187 gen_load_spr(hmer, sprn); 1188 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1189 gen_store_spr(sprn, hmer); 1190 spr_store_dump_spr(sprn); 1191 } 1192 1193 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1194 { 1195 gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1196 } 1197 1198 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1199 { 1200 gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1201 } 1202 1203 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1204 { 1205 translator_io_start(&ctx->base); 1206 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1207 } 1208 #endif /* !defined(CONFIG_USER_ONLY) */ 1209 1210 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1211 { 1212 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1213 spr_read_generic(ctx, gprn, sprn); 1214 } 1215 1216 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1217 { 1218 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1219 spr_write_generic(ctx, sprn, gprn); 1220 } 1221 1222 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1223 { 1224 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1225 spr_read_generic(ctx, gprn, sprn); 1226 } 1227 1228 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1229 { 1230 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1231 spr_write_generic(ctx, sprn, gprn); 1232 } 1233 1234 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1235 { 1236 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1237 spr_read_prev_upper32(ctx, gprn, sprn); 1238 } 1239 1240 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1241 { 1242 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1243 spr_write_prev_upper32(ctx, sprn, gprn); 1244 } 1245 1246 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1247 { 1248 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1249 spr_read_generic(ctx, gprn, sprn); 1250 } 1251 1252 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1253 { 1254 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1255 spr_write_generic(ctx, sprn, gprn); 1256 } 1257 1258 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1259 { 1260 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1261 spr_read_prev_upper32(ctx, gprn, sprn); 1262 } 1263 1264 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1265 { 1266 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1267 spr_write_prev_upper32(ctx, sprn, gprn); 1268 } 1269 1270 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1271 { 1272 TCGv t0 = tcg_temp_new(); 1273 1274 /* 1275 * Access to the (H)DEXCR in problem state is done using separated 1276 * SPR indexes which are 16 below the SPR indexes which have full 1277 * access to the (H)DEXCR in privileged state. Problem state can 1278 * only read bits 32:63, bits 0:31 return 0. 1279 * 1280 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1281 */ 1282 1283 gen_load_spr(t0, sprn + 16); 1284 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1285 } 1286 #endif 1287 1288 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1289 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1290 1291 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1292 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1293 1294 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1295 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1296 1297 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1298 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1299 1300 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1301 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1302 1303 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1304 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1305 1306 typedef struct opcode_t { 1307 unsigned char opc1, opc2, opc3, opc4; 1308 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1309 unsigned char pad[4]; 1310 #endif 1311 opc_handler_t handler; 1312 const char *oname; 1313 } opcode_t; 1314 1315 static void gen_priv_opc(DisasContext *ctx) 1316 { 1317 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1318 } 1319 1320 /* Helpers for priv. check */ 1321 #define GEN_PRIV(CTX) \ 1322 do { \ 1323 gen_priv_opc(CTX); return; \ 1324 } while (0) 1325 1326 #if defined(CONFIG_USER_ONLY) 1327 #define CHK_HV(CTX) GEN_PRIV(CTX) 1328 #define CHK_SV(CTX) GEN_PRIV(CTX) 1329 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1330 #else 1331 #define CHK_HV(CTX) \ 1332 do { \ 1333 if (unlikely(ctx->pr || !ctx->hv)) {\ 1334 GEN_PRIV(CTX); \ 1335 } \ 1336 } while (0) 1337 #define CHK_SV(CTX) \ 1338 do { \ 1339 if (unlikely(ctx->pr)) { \ 1340 GEN_PRIV(CTX); \ 1341 } \ 1342 } while (0) 1343 #define CHK_HVRM(CTX) \ 1344 do { \ 1345 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1346 GEN_PRIV(CTX); \ 1347 } \ 1348 } while (0) 1349 #endif 1350 1351 #define CHK_NONE(CTX) 1352 1353 /*****************************************************************************/ 1354 /* PowerPC instructions table */ 1355 1356 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1357 { \ 1358 .opc1 = op1, \ 1359 .opc2 = op2, \ 1360 .opc3 = op3, \ 1361 .opc4 = 0xff, \ 1362 .handler = { \ 1363 .inval1 = invl, \ 1364 .type = _typ, \ 1365 .type2 = _typ2, \ 1366 .handler = &gen_##name, \ 1367 }, \ 1368 .oname = stringify(name), \ 1369 } 1370 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1371 { \ 1372 .opc1 = op1, \ 1373 .opc2 = op2, \ 1374 .opc3 = op3, \ 1375 .opc4 = 0xff, \ 1376 .handler = { \ 1377 .inval1 = invl1, \ 1378 .inval2 = invl2, \ 1379 .type = _typ, \ 1380 .type2 = _typ2, \ 1381 .handler = &gen_##name, \ 1382 }, \ 1383 .oname = stringify(name), \ 1384 } 1385 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1386 { \ 1387 .opc1 = op1, \ 1388 .opc2 = op2, \ 1389 .opc3 = op3, \ 1390 .opc4 = 0xff, \ 1391 .handler = { \ 1392 .inval1 = invl, \ 1393 .type = _typ, \ 1394 .type2 = _typ2, \ 1395 .handler = &gen_##name, \ 1396 }, \ 1397 .oname = onam, \ 1398 } 1399 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1400 { \ 1401 .opc1 = op1, \ 1402 .opc2 = op2, \ 1403 .opc3 = op3, \ 1404 .opc4 = op4, \ 1405 .handler = { \ 1406 .inval1 = invl, \ 1407 .type = _typ, \ 1408 .type2 = _typ2, \ 1409 .handler = &gen_##name, \ 1410 }, \ 1411 .oname = stringify(name), \ 1412 } 1413 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1414 { \ 1415 .opc1 = op1, \ 1416 .opc2 = op2, \ 1417 .opc3 = op3, \ 1418 .opc4 = op4, \ 1419 .handler = { \ 1420 .inval1 = invl, \ 1421 .type = _typ, \ 1422 .type2 = _typ2, \ 1423 .handler = &gen_##name, \ 1424 }, \ 1425 .oname = onam, \ 1426 } 1427 1428 /* Invalid instruction */ 1429 static void gen_invalid(DisasContext *ctx) 1430 { 1431 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1432 } 1433 1434 static opc_handler_t invalid_handler = { 1435 .inval1 = 0xFFFFFFFF, 1436 .inval2 = 0xFFFFFFFF, 1437 .type = PPC_NONE, 1438 .type2 = PPC_NONE, 1439 .handler = gen_invalid, 1440 }; 1441 1442 /*** Integer comparison ***/ 1443 1444 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1445 { 1446 TCGv t0 = tcg_temp_new(); 1447 TCGv t1 = tcg_temp_new(); 1448 TCGv_i32 t = tcg_temp_new_i32(); 1449 1450 tcg_gen_movi_tl(t0, CRF_EQ); 1451 tcg_gen_movi_tl(t1, CRF_LT); 1452 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1453 t0, arg0, arg1, t1, t0); 1454 tcg_gen_movi_tl(t1, CRF_GT); 1455 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1456 t0, arg0, arg1, t1, t0); 1457 1458 tcg_gen_trunc_tl_i32(t, t0); 1459 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1460 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1461 } 1462 1463 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1464 { 1465 TCGv t0 = tcg_constant_tl(arg1); 1466 gen_op_cmp(arg0, t0, s, crf); 1467 } 1468 1469 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1470 { 1471 TCGv t0, t1; 1472 t0 = tcg_temp_new(); 1473 t1 = tcg_temp_new(); 1474 if (s) { 1475 tcg_gen_ext32s_tl(t0, arg0); 1476 tcg_gen_ext32s_tl(t1, arg1); 1477 } else { 1478 tcg_gen_ext32u_tl(t0, arg0); 1479 tcg_gen_ext32u_tl(t1, arg1); 1480 } 1481 gen_op_cmp(t0, t1, s, crf); 1482 } 1483 1484 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1485 { 1486 TCGv t0 = tcg_constant_tl(arg1); 1487 gen_op_cmp32(arg0, t0, s, crf); 1488 } 1489 1490 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1491 { 1492 if (NARROW_MODE(ctx)) { 1493 gen_op_cmpi32(reg, 0, 1, 0); 1494 } else { 1495 gen_op_cmpi(reg, 0, 1, 0); 1496 } 1497 } 1498 1499 /* cmprb - range comparison: isupper, isaplha, islower*/ 1500 static void gen_cmprb(DisasContext *ctx) 1501 { 1502 TCGv_i32 src1 = tcg_temp_new_i32(); 1503 TCGv_i32 src2 = tcg_temp_new_i32(); 1504 TCGv_i32 src2lo = tcg_temp_new_i32(); 1505 TCGv_i32 src2hi = tcg_temp_new_i32(); 1506 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1507 1508 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1509 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1510 1511 tcg_gen_andi_i32(src1, src1, 0xFF); 1512 tcg_gen_ext8u_i32(src2lo, src2); 1513 tcg_gen_shri_i32(src2, src2, 8); 1514 tcg_gen_ext8u_i32(src2hi, src2); 1515 1516 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1517 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1518 tcg_gen_and_i32(crf, src2lo, src2hi); 1519 1520 if (ctx->opcode & 0x00200000) { 1521 tcg_gen_shri_i32(src2, src2, 8); 1522 tcg_gen_ext8u_i32(src2lo, src2); 1523 tcg_gen_shri_i32(src2, src2, 8); 1524 tcg_gen_ext8u_i32(src2hi, src2); 1525 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1526 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1527 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1528 tcg_gen_or_i32(crf, crf, src2lo); 1529 } 1530 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1531 } 1532 1533 #if defined(TARGET_PPC64) 1534 /* cmpeqb */ 1535 static void gen_cmpeqb(DisasContext *ctx) 1536 { 1537 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1538 cpu_gpr[rB(ctx->opcode)]); 1539 } 1540 #endif 1541 1542 /* isel (PowerPC 2.03 specification) */ 1543 static void gen_isel(DisasContext *ctx) 1544 { 1545 uint32_t bi = rC(ctx->opcode); 1546 uint32_t mask = 0x08 >> (bi & 0x03); 1547 TCGv t0 = tcg_temp_new(); 1548 TCGv zr; 1549 1550 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1551 tcg_gen_andi_tl(t0, t0, mask); 1552 1553 zr = tcg_constant_tl(0); 1554 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1555 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1556 cpu_gpr[rB(ctx->opcode)]); 1557 } 1558 1559 /* cmpb: PowerPC 2.05 specification */ 1560 static void gen_cmpb(DisasContext *ctx) 1561 { 1562 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1563 cpu_gpr[rB(ctx->opcode)]); 1564 } 1565 1566 /*** Integer arithmetic ***/ 1567 1568 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1569 TCGv arg1, TCGv arg2, int sub) 1570 { 1571 TCGv t0 = tcg_temp_new(); 1572 1573 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1574 tcg_gen_xor_tl(t0, arg1, arg2); 1575 if (sub) { 1576 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1577 } else { 1578 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1579 } 1580 if (NARROW_MODE(ctx)) { 1581 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1582 if (is_isa300(ctx)) { 1583 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1584 } 1585 } else { 1586 if (is_isa300(ctx)) { 1587 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1588 } 1589 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1590 } 1591 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1592 } 1593 1594 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1595 TCGv res, TCGv arg0, TCGv arg1, 1596 TCGv ca32, int sub) 1597 { 1598 TCGv t0; 1599 1600 if (!is_isa300(ctx)) { 1601 return; 1602 } 1603 1604 t0 = tcg_temp_new(); 1605 if (sub) { 1606 tcg_gen_eqv_tl(t0, arg0, arg1); 1607 } else { 1608 tcg_gen_xor_tl(t0, arg0, arg1); 1609 } 1610 tcg_gen_xor_tl(t0, t0, res); 1611 tcg_gen_extract_tl(ca32, t0, 32, 1); 1612 } 1613 1614 /* Common add function */ 1615 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1616 TCGv arg2, TCGv ca, TCGv ca32, 1617 bool add_ca, bool compute_ca, 1618 bool compute_ov, bool compute_rc0) 1619 { 1620 TCGv t0 = ret; 1621 1622 if (compute_ca || compute_ov) { 1623 t0 = tcg_temp_new(); 1624 } 1625 1626 if (compute_ca) { 1627 if (NARROW_MODE(ctx)) { 1628 /* 1629 * Caution: a non-obvious corner case of the spec is that 1630 * we must produce the *entire* 64-bit addition, but 1631 * produce the carry into bit 32. 1632 */ 1633 TCGv t1 = tcg_temp_new(); 1634 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1635 tcg_gen_add_tl(t0, arg1, arg2); 1636 if (add_ca) { 1637 tcg_gen_add_tl(t0, t0, ca); 1638 } 1639 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1640 tcg_gen_extract_tl(ca, ca, 32, 1); 1641 if (is_isa300(ctx)) { 1642 tcg_gen_mov_tl(ca32, ca); 1643 } 1644 } else { 1645 TCGv zero = tcg_constant_tl(0); 1646 if (add_ca) { 1647 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1648 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1649 } else { 1650 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1651 } 1652 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1653 } 1654 } else { 1655 tcg_gen_add_tl(t0, arg1, arg2); 1656 if (add_ca) { 1657 tcg_gen_add_tl(t0, t0, ca); 1658 } 1659 } 1660 1661 if (compute_ov) { 1662 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1663 } 1664 if (unlikely(compute_rc0)) { 1665 gen_set_Rc0(ctx, t0); 1666 } 1667 1668 if (t0 != ret) { 1669 tcg_gen_mov_tl(ret, t0); 1670 } 1671 } 1672 /* Add functions with two operands */ 1673 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1674 static void glue(gen_, name)(DisasContext *ctx) \ 1675 { \ 1676 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1677 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1678 ca, glue(ca, 32), \ 1679 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1680 } 1681 /* Add functions with one operand and one immediate */ 1682 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1683 add_ca, compute_ca, compute_ov) \ 1684 static void glue(gen_, name)(DisasContext *ctx) \ 1685 { \ 1686 TCGv t0 = tcg_constant_tl(const_val); \ 1687 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1688 cpu_gpr[rA(ctx->opcode)], t0, \ 1689 ca, glue(ca, 32), \ 1690 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1691 } 1692 1693 /* add add. addo addo. */ 1694 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1695 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1696 /* addc addc. addco addco. */ 1697 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1698 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1699 /* adde adde. addeo addeo. */ 1700 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1701 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1702 /* addme addme. addmeo addmeo. */ 1703 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1704 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1705 /* addex */ 1706 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1707 /* addze addze. addzeo addzeo.*/ 1708 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1709 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1710 /* addic addic.*/ 1711 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1712 { 1713 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1714 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1715 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1716 } 1717 1718 static void gen_addic(DisasContext *ctx) 1719 { 1720 gen_op_addic(ctx, 0); 1721 } 1722 1723 static void gen_addic_(DisasContext *ctx) 1724 { 1725 gen_op_addic(ctx, 1); 1726 } 1727 1728 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1729 TCGv arg2, int sign, int compute_ov) 1730 { 1731 TCGv_i32 t0 = tcg_temp_new_i32(); 1732 TCGv_i32 t1 = tcg_temp_new_i32(); 1733 TCGv_i32 t2 = tcg_temp_new_i32(); 1734 TCGv_i32 t3 = tcg_temp_new_i32(); 1735 1736 tcg_gen_trunc_tl_i32(t0, arg1); 1737 tcg_gen_trunc_tl_i32(t1, arg2); 1738 if (sign) { 1739 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1740 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1741 tcg_gen_and_i32(t2, t2, t3); 1742 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1743 tcg_gen_or_i32(t2, t2, t3); 1744 tcg_gen_movi_i32(t3, 0); 1745 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1746 tcg_gen_div_i32(t3, t0, t1); 1747 tcg_gen_extu_i32_tl(ret, t3); 1748 } else { 1749 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1750 tcg_gen_movi_i32(t3, 0); 1751 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1752 tcg_gen_divu_i32(t3, t0, t1); 1753 tcg_gen_extu_i32_tl(ret, t3); 1754 } 1755 if (compute_ov) { 1756 tcg_gen_extu_i32_tl(cpu_ov, t2); 1757 if (is_isa300(ctx)) { 1758 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1759 } 1760 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1761 } 1762 1763 if (unlikely(Rc(ctx->opcode) != 0)) { 1764 gen_set_Rc0(ctx, ret); 1765 } 1766 } 1767 /* Div functions */ 1768 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1769 static void glue(gen_, name)(DisasContext *ctx) \ 1770 { \ 1771 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1772 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1773 sign, compute_ov); \ 1774 } 1775 /* divwu divwu. divwuo divwuo. */ 1776 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1777 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1778 /* divw divw. divwo divwo. */ 1779 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1780 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1781 1782 /* div[wd]eu[o][.] */ 1783 #define GEN_DIVE(name, hlpr, compute_ov) \ 1784 static void gen_##name(DisasContext *ctx) \ 1785 { \ 1786 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1787 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1788 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1789 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1790 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1791 } \ 1792 } 1793 1794 GEN_DIVE(divweu, divweu, 0); 1795 GEN_DIVE(divweuo, divweu, 1); 1796 GEN_DIVE(divwe, divwe, 0); 1797 GEN_DIVE(divweo, divwe, 1); 1798 1799 #if defined(TARGET_PPC64) 1800 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1801 TCGv arg2, int sign, int compute_ov) 1802 { 1803 TCGv_i64 t0 = tcg_temp_new_i64(); 1804 TCGv_i64 t1 = tcg_temp_new_i64(); 1805 TCGv_i64 t2 = tcg_temp_new_i64(); 1806 TCGv_i64 t3 = tcg_temp_new_i64(); 1807 1808 tcg_gen_mov_i64(t0, arg1); 1809 tcg_gen_mov_i64(t1, arg2); 1810 if (sign) { 1811 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1812 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1813 tcg_gen_and_i64(t2, t2, t3); 1814 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1815 tcg_gen_or_i64(t2, t2, t3); 1816 tcg_gen_movi_i64(t3, 0); 1817 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1818 tcg_gen_div_i64(ret, t0, t1); 1819 } else { 1820 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1821 tcg_gen_movi_i64(t3, 0); 1822 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1823 tcg_gen_divu_i64(ret, t0, t1); 1824 } 1825 if (compute_ov) { 1826 tcg_gen_mov_tl(cpu_ov, t2); 1827 if (is_isa300(ctx)) { 1828 tcg_gen_mov_tl(cpu_ov32, t2); 1829 } 1830 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1831 } 1832 1833 if (unlikely(Rc(ctx->opcode) != 0)) { 1834 gen_set_Rc0(ctx, ret); 1835 } 1836 } 1837 1838 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1839 static void glue(gen_, name)(DisasContext *ctx) \ 1840 { \ 1841 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1842 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1843 sign, compute_ov); \ 1844 } 1845 /* divdu divdu. divduo divduo. */ 1846 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1847 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1848 /* divd divd. divdo divdo. */ 1849 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1850 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1851 1852 GEN_DIVE(divdeu, divdeu, 0); 1853 GEN_DIVE(divdeuo, divdeu, 1); 1854 GEN_DIVE(divde, divde, 0); 1855 GEN_DIVE(divdeo, divde, 1); 1856 #endif 1857 1858 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1859 TCGv arg2, int sign) 1860 { 1861 TCGv_i32 t0 = tcg_temp_new_i32(); 1862 TCGv_i32 t1 = tcg_temp_new_i32(); 1863 1864 tcg_gen_trunc_tl_i32(t0, arg1); 1865 tcg_gen_trunc_tl_i32(t1, arg2); 1866 if (sign) { 1867 TCGv_i32 t2 = tcg_temp_new_i32(); 1868 TCGv_i32 t3 = tcg_temp_new_i32(); 1869 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1870 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1871 tcg_gen_and_i32(t2, t2, t3); 1872 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1873 tcg_gen_or_i32(t2, t2, t3); 1874 tcg_gen_movi_i32(t3, 0); 1875 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1876 tcg_gen_rem_i32(t3, t0, t1); 1877 tcg_gen_ext_i32_tl(ret, t3); 1878 } else { 1879 TCGv_i32 t2 = tcg_constant_i32(1); 1880 TCGv_i32 t3 = tcg_constant_i32(0); 1881 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1882 tcg_gen_remu_i32(t0, t0, t1); 1883 tcg_gen_extu_i32_tl(ret, t0); 1884 } 1885 } 1886 1887 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1888 static void glue(gen_, name)(DisasContext *ctx) \ 1889 { \ 1890 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1891 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1892 sign); \ 1893 } 1894 1895 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1896 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1897 1898 #if defined(TARGET_PPC64) 1899 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1900 TCGv arg2, int sign) 1901 { 1902 TCGv_i64 t0 = tcg_temp_new_i64(); 1903 TCGv_i64 t1 = tcg_temp_new_i64(); 1904 1905 tcg_gen_mov_i64(t0, arg1); 1906 tcg_gen_mov_i64(t1, arg2); 1907 if (sign) { 1908 TCGv_i64 t2 = tcg_temp_new_i64(); 1909 TCGv_i64 t3 = tcg_temp_new_i64(); 1910 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1911 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1912 tcg_gen_and_i64(t2, t2, t3); 1913 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1914 tcg_gen_or_i64(t2, t2, t3); 1915 tcg_gen_movi_i64(t3, 0); 1916 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1917 tcg_gen_rem_i64(ret, t0, t1); 1918 } else { 1919 TCGv_i64 t2 = tcg_constant_i64(1); 1920 TCGv_i64 t3 = tcg_constant_i64(0); 1921 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1922 tcg_gen_remu_i64(ret, t0, t1); 1923 } 1924 } 1925 1926 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1927 static void glue(gen_, name)(DisasContext *ctx) \ 1928 { \ 1929 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1930 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1931 sign); \ 1932 } 1933 1934 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1935 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1936 #endif 1937 1938 /* mulhw mulhw. */ 1939 static void gen_mulhw(DisasContext *ctx) 1940 { 1941 TCGv_i32 t0 = tcg_temp_new_i32(); 1942 TCGv_i32 t1 = tcg_temp_new_i32(); 1943 1944 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1945 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1946 tcg_gen_muls2_i32(t0, t1, t0, t1); 1947 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1948 if (unlikely(Rc(ctx->opcode) != 0)) { 1949 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1950 } 1951 } 1952 1953 /* mulhwu mulhwu. */ 1954 static void gen_mulhwu(DisasContext *ctx) 1955 { 1956 TCGv_i32 t0 = tcg_temp_new_i32(); 1957 TCGv_i32 t1 = tcg_temp_new_i32(); 1958 1959 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1960 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1961 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1962 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1963 if (unlikely(Rc(ctx->opcode) != 0)) { 1964 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1965 } 1966 } 1967 1968 /* mullw mullw. */ 1969 static void gen_mullw(DisasContext *ctx) 1970 { 1971 #if defined(TARGET_PPC64) 1972 TCGv_i64 t0, t1; 1973 t0 = tcg_temp_new_i64(); 1974 t1 = tcg_temp_new_i64(); 1975 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1976 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1977 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1978 #else 1979 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1980 cpu_gpr[rB(ctx->opcode)]); 1981 #endif 1982 if (unlikely(Rc(ctx->opcode) != 0)) { 1983 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1984 } 1985 } 1986 1987 /* mullwo mullwo. */ 1988 static void gen_mullwo(DisasContext *ctx) 1989 { 1990 TCGv_i32 t0 = tcg_temp_new_i32(); 1991 TCGv_i32 t1 = tcg_temp_new_i32(); 1992 1993 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1994 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1995 tcg_gen_muls2_i32(t0, t1, t0, t1); 1996 #if defined(TARGET_PPC64) 1997 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1998 #else 1999 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2000 #endif 2001 2002 tcg_gen_sari_i32(t0, t0, 31); 2003 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2004 tcg_gen_extu_i32_tl(cpu_ov, t0); 2005 if (is_isa300(ctx)) { 2006 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2007 } 2008 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2009 2010 if (unlikely(Rc(ctx->opcode) != 0)) { 2011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2012 } 2013 } 2014 2015 /* mulli */ 2016 static void gen_mulli(DisasContext *ctx) 2017 { 2018 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2019 SIMM(ctx->opcode)); 2020 } 2021 2022 #if defined(TARGET_PPC64) 2023 /* mulhd mulhd. */ 2024 static void gen_mulhd(DisasContext *ctx) 2025 { 2026 TCGv lo = tcg_temp_new(); 2027 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2028 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2029 if (unlikely(Rc(ctx->opcode) != 0)) { 2030 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2031 } 2032 } 2033 2034 /* mulhdu mulhdu. */ 2035 static void gen_mulhdu(DisasContext *ctx) 2036 { 2037 TCGv lo = tcg_temp_new(); 2038 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2039 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2040 if (unlikely(Rc(ctx->opcode) != 0)) { 2041 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2042 } 2043 } 2044 2045 /* mulld mulld. */ 2046 static void gen_mulld(DisasContext *ctx) 2047 { 2048 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2049 cpu_gpr[rB(ctx->opcode)]); 2050 if (unlikely(Rc(ctx->opcode) != 0)) { 2051 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2052 } 2053 } 2054 2055 /* mulldo mulldo. */ 2056 static void gen_mulldo(DisasContext *ctx) 2057 { 2058 TCGv_i64 t0 = tcg_temp_new_i64(); 2059 TCGv_i64 t1 = tcg_temp_new_i64(); 2060 2061 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2062 cpu_gpr[rB(ctx->opcode)]); 2063 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2064 2065 tcg_gen_sari_i64(t0, t0, 63); 2066 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2067 if (is_isa300(ctx)) { 2068 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2069 } 2070 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2071 2072 if (unlikely(Rc(ctx->opcode) != 0)) { 2073 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2074 } 2075 } 2076 #endif 2077 2078 /* Common subf function */ 2079 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2080 TCGv arg2, bool add_ca, bool compute_ca, 2081 bool compute_ov, bool compute_rc0) 2082 { 2083 TCGv t0 = ret; 2084 2085 if (compute_ca || compute_ov) { 2086 t0 = tcg_temp_new(); 2087 } 2088 2089 if (compute_ca) { 2090 /* dest = ~arg1 + arg2 [+ ca]. */ 2091 if (NARROW_MODE(ctx)) { 2092 /* 2093 * Caution: a non-obvious corner case of the spec is that 2094 * we must produce the *entire* 64-bit addition, but 2095 * produce the carry into bit 32. 2096 */ 2097 TCGv inv1 = tcg_temp_new(); 2098 TCGv t1 = tcg_temp_new(); 2099 tcg_gen_not_tl(inv1, arg1); 2100 if (add_ca) { 2101 tcg_gen_add_tl(t0, arg2, cpu_ca); 2102 } else { 2103 tcg_gen_addi_tl(t0, arg2, 1); 2104 } 2105 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2106 tcg_gen_add_tl(t0, t0, inv1); 2107 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2108 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2109 if (is_isa300(ctx)) { 2110 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2111 } 2112 } else if (add_ca) { 2113 TCGv zero, inv1 = tcg_temp_new(); 2114 tcg_gen_not_tl(inv1, arg1); 2115 zero = tcg_constant_tl(0); 2116 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2117 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2118 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2119 } else { 2120 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2121 tcg_gen_sub_tl(t0, arg2, arg1); 2122 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2123 } 2124 } else if (add_ca) { 2125 /* 2126 * Since we're ignoring carry-out, we can simplify the 2127 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2128 */ 2129 tcg_gen_sub_tl(t0, arg2, arg1); 2130 tcg_gen_add_tl(t0, t0, cpu_ca); 2131 tcg_gen_subi_tl(t0, t0, 1); 2132 } else { 2133 tcg_gen_sub_tl(t0, arg2, arg1); 2134 } 2135 2136 if (compute_ov) { 2137 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2138 } 2139 if (unlikely(compute_rc0)) { 2140 gen_set_Rc0(ctx, t0); 2141 } 2142 2143 if (t0 != ret) { 2144 tcg_gen_mov_tl(ret, t0); 2145 } 2146 } 2147 /* Sub functions with Two operands functions */ 2148 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2149 static void glue(gen_, name)(DisasContext *ctx) \ 2150 { \ 2151 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2152 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2153 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2154 } 2155 /* Sub functions with one operand and one immediate */ 2156 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2157 add_ca, compute_ca, compute_ov) \ 2158 static void glue(gen_, name)(DisasContext *ctx) \ 2159 { \ 2160 TCGv t0 = tcg_constant_tl(const_val); \ 2161 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2162 cpu_gpr[rA(ctx->opcode)], t0, \ 2163 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2164 } 2165 /* subf subf. subfo subfo. */ 2166 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2167 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2168 /* subfc subfc. subfco subfco. */ 2169 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2170 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2171 /* subfe subfe. subfeo subfo. */ 2172 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2173 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2174 /* subfme subfme. subfmeo subfmeo. */ 2175 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2176 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2177 /* subfze subfze. subfzeo subfzeo.*/ 2178 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2179 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2180 2181 /* subfic */ 2182 static void gen_subfic(DisasContext *ctx) 2183 { 2184 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2185 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2186 c, 0, 1, 0, 0); 2187 } 2188 2189 /* neg neg. nego nego. */ 2190 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2191 { 2192 TCGv zero = tcg_constant_tl(0); 2193 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2194 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2195 } 2196 2197 static void gen_neg(DisasContext *ctx) 2198 { 2199 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2200 if (unlikely(Rc(ctx->opcode))) { 2201 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2202 } 2203 } 2204 2205 static void gen_nego(DisasContext *ctx) 2206 { 2207 gen_op_arith_neg(ctx, 1); 2208 } 2209 2210 /*** Integer logical ***/ 2211 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2212 static void glue(gen_, name)(DisasContext *ctx) \ 2213 { \ 2214 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2215 cpu_gpr[rB(ctx->opcode)]); \ 2216 if (unlikely(Rc(ctx->opcode) != 0)) \ 2217 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2218 } 2219 2220 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2221 static void glue(gen_, name)(DisasContext *ctx) \ 2222 { \ 2223 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2224 if (unlikely(Rc(ctx->opcode) != 0)) \ 2225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2226 } 2227 2228 /* and & and. */ 2229 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2230 /* andc & andc. */ 2231 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2232 2233 /* andi. */ 2234 static void gen_andi_(DisasContext *ctx) 2235 { 2236 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2237 UIMM(ctx->opcode)); 2238 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2239 } 2240 2241 /* andis. */ 2242 static void gen_andis_(DisasContext *ctx) 2243 { 2244 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2245 UIMM(ctx->opcode) << 16); 2246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2247 } 2248 2249 /* cntlzw */ 2250 static void gen_cntlzw(DisasContext *ctx) 2251 { 2252 TCGv_i32 t = tcg_temp_new_i32(); 2253 2254 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2255 tcg_gen_clzi_i32(t, t, 32); 2256 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2257 2258 if (unlikely(Rc(ctx->opcode) != 0)) { 2259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2260 } 2261 } 2262 2263 /* cnttzw */ 2264 static void gen_cnttzw(DisasContext *ctx) 2265 { 2266 TCGv_i32 t = tcg_temp_new_i32(); 2267 2268 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2269 tcg_gen_ctzi_i32(t, t, 32); 2270 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2271 2272 if (unlikely(Rc(ctx->opcode) != 0)) { 2273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2274 } 2275 } 2276 2277 /* eqv & eqv. */ 2278 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2279 /* extsb & extsb. */ 2280 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2281 /* extsh & extsh. */ 2282 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2283 /* nand & nand. */ 2284 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2285 /* nor & nor. */ 2286 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2287 2288 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2289 static void gen_pause(DisasContext *ctx) 2290 { 2291 TCGv_i32 t0 = tcg_constant_i32(0); 2292 tcg_gen_st_i32(t0, cpu_env, 2293 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2294 2295 /* Stop translation, this gives other CPUs a chance to run */ 2296 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2297 } 2298 #endif /* defined(TARGET_PPC64) */ 2299 2300 /* or & or. */ 2301 static void gen_or(DisasContext *ctx) 2302 { 2303 int rs, ra, rb; 2304 2305 rs = rS(ctx->opcode); 2306 ra = rA(ctx->opcode); 2307 rb = rB(ctx->opcode); 2308 /* Optimisation for mr. ri case */ 2309 if (rs != ra || rs != rb) { 2310 if (rs != rb) { 2311 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2312 } else { 2313 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2314 } 2315 if (unlikely(Rc(ctx->opcode) != 0)) { 2316 gen_set_Rc0(ctx, cpu_gpr[ra]); 2317 } 2318 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2319 gen_set_Rc0(ctx, cpu_gpr[rs]); 2320 #if defined(TARGET_PPC64) 2321 } else if (rs != 0) { /* 0 is nop */ 2322 int prio = 0; 2323 2324 switch (rs) { 2325 case 1: 2326 /* Set process priority to low */ 2327 prio = 2; 2328 break; 2329 case 6: 2330 /* Set process priority to medium-low */ 2331 prio = 3; 2332 break; 2333 case 2: 2334 /* Set process priority to normal */ 2335 prio = 4; 2336 break; 2337 #if !defined(CONFIG_USER_ONLY) 2338 case 31: 2339 if (!ctx->pr) { 2340 /* Set process priority to very low */ 2341 prio = 1; 2342 } 2343 break; 2344 case 5: 2345 if (!ctx->pr) { 2346 /* Set process priority to medium-hight */ 2347 prio = 5; 2348 } 2349 break; 2350 case 3: 2351 if (!ctx->pr) { 2352 /* Set process priority to high */ 2353 prio = 6; 2354 } 2355 break; 2356 case 7: 2357 if (ctx->hv && !ctx->pr) { 2358 /* Set process priority to very high */ 2359 prio = 7; 2360 } 2361 break; 2362 #endif 2363 default: 2364 break; 2365 } 2366 if (prio) { 2367 TCGv t0 = tcg_temp_new(); 2368 gen_load_spr(t0, SPR_PPR); 2369 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2370 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2371 gen_store_spr(SPR_PPR, t0); 2372 } 2373 #if !defined(CONFIG_USER_ONLY) 2374 /* 2375 * Pause out of TCG otherwise spin loops with smt_low eat too 2376 * much CPU and the kernel hangs. This applies to all 2377 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2378 * mdoio(29), mdoom(30), and all currently undefined. 2379 */ 2380 gen_pause(ctx); 2381 #endif 2382 #endif 2383 } 2384 } 2385 /* orc & orc. */ 2386 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2387 2388 /* xor & xor. */ 2389 static void gen_xor(DisasContext *ctx) 2390 { 2391 /* Optimisation for "set to zero" case */ 2392 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2393 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2394 cpu_gpr[rB(ctx->opcode)]); 2395 } else { 2396 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2397 } 2398 if (unlikely(Rc(ctx->opcode) != 0)) { 2399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2400 } 2401 } 2402 2403 /* ori */ 2404 static void gen_ori(DisasContext *ctx) 2405 { 2406 target_ulong uimm = UIMM(ctx->opcode); 2407 2408 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2409 return; 2410 } 2411 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2412 } 2413 2414 /* oris */ 2415 static void gen_oris(DisasContext *ctx) 2416 { 2417 target_ulong uimm = UIMM(ctx->opcode); 2418 2419 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2420 /* NOP */ 2421 return; 2422 } 2423 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2424 uimm << 16); 2425 } 2426 2427 /* xori */ 2428 static void gen_xori(DisasContext *ctx) 2429 { 2430 target_ulong uimm = UIMM(ctx->opcode); 2431 2432 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2433 /* NOP */ 2434 return; 2435 } 2436 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2437 } 2438 2439 /* xoris */ 2440 static void gen_xoris(DisasContext *ctx) 2441 { 2442 target_ulong uimm = UIMM(ctx->opcode); 2443 2444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2445 /* NOP */ 2446 return; 2447 } 2448 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2449 uimm << 16); 2450 } 2451 2452 /* popcntb : PowerPC 2.03 specification */ 2453 static void gen_popcntb(DisasContext *ctx) 2454 { 2455 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2456 } 2457 2458 static void gen_popcntw(DisasContext *ctx) 2459 { 2460 #if defined(TARGET_PPC64) 2461 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2462 #else 2463 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2464 #endif 2465 } 2466 2467 #if defined(TARGET_PPC64) 2468 /* popcntd: PowerPC 2.06 specification */ 2469 static void gen_popcntd(DisasContext *ctx) 2470 { 2471 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2472 } 2473 #endif 2474 2475 /* prtyw: PowerPC 2.05 specification */ 2476 static void gen_prtyw(DisasContext *ctx) 2477 { 2478 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2479 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2480 TCGv t0 = tcg_temp_new(); 2481 tcg_gen_shri_tl(t0, rs, 16); 2482 tcg_gen_xor_tl(ra, rs, t0); 2483 tcg_gen_shri_tl(t0, ra, 8); 2484 tcg_gen_xor_tl(ra, ra, t0); 2485 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2486 } 2487 2488 #if defined(TARGET_PPC64) 2489 /* prtyd: PowerPC 2.05 specification */ 2490 static void gen_prtyd(DisasContext *ctx) 2491 { 2492 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2493 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2494 TCGv t0 = tcg_temp_new(); 2495 tcg_gen_shri_tl(t0, rs, 32); 2496 tcg_gen_xor_tl(ra, rs, t0); 2497 tcg_gen_shri_tl(t0, ra, 16); 2498 tcg_gen_xor_tl(ra, ra, t0); 2499 tcg_gen_shri_tl(t0, ra, 8); 2500 tcg_gen_xor_tl(ra, ra, t0); 2501 tcg_gen_andi_tl(ra, ra, 1); 2502 } 2503 #endif 2504 2505 #if defined(TARGET_PPC64) 2506 /* bpermd */ 2507 static void gen_bpermd(DisasContext *ctx) 2508 { 2509 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2510 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2511 } 2512 #endif 2513 2514 #if defined(TARGET_PPC64) 2515 /* extsw & extsw. */ 2516 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2517 2518 /* cntlzd */ 2519 static void gen_cntlzd(DisasContext *ctx) 2520 { 2521 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2522 if (unlikely(Rc(ctx->opcode) != 0)) { 2523 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2524 } 2525 } 2526 2527 /* cnttzd */ 2528 static void gen_cnttzd(DisasContext *ctx) 2529 { 2530 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2531 if (unlikely(Rc(ctx->opcode) != 0)) { 2532 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2533 } 2534 } 2535 2536 /* darn */ 2537 static void gen_darn(DisasContext *ctx) 2538 { 2539 int l = L(ctx->opcode); 2540 2541 if (l > 2) { 2542 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2543 } else { 2544 translator_io_start(&ctx->base); 2545 if (l == 0) { 2546 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2547 } else { 2548 /* Return 64-bit random for both CRN and RRN */ 2549 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2550 } 2551 } 2552 } 2553 #endif 2554 2555 /*** Integer rotate ***/ 2556 2557 /* rlwimi & rlwimi. */ 2558 static void gen_rlwimi(DisasContext *ctx) 2559 { 2560 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2561 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2562 uint32_t sh = SH(ctx->opcode); 2563 uint32_t mb = MB(ctx->opcode); 2564 uint32_t me = ME(ctx->opcode); 2565 2566 if (sh == (31 - me) && mb <= me) { 2567 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2568 } else { 2569 target_ulong mask; 2570 bool mask_in_32b = true; 2571 TCGv t1; 2572 2573 #if defined(TARGET_PPC64) 2574 mb += 32; 2575 me += 32; 2576 #endif 2577 mask = MASK(mb, me); 2578 2579 #if defined(TARGET_PPC64) 2580 if (mask > 0xffffffffu) { 2581 mask_in_32b = false; 2582 } 2583 #endif 2584 t1 = tcg_temp_new(); 2585 if (mask_in_32b) { 2586 TCGv_i32 t0 = tcg_temp_new_i32(); 2587 tcg_gen_trunc_tl_i32(t0, t_rs); 2588 tcg_gen_rotli_i32(t0, t0, sh); 2589 tcg_gen_extu_i32_tl(t1, t0); 2590 } else { 2591 #if defined(TARGET_PPC64) 2592 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2593 tcg_gen_rotli_i64(t1, t1, sh); 2594 #else 2595 g_assert_not_reached(); 2596 #endif 2597 } 2598 2599 tcg_gen_andi_tl(t1, t1, mask); 2600 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2601 tcg_gen_or_tl(t_ra, t_ra, t1); 2602 } 2603 if (unlikely(Rc(ctx->opcode) != 0)) { 2604 gen_set_Rc0(ctx, t_ra); 2605 } 2606 } 2607 2608 /* rlwinm & rlwinm. */ 2609 static void gen_rlwinm(DisasContext *ctx) 2610 { 2611 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2612 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2613 int sh = SH(ctx->opcode); 2614 int mb = MB(ctx->opcode); 2615 int me = ME(ctx->opcode); 2616 int len = me - mb + 1; 2617 int rsh = (32 - sh) & 31; 2618 2619 if (sh != 0 && len > 0 && me == (31 - sh)) { 2620 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2621 } else if (me == 31 && rsh + len <= 32) { 2622 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2623 } else { 2624 target_ulong mask; 2625 bool mask_in_32b = true; 2626 #if defined(TARGET_PPC64) 2627 mb += 32; 2628 me += 32; 2629 #endif 2630 mask = MASK(mb, me); 2631 #if defined(TARGET_PPC64) 2632 if (mask > 0xffffffffu) { 2633 mask_in_32b = false; 2634 } 2635 #endif 2636 if (mask_in_32b) { 2637 if (sh == 0) { 2638 tcg_gen_andi_tl(t_ra, t_rs, mask); 2639 } else { 2640 TCGv_i32 t0 = tcg_temp_new_i32(); 2641 tcg_gen_trunc_tl_i32(t0, t_rs); 2642 tcg_gen_rotli_i32(t0, t0, sh); 2643 tcg_gen_andi_i32(t0, t0, mask); 2644 tcg_gen_extu_i32_tl(t_ra, t0); 2645 } 2646 } else { 2647 #if defined(TARGET_PPC64) 2648 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2649 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2650 tcg_gen_andi_i64(t_ra, t_ra, mask); 2651 #else 2652 g_assert_not_reached(); 2653 #endif 2654 } 2655 } 2656 if (unlikely(Rc(ctx->opcode) != 0)) { 2657 gen_set_Rc0(ctx, t_ra); 2658 } 2659 } 2660 2661 /* rlwnm & rlwnm. */ 2662 static void gen_rlwnm(DisasContext *ctx) 2663 { 2664 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2665 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2666 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2667 uint32_t mb = MB(ctx->opcode); 2668 uint32_t me = ME(ctx->opcode); 2669 target_ulong mask; 2670 bool mask_in_32b = true; 2671 2672 #if defined(TARGET_PPC64) 2673 mb += 32; 2674 me += 32; 2675 #endif 2676 mask = MASK(mb, me); 2677 2678 #if defined(TARGET_PPC64) 2679 if (mask > 0xffffffffu) { 2680 mask_in_32b = false; 2681 } 2682 #endif 2683 if (mask_in_32b) { 2684 TCGv_i32 t0 = tcg_temp_new_i32(); 2685 TCGv_i32 t1 = tcg_temp_new_i32(); 2686 tcg_gen_trunc_tl_i32(t0, t_rb); 2687 tcg_gen_trunc_tl_i32(t1, t_rs); 2688 tcg_gen_andi_i32(t0, t0, 0x1f); 2689 tcg_gen_rotl_i32(t1, t1, t0); 2690 tcg_gen_extu_i32_tl(t_ra, t1); 2691 } else { 2692 #if defined(TARGET_PPC64) 2693 TCGv_i64 t0 = tcg_temp_new_i64(); 2694 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2695 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2696 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2697 #else 2698 g_assert_not_reached(); 2699 #endif 2700 } 2701 2702 tcg_gen_andi_tl(t_ra, t_ra, mask); 2703 2704 if (unlikely(Rc(ctx->opcode) != 0)) { 2705 gen_set_Rc0(ctx, t_ra); 2706 } 2707 } 2708 2709 #if defined(TARGET_PPC64) 2710 #define GEN_PPC64_R2(name, opc1, opc2) \ 2711 static void glue(gen_, name##0)(DisasContext *ctx) \ 2712 { \ 2713 gen_##name(ctx, 0); \ 2714 } \ 2715 \ 2716 static void glue(gen_, name##1)(DisasContext *ctx) \ 2717 { \ 2718 gen_##name(ctx, 1); \ 2719 } 2720 #define GEN_PPC64_R4(name, opc1, opc2) \ 2721 static void glue(gen_, name##0)(DisasContext *ctx) \ 2722 { \ 2723 gen_##name(ctx, 0, 0); \ 2724 } \ 2725 \ 2726 static void glue(gen_, name##1)(DisasContext *ctx) \ 2727 { \ 2728 gen_##name(ctx, 0, 1); \ 2729 } \ 2730 \ 2731 static void glue(gen_, name##2)(DisasContext *ctx) \ 2732 { \ 2733 gen_##name(ctx, 1, 0); \ 2734 } \ 2735 \ 2736 static void glue(gen_, name##3)(DisasContext *ctx) \ 2737 { \ 2738 gen_##name(ctx, 1, 1); \ 2739 } 2740 2741 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2742 { 2743 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2744 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2745 int len = me - mb + 1; 2746 int rsh = (64 - sh) & 63; 2747 2748 if (sh != 0 && len > 0 && me == (63 - sh)) { 2749 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2750 } else if (me == 63 && rsh + len <= 64) { 2751 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2752 } else { 2753 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2754 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2755 } 2756 if (unlikely(Rc(ctx->opcode) != 0)) { 2757 gen_set_Rc0(ctx, t_ra); 2758 } 2759 } 2760 2761 /* rldicl - rldicl. */ 2762 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2763 { 2764 uint32_t sh, mb; 2765 2766 sh = SH(ctx->opcode) | (shn << 5); 2767 mb = MB(ctx->opcode) | (mbn << 5); 2768 gen_rldinm(ctx, mb, 63, sh); 2769 } 2770 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2771 2772 /* rldicr - rldicr. */ 2773 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2774 { 2775 uint32_t sh, me; 2776 2777 sh = SH(ctx->opcode) | (shn << 5); 2778 me = MB(ctx->opcode) | (men << 5); 2779 gen_rldinm(ctx, 0, me, sh); 2780 } 2781 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2782 2783 /* rldic - rldic. */ 2784 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2785 { 2786 uint32_t sh, mb; 2787 2788 sh = SH(ctx->opcode) | (shn << 5); 2789 mb = MB(ctx->opcode) | (mbn << 5); 2790 gen_rldinm(ctx, mb, 63 - sh, sh); 2791 } 2792 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2793 2794 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2795 { 2796 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2797 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2798 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2799 TCGv t0; 2800 2801 t0 = tcg_temp_new(); 2802 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2803 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2804 2805 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2806 if (unlikely(Rc(ctx->opcode) != 0)) { 2807 gen_set_Rc0(ctx, t_ra); 2808 } 2809 } 2810 2811 /* rldcl - rldcl. */ 2812 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2813 { 2814 uint32_t mb; 2815 2816 mb = MB(ctx->opcode) | (mbn << 5); 2817 gen_rldnm(ctx, mb, 63); 2818 } 2819 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2820 2821 /* rldcr - rldcr. */ 2822 static inline void gen_rldcr(DisasContext *ctx, int men) 2823 { 2824 uint32_t me; 2825 2826 me = MB(ctx->opcode) | (men << 5); 2827 gen_rldnm(ctx, 0, me); 2828 } 2829 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2830 2831 /* rldimi - rldimi. */ 2832 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2833 { 2834 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2835 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2836 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2837 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2838 uint32_t me = 63 - sh; 2839 2840 if (mb <= me) { 2841 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2842 } else { 2843 target_ulong mask = MASK(mb, me); 2844 TCGv t1 = tcg_temp_new(); 2845 2846 tcg_gen_rotli_tl(t1, t_rs, sh); 2847 tcg_gen_andi_tl(t1, t1, mask); 2848 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2849 tcg_gen_or_tl(t_ra, t_ra, t1); 2850 } 2851 if (unlikely(Rc(ctx->opcode) != 0)) { 2852 gen_set_Rc0(ctx, t_ra); 2853 } 2854 } 2855 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2856 #endif 2857 2858 /*** Integer shift ***/ 2859 2860 /* slw & slw. */ 2861 static void gen_slw(DisasContext *ctx) 2862 { 2863 TCGv t0, t1; 2864 2865 t0 = tcg_temp_new(); 2866 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2867 #if defined(TARGET_PPC64) 2868 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2869 tcg_gen_sari_tl(t0, t0, 0x3f); 2870 #else 2871 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2872 tcg_gen_sari_tl(t0, t0, 0x1f); 2873 #endif 2874 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2875 t1 = tcg_temp_new(); 2876 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2877 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2878 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2879 if (unlikely(Rc(ctx->opcode) != 0)) { 2880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2881 } 2882 } 2883 2884 /* sraw & sraw. */ 2885 static void gen_sraw(DisasContext *ctx) 2886 { 2887 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2888 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2889 if (unlikely(Rc(ctx->opcode) != 0)) { 2890 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2891 } 2892 } 2893 2894 /* srawi & srawi. */ 2895 static void gen_srawi(DisasContext *ctx) 2896 { 2897 int sh = SH(ctx->opcode); 2898 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2899 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2900 if (sh == 0) { 2901 tcg_gen_ext32s_tl(dst, src); 2902 tcg_gen_movi_tl(cpu_ca, 0); 2903 if (is_isa300(ctx)) { 2904 tcg_gen_movi_tl(cpu_ca32, 0); 2905 } 2906 } else { 2907 TCGv t0; 2908 tcg_gen_ext32s_tl(dst, src); 2909 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2910 t0 = tcg_temp_new(); 2911 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2912 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2913 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2914 if (is_isa300(ctx)) { 2915 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2916 } 2917 tcg_gen_sari_tl(dst, dst, sh); 2918 } 2919 if (unlikely(Rc(ctx->opcode) != 0)) { 2920 gen_set_Rc0(ctx, dst); 2921 } 2922 } 2923 2924 /* srw & srw. */ 2925 static void gen_srw(DisasContext *ctx) 2926 { 2927 TCGv t0, t1; 2928 2929 t0 = tcg_temp_new(); 2930 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2931 #if defined(TARGET_PPC64) 2932 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2933 tcg_gen_sari_tl(t0, t0, 0x3f); 2934 #else 2935 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2936 tcg_gen_sari_tl(t0, t0, 0x1f); 2937 #endif 2938 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2939 tcg_gen_ext32u_tl(t0, t0); 2940 t1 = tcg_temp_new(); 2941 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2942 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2943 if (unlikely(Rc(ctx->opcode) != 0)) { 2944 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2945 } 2946 } 2947 2948 #if defined(TARGET_PPC64) 2949 /* sld & sld. */ 2950 static void gen_sld(DisasContext *ctx) 2951 { 2952 TCGv t0, t1; 2953 2954 t0 = tcg_temp_new(); 2955 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2957 tcg_gen_sari_tl(t0, t0, 0x3f); 2958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2959 t1 = tcg_temp_new(); 2960 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2961 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2962 if (unlikely(Rc(ctx->opcode) != 0)) { 2963 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2964 } 2965 } 2966 2967 /* srad & srad. */ 2968 static void gen_srad(DisasContext *ctx) 2969 { 2970 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2971 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2972 if (unlikely(Rc(ctx->opcode) != 0)) { 2973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2974 } 2975 } 2976 /* sradi & sradi. */ 2977 static inline void gen_sradi(DisasContext *ctx, int n) 2978 { 2979 int sh = SH(ctx->opcode) + (n << 5); 2980 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2981 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2982 if (sh == 0) { 2983 tcg_gen_mov_tl(dst, src); 2984 tcg_gen_movi_tl(cpu_ca, 0); 2985 if (is_isa300(ctx)) { 2986 tcg_gen_movi_tl(cpu_ca32, 0); 2987 } 2988 } else { 2989 TCGv t0; 2990 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2991 t0 = tcg_temp_new(); 2992 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2993 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2994 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2995 if (is_isa300(ctx)) { 2996 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2997 } 2998 tcg_gen_sari_tl(dst, src, sh); 2999 } 3000 if (unlikely(Rc(ctx->opcode) != 0)) { 3001 gen_set_Rc0(ctx, dst); 3002 } 3003 } 3004 3005 static void gen_sradi0(DisasContext *ctx) 3006 { 3007 gen_sradi(ctx, 0); 3008 } 3009 3010 static void gen_sradi1(DisasContext *ctx) 3011 { 3012 gen_sradi(ctx, 1); 3013 } 3014 3015 /* extswsli & extswsli. */ 3016 static inline void gen_extswsli(DisasContext *ctx, int n) 3017 { 3018 int sh = SH(ctx->opcode) + (n << 5); 3019 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3020 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3021 3022 tcg_gen_ext32s_tl(dst, src); 3023 tcg_gen_shli_tl(dst, dst, sh); 3024 if (unlikely(Rc(ctx->opcode) != 0)) { 3025 gen_set_Rc0(ctx, dst); 3026 } 3027 } 3028 3029 static void gen_extswsli0(DisasContext *ctx) 3030 { 3031 gen_extswsli(ctx, 0); 3032 } 3033 3034 static void gen_extswsli1(DisasContext *ctx) 3035 { 3036 gen_extswsli(ctx, 1); 3037 } 3038 3039 /* srd & srd. */ 3040 static void gen_srd(DisasContext *ctx) 3041 { 3042 TCGv t0, t1; 3043 3044 t0 = tcg_temp_new(); 3045 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3046 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3047 tcg_gen_sari_tl(t0, t0, 0x3f); 3048 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3049 t1 = tcg_temp_new(); 3050 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3051 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3052 if (unlikely(Rc(ctx->opcode) != 0)) { 3053 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3054 } 3055 } 3056 #endif 3057 3058 /*** Addressing modes ***/ 3059 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3060 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3061 target_long maskl) 3062 { 3063 target_long simm = SIMM(ctx->opcode); 3064 3065 simm &= ~maskl; 3066 if (rA(ctx->opcode) == 0) { 3067 if (NARROW_MODE(ctx)) { 3068 simm = (uint32_t)simm; 3069 } 3070 tcg_gen_movi_tl(EA, simm); 3071 } else if (likely(simm != 0)) { 3072 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3073 if (NARROW_MODE(ctx)) { 3074 tcg_gen_ext32u_tl(EA, EA); 3075 } 3076 } else { 3077 if (NARROW_MODE(ctx)) { 3078 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3079 } else { 3080 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3081 } 3082 } 3083 } 3084 3085 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3086 { 3087 if (rA(ctx->opcode) == 0) { 3088 if (NARROW_MODE(ctx)) { 3089 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3090 } else { 3091 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3092 } 3093 } else { 3094 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3095 if (NARROW_MODE(ctx)) { 3096 tcg_gen_ext32u_tl(EA, EA); 3097 } 3098 } 3099 } 3100 3101 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3102 { 3103 if (rA(ctx->opcode) == 0) { 3104 tcg_gen_movi_tl(EA, 0); 3105 } else if (NARROW_MODE(ctx)) { 3106 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3107 } else { 3108 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3109 } 3110 } 3111 3112 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3113 target_long val) 3114 { 3115 tcg_gen_addi_tl(ret, arg1, val); 3116 if (NARROW_MODE(ctx)) { 3117 tcg_gen_ext32u_tl(ret, ret); 3118 } 3119 } 3120 3121 static inline void gen_align_no_le(DisasContext *ctx) 3122 { 3123 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3124 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3125 } 3126 3127 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3128 { 3129 TCGv ea = tcg_temp_new(); 3130 if (ra) { 3131 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3132 } else { 3133 tcg_gen_mov_tl(ea, displ); 3134 } 3135 if (NARROW_MODE(ctx)) { 3136 tcg_gen_ext32u_tl(ea, ea); 3137 } 3138 return ea; 3139 } 3140 3141 /*** Integer load ***/ 3142 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3143 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3144 3145 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3146 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3147 TCGv val, \ 3148 TCGv addr) \ 3149 { \ 3150 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3151 } 3152 3153 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3154 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3155 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3156 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3157 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3158 3159 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3160 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3161 3162 #define GEN_QEMU_LOAD_64(ldop, op) \ 3163 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3164 TCGv_i64 val, \ 3165 TCGv addr) \ 3166 { \ 3167 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3168 } 3169 3170 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3171 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3172 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3173 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3174 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3175 3176 #if defined(TARGET_PPC64) 3177 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3178 #endif 3179 3180 #define GEN_QEMU_STORE_TL(stop, op) \ 3181 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3182 TCGv val, \ 3183 TCGv addr) \ 3184 { \ 3185 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3186 } 3187 3188 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3189 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3190 #endif 3191 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3192 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3193 3194 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3195 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3196 3197 #define GEN_QEMU_STORE_64(stop, op) \ 3198 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3199 TCGv_i64 val, \ 3200 TCGv addr) \ 3201 { \ 3202 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3203 } 3204 3205 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3206 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3207 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3208 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3209 3210 #if defined(TARGET_PPC64) 3211 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3212 #endif 3213 3214 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3215 static void glue(gen_, name##x)(DisasContext *ctx) \ 3216 { \ 3217 TCGv EA; \ 3218 chk(ctx); \ 3219 gen_set_access_type(ctx, ACCESS_INT); \ 3220 EA = tcg_temp_new(); \ 3221 gen_addr_reg_index(ctx, EA); \ 3222 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3223 } 3224 3225 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3226 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3227 3228 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3229 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3230 3231 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3232 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3233 { \ 3234 TCGv EA; \ 3235 CHK_SV(ctx); \ 3236 gen_set_access_type(ctx, ACCESS_INT); \ 3237 EA = tcg_temp_new(); \ 3238 gen_addr_reg_index(ctx, EA); \ 3239 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3240 } 3241 3242 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3243 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3244 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3245 #if defined(TARGET_PPC64) 3246 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3247 #endif 3248 3249 #if defined(TARGET_PPC64) 3250 /* CI load/store variants */ 3251 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3252 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3253 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3254 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3255 #endif 3256 3257 /*** Integer store ***/ 3258 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3259 static void glue(gen_, name##x)(DisasContext *ctx) \ 3260 { \ 3261 TCGv EA; \ 3262 chk(ctx); \ 3263 gen_set_access_type(ctx, ACCESS_INT); \ 3264 EA = tcg_temp_new(); \ 3265 gen_addr_reg_index(ctx, EA); \ 3266 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3267 } 3268 #define GEN_STX(name, stop, opc2, opc3, type) \ 3269 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3270 3271 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3272 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3273 3274 #define GEN_STEPX(name, stop, opc2, opc3) \ 3275 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3276 { \ 3277 TCGv EA; \ 3278 CHK_SV(ctx); \ 3279 gen_set_access_type(ctx, ACCESS_INT); \ 3280 EA = tcg_temp_new(); \ 3281 gen_addr_reg_index(ctx, EA); \ 3282 tcg_gen_qemu_st_tl( \ 3283 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3284 } 3285 3286 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3287 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3288 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3289 #if defined(TARGET_PPC64) 3290 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3291 #endif 3292 3293 #if defined(TARGET_PPC64) 3294 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3295 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3296 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3297 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3298 #endif 3299 /*** Integer load and store with byte reverse ***/ 3300 3301 /* lhbrx */ 3302 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3303 3304 /* lwbrx */ 3305 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3306 3307 #if defined(TARGET_PPC64) 3308 /* ldbrx */ 3309 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3310 /* stdbrx */ 3311 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3312 #endif /* TARGET_PPC64 */ 3313 3314 /* sthbrx */ 3315 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3316 /* stwbrx */ 3317 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3318 3319 /*** Integer load and store multiple ***/ 3320 3321 /* lmw */ 3322 static void gen_lmw(DisasContext *ctx) 3323 { 3324 TCGv t0; 3325 TCGv_i32 t1; 3326 3327 if (ctx->le_mode) { 3328 gen_align_no_le(ctx); 3329 return; 3330 } 3331 gen_set_access_type(ctx, ACCESS_INT); 3332 t0 = tcg_temp_new(); 3333 t1 = tcg_constant_i32(rD(ctx->opcode)); 3334 gen_addr_imm_index(ctx, t0, 0); 3335 gen_helper_lmw(cpu_env, t0, t1); 3336 } 3337 3338 /* stmw */ 3339 static void gen_stmw(DisasContext *ctx) 3340 { 3341 TCGv t0; 3342 TCGv_i32 t1; 3343 3344 if (ctx->le_mode) { 3345 gen_align_no_le(ctx); 3346 return; 3347 } 3348 gen_set_access_type(ctx, ACCESS_INT); 3349 t0 = tcg_temp_new(); 3350 t1 = tcg_constant_i32(rS(ctx->opcode)); 3351 gen_addr_imm_index(ctx, t0, 0); 3352 gen_helper_stmw(cpu_env, t0, t1); 3353 } 3354 3355 /*** Integer load and store strings ***/ 3356 3357 /* lswi */ 3358 /* 3359 * PowerPC32 specification says we must generate an exception if rA is 3360 * in the range of registers to be loaded. In an other hand, IBM says 3361 * this is valid, but rA won't be loaded. For now, I'll follow the 3362 * spec... 3363 */ 3364 static void gen_lswi(DisasContext *ctx) 3365 { 3366 TCGv t0; 3367 TCGv_i32 t1, t2; 3368 int nb = NB(ctx->opcode); 3369 int start = rD(ctx->opcode); 3370 int ra = rA(ctx->opcode); 3371 int nr; 3372 3373 if (ctx->le_mode) { 3374 gen_align_no_le(ctx); 3375 return; 3376 } 3377 if (nb == 0) { 3378 nb = 32; 3379 } 3380 nr = DIV_ROUND_UP(nb, 4); 3381 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3382 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3383 return; 3384 } 3385 gen_set_access_type(ctx, ACCESS_INT); 3386 t0 = tcg_temp_new(); 3387 gen_addr_register(ctx, t0); 3388 t1 = tcg_constant_i32(nb); 3389 t2 = tcg_constant_i32(start); 3390 gen_helper_lsw(cpu_env, t0, t1, t2); 3391 } 3392 3393 /* lswx */ 3394 static void gen_lswx(DisasContext *ctx) 3395 { 3396 TCGv t0; 3397 TCGv_i32 t1, t2, t3; 3398 3399 if (ctx->le_mode) { 3400 gen_align_no_le(ctx); 3401 return; 3402 } 3403 gen_set_access_type(ctx, ACCESS_INT); 3404 t0 = tcg_temp_new(); 3405 gen_addr_reg_index(ctx, t0); 3406 t1 = tcg_constant_i32(rD(ctx->opcode)); 3407 t2 = tcg_constant_i32(rA(ctx->opcode)); 3408 t3 = tcg_constant_i32(rB(ctx->opcode)); 3409 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3410 } 3411 3412 /* stswi */ 3413 static void gen_stswi(DisasContext *ctx) 3414 { 3415 TCGv t0; 3416 TCGv_i32 t1, t2; 3417 int nb = NB(ctx->opcode); 3418 3419 if (ctx->le_mode) { 3420 gen_align_no_le(ctx); 3421 return; 3422 } 3423 gen_set_access_type(ctx, ACCESS_INT); 3424 t0 = tcg_temp_new(); 3425 gen_addr_register(ctx, t0); 3426 if (nb == 0) { 3427 nb = 32; 3428 } 3429 t1 = tcg_constant_i32(nb); 3430 t2 = tcg_constant_i32(rS(ctx->opcode)); 3431 gen_helper_stsw(cpu_env, t0, t1, t2); 3432 } 3433 3434 /* stswx */ 3435 static void gen_stswx(DisasContext *ctx) 3436 { 3437 TCGv t0; 3438 TCGv_i32 t1, t2; 3439 3440 if (ctx->le_mode) { 3441 gen_align_no_le(ctx); 3442 return; 3443 } 3444 gen_set_access_type(ctx, ACCESS_INT); 3445 t0 = tcg_temp_new(); 3446 gen_addr_reg_index(ctx, t0); 3447 t1 = tcg_temp_new_i32(); 3448 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3449 tcg_gen_andi_i32(t1, t1, 0x7F); 3450 t2 = tcg_constant_i32(rS(ctx->opcode)); 3451 gen_helper_stsw(cpu_env, t0, t1, t2); 3452 } 3453 3454 /*** Memory synchronisation ***/ 3455 /* eieio */ 3456 static void gen_eieio(DisasContext *ctx) 3457 { 3458 TCGBar bar = TCG_MO_ALL; 3459 3460 /* 3461 * eieio has complex semanitcs. It provides memory ordering between 3462 * operations in the set: 3463 * - loads from CI memory. 3464 * - stores to CI memory. 3465 * - stores to WT memory. 3466 * 3467 * It separately also orders memory for operations in the set: 3468 * - stores to cacheble memory. 3469 * 3470 * It also serializes instructions: 3471 * - dcbt and dcbst. 3472 * 3473 * It separately serializes: 3474 * - tlbie and tlbsync. 3475 * 3476 * And separately serializes: 3477 * - slbieg, slbiag, and slbsync. 3478 * 3479 * The end result is that CI memory ordering requires TCG_MO_ALL 3480 * and it is not possible to special-case more relaxed ordering for 3481 * cacheable accesses. TCG_BAR_SC is required to provide this 3482 * serialization. 3483 */ 3484 3485 /* 3486 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3487 * tell the CPU it is a store-forwarding barrier. 3488 */ 3489 if (ctx->opcode & 0x2000000) { 3490 /* 3491 * ISA says that "Reserved fields in instructions are ignored 3492 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3493 * as this is not an instruction software should be using, 3494 * complain to the user. 3495 */ 3496 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3497 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3498 TARGET_FMT_lx "\n", ctx->cia); 3499 } else { 3500 bar = TCG_MO_ST_LD; 3501 } 3502 } 3503 3504 tcg_gen_mb(bar | TCG_BAR_SC); 3505 } 3506 3507 #if !defined(CONFIG_USER_ONLY) 3508 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3509 { 3510 TCGv_i32 t; 3511 TCGLabel *l; 3512 3513 if (!ctx->lazy_tlb_flush) { 3514 return; 3515 } 3516 l = gen_new_label(); 3517 t = tcg_temp_new_i32(); 3518 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3519 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3520 if (global) { 3521 gen_helper_check_tlb_flush_global(cpu_env); 3522 } else { 3523 gen_helper_check_tlb_flush_local(cpu_env); 3524 } 3525 gen_set_label(l); 3526 } 3527 #else 3528 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3529 #endif 3530 3531 /* isync */ 3532 static void gen_isync(DisasContext *ctx) 3533 { 3534 /* 3535 * We need to check for a pending TLB flush. This can only happen in 3536 * kernel mode however so check MSR_PR 3537 */ 3538 if (!ctx->pr) { 3539 gen_check_tlb_flush(ctx, false); 3540 } 3541 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3542 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3543 } 3544 3545 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3546 3547 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3548 { 3549 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3550 TCGv t0 = tcg_temp_new(); 3551 3552 gen_set_access_type(ctx, ACCESS_RES); 3553 gen_addr_reg_index(ctx, t0); 3554 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3555 tcg_gen_mov_tl(cpu_reserve, t0); 3556 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3557 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3558 } 3559 3560 #define LARX(name, memop) \ 3561 static void gen_##name(DisasContext *ctx) \ 3562 { \ 3563 gen_load_locked(ctx, memop); \ 3564 } 3565 3566 /* lwarx */ 3567 LARX(lbarx, DEF_MEMOP(MO_UB)) 3568 LARX(lharx, DEF_MEMOP(MO_UW)) 3569 LARX(lwarx, DEF_MEMOP(MO_UL)) 3570 3571 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3572 TCGv EA, TCGCond cond, int addend) 3573 { 3574 TCGv t = tcg_temp_new(); 3575 TCGv t2 = tcg_temp_new(); 3576 TCGv u = tcg_temp_new(); 3577 3578 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3579 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3580 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3581 tcg_gen_addi_tl(u, t, addend); 3582 3583 /* E.g. for fetch and increment bounded... */ 3584 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3585 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3586 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3587 3588 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3589 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3590 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3591 } 3592 3593 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3594 { 3595 uint32_t gpr_FC = FC(ctx->opcode); 3596 TCGv EA = tcg_temp_new(); 3597 int rt = rD(ctx->opcode); 3598 bool need_serial; 3599 TCGv src, dst; 3600 3601 gen_addr_register(ctx, EA); 3602 dst = cpu_gpr[rt]; 3603 src = cpu_gpr[(rt + 1) & 31]; 3604 3605 need_serial = false; 3606 memop |= MO_ALIGN; 3607 switch (gpr_FC) { 3608 case 0: /* Fetch and add */ 3609 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3610 break; 3611 case 1: /* Fetch and xor */ 3612 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3613 break; 3614 case 2: /* Fetch and or */ 3615 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3616 break; 3617 case 3: /* Fetch and 'and' */ 3618 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3619 break; 3620 case 4: /* Fetch and max unsigned */ 3621 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3622 break; 3623 case 5: /* Fetch and max signed */ 3624 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3625 break; 3626 case 6: /* Fetch and min unsigned */ 3627 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3628 break; 3629 case 7: /* Fetch and min signed */ 3630 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3631 break; 3632 case 8: /* Swap */ 3633 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3634 break; 3635 3636 case 16: /* Compare and swap not equal */ 3637 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3638 need_serial = true; 3639 } else { 3640 TCGv t0 = tcg_temp_new(); 3641 TCGv t1 = tcg_temp_new(); 3642 3643 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3644 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3645 tcg_gen_mov_tl(t1, src); 3646 } else { 3647 tcg_gen_ext32u_tl(t1, src); 3648 } 3649 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3650 cpu_gpr[(rt + 2) & 31], t0); 3651 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3652 tcg_gen_mov_tl(dst, t0); 3653 } 3654 break; 3655 3656 case 24: /* Fetch and increment bounded */ 3657 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3658 need_serial = true; 3659 } else { 3660 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3661 } 3662 break; 3663 case 25: /* Fetch and increment equal */ 3664 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3665 need_serial = true; 3666 } else { 3667 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3668 } 3669 break; 3670 case 28: /* Fetch and decrement bounded */ 3671 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3672 need_serial = true; 3673 } else { 3674 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3675 } 3676 break; 3677 3678 default: 3679 /* invoke data storage error handler */ 3680 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3681 } 3682 3683 if (need_serial) { 3684 /* Restart with exclusive lock. */ 3685 gen_helper_exit_atomic(cpu_env); 3686 ctx->base.is_jmp = DISAS_NORETURN; 3687 } 3688 } 3689 3690 static void gen_lwat(DisasContext *ctx) 3691 { 3692 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3693 } 3694 3695 #ifdef TARGET_PPC64 3696 static void gen_ldat(DisasContext *ctx) 3697 { 3698 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3699 } 3700 #endif 3701 3702 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3703 { 3704 uint32_t gpr_FC = FC(ctx->opcode); 3705 TCGv EA = tcg_temp_new(); 3706 TCGv src, discard; 3707 3708 gen_addr_register(ctx, EA); 3709 src = cpu_gpr[rD(ctx->opcode)]; 3710 discard = tcg_temp_new(); 3711 3712 memop |= MO_ALIGN; 3713 switch (gpr_FC) { 3714 case 0: /* add and Store */ 3715 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3716 break; 3717 case 1: /* xor and Store */ 3718 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3719 break; 3720 case 2: /* Or and Store */ 3721 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3722 break; 3723 case 3: /* 'and' and Store */ 3724 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3725 break; 3726 case 4: /* Store max unsigned */ 3727 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3728 break; 3729 case 5: /* Store max signed */ 3730 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3731 break; 3732 case 6: /* Store min unsigned */ 3733 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3734 break; 3735 case 7: /* Store min signed */ 3736 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3737 break; 3738 case 24: /* Store twin */ 3739 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3740 /* Restart with exclusive lock. */ 3741 gen_helper_exit_atomic(cpu_env); 3742 ctx->base.is_jmp = DISAS_NORETURN; 3743 } else { 3744 TCGv t = tcg_temp_new(); 3745 TCGv t2 = tcg_temp_new(); 3746 TCGv s = tcg_temp_new(); 3747 TCGv s2 = tcg_temp_new(); 3748 TCGv ea_plus_s = tcg_temp_new(); 3749 3750 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3751 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3752 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3753 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3754 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3755 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3756 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3757 } 3758 break; 3759 default: 3760 /* invoke data storage error handler */ 3761 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3762 } 3763 } 3764 3765 static void gen_stwat(DisasContext *ctx) 3766 { 3767 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3768 } 3769 3770 #ifdef TARGET_PPC64 3771 static void gen_stdat(DisasContext *ctx) 3772 { 3773 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3774 } 3775 #endif 3776 3777 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3778 { 3779 TCGLabel *lfail; 3780 TCGv EA; 3781 TCGv cr0; 3782 TCGv t0; 3783 int rs = rS(ctx->opcode); 3784 3785 lfail = gen_new_label(); 3786 EA = tcg_temp_new(); 3787 cr0 = tcg_temp_new(); 3788 t0 = tcg_temp_new(); 3789 3790 tcg_gen_mov_tl(cr0, cpu_so); 3791 gen_set_access_type(ctx, ACCESS_RES); 3792 gen_addr_reg_index(ctx, EA); 3793 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3794 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3795 3796 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3797 cpu_gpr[rs], ctx->mem_idx, 3798 DEF_MEMOP(memop) | MO_ALIGN); 3799 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3800 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3801 tcg_gen_or_tl(cr0, cr0, t0); 3802 3803 gen_set_label(lfail); 3804 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3805 tcg_gen_movi_tl(cpu_reserve, -1); 3806 } 3807 3808 #define STCX(name, memop) \ 3809 static void gen_##name(DisasContext *ctx) \ 3810 { \ 3811 gen_conditional_store(ctx, memop); \ 3812 } 3813 3814 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3815 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3816 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3817 3818 #if defined(TARGET_PPC64) 3819 /* ldarx */ 3820 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3821 /* stdcx. */ 3822 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3823 3824 /* lqarx */ 3825 static void gen_lqarx(DisasContext *ctx) 3826 { 3827 int rd = rD(ctx->opcode); 3828 TCGv EA, hi, lo; 3829 TCGv_i128 t16; 3830 3831 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3832 (rd == rB(ctx->opcode)))) { 3833 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3834 return; 3835 } 3836 3837 gen_set_access_type(ctx, ACCESS_RES); 3838 EA = tcg_temp_new(); 3839 gen_addr_reg_index(ctx, EA); 3840 3841 /* Note that the low part is always in RD+1, even in LE mode. */ 3842 lo = cpu_gpr[rd + 1]; 3843 hi = cpu_gpr[rd]; 3844 3845 t16 = tcg_temp_new_i128(); 3846 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3847 tcg_gen_extr_i128_i64(lo, hi, t16); 3848 3849 tcg_gen_mov_tl(cpu_reserve, EA); 3850 tcg_gen_movi_tl(cpu_reserve_length, 16); 3851 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3852 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3853 } 3854 3855 /* stqcx. */ 3856 static void gen_stqcx_(DisasContext *ctx) 3857 { 3858 TCGLabel *lfail; 3859 TCGv EA, t0, t1; 3860 TCGv cr0; 3861 TCGv_i128 cmp, val; 3862 int rs = rS(ctx->opcode); 3863 3864 if (unlikely(rs & 1)) { 3865 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3866 return; 3867 } 3868 3869 lfail = gen_new_label(); 3870 EA = tcg_temp_new(); 3871 cr0 = tcg_temp_new(); 3872 3873 tcg_gen_mov_tl(cr0, cpu_so); 3874 gen_set_access_type(ctx, ACCESS_RES); 3875 gen_addr_reg_index(ctx, EA); 3876 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3877 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3878 3879 cmp = tcg_temp_new_i128(); 3880 val = tcg_temp_new_i128(); 3881 3882 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3883 3884 /* Note that the low part is always in RS+1, even in LE mode. */ 3885 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3886 3887 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3888 DEF_MEMOP(MO_128 | MO_ALIGN)); 3889 3890 t0 = tcg_temp_new(); 3891 t1 = tcg_temp_new(); 3892 tcg_gen_extr_i128_i64(t1, t0, val); 3893 3894 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3895 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3896 tcg_gen_or_tl(t0, t0, t1); 3897 3898 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3899 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3900 tcg_gen_or_tl(cr0, cr0, t0); 3901 3902 gen_set_label(lfail); 3903 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3904 tcg_gen_movi_tl(cpu_reserve, -1); 3905 } 3906 #endif /* defined(TARGET_PPC64) */ 3907 3908 /* sync */ 3909 static void gen_sync(DisasContext *ctx) 3910 { 3911 TCGBar bar = TCG_MO_ALL; 3912 uint32_t l = (ctx->opcode >> 21) & 3; 3913 3914 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3915 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3916 } 3917 3918 /* 3919 * We may need to check for a pending TLB flush. 3920 * 3921 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3922 * 3923 * Additionally, this can only happen in kernel mode however so 3924 * check MSR_PR as well. 3925 */ 3926 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3927 gen_check_tlb_flush(ctx, true); 3928 } 3929 3930 tcg_gen_mb(bar | TCG_BAR_SC); 3931 } 3932 3933 /* wait */ 3934 static void gen_wait(DisasContext *ctx) 3935 { 3936 uint32_t wc; 3937 3938 if (ctx->insns_flags & PPC_WAIT) { 3939 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3940 3941 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3942 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3943 wc = WC(ctx->opcode); 3944 } else { 3945 wc = 0; 3946 } 3947 3948 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3949 /* v3.0 defines a new 'wait' encoding. */ 3950 wc = WC(ctx->opcode); 3951 if (ctx->insns_flags2 & PPC2_ISA310) { 3952 uint32_t pl = PL(ctx->opcode); 3953 3954 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3955 if (wc == 3) { 3956 gen_invalid(ctx); 3957 return; 3958 } 3959 3960 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3961 if (pl > 0 && wc != 2) { 3962 gen_invalid(ctx); 3963 return; 3964 } 3965 3966 } else { /* ISA300 */ 3967 /* WC 1-3 are reserved */ 3968 if (wc > 0) { 3969 gen_invalid(ctx); 3970 return; 3971 } 3972 } 3973 3974 } else { 3975 warn_report("wait instruction decoded with wrong ISA flags."); 3976 gen_invalid(ctx); 3977 return; 3978 } 3979 3980 /* 3981 * wait without WC field or with WC=0 waits for an exception / interrupt 3982 * to occur. 3983 */ 3984 if (wc == 0) { 3985 TCGv_i32 t0 = tcg_constant_i32(1); 3986 tcg_gen_st_i32(t0, cpu_env, 3987 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3988 /* Stop translation, as the CPU is supposed to sleep from now */ 3989 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3990 } 3991 3992 /* 3993 * Other wait types must not just wait until an exception occurs because 3994 * ignoring their other wake-up conditions could cause a hang. 3995 * 3996 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3997 * no-ops. 3998 * 3999 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 4000 * 4001 * wc=2 waits for an implementation-specific condition, such could be 4002 * always true, so it can be implemented as a no-op. 4003 * 4004 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 4005 * 4006 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 4007 * Reservation-loss may have implementation-specific conditions, so it 4008 * can be implemented as a no-op. 4009 * 4010 * wc=2 waits for an exception or an amount of time to pass. This 4011 * amount is implementation-specific so it can be implemented as a 4012 * no-op. 4013 * 4014 * ISA v3.1 allows for execution to resume "in the rare case of 4015 * an implementation-dependent event", so in any case software must 4016 * not depend on the architected resumption condition to become 4017 * true, so no-op implementations should be architecturally correct 4018 * (if suboptimal). 4019 */ 4020 } 4021 4022 #if defined(TARGET_PPC64) 4023 static void gen_doze(DisasContext *ctx) 4024 { 4025 #if defined(CONFIG_USER_ONLY) 4026 GEN_PRIV(ctx); 4027 #else 4028 TCGv_i32 t; 4029 4030 CHK_HV(ctx); 4031 translator_io_start(&ctx->base); 4032 t = tcg_constant_i32(PPC_PM_DOZE); 4033 gen_helper_pminsn(cpu_env, t); 4034 /* Stop translation, as the CPU is supposed to sleep from now */ 4035 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4036 #endif /* defined(CONFIG_USER_ONLY) */ 4037 } 4038 4039 static void gen_nap(DisasContext *ctx) 4040 { 4041 #if defined(CONFIG_USER_ONLY) 4042 GEN_PRIV(ctx); 4043 #else 4044 TCGv_i32 t; 4045 4046 CHK_HV(ctx); 4047 translator_io_start(&ctx->base); 4048 t = tcg_constant_i32(PPC_PM_NAP); 4049 gen_helper_pminsn(cpu_env, t); 4050 /* Stop translation, as the CPU is supposed to sleep from now */ 4051 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4052 #endif /* defined(CONFIG_USER_ONLY) */ 4053 } 4054 4055 static void gen_stop(DisasContext *ctx) 4056 { 4057 #if defined(CONFIG_USER_ONLY) 4058 GEN_PRIV(ctx); 4059 #else 4060 TCGv_i32 t; 4061 4062 CHK_HV(ctx); 4063 translator_io_start(&ctx->base); 4064 t = tcg_constant_i32(PPC_PM_STOP); 4065 gen_helper_pminsn(cpu_env, t); 4066 /* Stop translation, as the CPU is supposed to sleep from now */ 4067 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4068 #endif /* defined(CONFIG_USER_ONLY) */ 4069 } 4070 4071 static void gen_sleep(DisasContext *ctx) 4072 { 4073 #if defined(CONFIG_USER_ONLY) 4074 GEN_PRIV(ctx); 4075 #else 4076 TCGv_i32 t; 4077 4078 CHK_HV(ctx); 4079 translator_io_start(&ctx->base); 4080 t = tcg_constant_i32(PPC_PM_SLEEP); 4081 gen_helper_pminsn(cpu_env, t); 4082 /* Stop translation, as the CPU is supposed to sleep from now */ 4083 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4084 #endif /* defined(CONFIG_USER_ONLY) */ 4085 } 4086 4087 static void gen_rvwinkle(DisasContext *ctx) 4088 { 4089 #if defined(CONFIG_USER_ONLY) 4090 GEN_PRIV(ctx); 4091 #else 4092 TCGv_i32 t; 4093 4094 CHK_HV(ctx); 4095 translator_io_start(&ctx->base); 4096 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4097 gen_helper_pminsn(cpu_env, t); 4098 /* Stop translation, as the CPU is supposed to sleep from now */ 4099 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4100 #endif /* defined(CONFIG_USER_ONLY) */ 4101 } 4102 #endif /* #if defined(TARGET_PPC64) */ 4103 4104 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4105 { 4106 #if defined(TARGET_PPC64) 4107 if (ctx->has_cfar) { 4108 tcg_gen_movi_tl(cpu_cfar, nip); 4109 } 4110 #endif 4111 } 4112 4113 #if defined(TARGET_PPC64) 4114 static void pmu_count_insns(DisasContext *ctx) 4115 { 4116 /* 4117 * Do not bother calling the helper if the PMU isn't counting 4118 * instructions. 4119 */ 4120 if (!ctx->pmu_insn_cnt) { 4121 return; 4122 } 4123 4124 #if !defined(CONFIG_USER_ONLY) 4125 TCGLabel *l; 4126 TCGv t0; 4127 4128 /* 4129 * The PMU insns_inc() helper stops the internal PMU timer if a 4130 * counter overflows happens. In that case, if the guest is 4131 * running with icount and we do not handle it beforehand, 4132 * the helper can trigger a 'bad icount read'. 4133 */ 4134 translator_io_start(&ctx->base); 4135 4136 /* Avoid helper calls when only PMC5-6 are enabled. */ 4137 if (!ctx->pmc_other) { 4138 l = gen_new_label(); 4139 t0 = tcg_temp_new(); 4140 4141 gen_load_spr(t0, SPR_POWER_PMC5); 4142 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4143 gen_store_spr(SPR_POWER_PMC5, t0); 4144 /* Check for overflow, if it's enabled */ 4145 if (ctx->mmcr0_pmcjce) { 4146 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4147 gen_helper_handle_pmc5_overflow(cpu_env); 4148 } 4149 4150 gen_set_label(l); 4151 } else { 4152 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4153 } 4154 #else 4155 /* 4156 * User mode can read (but not write) PMC5 and start/stop 4157 * the PMU via MMCR0_FC. In this case just increment 4158 * PMC5 with base.num_insns. 4159 */ 4160 TCGv t0 = tcg_temp_new(); 4161 4162 gen_load_spr(t0, SPR_POWER_PMC5); 4163 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4164 gen_store_spr(SPR_POWER_PMC5, t0); 4165 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4166 } 4167 #else 4168 static void pmu_count_insns(DisasContext *ctx) 4169 { 4170 return; 4171 } 4172 #endif /* #if defined(TARGET_PPC64) */ 4173 4174 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4175 { 4176 if (unlikely(ctx->singlestep_enabled)) { 4177 return false; 4178 } 4179 return translator_use_goto_tb(&ctx->base, dest); 4180 } 4181 4182 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4183 { 4184 if (unlikely(ctx->singlestep_enabled)) { 4185 gen_debug_exception(ctx); 4186 } else { 4187 /* 4188 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4189 * CF_NO_GOTO_PTR is set. Count insns now. 4190 */ 4191 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4192 pmu_count_insns(ctx); 4193 } 4194 4195 tcg_gen_lookup_and_goto_ptr(); 4196 } 4197 } 4198 4199 /*** Branch ***/ 4200 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4201 { 4202 if (NARROW_MODE(ctx)) { 4203 dest = (uint32_t) dest; 4204 } 4205 if (use_goto_tb(ctx, dest)) { 4206 pmu_count_insns(ctx); 4207 tcg_gen_goto_tb(n); 4208 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4209 tcg_gen_exit_tb(ctx->base.tb, n); 4210 } else { 4211 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4212 gen_lookup_and_goto_ptr(ctx); 4213 } 4214 } 4215 4216 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4217 { 4218 if (NARROW_MODE(ctx)) { 4219 nip = (uint32_t)nip; 4220 } 4221 tcg_gen_movi_tl(cpu_lr, nip); 4222 } 4223 4224 /* b ba bl bla */ 4225 static void gen_b(DisasContext *ctx) 4226 { 4227 target_ulong li, target; 4228 4229 /* sign extend LI */ 4230 li = LI(ctx->opcode); 4231 li = (li ^ 0x02000000) - 0x02000000; 4232 if (likely(AA(ctx->opcode) == 0)) { 4233 target = ctx->cia + li; 4234 } else { 4235 target = li; 4236 } 4237 if (LK(ctx->opcode)) { 4238 gen_setlr(ctx, ctx->base.pc_next); 4239 } 4240 gen_update_cfar(ctx, ctx->cia); 4241 gen_goto_tb(ctx, 0, target); 4242 ctx->base.is_jmp = DISAS_NORETURN; 4243 } 4244 4245 #define BCOND_IM 0 4246 #define BCOND_LR 1 4247 #define BCOND_CTR 2 4248 #define BCOND_TAR 3 4249 4250 static void gen_bcond(DisasContext *ctx, int type) 4251 { 4252 uint32_t bo = BO(ctx->opcode); 4253 TCGLabel *l1; 4254 TCGv target; 4255 4256 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4257 target = tcg_temp_new(); 4258 if (type == BCOND_CTR) { 4259 tcg_gen_mov_tl(target, cpu_ctr); 4260 } else if (type == BCOND_TAR) { 4261 gen_load_spr(target, SPR_TAR); 4262 } else { 4263 tcg_gen_mov_tl(target, cpu_lr); 4264 } 4265 } else { 4266 target = NULL; 4267 } 4268 if (LK(ctx->opcode)) { 4269 gen_setlr(ctx, ctx->base.pc_next); 4270 } 4271 l1 = gen_new_label(); 4272 if ((bo & 0x4) == 0) { 4273 /* Decrement and test CTR */ 4274 TCGv temp = tcg_temp_new(); 4275 4276 if (type == BCOND_CTR) { 4277 /* 4278 * All ISAs up to v3 describe this form of bcctr as invalid but 4279 * some processors, ie. 64-bit server processors compliant with 4280 * arch 2.x, do implement a "test and decrement" logic instead, 4281 * as described in their respective UMs. This logic involves CTR 4282 * to act as both the branch target and a counter, which makes 4283 * it basically useless and thus never used in real code. 4284 * 4285 * This form was hence chosen to trigger extra micro-architectural 4286 * side-effect on real HW needed for the Spectre v2 workaround. 4287 * It is up to guests that implement such workaround, ie. linux, to 4288 * use this form in a way it just triggers the side-effect without 4289 * doing anything else harmful. 4290 */ 4291 if (unlikely(!is_book3s_arch2x(ctx))) { 4292 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4293 return; 4294 } 4295 4296 if (NARROW_MODE(ctx)) { 4297 tcg_gen_ext32u_tl(temp, cpu_ctr); 4298 } else { 4299 tcg_gen_mov_tl(temp, cpu_ctr); 4300 } 4301 if (bo & 0x2) { 4302 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4303 } else { 4304 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4305 } 4306 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4307 } else { 4308 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4309 if (NARROW_MODE(ctx)) { 4310 tcg_gen_ext32u_tl(temp, cpu_ctr); 4311 } else { 4312 tcg_gen_mov_tl(temp, cpu_ctr); 4313 } 4314 if (bo & 0x2) { 4315 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4316 } else { 4317 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4318 } 4319 } 4320 } 4321 if ((bo & 0x10) == 0) { 4322 /* Test CR */ 4323 uint32_t bi = BI(ctx->opcode); 4324 uint32_t mask = 0x08 >> (bi & 0x03); 4325 TCGv_i32 temp = tcg_temp_new_i32(); 4326 4327 if (bo & 0x8) { 4328 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4329 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4330 } else { 4331 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4332 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4333 } 4334 } 4335 gen_update_cfar(ctx, ctx->cia); 4336 if (type == BCOND_IM) { 4337 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4338 if (likely(AA(ctx->opcode) == 0)) { 4339 gen_goto_tb(ctx, 0, ctx->cia + li); 4340 } else { 4341 gen_goto_tb(ctx, 0, li); 4342 } 4343 } else { 4344 if (NARROW_MODE(ctx)) { 4345 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4346 } else { 4347 tcg_gen_andi_tl(cpu_nip, target, ~3); 4348 } 4349 gen_lookup_and_goto_ptr(ctx); 4350 } 4351 if ((bo & 0x14) != 0x14) { 4352 /* fallthrough case */ 4353 gen_set_label(l1); 4354 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4355 } 4356 ctx->base.is_jmp = DISAS_NORETURN; 4357 } 4358 4359 static void gen_bc(DisasContext *ctx) 4360 { 4361 gen_bcond(ctx, BCOND_IM); 4362 } 4363 4364 static void gen_bcctr(DisasContext *ctx) 4365 { 4366 gen_bcond(ctx, BCOND_CTR); 4367 } 4368 4369 static void gen_bclr(DisasContext *ctx) 4370 { 4371 gen_bcond(ctx, BCOND_LR); 4372 } 4373 4374 static void gen_bctar(DisasContext *ctx) 4375 { 4376 gen_bcond(ctx, BCOND_TAR); 4377 } 4378 4379 /*** Condition register logical ***/ 4380 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4381 static void glue(gen_, name)(DisasContext *ctx) \ 4382 { \ 4383 uint8_t bitmask; \ 4384 int sh; \ 4385 TCGv_i32 t0, t1; \ 4386 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4387 t0 = tcg_temp_new_i32(); \ 4388 if (sh > 0) \ 4389 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4390 else if (sh < 0) \ 4391 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4392 else \ 4393 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4394 t1 = tcg_temp_new_i32(); \ 4395 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4396 if (sh > 0) \ 4397 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4398 else if (sh < 0) \ 4399 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4400 else \ 4401 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4402 tcg_op(t0, t0, t1); \ 4403 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4404 tcg_gen_andi_i32(t0, t0, bitmask); \ 4405 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4406 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4407 } 4408 4409 /* crand */ 4410 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4411 /* crandc */ 4412 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4413 /* creqv */ 4414 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4415 /* crnand */ 4416 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4417 /* crnor */ 4418 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4419 /* cror */ 4420 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4421 /* crorc */ 4422 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4423 /* crxor */ 4424 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4425 4426 /* mcrf */ 4427 static void gen_mcrf(DisasContext *ctx) 4428 { 4429 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4430 } 4431 4432 /*** System linkage ***/ 4433 4434 /* rfi (supervisor only) */ 4435 static void gen_rfi(DisasContext *ctx) 4436 { 4437 #if defined(CONFIG_USER_ONLY) 4438 GEN_PRIV(ctx); 4439 #else 4440 /* 4441 * This instruction doesn't exist anymore on 64-bit server 4442 * processors compliant with arch 2.x 4443 */ 4444 if (is_book3s_arch2x(ctx)) { 4445 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4446 return; 4447 } 4448 /* Restore CPU state */ 4449 CHK_SV(ctx); 4450 translator_io_start(&ctx->base); 4451 gen_update_cfar(ctx, ctx->cia); 4452 gen_helper_rfi(cpu_env); 4453 ctx->base.is_jmp = DISAS_EXIT; 4454 #endif 4455 } 4456 4457 #if defined(TARGET_PPC64) 4458 static void gen_rfid(DisasContext *ctx) 4459 { 4460 #if defined(CONFIG_USER_ONLY) 4461 GEN_PRIV(ctx); 4462 #else 4463 /* Restore CPU state */ 4464 CHK_SV(ctx); 4465 translator_io_start(&ctx->base); 4466 gen_update_cfar(ctx, ctx->cia); 4467 gen_helper_rfid(cpu_env); 4468 ctx->base.is_jmp = DISAS_EXIT; 4469 #endif 4470 } 4471 4472 #if !defined(CONFIG_USER_ONLY) 4473 static void gen_rfscv(DisasContext *ctx) 4474 { 4475 #if defined(CONFIG_USER_ONLY) 4476 GEN_PRIV(ctx); 4477 #else 4478 /* Restore CPU state */ 4479 CHK_SV(ctx); 4480 translator_io_start(&ctx->base); 4481 gen_update_cfar(ctx, ctx->cia); 4482 gen_helper_rfscv(cpu_env); 4483 ctx->base.is_jmp = DISAS_EXIT; 4484 #endif 4485 } 4486 #endif 4487 4488 static void gen_hrfid(DisasContext *ctx) 4489 { 4490 #if defined(CONFIG_USER_ONLY) 4491 GEN_PRIV(ctx); 4492 #else 4493 /* Restore CPU state */ 4494 CHK_HV(ctx); 4495 translator_io_start(&ctx->base); 4496 gen_helper_hrfid(cpu_env); 4497 ctx->base.is_jmp = DISAS_EXIT; 4498 #endif 4499 } 4500 #endif 4501 4502 /* sc */ 4503 #if defined(CONFIG_USER_ONLY) 4504 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4505 #else 4506 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4507 #endif 4508 static void gen_sc(DisasContext *ctx) 4509 { 4510 uint32_t lev; 4511 4512 /* 4513 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4514 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4515 * for Ultravisor which TCG does not support, so just ignore the top 6. 4516 */ 4517 lev = (ctx->opcode >> 5) & 0x1; 4518 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4519 } 4520 4521 #if defined(TARGET_PPC64) 4522 #if !defined(CONFIG_USER_ONLY) 4523 static void gen_scv(DisasContext *ctx) 4524 { 4525 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4526 4527 /* Set the PC back to the faulting instruction. */ 4528 gen_update_nip(ctx, ctx->cia); 4529 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4530 4531 ctx->base.is_jmp = DISAS_NORETURN; 4532 } 4533 #endif 4534 #endif 4535 4536 /*** Trap ***/ 4537 4538 /* Check for unconditional traps (always or never) */ 4539 static bool check_unconditional_trap(DisasContext *ctx) 4540 { 4541 /* Trap never */ 4542 if (TO(ctx->opcode) == 0) { 4543 return true; 4544 } 4545 /* Trap always */ 4546 if (TO(ctx->opcode) == 31) { 4547 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4548 return true; 4549 } 4550 return false; 4551 } 4552 4553 /* tw */ 4554 static void gen_tw(DisasContext *ctx) 4555 { 4556 TCGv_i32 t0; 4557 4558 if (check_unconditional_trap(ctx)) { 4559 return; 4560 } 4561 t0 = tcg_constant_i32(TO(ctx->opcode)); 4562 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4563 t0); 4564 } 4565 4566 /* twi */ 4567 static void gen_twi(DisasContext *ctx) 4568 { 4569 TCGv t0; 4570 TCGv_i32 t1; 4571 4572 if (check_unconditional_trap(ctx)) { 4573 return; 4574 } 4575 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4576 t1 = tcg_constant_i32(TO(ctx->opcode)); 4577 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4578 } 4579 4580 #if defined(TARGET_PPC64) 4581 /* td */ 4582 static void gen_td(DisasContext *ctx) 4583 { 4584 TCGv_i32 t0; 4585 4586 if (check_unconditional_trap(ctx)) { 4587 return; 4588 } 4589 t0 = tcg_constant_i32(TO(ctx->opcode)); 4590 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4591 t0); 4592 } 4593 4594 /* tdi */ 4595 static void gen_tdi(DisasContext *ctx) 4596 { 4597 TCGv t0; 4598 TCGv_i32 t1; 4599 4600 if (check_unconditional_trap(ctx)) { 4601 return; 4602 } 4603 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4604 t1 = tcg_constant_i32(TO(ctx->opcode)); 4605 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4606 } 4607 #endif 4608 4609 /*** Processor control ***/ 4610 4611 /* mcrxr */ 4612 static void gen_mcrxr(DisasContext *ctx) 4613 { 4614 TCGv_i32 t0 = tcg_temp_new_i32(); 4615 TCGv_i32 t1 = tcg_temp_new_i32(); 4616 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4617 4618 tcg_gen_trunc_tl_i32(t0, cpu_so); 4619 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4620 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4621 tcg_gen_shli_i32(t0, t0, 3); 4622 tcg_gen_shli_i32(t1, t1, 2); 4623 tcg_gen_shli_i32(dst, dst, 1); 4624 tcg_gen_or_i32(dst, dst, t0); 4625 tcg_gen_or_i32(dst, dst, t1); 4626 4627 tcg_gen_movi_tl(cpu_so, 0); 4628 tcg_gen_movi_tl(cpu_ov, 0); 4629 tcg_gen_movi_tl(cpu_ca, 0); 4630 } 4631 4632 #ifdef TARGET_PPC64 4633 /* mcrxrx */ 4634 static void gen_mcrxrx(DisasContext *ctx) 4635 { 4636 TCGv t0 = tcg_temp_new(); 4637 TCGv t1 = tcg_temp_new(); 4638 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4639 4640 /* copy OV and OV32 */ 4641 tcg_gen_shli_tl(t0, cpu_ov, 1); 4642 tcg_gen_or_tl(t0, t0, cpu_ov32); 4643 tcg_gen_shli_tl(t0, t0, 2); 4644 /* copy CA and CA32 */ 4645 tcg_gen_shli_tl(t1, cpu_ca, 1); 4646 tcg_gen_or_tl(t1, t1, cpu_ca32); 4647 tcg_gen_or_tl(t0, t0, t1); 4648 tcg_gen_trunc_tl_i32(dst, t0); 4649 } 4650 #endif 4651 4652 /* mfcr mfocrf */ 4653 static void gen_mfcr(DisasContext *ctx) 4654 { 4655 uint32_t crm, crn; 4656 4657 if (likely(ctx->opcode & 0x00100000)) { 4658 crm = CRM(ctx->opcode); 4659 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4660 crn = ctz32(crm); 4661 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4662 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4663 cpu_gpr[rD(ctx->opcode)], crn * 4); 4664 } 4665 } else { 4666 TCGv_i32 t0 = tcg_temp_new_i32(); 4667 tcg_gen_mov_i32(t0, cpu_crf[0]); 4668 tcg_gen_shli_i32(t0, t0, 4); 4669 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4670 tcg_gen_shli_i32(t0, t0, 4); 4671 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4672 tcg_gen_shli_i32(t0, t0, 4); 4673 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4674 tcg_gen_shli_i32(t0, t0, 4); 4675 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4676 tcg_gen_shli_i32(t0, t0, 4); 4677 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4678 tcg_gen_shli_i32(t0, t0, 4); 4679 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4680 tcg_gen_shli_i32(t0, t0, 4); 4681 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4682 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4683 } 4684 } 4685 4686 /* mfmsr */ 4687 static void gen_mfmsr(DisasContext *ctx) 4688 { 4689 CHK_SV(ctx); 4690 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4691 } 4692 4693 /* mfspr */ 4694 static inline void gen_op_mfspr(DisasContext *ctx) 4695 { 4696 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4697 uint32_t sprn = SPR(ctx->opcode); 4698 4699 #if defined(CONFIG_USER_ONLY) 4700 read_cb = ctx->spr_cb[sprn].uea_read; 4701 #else 4702 if (ctx->pr) { 4703 read_cb = ctx->spr_cb[sprn].uea_read; 4704 } else if (ctx->hv) { 4705 read_cb = ctx->spr_cb[sprn].hea_read; 4706 } else { 4707 read_cb = ctx->spr_cb[sprn].oea_read; 4708 } 4709 #endif 4710 if (likely(read_cb != NULL)) { 4711 if (likely(read_cb != SPR_NOACCESS)) { 4712 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4713 } else { 4714 /* Privilege exception */ 4715 /* 4716 * This is a hack to avoid warnings when running Linux: 4717 * this OS breaks the PowerPC virtualisation model, 4718 * allowing userland application to read the PVR 4719 */ 4720 if (sprn != SPR_PVR) { 4721 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4722 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4723 ctx->cia); 4724 } 4725 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4726 } 4727 } else { 4728 /* ISA 2.07 defines these as no-ops */ 4729 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4730 (sprn >= 808 && sprn <= 811)) { 4731 /* This is a nop */ 4732 return; 4733 } 4734 /* Not defined */ 4735 qemu_log_mask(LOG_GUEST_ERROR, 4736 "Trying to read invalid spr %d (0x%03x) at " 4737 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4738 4739 /* 4740 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4741 * generate a priv, a hv emu or a no-op 4742 */ 4743 if (sprn & 0x10) { 4744 if (ctx->pr) { 4745 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4746 } 4747 } else { 4748 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4749 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4750 } 4751 } 4752 } 4753 } 4754 4755 static void gen_mfspr(DisasContext *ctx) 4756 { 4757 gen_op_mfspr(ctx); 4758 } 4759 4760 /* mftb */ 4761 static void gen_mftb(DisasContext *ctx) 4762 { 4763 gen_op_mfspr(ctx); 4764 } 4765 4766 /* mtcrf mtocrf*/ 4767 static void gen_mtcrf(DisasContext *ctx) 4768 { 4769 uint32_t crm, crn; 4770 4771 crm = CRM(ctx->opcode); 4772 if (likely((ctx->opcode & 0x00100000))) { 4773 if (crm && ((crm & (crm - 1)) == 0)) { 4774 TCGv_i32 temp = tcg_temp_new_i32(); 4775 crn = ctz32(crm); 4776 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4777 tcg_gen_shri_i32(temp, temp, crn * 4); 4778 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4779 } 4780 } else { 4781 TCGv_i32 temp = tcg_temp_new_i32(); 4782 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4783 for (crn = 0 ; crn < 8 ; crn++) { 4784 if (crm & (1 << crn)) { 4785 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4786 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4787 } 4788 } 4789 } 4790 } 4791 4792 /* mtmsr */ 4793 #if defined(TARGET_PPC64) 4794 static void gen_mtmsrd(DisasContext *ctx) 4795 { 4796 if (unlikely(!is_book3s_arch2x(ctx))) { 4797 gen_invalid(ctx); 4798 return; 4799 } 4800 4801 CHK_SV(ctx); 4802 4803 #if !defined(CONFIG_USER_ONLY) 4804 TCGv t0, t1; 4805 target_ulong mask; 4806 4807 t0 = tcg_temp_new(); 4808 t1 = tcg_temp_new(); 4809 4810 translator_io_start(&ctx->base); 4811 4812 if (ctx->opcode & 0x00010000) { 4813 /* L=1 form only updates EE and RI */ 4814 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4815 } else { 4816 /* mtmsrd does not alter HV, S, ME, or LE */ 4817 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4818 (1ULL << MSR_HV)); 4819 /* 4820 * XXX: we need to update nip before the store if we enter 4821 * power saving mode, we will exit the loop directly from 4822 * ppc_store_msr 4823 */ 4824 gen_update_nip(ctx, ctx->base.pc_next); 4825 } 4826 4827 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4828 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4829 tcg_gen_or_tl(t0, t0, t1); 4830 4831 gen_helper_store_msr(cpu_env, t0); 4832 4833 /* Must stop the translation as machine state (may have) changed */ 4834 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4835 #endif /* !defined(CONFIG_USER_ONLY) */ 4836 } 4837 #endif /* defined(TARGET_PPC64) */ 4838 4839 static void gen_mtmsr(DisasContext *ctx) 4840 { 4841 CHK_SV(ctx); 4842 4843 #if !defined(CONFIG_USER_ONLY) 4844 TCGv t0, t1; 4845 target_ulong mask = 0xFFFFFFFF; 4846 4847 t0 = tcg_temp_new(); 4848 t1 = tcg_temp_new(); 4849 4850 translator_io_start(&ctx->base); 4851 if (ctx->opcode & 0x00010000) { 4852 /* L=1 form only updates EE and RI */ 4853 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4854 } else { 4855 /* mtmsr does not alter S, ME, or LE */ 4856 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4857 4858 /* 4859 * XXX: we need to update nip before the store if we enter 4860 * power saving mode, we will exit the loop directly from 4861 * ppc_store_msr 4862 */ 4863 gen_update_nip(ctx, ctx->base.pc_next); 4864 } 4865 4866 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4867 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4868 tcg_gen_or_tl(t0, t0, t1); 4869 4870 gen_helper_store_msr(cpu_env, t0); 4871 4872 /* Must stop the translation as machine state (may have) changed */ 4873 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4874 #endif 4875 } 4876 4877 /* mtspr */ 4878 static void gen_mtspr(DisasContext *ctx) 4879 { 4880 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4881 uint32_t sprn = SPR(ctx->opcode); 4882 4883 #if defined(CONFIG_USER_ONLY) 4884 write_cb = ctx->spr_cb[sprn].uea_write; 4885 #else 4886 if (ctx->pr) { 4887 write_cb = ctx->spr_cb[sprn].uea_write; 4888 } else if (ctx->hv) { 4889 write_cb = ctx->spr_cb[sprn].hea_write; 4890 } else { 4891 write_cb = ctx->spr_cb[sprn].oea_write; 4892 } 4893 #endif 4894 if (likely(write_cb != NULL)) { 4895 if (likely(write_cb != SPR_NOACCESS)) { 4896 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4897 } else { 4898 /* Privilege exception */ 4899 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4900 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4901 ctx->cia); 4902 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4903 } 4904 } else { 4905 /* ISA 2.07 defines these as no-ops */ 4906 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4907 (sprn >= 808 && sprn <= 811)) { 4908 /* This is a nop */ 4909 return; 4910 } 4911 4912 /* Not defined */ 4913 qemu_log_mask(LOG_GUEST_ERROR, 4914 "Trying to write invalid spr %d (0x%03x) at " 4915 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4916 4917 4918 /* 4919 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4920 * generate a priv, a hv emu or a no-op 4921 */ 4922 if (sprn & 0x10) { 4923 if (ctx->pr) { 4924 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4925 } 4926 } else { 4927 if (ctx->pr || sprn == 0) { 4928 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4929 } 4930 } 4931 } 4932 } 4933 4934 #if defined(TARGET_PPC64) 4935 /* setb */ 4936 static void gen_setb(DisasContext *ctx) 4937 { 4938 TCGv_i32 t0 = tcg_temp_new_i32(); 4939 TCGv_i32 t8 = tcg_constant_i32(8); 4940 TCGv_i32 tm1 = tcg_constant_i32(-1); 4941 int crf = crfS(ctx->opcode); 4942 4943 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4944 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4945 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4946 } 4947 #endif 4948 4949 /*** Cache management ***/ 4950 4951 /* dcbf */ 4952 static void gen_dcbf(DisasContext *ctx) 4953 { 4954 /* XXX: specification says this is treated as a load by the MMU */ 4955 TCGv t0; 4956 gen_set_access_type(ctx, ACCESS_CACHE); 4957 t0 = tcg_temp_new(); 4958 gen_addr_reg_index(ctx, t0); 4959 gen_qemu_ld8u(ctx, t0, t0); 4960 } 4961 4962 /* dcbfep (external PID dcbf) */ 4963 static void gen_dcbfep(DisasContext *ctx) 4964 { 4965 /* XXX: specification says this is treated as a load by the MMU */ 4966 TCGv t0; 4967 CHK_SV(ctx); 4968 gen_set_access_type(ctx, ACCESS_CACHE); 4969 t0 = tcg_temp_new(); 4970 gen_addr_reg_index(ctx, t0); 4971 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4972 } 4973 4974 /* dcbi (Supervisor only) */ 4975 static void gen_dcbi(DisasContext *ctx) 4976 { 4977 #if defined(CONFIG_USER_ONLY) 4978 GEN_PRIV(ctx); 4979 #else 4980 TCGv EA, val; 4981 4982 CHK_SV(ctx); 4983 EA = tcg_temp_new(); 4984 gen_set_access_type(ctx, ACCESS_CACHE); 4985 gen_addr_reg_index(ctx, EA); 4986 val = tcg_temp_new(); 4987 /* XXX: specification says this should be treated as a store by the MMU */ 4988 gen_qemu_ld8u(ctx, val, EA); 4989 gen_qemu_st8(ctx, val, EA); 4990 #endif /* defined(CONFIG_USER_ONLY) */ 4991 } 4992 4993 /* dcdst */ 4994 static void gen_dcbst(DisasContext *ctx) 4995 { 4996 /* XXX: specification say this is treated as a load by the MMU */ 4997 TCGv t0; 4998 gen_set_access_type(ctx, ACCESS_CACHE); 4999 t0 = tcg_temp_new(); 5000 gen_addr_reg_index(ctx, t0); 5001 gen_qemu_ld8u(ctx, t0, t0); 5002 } 5003 5004 /* dcbstep (dcbstep External PID version) */ 5005 static void gen_dcbstep(DisasContext *ctx) 5006 { 5007 /* XXX: specification say this is treated as a load by the MMU */ 5008 TCGv t0; 5009 gen_set_access_type(ctx, ACCESS_CACHE); 5010 t0 = tcg_temp_new(); 5011 gen_addr_reg_index(ctx, t0); 5012 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 5013 } 5014 5015 /* dcbt */ 5016 static void gen_dcbt(DisasContext *ctx) 5017 { 5018 /* 5019 * interpreted as no-op 5020 * XXX: specification say this is treated as a load by the MMU but 5021 * does not generate any exception 5022 */ 5023 } 5024 5025 /* dcbtep */ 5026 static void gen_dcbtep(DisasContext *ctx) 5027 { 5028 /* 5029 * interpreted as no-op 5030 * XXX: specification say this is treated as a load by the MMU but 5031 * does not generate any exception 5032 */ 5033 } 5034 5035 /* dcbtst */ 5036 static void gen_dcbtst(DisasContext *ctx) 5037 { 5038 /* 5039 * interpreted as no-op 5040 * XXX: specification say this is treated as a load by the MMU but 5041 * does not generate any exception 5042 */ 5043 } 5044 5045 /* dcbtstep */ 5046 static void gen_dcbtstep(DisasContext *ctx) 5047 { 5048 /* 5049 * interpreted as no-op 5050 * XXX: specification say this is treated as a load by the MMU but 5051 * does not generate any exception 5052 */ 5053 } 5054 5055 /* dcbtls */ 5056 static void gen_dcbtls(DisasContext *ctx) 5057 { 5058 /* Always fails locking the cache */ 5059 TCGv t0 = tcg_temp_new(); 5060 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5061 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5062 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5063 } 5064 5065 /* dcblc */ 5066 static void gen_dcblc(DisasContext *ctx) 5067 { 5068 /* 5069 * interpreted as no-op 5070 */ 5071 } 5072 5073 /* dcbz */ 5074 static void gen_dcbz(DisasContext *ctx) 5075 { 5076 TCGv tcgv_addr; 5077 TCGv_i32 tcgv_op; 5078 5079 gen_set_access_type(ctx, ACCESS_CACHE); 5080 tcgv_addr = tcg_temp_new(); 5081 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5082 gen_addr_reg_index(ctx, tcgv_addr); 5083 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5084 } 5085 5086 /* dcbzep */ 5087 static void gen_dcbzep(DisasContext *ctx) 5088 { 5089 TCGv tcgv_addr; 5090 TCGv_i32 tcgv_op; 5091 5092 gen_set_access_type(ctx, ACCESS_CACHE); 5093 tcgv_addr = tcg_temp_new(); 5094 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5095 gen_addr_reg_index(ctx, tcgv_addr); 5096 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5097 } 5098 5099 /* dst / dstt */ 5100 static void gen_dst(DisasContext *ctx) 5101 { 5102 if (rA(ctx->opcode) == 0) { 5103 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5104 } else { 5105 /* interpreted as no-op */ 5106 } 5107 } 5108 5109 /* dstst /dststt */ 5110 static void gen_dstst(DisasContext *ctx) 5111 { 5112 if (rA(ctx->opcode) == 0) { 5113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5114 } else { 5115 /* interpreted as no-op */ 5116 } 5117 5118 } 5119 5120 /* dss / dssall */ 5121 static void gen_dss(DisasContext *ctx) 5122 { 5123 /* interpreted as no-op */ 5124 } 5125 5126 /* icbi */ 5127 static void gen_icbi(DisasContext *ctx) 5128 { 5129 TCGv t0; 5130 gen_set_access_type(ctx, ACCESS_CACHE); 5131 t0 = tcg_temp_new(); 5132 gen_addr_reg_index(ctx, t0); 5133 gen_helper_icbi(cpu_env, t0); 5134 } 5135 5136 /* icbiep */ 5137 static void gen_icbiep(DisasContext *ctx) 5138 { 5139 TCGv t0; 5140 gen_set_access_type(ctx, ACCESS_CACHE); 5141 t0 = tcg_temp_new(); 5142 gen_addr_reg_index(ctx, t0); 5143 gen_helper_icbiep(cpu_env, t0); 5144 } 5145 5146 /* Optional: */ 5147 /* dcba */ 5148 static void gen_dcba(DisasContext *ctx) 5149 { 5150 /* 5151 * interpreted as no-op 5152 * XXX: specification say this is treated as a store by the MMU 5153 * but does not generate any exception 5154 */ 5155 } 5156 5157 /*** Segment register manipulation ***/ 5158 /* Supervisor only: */ 5159 5160 /* mfsr */ 5161 static void gen_mfsr(DisasContext *ctx) 5162 { 5163 #if defined(CONFIG_USER_ONLY) 5164 GEN_PRIV(ctx); 5165 #else 5166 TCGv t0; 5167 5168 CHK_SV(ctx); 5169 t0 = tcg_constant_tl(SR(ctx->opcode)); 5170 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5171 #endif /* defined(CONFIG_USER_ONLY) */ 5172 } 5173 5174 /* mfsrin */ 5175 static void gen_mfsrin(DisasContext *ctx) 5176 { 5177 #if defined(CONFIG_USER_ONLY) 5178 GEN_PRIV(ctx); 5179 #else 5180 TCGv t0; 5181 5182 CHK_SV(ctx); 5183 t0 = tcg_temp_new(); 5184 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5185 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5186 #endif /* defined(CONFIG_USER_ONLY) */ 5187 } 5188 5189 /* mtsr */ 5190 static void gen_mtsr(DisasContext *ctx) 5191 { 5192 #if defined(CONFIG_USER_ONLY) 5193 GEN_PRIV(ctx); 5194 #else 5195 TCGv t0; 5196 5197 CHK_SV(ctx); 5198 t0 = tcg_constant_tl(SR(ctx->opcode)); 5199 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5200 #endif /* defined(CONFIG_USER_ONLY) */ 5201 } 5202 5203 /* mtsrin */ 5204 static void gen_mtsrin(DisasContext *ctx) 5205 { 5206 #if defined(CONFIG_USER_ONLY) 5207 GEN_PRIV(ctx); 5208 #else 5209 TCGv t0; 5210 CHK_SV(ctx); 5211 5212 t0 = tcg_temp_new(); 5213 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5214 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5215 #endif /* defined(CONFIG_USER_ONLY) */ 5216 } 5217 5218 #if defined(TARGET_PPC64) 5219 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5220 5221 /* mfsr */ 5222 static void gen_mfsr_64b(DisasContext *ctx) 5223 { 5224 #if defined(CONFIG_USER_ONLY) 5225 GEN_PRIV(ctx); 5226 #else 5227 TCGv t0; 5228 5229 CHK_SV(ctx); 5230 t0 = tcg_constant_tl(SR(ctx->opcode)); 5231 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5232 #endif /* defined(CONFIG_USER_ONLY) */ 5233 } 5234 5235 /* mfsrin */ 5236 static void gen_mfsrin_64b(DisasContext *ctx) 5237 { 5238 #if defined(CONFIG_USER_ONLY) 5239 GEN_PRIV(ctx); 5240 #else 5241 TCGv t0; 5242 5243 CHK_SV(ctx); 5244 t0 = tcg_temp_new(); 5245 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5246 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5247 #endif /* defined(CONFIG_USER_ONLY) */ 5248 } 5249 5250 /* mtsr */ 5251 static void gen_mtsr_64b(DisasContext *ctx) 5252 { 5253 #if defined(CONFIG_USER_ONLY) 5254 GEN_PRIV(ctx); 5255 #else 5256 TCGv t0; 5257 5258 CHK_SV(ctx); 5259 t0 = tcg_constant_tl(SR(ctx->opcode)); 5260 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5261 #endif /* defined(CONFIG_USER_ONLY) */ 5262 } 5263 5264 /* mtsrin */ 5265 static void gen_mtsrin_64b(DisasContext *ctx) 5266 { 5267 #if defined(CONFIG_USER_ONLY) 5268 GEN_PRIV(ctx); 5269 #else 5270 TCGv t0; 5271 5272 CHK_SV(ctx); 5273 t0 = tcg_temp_new(); 5274 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5275 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5276 #endif /* defined(CONFIG_USER_ONLY) */ 5277 } 5278 5279 #endif /* defined(TARGET_PPC64) */ 5280 5281 /*** Lookaside buffer management ***/ 5282 /* Optional & supervisor only: */ 5283 5284 /* tlbia */ 5285 static void gen_tlbia(DisasContext *ctx) 5286 { 5287 #if defined(CONFIG_USER_ONLY) 5288 GEN_PRIV(ctx); 5289 #else 5290 CHK_HV(ctx); 5291 5292 gen_helper_tlbia(cpu_env); 5293 #endif /* defined(CONFIG_USER_ONLY) */ 5294 } 5295 5296 /* tlbsync */ 5297 static void gen_tlbsync(DisasContext *ctx) 5298 { 5299 #if defined(CONFIG_USER_ONLY) 5300 GEN_PRIV(ctx); 5301 #else 5302 5303 if (ctx->gtse) { 5304 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5305 } else { 5306 CHK_HV(ctx); /* Else hypervisor privileged */ 5307 } 5308 5309 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5310 if (ctx->insns_flags & PPC_BOOKE) { 5311 gen_check_tlb_flush(ctx, true); 5312 } 5313 #endif /* defined(CONFIG_USER_ONLY) */ 5314 } 5315 5316 /*** External control ***/ 5317 /* Optional: */ 5318 5319 /* eciwx */ 5320 static void gen_eciwx(DisasContext *ctx) 5321 { 5322 TCGv t0; 5323 /* Should check EAR[E] ! */ 5324 gen_set_access_type(ctx, ACCESS_EXT); 5325 t0 = tcg_temp_new(); 5326 gen_addr_reg_index(ctx, t0); 5327 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5328 DEF_MEMOP(MO_UL | MO_ALIGN)); 5329 } 5330 5331 /* ecowx */ 5332 static void gen_ecowx(DisasContext *ctx) 5333 { 5334 TCGv t0; 5335 /* Should check EAR[E] ! */ 5336 gen_set_access_type(ctx, ACCESS_EXT); 5337 t0 = tcg_temp_new(); 5338 gen_addr_reg_index(ctx, t0); 5339 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5340 DEF_MEMOP(MO_UL | MO_ALIGN)); 5341 } 5342 5343 /* 602 - 603 - G2 TLB management */ 5344 5345 /* tlbld */ 5346 static void gen_tlbld_6xx(DisasContext *ctx) 5347 { 5348 #if defined(CONFIG_USER_ONLY) 5349 GEN_PRIV(ctx); 5350 #else 5351 CHK_SV(ctx); 5352 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5353 #endif /* defined(CONFIG_USER_ONLY) */ 5354 } 5355 5356 /* tlbli */ 5357 static void gen_tlbli_6xx(DisasContext *ctx) 5358 { 5359 #if defined(CONFIG_USER_ONLY) 5360 GEN_PRIV(ctx); 5361 #else 5362 CHK_SV(ctx); 5363 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364 #endif /* defined(CONFIG_USER_ONLY) */ 5365 } 5366 5367 /* BookE specific instructions */ 5368 5369 /* XXX: not implemented on 440 ? */ 5370 static void gen_mfapidi(DisasContext *ctx) 5371 { 5372 /* XXX: TODO */ 5373 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5374 } 5375 5376 /* XXX: not implemented on 440 ? */ 5377 static void gen_tlbiva(DisasContext *ctx) 5378 { 5379 #if defined(CONFIG_USER_ONLY) 5380 GEN_PRIV(ctx); 5381 #else 5382 TCGv t0; 5383 5384 CHK_SV(ctx); 5385 t0 = tcg_temp_new(); 5386 gen_addr_reg_index(ctx, t0); 5387 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5388 #endif /* defined(CONFIG_USER_ONLY) */ 5389 } 5390 5391 /* All 405 MAC instructions are translated here */ 5392 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5393 int ra, int rb, int rt, int Rc) 5394 { 5395 TCGv t0, t1; 5396 5397 t0 = tcg_temp_new(); 5398 t1 = tcg_temp_new(); 5399 5400 switch (opc3 & 0x0D) { 5401 case 0x05: 5402 /* macchw - macchw. - macchwo - macchwo. */ 5403 /* macchws - macchws. - macchwso - macchwso. */ 5404 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5405 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5406 /* mulchw - mulchw. */ 5407 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5408 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5409 tcg_gen_ext16s_tl(t1, t1); 5410 break; 5411 case 0x04: 5412 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5413 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5414 /* mulchwu - mulchwu. */ 5415 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5416 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5417 tcg_gen_ext16u_tl(t1, t1); 5418 break; 5419 case 0x01: 5420 /* machhw - machhw. - machhwo - machhwo. */ 5421 /* machhws - machhws. - machhwso - machhwso. */ 5422 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5423 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5424 /* mulhhw - mulhhw. */ 5425 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5426 tcg_gen_ext16s_tl(t0, t0); 5427 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5428 tcg_gen_ext16s_tl(t1, t1); 5429 break; 5430 case 0x00: 5431 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5432 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5433 /* mulhhwu - mulhhwu. */ 5434 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5435 tcg_gen_ext16u_tl(t0, t0); 5436 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5437 tcg_gen_ext16u_tl(t1, t1); 5438 break; 5439 case 0x0D: 5440 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5441 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5442 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5443 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5444 /* mullhw - mullhw. */ 5445 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5446 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5447 break; 5448 case 0x0C: 5449 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5450 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5451 /* mullhwu - mullhwu. */ 5452 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5453 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5454 break; 5455 } 5456 if (opc2 & 0x04) { 5457 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5458 tcg_gen_mul_tl(t1, t0, t1); 5459 if (opc2 & 0x02) { 5460 /* nmultiply-and-accumulate (0x0E) */ 5461 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5462 } else { 5463 /* multiply-and-accumulate (0x0C) */ 5464 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5465 } 5466 5467 if (opc3 & 0x12) { 5468 /* Check overflow and/or saturate */ 5469 TCGLabel *l1 = gen_new_label(); 5470 5471 if (opc3 & 0x10) { 5472 /* Start with XER OV disabled, the most likely case */ 5473 tcg_gen_movi_tl(cpu_ov, 0); 5474 } 5475 if (opc3 & 0x01) { 5476 /* Signed */ 5477 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5478 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5479 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5480 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5481 if (opc3 & 0x02) { 5482 /* Saturate */ 5483 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5484 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5485 } 5486 } else { 5487 /* Unsigned */ 5488 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5489 if (opc3 & 0x02) { 5490 /* Saturate */ 5491 tcg_gen_movi_tl(t0, UINT32_MAX); 5492 } 5493 } 5494 if (opc3 & 0x10) { 5495 /* Check overflow */ 5496 tcg_gen_movi_tl(cpu_ov, 1); 5497 tcg_gen_movi_tl(cpu_so, 1); 5498 } 5499 gen_set_label(l1); 5500 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5501 } 5502 } else { 5503 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5504 } 5505 if (unlikely(Rc) != 0) { 5506 /* Update Rc0 */ 5507 gen_set_Rc0(ctx, cpu_gpr[rt]); 5508 } 5509 } 5510 5511 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5512 static void glue(gen_, name)(DisasContext *ctx) \ 5513 { \ 5514 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5515 rD(ctx->opcode), Rc(ctx->opcode)); \ 5516 } 5517 5518 /* macchw - macchw. */ 5519 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5520 /* macchwo - macchwo. */ 5521 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5522 /* macchws - macchws. */ 5523 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5524 /* macchwso - macchwso. */ 5525 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5526 /* macchwsu - macchwsu. */ 5527 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5528 /* macchwsuo - macchwsuo. */ 5529 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5530 /* macchwu - macchwu. */ 5531 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5532 /* macchwuo - macchwuo. */ 5533 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5534 /* machhw - machhw. */ 5535 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5536 /* machhwo - machhwo. */ 5537 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5538 /* machhws - machhws. */ 5539 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5540 /* machhwso - machhwso. */ 5541 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5542 /* machhwsu - machhwsu. */ 5543 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5544 /* machhwsuo - machhwsuo. */ 5545 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5546 /* machhwu - machhwu. */ 5547 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5548 /* machhwuo - machhwuo. */ 5549 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5550 /* maclhw - maclhw. */ 5551 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5552 /* maclhwo - maclhwo. */ 5553 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5554 /* maclhws - maclhws. */ 5555 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5556 /* maclhwso - maclhwso. */ 5557 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5558 /* maclhwu - maclhwu. */ 5559 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5560 /* maclhwuo - maclhwuo. */ 5561 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5562 /* maclhwsu - maclhwsu. */ 5563 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5564 /* maclhwsuo - maclhwsuo. */ 5565 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5566 /* nmacchw - nmacchw. */ 5567 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5568 /* nmacchwo - nmacchwo. */ 5569 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5570 /* nmacchws - nmacchws. */ 5571 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5572 /* nmacchwso - nmacchwso. */ 5573 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5574 /* nmachhw - nmachhw. */ 5575 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5576 /* nmachhwo - nmachhwo. */ 5577 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5578 /* nmachhws - nmachhws. */ 5579 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5580 /* nmachhwso - nmachhwso. */ 5581 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5582 /* nmaclhw - nmaclhw. */ 5583 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5584 /* nmaclhwo - nmaclhwo. */ 5585 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5586 /* nmaclhws - nmaclhws. */ 5587 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5588 /* nmaclhwso - nmaclhwso. */ 5589 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5590 5591 /* mulchw - mulchw. */ 5592 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5593 /* mulchwu - mulchwu. */ 5594 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5595 /* mulhhw - mulhhw. */ 5596 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5597 /* mulhhwu - mulhhwu. */ 5598 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5599 /* mullhw - mullhw. */ 5600 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5601 /* mullhwu - mullhwu. */ 5602 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5603 5604 /* mfdcr */ 5605 static void gen_mfdcr(DisasContext *ctx) 5606 { 5607 #if defined(CONFIG_USER_ONLY) 5608 GEN_PRIV(ctx); 5609 #else 5610 TCGv dcrn; 5611 5612 CHK_SV(ctx); 5613 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5614 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5615 #endif /* defined(CONFIG_USER_ONLY) */ 5616 } 5617 5618 /* mtdcr */ 5619 static void gen_mtdcr(DisasContext *ctx) 5620 { 5621 #if defined(CONFIG_USER_ONLY) 5622 GEN_PRIV(ctx); 5623 #else 5624 TCGv dcrn; 5625 5626 CHK_SV(ctx); 5627 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5628 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5629 #endif /* defined(CONFIG_USER_ONLY) */ 5630 } 5631 5632 /* mfdcrx */ 5633 /* XXX: not implemented on 440 ? */ 5634 static void gen_mfdcrx(DisasContext *ctx) 5635 { 5636 #if defined(CONFIG_USER_ONLY) 5637 GEN_PRIV(ctx); 5638 #else 5639 CHK_SV(ctx); 5640 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5641 cpu_gpr[rA(ctx->opcode)]); 5642 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5643 #endif /* defined(CONFIG_USER_ONLY) */ 5644 } 5645 5646 /* mtdcrx */ 5647 /* XXX: not implemented on 440 ? */ 5648 static void gen_mtdcrx(DisasContext *ctx) 5649 { 5650 #if defined(CONFIG_USER_ONLY) 5651 GEN_PRIV(ctx); 5652 #else 5653 CHK_SV(ctx); 5654 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5655 cpu_gpr[rS(ctx->opcode)]); 5656 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5657 #endif /* defined(CONFIG_USER_ONLY) */ 5658 } 5659 5660 /* dccci */ 5661 static void gen_dccci(DisasContext *ctx) 5662 { 5663 CHK_SV(ctx); 5664 /* interpreted as no-op */ 5665 } 5666 5667 /* dcread */ 5668 static void gen_dcread(DisasContext *ctx) 5669 { 5670 #if defined(CONFIG_USER_ONLY) 5671 GEN_PRIV(ctx); 5672 #else 5673 TCGv EA, val; 5674 5675 CHK_SV(ctx); 5676 gen_set_access_type(ctx, ACCESS_CACHE); 5677 EA = tcg_temp_new(); 5678 gen_addr_reg_index(ctx, EA); 5679 val = tcg_temp_new(); 5680 gen_qemu_ld32u(ctx, val, EA); 5681 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5682 #endif /* defined(CONFIG_USER_ONLY) */ 5683 } 5684 5685 /* icbt */ 5686 static void gen_icbt_40x(DisasContext *ctx) 5687 { 5688 /* 5689 * interpreted as no-op 5690 * XXX: specification say this is treated as a load by the MMU but 5691 * does not generate any exception 5692 */ 5693 } 5694 5695 /* iccci */ 5696 static void gen_iccci(DisasContext *ctx) 5697 { 5698 CHK_SV(ctx); 5699 /* interpreted as no-op */ 5700 } 5701 5702 /* icread */ 5703 static void gen_icread(DisasContext *ctx) 5704 { 5705 CHK_SV(ctx); 5706 /* interpreted as no-op */ 5707 } 5708 5709 /* rfci (supervisor only) */ 5710 static void gen_rfci_40x(DisasContext *ctx) 5711 { 5712 #if defined(CONFIG_USER_ONLY) 5713 GEN_PRIV(ctx); 5714 #else 5715 CHK_SV(ctx); 5716 /* Restore CPU state */ 5717 gen_helper_40x_rfci(cpu_env); 5718 ctx->base.is_jmp = DISAS_EXIT; 5719 #endif /* defined(CONFIG_USER_ONLY) */ 5720 } 5721 5722 static void gen_rfci(DisasContext *ctx) 5723 { 5724 #if defined(CONFIG_USER_ONLY) 5725 GEN_PRIV(ctx); 5726 #else 5727 CHK_SV(ctx); 5728 /* Restore CPU state */ 5729 gen_helper_rfci(cpu_env); 5730 ctx->base.is_jmp = DISAS_EXIT; 5731 #endif /* defined(CONFIG_USER_ONLY) */ 5732 } 5733 5734 /* BookE specific */ 5735 5736 /* XXX: not implemented on 440 ? */ 5737 static void gen_rfdi(DisasContext *ctx) 5738 { 5739 #if defined(CONFIG_USER_ONLY) 5740 GEN_PRIV(ctx); 5741 #else 5742 CHK_SV(ctx); 5743 /* Restore CPU state */ 5744 gen_helper_rfdi(cpu_env); 5745 ctx->base.is_jmp = DISAS_EXIT; 5746 #endif /* defined(CONFIG_USER_ONLY) */ 5747 } 5748 5749 /* XXX: not implemented on 440 ? */ 5750 static void gen_rfmci(DisasContext *ctx) 5751 { 5752 #if defined(CONFIG_USER_ONLY) 5753 GEN_PRIV(ctx); 5754 #else 5755 CHK_SV(ctx); 5756 /* Restore CPU state */ 5757 gen_helper_rfmci(cpu_env); 5758 ctx->base.is_jmp = DISAS_EXIT; 5759 #endif /* defined(CONFIG_USER_ONLY) */ 5760 } 5761 5762 /* TLB management - PowerPC 405 implementation */ 5763 5764 /* tlbre */ 5765 static void gen_tlbre_40x(DisasContext *ctx) 5766 { 5767 #if defined(CONFIG_USER_ONLY) 5768 GEN_PRIV(ctx); 5769 #else 5770 CHK_SV(ctx); 5771 switch (rB(ctx->opcode)) { 5772 case 0: 5773 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5774 cpu_gpr[rA(ctx->opcode)]); 5775 break; 5776 case 1: 5777 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5778 cpu_gpr[rA(ctx->opcode)]); 5779 break; 5780 default: 5781 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5782 break; 5783 } 5784 #endif /* defined(CONFIG_USER_ONLY) */ 5785 } 5786 5787 /* tlbsx - tlbsx. */ 5788 static void gen_tlbsx_40x(DisasContext *ctx) 5789 { 5790 #if defined(CONFIG_USER_ONLY) 5791 GEN_PRIV(ctx); 5792 #else 5793 TCGv t0; 5794 5795 CHK_SV(ctx); 5796 t0 = tcg_temp_new(); 5797 gen_addr_reg_index(ctx, t0); 5798 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5799 if (Rc(ctx->opcode)) { 5800 TCGLabel *l1 = gen_new_label(); 5801 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5802 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5803 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5804 gen_set_label(l1); 5805 } 5806 #endif /* defined(CONFIG_USER_ONLY) */ 5807 } 5808 5809 /* tlbwe */ 5810 static void gen_tlbwe_40x(DisasContext *ctx) 5811 { 5812 #if defined(CONFIG_USER_ONLY) 5813 GEN_PRIV(ctx); 5814 #else 5815 CHK_SV(ctx); 5816 5817 switch (rB(ctx->opcode)) { 5818 case 0: 5819 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5820 cpu_gpr[rS(ctx->opcode)]); 5821 break; 5822 case 1: 5823 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5824 cpu_gpr[rS(ctx->opcode)]); 5825 break; 5826 default: 5827 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5828 break; 5829 } 5830 #endif /* defined(CONFIG_USER_ONLY) */ 5831 } 5832 5833 /* TLB management - PowerPC 440 implementation */ 5834 5835 /* tlbre */ 5836 static void gen_tlbre_440(DisasContext *ctx) 5837 { 5838 #if defined(CONFIG_USER_ONLY) 5839 GEN_PRIV(ctx); 5840 #else 5841 CHK_SV(ctx); 5842 5843 switch (rB(ctx->opcode)) { 5844 case 0: 5845 case 1: 5846 case 2: 5847 { 5848 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5849 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5850 t0, cpu_gpr[rA(ctx->opcode)]); 5851 } 5852 break; 5853 default: 5854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5855 break; 5856 } 5857 #endif /* defined(CONFIG_USER_ONLY) */ 5858 } 5859 5860 /* tlbsx - tlbsx. */ 5861 static void gen_tlbsx_440(DisasContext *ctx) 5862 { 5863 #if defined(CONFIG_USER_ONLY) 5864 GEN_PRIV(ctx); 5865 #else 5866 TCGv t0; 5867 5868 CHK_SV(ctx); 5869 t0 = tcg_temp_new(); 5870 gen_addr_reg_index(ctx, t0); 5871 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5872 if (Rc(ctx->opcode)) { 5873 TCGLabel *l1 = gen_new_label(); 5874 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5875 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5876 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5877 gen_set_label(l1); 5878 } 5879 #endif /* defined(CONFIG_USER_ONLY) */ 5880 } 5881 5882 /* tlbwe */ 5883 static void gen_tlbwe_440(DisasContext *ctx) 5884 { 5885 #if defined(CONFIG_USER_ONLY) 5886 GEN_PRIV(ctx); 5887 #else 5888 CHK_SV(ctx); 5889 switch (rB(ctx->opcode)) { 5890 case 0: 5891 case 1: 5892 case 2: 5893 { 5894 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5895 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5896 cpu_gpr[rS(ctx->opcode)]); 5897 } 5898 break; 5899 default: 5900 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5901 break; 5902 } 5903 #endif /* defined(CONFIG_USER_ONLY) */ 5904 } 5905 5906 /* TLB management - PowerPC BookE 2.06 implementation */ 5907 5908 /* tlbre */ 5909 static void gen_tlbre_booke206(DisasContext *ctx) 5910 { 5911 #if defined(CONFIG_USER_ONLY) 5912 GEN_PRIV(ctx); 5913 #else 5914 CHK_SV(ctx); 5915 gen_helper_booke206_tlbre(cpu_env); 5916 #endif /* defined(CONFIG_USER_ONLY) */ 5917 } 5918 5919 /* tlbsx - tlbsx. */ 5920 static void gen_tlbsx_booke206(DisasContext *ctx) 5921 { 5922 #if defined(CONFIG_USER_ONLY) 5923 GEN_PRIV(ctx); 5924 #else 5925 TCGv t0; 5926 5927 CHK_SV(ctx); 5928 if (rA(ctx->opcode)) { 5929 t0 = tcg_temp_new(); 5930 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5931 } else { 5932 t0 = cpu_gpr[rB(ctx->opcode)]; 5933 } 5934 gen_helper_booke206_tlbsx(cpu_env, t0); 5935 #endif /* defined(CONFIG_USER_ONLY) */ 5936 } 5937 5938 /* tlbwe */ 5939 static void gen_tlbwe_booke206(DisasContext *ctx) 5940 { 5941 #if defined(CONFIG_USER_ONLY) 5942 GEN_PRIV(ctx); 5943 #else 5944 CHK_SV(ctx); 5945 gen_helper_booke206_tlbwe(cpu_env); 5946 #endif /* defined(CONFIG_USER_ONLY) */ 5947 } 5948 5949 static void gen_tlbivax_booke206(DisasContext *ctx) 5950 { 5951 #if defined(CONFIG_USER_ONLY) 5952 GEN_PRIV(ctx); 5953 #else 5954 TCGv t0; 5955 5956 CHK_SV(ctx); 5957 t0 = tcg_temp_new(); 5958 gen_addr_reg_index(ctx, t0); 5959 gen_helper_booke206_tlbivax(cpu_env, t0); 5960 #endif /* defined(CONFIG_USER_ONLY) */ 5961 } 5962 5963 static void gen_tlbilx_booke206(DisasContext *ctx) 5964 { 5965 #if defined(CONFIG_USER_ONLY) 5966 GEN_PRIV(ctx); 5967 #else 5968 TCGv t0; 5969 5970 CHK_SV(ctx); 5971 t0 = tcg_temp_new(); 5972 gen_addr_reg_index(ctx, t0); 5973 5974 switch ((ctx->opcode >> 21) & 0x3) { 5975 case 0: 5976 gen_helper_booke206_tlbilx0(cpu_env, t0); 5977 break; 5978 case 1: 5979 gen_helper_booke206_tlbilx1(cpu_env, t0); 5980 break; 5981 case 3: 5982 gen_helper_booke206_tlbilx3(cpu_env, t0); 5983 break; 5984 default: 5985 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5986 break; 5987 } 5988 #endif /* defined(CONFIG_USER_ONLY) */ 5989 } 5990 5991 /* wrtee */ 5992 static void gen_wrtee(DisasContext *ctx) 5993 { 5994 #if defined(CONFIG_USER_ONLY) 5995 GEN_PRIV(ctx); 5996 #else 5997 TCGv t0; 5998 5999 CHK_SV(ctx); 6000 t0 = tcg_temp_new(); 6001 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6002 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6003 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6004 gen_ppc_maybe_interrupt(ctx); 6005 /* 6006 * Stop translation to have a chance to raise an exception if we 6007 * just set msr_ee to 1 6008 */ 6009 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6010 #endif /* defined(CONFIG_USER_ONLY) */ 6011 } 6012 6013 /* wrteei */ 6014 static void gen_wrteei(DisasContext *ctx) 6015 { 6016 #if defined(CONFIG_USER_ONLY) 6017 GEN_PRIV(ctx); 6018 #else 6019 CHK_SV(ctx); 6020 if (ctx->opcode & 0x00008000) { 6021 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6022 gen_ppc_maybe_interrupt(ctx); 6023 /* Stop translation to have a chance to raise an exception */ 6024 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6025 } else { 6026 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6027 } 6028 #endif /* defined(CONFIG_USER_ONLY) */ 6029 } 6030 6031 /* PowerPC 440 specific instructions */ 6032 6033 /* dlmzb */ 6034 static void gen_dlmzb(DisasContext *ctx) 6035 { 6036 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6037 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6038 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6039 } 6040 6041 /* mbar replaces eieio on 440 */ 6042 static void gen_mbar(DisasContext *ctx) 6043 { 6044 /* interpreted as no-op */ 6045 } 6046 6047 /* msync replaces sync on 440 */ 6048 static void gen_msync_4xx(DisasContext *ctx) 6049 { 6050 /* Only e500 seems to treat reserved bits as invalid */ 6051 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6052 (ctx->opcode & 0x03FFF801)) { 6053 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6054 } 6055 /* otherwise interpreted as no-op */ 6056 } 6057 6058 /* icbt */ 6059 static void gen_icbt_440(DisasContext *ctx) 6060 { 6061 /* 6062 * interpreted as no-op 6063 * XXX: specification say this is treated as a load by the MMU but 6064 * does not generate any exception 6065 */ 6066 } 6067 6068 #if defined(TARGET_PPC64) 6069 static void gen_maddld(DisasContext *ctx) 6070 { 6071 TCGv_i64 t1 = tcg_temp_new_i64(); 6072 6073 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6074 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6075 } 6076 6077 /* maddhd maddhdu */ 6078 static void gen_maddhd_maddhdu(DisasContext *ctx) 6079 { 6080 TCGv_i64 lo = tcg_temp_new_i64(); 6081 TCGv_i64 hi = tcg_temp_new_i64(); 6082 TCGv_i64 t1 = tcg_temp_new_i64(); 6083 6084 if (Rc(ctx->opcode)) { 6085 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6086 cpu_gpr[rB(ctx->opcode)]); 6087 tcg_gen_movi_i64(t1, 0); 6088 } else { 6089 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6090 cpu_gpr[rB(ctx->opcode)]); 6091 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6092 } 6093 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6094 cpu_gpr[rC(ctx->opcode)], t1); 6095 } 6096 #endif /* defined(TARGET_PPC64) */ 6097 6098 static void gen_tbegin(DisasContext *ctx) 6099 { 6100 if (unlikely(!ctx->tm_enabled)) { 6101 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6102 return; 6103 } 6104 gen_helper_tbegin(cpu_env); 6105 } 6106 6107 #define GEN_TM_NOOP(name) \ 6108 static inline void gen_##name(DisasContext *ctx) \ 6109 { \ 6110 if (unlikely(!ctx->tm_enabled)) { \ 6111 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6112 return; \ 6113 } \ 6114 /* \ 6115 * Because tbegin always fails in QEMU, these user \ 6116 * space instructions all have a simple implementation: \ 6117 * \ 6118 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6119 * = 0b0 || 0b00 || 0b0 \ 6120 */ \ 6121 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6122 } 6123 6124 GEN_TM_NOOP(tend); 6125 GEN_TM_NOOP(tabort); 6126 GEN_TM_NOOP(tabortwc); 6127 GEN_TM_NOOP(tabortwci); 6128 GEN_TM_NOOP(tabortdc); 6129 GEN_TM_NOOP(tabortdci); 6130 GEN_TM_NOOP(tsr); 6131 6132 static inline void gen_cp_abort(DisasContext *ctx) 6133 { 6134 /* Do Nothing */ 6135 } 6136 6137 #define GEN_CP_PASTE_NOOP(name) \ 6138 static inline void gen_##name(DisasContext *ctx) \ 6139 { \ 6140 /* \ 6141 * Generate invalid exception until we have an \ 6142 * implementation of the copy paste facility \ 6143 */ \ 6144 gen_invalid(ctx); \ 6145 } 6146 6147 GEN_CP_PASTE_NOOP(copy) 6148 GEN_CP_PASTE_NOOP(paste) 6149 6150 static void gen_tcheck(DisasContext *ctx) 6151 { 6152 if (unlikely(!ctx->tm_enabled)) { 6153 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6154 return; 6155 } 6156 /* 6157 * Because tbegin always fails, the tcheck implementation is 6158 * simple: 6159 * 6160 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6161 * = 0b1 || 0b00 || 0b0 6162 */ 6163 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6164 } 6165 6166 #if defined(CONFIG_USER_ONLY) 6167 #define GEN_TM_PRIV_NOOP(name) \ 6168 static inline void gen_##name(DisasContext *ctx) \ 6169 { \ 6170 gen_priv_opc(ctx); \ 6171 } 6172 6173 #else 6174 6175 #define GEN_TM_PRIV_NOOP(name) \ 6176 static inline void gen_##name(DisasContext *ctx) \ 6177 { \ 6178 CHK_SV(ctx); \ 6179 if (unlikely(!ctx->tm_enabled)) { \ 6180 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6181 return; \ 6182 } \ 6183 /* \ 6184 * Because tbegin always fails, the implementation is \ 6185 * simple: \ 6186 * \ 6187 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6188 * = 0b0 || 0b00 | 0b0 \ 6189 */ \ 6190 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6191 } 6192 6193 #endif 6194 6195 GEN_TM_PRIV_NOOP(treclaim); 6196 GEN_TM_PRIV_NOOP(trechkpt); 6197 6198 static inline void get_fpr(TCGv_i64 dst, int regno) 6199 { 6200 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6201 } 6202 6203 static inline void set_fpr(int regno, TCGv_i64 src) 6204 { 6205 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6206 /* 6207 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6208 * corresponding to the target FPR was undefined. However, 6209 * most (if not all) real hardware were setting the result to 0. 6210 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6211 * to be 0. 6212 */ 6213 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6214 } 6215 6216 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6217 { 6218 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6219 } 6220 6221 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6222 { 6223 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6224 } 6225 6226 /* 6227 * Helpers for decodetree used by !function for decoding arguments. 6228 */ 6229 static int times_2(DisasContext *ctx, int x) 6230 { 6231 return x * 2; 6232 } 6233 6234 static int times_4(DisasContext *ctx, int x) 6235 { 6236 return x * 4; 6237 } 6238 6239 static int times_16(DisasContext *ctx, int x) 6240 { 6241 return x * 16; 6242 } 6243 6244 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6245 { 6246 return deposit64(0xfffffffffffffe00, 3, 6, x); 6247 } 6248 6249 /* 6250 * Helpers for trans_* functions to check for specific insns flags. 6251 * Use token pasting to ensure that we use the proper flag with the 6252 * proper variable. 6253 */ 6254 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6255 do { \ 6256 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6257 return false; \ 6258 } \ 6259 } while (0) 6260 6261 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6262 do { \ 6263 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6264 return false; \ 6265 } \ 6266 } while (0) 6267 6268 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6269 #if TARGET_LONG_BITS == 32 6270 # define REQUIRE_64BIT(CTX) return false 6271 #else 6272 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6273 #endif 6274 6275 #define REQUIRE_VECTOR(CTX) \ 6276 do { \ 6277 if (unlikely(!(CTX)->altivec_enabled)) { \ 6278 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6279 return true; \ 6280 } \ 6281 } while (0) 6282 6283 #define REQUIRE_VSX(CTX) \ 6284 do { \ 6285 if (unlikely(!(CTX)->vsx_enabled)) { \ 6286 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6287 return true; \ 6288 } \ 6289 } while (0) 6290 6291 #define REQUIRE_FPU(ctx) \ 6292 do { \ 6293 if (unlikely(!(ctx)->fpu_enabled)) { \ 6294 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6295 return true; \ 6296 } \ 6297 } while (0) 6298 6299 #if !defined(CONFIG_USER_ONLY) 6300 #define REQUIRE_SV(CTX) \ 6301 do { \ 6302 if (unlikely((CTX)->pr)) { \ 6303 gen_priv_opc(CTX); \ 6304 return true; \ 6305 } \ 6306 } while (0) 6307 6308 #define REQUIRE_HV(CTX) \ 6309 do { \ 6310 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6311 gen_priv_opc(CTX); \ 6312 return true; \ 6313 } \ 6314 } while (0) 6315 #else 6316 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6317 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6318 #endif 6319 6320 /* 6321 * Helpers for implementing sets of trans_* functions. 6322 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6323 */ 6324 #define TRANS(NAME, FUNC, ...) \ 6325 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6326 { return FUNC(ctx, a, __VA_ARGS__); } 6327 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6328 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6329 { \ 6330 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6331 return FUNC(ctx, a, __VA_ARGS__); \ 6332 } 6333 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6334 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6335 { \ 6336 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6337 return FUNC(ctx, a, __VA_ARGS__); \ 6338 } 6339 6340 #define TRANS64(NAME, FUNC, ...) \ 6341 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6342 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6343 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6344 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6345 { \ 6346 REQUIRE_64BIT(ctx); \ 6347 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6348 return FUNC(ctx, a, __VA_ARGS__); \ 6349 } 6350 6351 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6352 6353 6354 #include "decode-insn32.c.inc" 6355 #include "decode-insn64.c.inc" 6356 #include "power8-pmu-regs.c.inc" 6357 6358 /* 6359 * Incorporate CIA into the constant when R=1. 6360 * Validate that when R=1, RA=0. 6361 */ 6362 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6363 { 6364 d->rt = a->rt; 6365 d->ra = a->ra; 6366 d->si = a->si; 6367 if (a->r) { 6368 if (unlikely(a->ra != 0)) { 6369 gen_invalid(ctx); 6370 return false; 6371 } 6372 d->si += ctx->cia; 6373 } 6374 return true; 6375 } 6376 6377 #include "translate/fixedpoint-impl.c.inc" 6378 6379 #include "translate/fp-impl.c.inc" 6380 6381 #include "translate/vmx-impl.c.inc" 6382 6383 #include "translate/vsx-impl.c.inc" 6384 6385 #include "translate/dfp-impl.c.inc" 6386 6387 #include "translate/spe-impl.c.inc" 6388 6389 #include "translate/branch-impl.c.inc" 6390 6391 #include "translate/processor-ctrl-impl.c.inc" 6392 6393 #include "translate/storage-ctrl-impl.c.inc" 6394 6395 /* Handles lfdp */ 6396 static void gen_dform39(DisasContext *ctx) 6397 { 6398 if ((ctx->opcode & 0x3) == 0) { 6399 if (ctx->insns_flags2 & PPC2_ISA205) { 6400 return gen_lfdp(ctx); 6401 } 6402 } 6403 return gen_invalid(ctx); 6404 } 6405 6406 /* Handles stfdp */ 6407 static void gen_dform3D(DisasContext *ctx) 6408 { 6409 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6410 /* stfdp */ 6411 if (ctx->insns_flags2 & PPC2_ISA205) { 6412 return gen_stfdp(ctx); 6413 } 6414 } 6415 return gen_invalid(ctx); 6416 } 6417 6418 #if defined(TARGET_PPC64) 6419 /* brd */ 6420 static void gen_brd(DisasContext *ctx) 6421 { 6422 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6423 } 6424 6425 /* brw */ 6426 static void gen_brw(DisasContext *ctx) 6427 { 6428 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6429 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6430 6431 } 6432 6433 /* brh */ 6434 static void gen_brh(DisasContext *ctx) 6435 { 6436 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6437 TCGv_i64 t1 = tcg_temp_new_i64(); 6438 TCGv_i64 t2 = tcg_temp_new_i64(); 6439 6440 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6441 tcg_gen_and_i64(t2, t1, mask); 6442 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6443 tcg_gen_shli_i64(t1, t1, 8); 6444 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6445 } 6446 #endif 6447 6448 static opcode_t opcodes[] = { 6449 #if defined(TARGET_PPC64) 6450 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6451 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6452 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6453 #endif 6454 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6455 #if defined(TARGET_PPC64) 6456 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6457 #endif 6458 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6459 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6460 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6461 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6462 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6464 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6465 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6466 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6467 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468 #if defined(TARGET_PPC64) 6469 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6470 #endif 6471 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6472 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6473 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6474 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6477 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6478 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6479 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6480 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6481 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6482 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6483 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6484 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6485 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6486 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6487 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6488 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6489 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6490 #if defined(TARGET_PPC64) 6491 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6492 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6493 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6494 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6495 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6496 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6497 #endif 6498 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6499 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6500 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6501 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6502 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6503 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6504 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6505 #if defined(TARGET_PPC64) 6506 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6507 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6508 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6509 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6510 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6511 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6512 PPC_NONE, PPC2_ISA300), 6513 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6514 PPC_NONE, PPC2_ISA300), 6515 #endif 6516 /* handles lfdp, lxsd, lxssp */ 6517 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6518 /* handles stfdp, stxsd, stxssp */ 6519 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6520 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6521 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6522 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6523 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6524 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6525 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6526 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6527 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6528 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6529 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6530 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6531 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6532 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6533 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6534 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6535 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6536 #if defined(TARGET_PPC64) 6537 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6538 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6539 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6540 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6541 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6542 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6543 #endif 6544 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6545 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6546 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6547 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6548 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6549 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6550 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6551 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6552 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6553 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6554 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6555 #if defined(TARGET_PPC64) 6556 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6557 #if !defined(CONFIG_USER_ONLY) 6558 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6559 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6560 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6561 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6562 #endif 6563 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6564 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6565 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6566 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6567 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6568 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6569 #endif 6570 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6571 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6572 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6573 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6574 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6575 #if defined(TARGET_PPC64) 6576 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6577 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6578 #endif 6579 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6580 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6581 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6582 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6583 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6584 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6585 #if defined(TARGET_PPC64) 6586 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6587 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6588 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6589 #endif 6590 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6591 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6592 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6593 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6594 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6595 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6596 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6597 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6598 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6599 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6600 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6601 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6602 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6603 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6604 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6605 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6606 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6607 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6608 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6609 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6610 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6611 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6612 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6613 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6614 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6615 #if defined(TARGET_PPC64) 6616 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6617 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6618 PPC_SEGMENT_64B), 6619 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6620 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6621 PPC_SEGMENT_64B), 6622 #endif 6623 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6624 /* 6625 * XXX Those instructions will need to be handled differently for 6626 * different ISA versions 6627 */ 6628 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6629 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6630 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6631 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6632 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6633 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6634 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6635 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6636 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6637 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6638 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6639 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6640 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6641 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6642 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6643 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6644 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6645 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6646 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6647 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6648 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6649 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6650 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6651 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6652 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6653 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6654 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6655 PPC_NONE, PPC2_BOOKE206), 6656 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6657 PPC_NONE, PPC2_BOOKE206), 6658 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6659 PPC_NONE, PPC2_BOOKE206), 6660 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6661 PPC_NONE, PPC2_BOOKE206), 6662 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6663 PPC_NONE, PPC2_BOOKE206), 6664 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6665 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6666 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6667 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6668 PPC_BOOKE, PPC2_BOOKE206), 6669 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6670 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6671 PPC_BOOKE, PPC2_BOOKE206), 6672 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6673 PPC_440_SPEC), 6674 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6675 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6676 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6677 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6678 #if defined(TARGET_PPC64) 6679 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6680 PPC2_ISA300), 6681 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6682 #endif 6683 6684 #undef GEN_INT_ARITH_ADD 6685 #undef GEN_INT_ARITH_ADD_CONST 6686 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6687 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6688 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6689 add_ca, compute_ca, compute_ov) \ 6690 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6691 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6692 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6693 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6694 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6695 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6696 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6697 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6698 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6699 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6700 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6701 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6702 6703 #undef GEN_INT_ARITH_DIVW 6704 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6705 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6706 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6707 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6708 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6709 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6710 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6711 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6713 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6714 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6715 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6716 6717 #if defined(TARGET_PPC64) 6718 #undef GEN_INT_ARITH_DIVD 6719 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6720 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6721 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6722 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6723 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6724 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6725 6726 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6727 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6728 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6729 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6730 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6731 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6732 6733 #undef GEN_INT_ARITH_MUL_HELPER 6734 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6735 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6736 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6737 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6738 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6739 #endif 6740 6741 #undef GEN_INT_ARITH_SUBF 6742 #undef GEN_INT_ARITH_SUBF_CONST 6743 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6744 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6745 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6746 add_ca, compute_ca, compute_ov) \ 6747 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6748 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6749 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6750 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6751 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6752 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6753 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6754 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6755 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6756 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6757 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6758 6759 #undef GEN_LOGICAL1 6760 #undef GEN_LOGICAL2 6761 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6762 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6763 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6764 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6765 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6766 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6767 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6768 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6769 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6770 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6771 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6772 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6773 #if defined(TARGET_PPC64) 6774 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6775 #endif 6776 6777 #if defined(TARGET_PPC64) 6778 #undef GEN_PPC64_R2 6779 #undef GEN_PPC64_R4 6780 #define GEN_PPC64_R2(name, opc1, opc2) \ 6781 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6782 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6783 PPC_64B) 6784 #define GEN_PPC64_R4(name, opc1, opc2) \ 6785 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6786 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6787 PPC_64B), \ 6788 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6789 PPC_64B), \ 6790 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6791 PPC_64B) 6792 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6793 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6794 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6795 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6796 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6797 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6798 #endif 6799 6800 #undef GEN_LDX_E 6801 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6802 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6803 6804 #if defined(TARGET_PPC64) 6805 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6806 6807 /* HV/P7 and later only */ 6808 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6809 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6810 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6811 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6812 #endif 6813 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6814 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6815 6816 /* External PID based load */ 6817 #undef GEN_LDEPX 6818 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6819 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6820 0x00000001, PPC_NONE, PPC2_BOOKE206), 6821 6822 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6823 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6824 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6825 #if defined(TARGET_PPC64) 6826 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6827 #endif 6828 6829 #undef GEN_STX_E 6830 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6831 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6832 6833 #if defined(TARGET_PPC64) 6834 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6835 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6836 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6837 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6838 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6839 #endif 6840 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6841 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6842 6843 #undef GEN_STEPX 6844 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6845 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6846 0x00000001, PPC_NONE, PPC2_BOOKE206), 6847 6848 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6849 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6850 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6851 #if defined(TARGET_PPC64) 6852 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6853 #endif 6854 6855 #undef GEN_CRLOGIC 6856 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6857 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6858 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6859 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6860 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6861 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6862 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6863 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6864 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6865 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6866 6867 #undef GEN_MAC_HANDLER 6868 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6869 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6870 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6871 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6872 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6873 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6874 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6875 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6876 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6877 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6878 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6879 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6880 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6881 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6882 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6883 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6884 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6885 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6886 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6887 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6888 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6889 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6890 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6891 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6892 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6893 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6894 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6895 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6896 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6897 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6898 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6899 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6900 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6901 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6902 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6903 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6904 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6905 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6906 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6907 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6908 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6909 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6910 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6911 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6912 6913 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6914 PPC_NONE, PPC2_TM), 6915 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6916 PPC_NONE, PPC2_TM), 6917 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6918 PPC_NONE, PPC2_TM), 6919 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6920 PPC_NONE, PPC2_TM), 6921 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6922 PPC_NONE, PPC2_TM), 6923 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6924 PPC_NONE, PPC2_TM), 6925 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6926 PPC_NONE, PPC2_TM), 6927 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6928 PPC_NONE, PPC2_TM), 6929 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6930 PPC_NONE, PPC2_TM), 6931 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6932 PPC_NONE, PPC2_TM), 6933 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6934 PPC_NONE, PPC2_TM), 6935 6936 #include "translate/fp-ops.c.inc" 6937 6938 #include "translate/vmx-ops.c.inc" 6939 6940 #include "translate/vsx-ops.c.inc" 6941 6942 #include "translate/spe-ops.c.inc" 6943 }; 6944 6945 /*****************************************************************************/ 6946 /* Opcode types */ 6947 enum { 6948 PPC_DIRECT = 0, /* Opcode routine */ 6949 PPC_INDIRECT = 1, /* Indirect opcode table */ 6950 }; 6951 6952 #define PPC_OPCODE_MASK 0x3 6953 6954 static inline int is_indirect_opcode(void *handler) 6955 { 6956 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6957 } 6958 6959 static inline opc_handler_t **ind_table(void *handler) 6960 { 6961 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6962 } 6963 6964 /* Instruction table creation */ 6965 /* Opcodes tables creation */ 6966 static void fill_new_table(opc_handler_t **table, int len) 6967 { 6968 int i; 6969 6970 for (i = 0; i < len; i++) { 6971 table[i] = &invalid_handler; 6972 } 6973 } 6974 6975 static int create_new_table(opc_handler_t **table, unsigned char idx) 6976 { 6977 opc_handler_t **tmp; 6978 6979 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6980 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6981 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6982 6983 return 0; 6984 } 6985 6986 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6987 opc_handler_t *handler) 6988 { 6989 if (table[idx] != &invalid_handler) { 6990 return -1; 6991 } 6992 table[idx] = handler; 6993 6994 return 0; 6995 } 6996 6997 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6998 unsigned char idx, opc_handler_t *handler) 6999 { 7000 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 7001 printf("*** ERROR: opcode %02x already assigned in main " 7002 "opcode table\n", idx); 7003 return -1; 7004 } 7005 7006 return 0; 7007 } 7008 7009 static int register_ind_in_table(opc_handler_t **table, 7010 unsigned char idx1, unsigned char idx2, 7011 opc_handler_t *handler) 7012 { 7013 if (table[idx1] == &invalid_handler) { 7014 if (create_new_table(table, idx1) < 0) { 7015 printf("*** ERROR: unable to create indirect table " 7016 "idx=%02x\n", idx1); 7017 return -1; 7018 } 7019 } else { 7020 if (!is_indirect_opcode(table[idx1])) { 7021 printf("*** ERROR: idx %02x already assigned to a direct " 7022 "opcode\n", idx1); 7023 return -1; 7024 } 7025 } 7026 if (handler != NULL && 7027 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7028 printf("*** ERROR: opcode %02x already assigned in " 7029 "opcode table %02x\n", idx2, idx1); 7030 return -1; 7031 } 7032 7033 return 0; 7034 } 7035 7036 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7037 unsigned char idx1, unsigned char idx2, 7038 opc_handler_t *handler) 7039 { 7040 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7041 } 7042 7043 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7044 unsigned char idx1, unsigned char idx2, 7045 unsigned char idx3, opc_handler_t *handler) 7046 { 7047 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7048 printf("*** ERROR: unable to join indirect table idx " 7049 "[%02x-%02x]\n", idx1, idx2); 7050 return -1; 7051 } 7052 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7053 handler) < 0) { 7054 printf("*** ERROR: unable to insert opcode " 7055 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7056 return -1; 7057 } 7058 7059 return 0; 7060 } 7061 7062 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7063 unsigned char idx1, unsigned char idx2, 7064 unsigned char idx3, unsigned char idx4, 7065 opc_handler_t *handler) 7066 { 7067 opc_handler_t **table; 7068 7069 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7070 printf("*** ERROR: unable to join indirect table idx " 7071 "[%02x-%02x]\n", idx1, idx2); 7072 return -1; 7073 } 7074 table = ind_table(ppc_opcodes[idx1]); 7075 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7076 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7077 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7078 return -1; 7079 } 7080 table = ind_table(table[idx2]); 7081 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7082 printf("*** ERROR: unable to insert opcode " 7083 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7084 return -1; 7085 } 7086 return 0; 7087 } 7088 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7089 { 7090 if (insn->opc2 != 0xFF) { 7091 if (insn->opc3 != 0xFF) { 7092 if (insn->opc4 != 0xFF) { 7093 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7094 insn->opc3, insn->opc4, 7095 &insn->handler) < 0) { 7096 return -1; 7097 } 7098 } else { 7099 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7100 insn->opc3, &insn->handler) < 0) { 7101 return -1; 7102 } 7103 } 7104 } else { 7105 if (register_ind_insn(ppc_opcodes, insn->opc1, 7106 insn->opc2, &insn->handler) < 0) { 7107 return -1; 7108 } 7109 } 7110 } else { 7111 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7112 return -1; 7113 } 7114 } 7115 7116 return 0; 7117 } 7118 7119 static int test_opcode_table(opc_handler_t **table, int len) 7120 { 7121 int i, count, tmp; 7122 7123 for (i = 0, count = 0; i < len; i++) { 7124 /* Consistency fixup */ 7125 if (table[i] == NULL) { 7126 table[i] = &invalid_handler; 7127 } 7128 if (table[i] != &invalid_handler) { 7129 if (is_indirect_opcode(table[i])) { 7130 tmp = test_opcode_table(ind_table(table[i]), 7131 PPC_CPU_INDIRECT_OPCODES_LEN); 7132 if (tmp == 0) { 7133 free(table[i]); 7134 table[i] = &invalid_handler; 7135 } else { 7136 count++; 7137 } 7138 } else { 7139 count++; 7140 } 7141 } 7142 } 7143 7144 return count; 7145 } 7146 7147 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7148 { 7149 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7150 printf("*** WARNING: no opcode defined !\n"); 7151 } 7152 } 7153 7154 /*****************************************************************************/ 7155 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7156 { 7157 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7158 opcode_t *opc; 7159 7160 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7161 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7162 if (((opc->handler.type & pcc->insns_flags) != 0) || 7163 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7164 if (register_insn(cpu->opcodes, opc) < 0) { 7165 error_setg(errp, "ERROR initializing PowerPC instruction " 7166 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7167 opc->opc3); 7168 return; 7169 } 7170 } 7171 } 7172 fix_opcode_tables(cpu->opcodes); 7173 fflush(stdout); 7174 fflush(stderr); 7175 } 7176 7177 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7178 { 7179 opc_handler_t **table, **table_2; 7180 int i, j, k; 7181 7182 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7183 if (cpu->opcodes[i] == &invalid_handler) { 7184 continue; 7185 } 7186 if (is_indirect_opcode(cpu->opcodes[i])) { 7187 table = ind_table(cpu->opcodes[i]); 7188 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7189 if (table[j] == &invalid_handler) { 7190 continue; 7191 } 7192 if (is_indirect_opcode(table[j])) { 7193 table_2 = ind_table(table[j]); 7194 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7195 if (table_2[k] != &invalid_handler && 7196 is_indirect_opcode(table_2[k])) { 7197 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7198 ~PPC_INDIRECT)); 7199 } 7200 } 7201 g_free((opc_handler_t *)((uintptr_t)table[j] & 7202 ~PPC_INDIRECT)); 7203 } 7204 } 7205 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7206 ~PPC_INDIRECT)); 7207 } 7208 } 7209 } 7210 7211 int ppc_fixup_cpu(PowerPCCPU *cpu) 7212 { 7213 CPUPPCState *env = &cpu->env; 7214 7215 /* 7216 * TCG doesn't (yet) emulate some groups of instructions that are 7217 * implemented on some otherwise supported CPUs (e.g. VSX and 7218 * decimal floating point instructions on POWER7). We remove 7219 * unsupported instruction groups from the cpu state's instruction 7220 * masks and hope the guest can cope. For at least the pseries 7221 * machine, the unavailability of these instructions can be 7222 * advertised to the guest via the device tree. 7223 */ 7224 if ((env->insns_flags & ~PPC_TCG_INSNS) 7225 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7226 warn_report("Disabling some instructions which are not " 7227 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7228 env->insns_flags & ~PPC_TCG_INSNS, 7229 env->insns_flags2 & ~PPC_TCG_INSNS2); 7230 } 7231 env->insns_flags &= PPC_TCG_INSNS; 7232 env->insns_flags2 &= PPC_TCG_INSNS2; 7233 return 0; 7234 } 7235 7236 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7237 { 7238 opc_handler_t **table, *handler; 7239 uint32_t inval; 7240 7241 ctx->opcode = insn; 7242 7243 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7244 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7245 ctx->le_mode ? "little" : "big"); 7246 7247 table = cpu->opcodes; 7248 handler = table[opc1(insn)]; 7249 if (is_indirect_opcode(handler)) { 7250 table = ind_table(handler); 7251 handler = table[opc2(insn)]; 7252 if (is_indirect_opcode(handler)) { 7253 table = ind_table(handler); 7254 handler = table[opc3(insn)]; 7255 if (is_indirect_opcode(handler)) { 7256 table = ind_table(handler); 7257 handler = table[opc4(insn)]; 7258 } 7259 } 7260 } 7261 7262 /* Is opcode *REALLY* valid ? */ 7263 if (unlikely(handler->handler == &gen_invalid)) { 7264 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7265 "%02x - %02x - %02x - %02x (%08x) " 7266 TARGET_FMT_lx "\n", 7267 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7268 insn, ctx->cia); 7269 return false; 7270 } 7271 7272 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7273 && Rc(insn))) { 7274 inval = handler->inval2; 7275 } else { 7276 inval = handler->inval1; 7277 } 7278 7279 if (unlikely((insn & inval) != 0)) { 7280 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7281 "%02x - %02x - %02x - %02x (%08x) " 7282 TARGET_FMT_lx "\n", insn & inval, 7283 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7284 insn, ctx->cia); 7285 return false; 7286 } 7287 7288 handler->handler(ctx); 7289 return true; 7290 } 7291 7292 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7293 { 7294 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7295 CPUPPCState *env = cs->env_ptr; 7296 uint32_t hflags = ctx->base.tb->flags; 7297 7298 ctx->spr_cb = env->spr_cb; 7299 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7300 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7301 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7302 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7303 ctx->insns_flags = env->insns_flags; 7304 ctx->insns_flags2 = env->insns_flags2; 7305 ctx->access_type = -1; 7306 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7307 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7308 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7309 ctx->flags = env->flags; 7310 #if defined(TARGET_PPC64) 7311 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7312 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7313 #endif 7314 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7315 || env->mmu_model & POWERPC_MMU_64; 7316 7317 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7318 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7319 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7320 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7321 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7322 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7323 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7324 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7325 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7326 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7327 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7328 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7329 7330 ctx->singlestep_enabled = 0; 7331 if ((hflags >> HFLAGS_SE) & 1) { 7332 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7333 ctx->base.max_insns = 1; 7334 } 7335 if ((hflags >> HFLAGS_BE) & 1) { 7336 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7337 } 7338 } 7339 7340 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7341 { 7342 } 7343 7344 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7345 { 7346 tcg_gen_insn_start(dcbase->pc_next); 7347 } 7348 7349 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7350 { 7351 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7352 return opc1(insn) == 1; 7353 } 7354 7355 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7356 { 7357 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7358 PowerPCCPU *cpu = POWERPC_CPU(cs); 7359 CPUPPCState *env = cs->env_ptr; 7360 target_ulong pc; 7361 uint32_t insn; 7362 bool ok; 7363 7364 LOG_DISAS("----------------\n"); 7365 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7366 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7367 7368 ctx->cia = pc = ctx->base.pc_next; 7369 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7370 ctx->base.pc_next = pc += 4; 7371 7372 if (!is_prefix_insn(ctx, insn)) { 7373 ok = (decode_insn32(ctx, insn) || 7374 decode_legacy(cpu, ctx, insn)); 7375 } else if ((pc & 63) == 0) { 7376 /* 7377 * Power v3.1, section 1.9 Exceptions: 7378 * attempt to execute a prefixed instruction that crosses a 7379 * 64-byte address boundary (system alignment error). 7380 */ 7381 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7382 ok = true; 7383 } else { 7384 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7385 need_byteswap(ctx)); 7386 ctx->base.pc_next = pc += 4; 7387 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7388 } 7389 if (!ok) { 7390 gen_invalid(ctx); 7391 } 7392 7393 /* End the TB when crossing a page boundary. */ 7394 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7395 ctx->base.is_jmp = DISAS_TOO_MANY; 7396 } 7397 } 7398 7399 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7400 { 7401 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7402 DisasJumpType is_jmp = ctx->base.is_jmp; 7403 target_ulong nip = ctx->base.pc_next; 7404 7405 if (is_jmp == DISAS_NORETURN) { 7406 /* We have already exited the TB. */ 7407 return; 7408 } 7409 7410 /* Honor single stepping. */ 7411 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7412 switch (is_jmp) { 7413 case DISAS_TOO_MANY: 7414 case DISAS_EXIT_UPDATE: 7415 case DISAS_CHAIN_UPDATE: 7416 gen_update_nip(ctx, nip); 7417 break; 7418 case DISAS_EXIT: 7419 case DISAS_CHAIN: 7420 break; 7421 default: 7422 g_assert_not_reached(); 7423 } 7424 7425 gen_debug_exception(ctx); 7426 return; 7427 } 7428 7429 switch (is_jmp) { 7430 case DISAS_TOO_MANY: 7431 if (use_goto_tb(ctx, nip)) { 7432 pmu_count_insns(ctx); 7433 tcg_gen_goto_tb(0); 7434 gen_update_nip(ctx, nip); 7435 tcg_gen_exit_tb(ctx->base.tb, 0); 7436 break; 7437 } 7438 /* fall through */ 7439 case DISAS_CHAIN_UPDATE: 7440 gen_update_nip(ctx, nip); 7441 /* fall through */ 7442 case DISAS_CHAIN: 7443 /* 7444 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7445 * CF_NO_GOTO_PTR is set. Count insns now. 7446 */ 7447 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7448 pmu_count_insns(ctx); 7449 } 7450 7451 tcg_gen_lookup_and_goto_ptr(); 7452 break; 7453 7454 case DISAS_EXIT_UPDATE: 7455 gen_update_nip(ctx, nip); 7456 /* fall through */ 7457 case DISAS_EXIT: 7458 pmu_count_insns(ctx); 7459 tcg_gen_exit_tb(NULL, 0); 7460 break; 7461 7462 default: 7463 g_assert_not_reached(); 7464 } 7465 } 7466 7467 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7468 CPUState *cs, FILE *logfile) 7469 { 7470 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7471 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7472 } 7473 7474 static const TranslatorOps ppc_tr_ops = { 7475 .init_disas_context = ppc_tr_init_disas_context, 7476 .tb_start = ppc_tr_tb_start, 7477 .insn_start = ppc_tr_insn_start, 7478 .translate_insn = ppc_tr_translate_insn, 7479 .tb_stop = ppc_tr_tb_stop, 7480 .disas_log = ppc_tr_disas_log, 7481 }; 7482 7483 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7484 target_ulong pc, void *host_pc) 7485 { 7486 DisasContext ctx; 7487 7488 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7489 } 7490