1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 static inline bool gen_serialize(DisasContext *ctx) 238 { 239 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240 /* Restart with exclusive lock. */ 241 gen_helper_exit_atomic(cpu_env); 242 ctx->base.is_jmp = DISAS_NORETURN; 243 return false; 244 } 245 return true; 246 } 247 248 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 250 { 251 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 252 return gen_serialize(ctx); 253 } 254 255 return true; 256 } 257 #endif 258 259 /* SPR load/store helpers */ 260 static inline void gen_load_spr(TCGv t, int reg) 261 { 262 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 263 } 264 265 static inline void gen_store_spr(int reg, TCGv t) 266 { 267 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 268 } 269 270 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271 { 272 if (ctx->need_access_type && ctx->access_type != access_type) { 273 tcg_gen_movi_i32(cpu_access_type, access_type); 274 ctx->access_type = access_type; 275 } 276 } 277 278 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279 { 280 if (NARROW_MODE(ctx)) { 281 nip = (uint32_t)nip; 282 } 283 tcg_gen_movi_tl(cpu_nip, nip); 284 } 285 286 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287 { 288 TCGv_i32 t0, t1; 289 290 /* 291 * These are all synchronous exceptions, we set the PC back to the 292 * faulting instruction 293 */ 294 gen_update_nip(ctx, ctx->cia); 295 t0 = tcg_constant_i32(excp); 296 t1 = tcg_constant_i32(error); 297 gen_helper_raise_exception_err(cpu_env, t0, t1); 298 ctx->base.is_jmp = DISAS_NORETURN; 299 } 300 301 static void gen_exception(DisasContext *ctx, uint32_t excp) 302 { 303 TCGv_i32 t0; 304 305 /* 306 * These are all synchronous exceptions, we set the PC back to the 307 * faulting instruction 308 */ 309 gen_update_nip(ctx, ctx->cia); 310 t0 = tcg_constant_i32(excp); 311 gen_helper_raise_exception(cpu_env, t0); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316 target_ulong nip) 317 { 318 TCGv_i32 t0; 319 320 gen_update_nip(ctx, nip); 321 t0 = tcg_constant_i32(excp); 322 gen_helper_raise_exception(cpu_env, t0); 323 ctx->base.is_jmp = DISAS_NORETURN; 324 } 325 326 #if !defined(CONFIG_USER_ONLY) 327 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 328 { 329 translator_io_start(&ctx->base); 330 gen_helper_ppc_maybe_interrupt(cpu_env); 331 } 332 #endif 333 334 /* 335 * Tells the caller what is the appropriate exception to generate and prepares 336 * SPR registers for this exception. 337 * 338 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339 * POWERPC_EXCP_DEBUG (on BookE). 340 */ 341 static uint32_t gen_prep_dbgex(DisasContext *ctx) 342 { 343 if (ctx->flags & POWERPC_FLAG_DE) { 344 target_ulong dbsr = 0; 345 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 346 dbsr = DBCR0_ICMP; 347 } else { 348 /* Must have been branch */ 349 dbsr = DBCR0_BRT; 350 } 351 TCGv t0 = tcg_temp_new(); 352 gen_load_spr(t0, SPR_BOOKE_DBSR); 353 tcg_gen_ori_tl(t0, t0, dbsr); 354 gen_store_spr(SPR_BOOKE_DBSR, t0); 355 return POWERPC_EXCP_DEBUG; 356 } else { 357 return POWERPC_EXCP_TRACE; 358 } 359 } 360 361 static void gen_debug_exception(DisasContext *ctx) 362 { 363 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 364 ctx->base.is_jmp = DISAS_NORETURN; 365 } 366 367 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368 { 369 /* Will be converted to program check if needed */ 370 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371 } 372 373 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374 { 375 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376 } 377 378 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379 { 380 /* Will be converted to program check if needed */ 381 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382 } 383 384 /*****************************************************************************/ 385 /* SPR READ/WRITE CALLBACKS */ 386 387 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 388 { 389 #if 0 390 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 391 printf("ERROR: try to access SPR %d !\n", sprn); 392 #endif 393 } 394 395 /* #define PPC_DUMP_SPR_ACCESSES */ 396 397 /* 398 * Generic callbacks: 399 * do nothing but store/retrieve spr value 400 */ 401 static void spr_load_dump_spr(int sprn) 402 { 403 #ifdef PPC_DUMP_SPR_ACCESSES 404 TCGv_i32 t0 = tcg_constant_i32(sprn); 405 gen_helper_load_dump_spr(cpu_env, t0); 406 #endif 407 } 408 409 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 410 { 411 gen_load_spr(cpu_gpr[gprn], sprn); 412 spr_load_dump_spr(sprn); 413 } 414 415 static void spr_store_dump_spr(int sprn) 416 { 417 #ifdef PPC_DUMP_SPR_ACCESSES 418 TCGv_i32 t0 = tcg_constant_i32(sprn); 419 gen_helper_store_dump_spr(cpu_env, t0); 420 #endif 421 } 422 423 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 424 { 425 gen_store_spr(sprn, cpu_gpr[gprn]); 426 spr_store_dump_spr(sprn); 427 } 428 429 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 430 { 431 #ifdef TARGET_PPC64 432 TCGv t0 = tcg_temp_new(); 433 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 434 gen_store_spr(sprn, t0); 435 spr_store_dump_spr(sprn); 436 #else 437 spr_write_generic(ctx, sprn, gprn); 438 #endif 439 } 440 441 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442 { 443 /* This does not implement >1 thread */ 444 TCGv t0 = tcg_temp_new(); 445 TCGv t1 = tcg_temp_new(); 446 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448 tcg_gen_or_tl(t1, t1, t0); 449 gen_store_spr(sprn, t1); 450 } 451 452 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453 { 454 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 455 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 456 spr_write_CTRL_ST(ctx, sprn, gprn); 457 goto out; 458 } 459 460 if (!gen_serialize(ctx)) { 461 return; 462 } 463 464 gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 465 cpu_gpr[gprn]); 466 out: 467 spr_store_dump_spr(sprn); 468 469 /* 470 * SPR_CTRL writes must force a new translation block, 471 * allowing the PMU to calculate the run latch events with 472 * more accuracy. 473 */ 474 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 475 } 476 477 #if !defined(CONFIG_USER_ONLY) 478 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 479 { 480 TCGv t0 = tcg_temp_new(); 481 TCGv t1 = tcg_temp_new(); 482 gen_load_spr(t0, sprn); 483 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 484 tcg_gen_and_tl(t0, t0, t1); 485 gen_store_spr(sprn, t0); 486 } 487 488 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 489 { 490 } 491 492 #endif 493 494 /* SPR common to all PowerPC */ 495 /* XER */ 496 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 497 { 498 TCGv dst = cpu_gpr[gprn]; 499 TCGv t0 = tcg_temp_new(); 500 TCGv t1 = tcg_temp_new(); 501 TCGv t2 = tcg_temp_new(); 502 tcg_gen_mov_tl(dst, cpu_xer); 503 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 504 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 505 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 506 tcg_gen_or_tl(t0, t0, t1); 507 tcg_gen_or_tl(dst, dst, t2); 508 tcg_gen_or_tl(dst, dst, t0); 509 if (is_isa300(ctx)) { 510 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 511 tcg_gen_or_tl(dst, dst, t0); 512 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 513 tcg_gen_or_tl(dst, dst, t0); 514 } 515 } 516 517 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 518 { 519 TCGv src = cpu_gpr[gprn]; 520 /* Write all flags, while reading back check for isa300 */ 521 tcg_gen_andi_tl(cpu_xer, src, 522 ~((1u << XER_SO) | 523 (1u << XER_OV) | (1u << XER_OV32) | 524 (1u << XER_CA) | (1u << XER_CA32))); 525 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 526 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 527 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 528 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 529 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 530 } 531 532 /* LR */ 533 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 534 { 535 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 536 } 537 538 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 539 { 540 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 541 } 542 543 /* CFAR */ 544 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 545 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 546 { 547 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 548 } 549 550 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 551 { 552 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 553 } 554 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 555 556 /* CTR */ 557 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 558 { 559 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 560 } 561 562 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 563 { 564 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 565 } 566 567 /* User read access to SPR */ 568 /* USPRx */ 569 /* UMMCRx */ 570 /* UPMCx */ 571 /* USIA */ 572 /* UDECR */ 573 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 574 { 575 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 576 } 577 578 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 579 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 580 { 581 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 582 } 583 #endif 584 585 /* SPR common to all non-embedded PowerPC */ 586 /* DECR */ 587 #if !defined(CONFIG_USER_ONLY) 588 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 589 { 590 translator_io_start(&ctx->base); 591 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 592 } 593 594 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 595 { 596 translator_io_start(&ctx->base); 597 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 598 } 599 #endif 600 601 /* SPR common to all non-embedded PowerPC, except 601 */ 602 /* Time base */ 603 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 604 { 605 translator_io_start(&ctx->base); 606 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 607 } 608 609 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 610 { 611 translator_io_start(&ctx->base); 612 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 613 } 614 615 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 616 { 617 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 618 } 619 620 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 621 { 622 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 623 } 624 625 #if !defined(CONFIG_USER_ONLY) 626 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 627 { 628 translator_io_start(&ctx->base); 629 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 630 } 631 632 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 633 { 634 translator_io_start(&ctx->base); 635 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 636 } 637 638 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 639 { 640 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 641 } 642 643 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 644 { 645 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 646 } 647 648 #if defined(TARGET_PPC64) 649 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 650 { 651 translator_io_start(&ctx->base); 652 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 653 } 654 655 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 656 { 657 translator_io_start(&ctx->base); 658 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 659 } 660 661 /* HDECR */ 662 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 663 { 664 translator_io_start(&ctx->base); 665 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 666 } 667 668 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 669 { 670 translator_io_start(&ctx->base); 671 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 672 } 673 674 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 675 { 676 translator_io_start(&ctx->base); 677 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 678 } 679 680 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 681 { 682 translator_io_start(&ctx->base); 683 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 684 } 685 686 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 687 { 688 translator_io_start(&ctx->base); 689 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 690 } 691 692 #endif 693 #endif 694 695 #if !defined(CONFIG_USER_ONLY) 696 /* IBAT0U...IBAT0U */ 697 /* IBAT0L...IBAT7L */ 698 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 699 { 700 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 701 offsetof(CPUPPCState, 702 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 703 } 704 705 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 706 { 707 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 708 offsetof(CPUPPCState, 709 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 710 } 711 712 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 713 { 714 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 715 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 716 } 717 718 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 719 { 720 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 721 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 722 } 723 724 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 725 { 726 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 727 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 728 } 729 730 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 731 { 732 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 733 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 734 } 735 736 /* DBAT0U...DBAT7U */ 737 /* DBAT0L...DBAT7L */ 738 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 739 { 740 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 741 offsetof(CPUPPCState, 742 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 743 } 744 745 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 746 { 747 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 748 offsetof(CPUPPCState, 749 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 750 } 751 752 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 753 { 754 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 755 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 756 } 757 758 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 759 { 760 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 761 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 762 } 763 764 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 765 { 766 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 767 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 768 } 769 770 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 771 { 772 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 773 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 774 } 775 776 /* SDR1 */ 777 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 778 { 779 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 780 } 781 782 #if defined(TARGET_PPC64) 783 /* 64 bits PowerPC specific SPRs */ 784 /* PIDR */ 785 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 786 { 787 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 788 } 789 790 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 791 { 792 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 793 } 794 795 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 796 { 797 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 798 } 799 800 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 801 { 802 TCGv t0 = tcg_temp_new(); 803 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 804 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 805 } 806 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 807 { 808 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 809 } 810 811 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 812 { 813 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 814 } 815 816 /* DPDES */ 817 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 818 { 819 if (!gen_serialize_core_lpar(ctx)) { 820 return; 821 } 822 823 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 824 } 825 826 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 827 { 828 if (!gen_serialize_core_lpar(ctx)) { 829 return; 830 } 831 832 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 833 } 834 #endif 835 #endif 836 837 /* PowerPC 40x specific registers */ 838 #if !defined(CONFIG_USER_ONLY) 839 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 840 { 841 translator_io_start(&ctx->base); 842 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 843 } 844 845 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 846 { 847 translator_io_start(&ctx->base); 848 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 849 } 850 851 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 852 { 853 translator_io_start(&ctx->base); 854 gen_store_spr(sprn, cpu_gpr[gprn]); 855 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 856 /* We must stop translation as we may have rebooted */ 857 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 858 } 859 860 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 861 { 862 translator_io_start(&ctx->base); 863 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 864 } 865 866 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 867 { 868 translator_io_start(&ctx->base); 869 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 870 } 871 872 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 873 { 874 translator_io_start(&ctx->base); 875 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 876 } 877 878 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 879 { 880 TCGv t0 = tcg_temp_new(); 881 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 882 gen_helper_store_40x_pid(cpu_env, t0); 883 } 884 885 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 886 { 887 translator_io_start(&ctx->base); 888 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 889 } 890 891 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 892 { 893 translator_io_start(&ctx->base); 894 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 895 } 896 #endif 897 898 /* PIR */ 899 #if !defined(CONFIG_USER_ONLY) 900 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 901 { 902 TCGv t0 = tcg_temp_new(); 903 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 904 gen_store_spr(SPR_PIR, t0); 905 } 906 #endif 907 908 /* SPE specific registers */ 909 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 910 { 911 TCGv_i32 t0 = tcg_temp_new_i32(); 912 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 913 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 914 } 915 916 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 917 { 918 TCGv_i32 t0 = tcg_temp_new_i32(); 919 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 920 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 921 } 922 923 #if !defined(CONFIG_USER_ONLY) 924 /* Callback used to write the exception vector base */ 925 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 926 { 927 TCGv t0 = tcg_temp_new(); 928 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 929 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 930 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 931 gen_store_spr(sprn, t0); 932 } 933 934 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 935 { 936 int sprn_offs; 937 938 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 939 sprn_offs = sprn - SPR_BOOKE_IVOR0; 940 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 941 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 942 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 943 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 944 } else { 945 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 946 " vector 0x%03x\n", sprn); 947 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 948 return; 949 } 950 951 TCGv t0 = tcg_temp_new(); 952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 953 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 954 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 955 gen_store_spr(sprn, t0); 956 } 957 #endif 958 959 #ifdef TARGET_PPC64 960 #ifndef CONFIG_USER_ONLY 961 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 962 { 963 TCGv t0 = tcg_temp_new(); 964 TCGv t1 = tcg_temp_new(); 965 TCGv t2 = tcg_temp_new(); 966 967 /* 968 * Note, the HV=1 PR=0 case is handled earlier by simply using 969 * spr_write_generic for HV mode in the SPR table 970 */ 971 972 /* Build insertion mask into t1 based on context */ 973 if (ctx->pr) { 974 gen_load_spr(t1, SPR_UAMOR); 975 } else { 976 gen_load_spr(t1, SPR_AMOR); 977 } 978 979 /* Mask new bits into t2 */ 980 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 981 982 /* Load AMR and clear new bits in t0 */ 983 gen_load_spr(t0, SPR_AMR); 984 tcg_gen_andc_tl(t0, t0, t1); 985 986 /* Or'in new bits and write it out */ 987 tcg_gen_or_tl(t0, t0, t2); 988 gen_store_spr(SPR_AMR, t0); 989 spr_store_dump_spr(SPR_AMR); 990 } 991 992 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 993 { 994 TCGv t0 = tcg_temp_new(); 995 TCGv t1 = tcg_temp_new(); 996 TCGv t2 = tcg_temp_new(); 997 998 /* 999 * Note, the HV=1 case is handled earlier by simply using 1000 * spr_write_generic for HV mode in the SPR table 1001 */ 1002 1003 /* Build insertion mask into t1 based on context */ 1004 gen_load_spr(t1, SPR_AMOR); 1005 1006 /* Mask new bits into t2 */ 1007 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1008 1009 /* Load AMR and clear new bits in t0 */ 1010 gen_load_spr(t0, SPR_UAMOR); 1011 tcg_gen_andc_tl(t0, t0, t1); 1012 1013 /* Or'in new bits and write it out */ 1014 tcg_gen_or_tl(t0, t0, t2); 1015 gen_store_spr(SPR_UAMOR, t0); 1016 spr_store_dump_spr(SPR_UAMOR); 1017 } 1018 1019 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1020 { 1021 TCGv t0 = tcg_temp_new(); 1022 TCGv t1 = tcg_temp_new(); 1023 TCGv t2 = tcg_temp_new(); 1024 1025 /* 1026 * Note, the HV=1 case is handled earlier by simply using 1027 * spr_write_generic for HV mode in the SPR table 1028 */ 1029 1030 /* Build insertion mask into t1 based on context */ 1031 gen_load_spr(t1, SPR_AMOR); 1032 1033 /* Mask new bits into t2 */ 1034 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1035 1036 /* Load AMR and clear new bits in t0 */ 1037 gen_load_spr(t0, SPR_IAMR); 1038 tcg_gen_andc_tl(t0, t0, t1); 1039 1040 /* Or'in new bits and write it out */ 1041 tcg_gen_or_tl(t0, t0, t2); 1042 gen_store_spr(SPR_IAMR, t0); 1043 spr_store_dump_spr(SPR_IAMR); 1044 } 1045 #endif 1046 #endif 1047 1048 #ifndef CONFIG_USER_ONLY 1049 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1050 { 1051 gen_helper_fixup_thrm(cpu_env); 1052 gen_load_spr(cpu_gpr[gprn], sprn); 1053 spr_load_dump_spr(sprn); 1054 } 1055 #endif /* !CONFIG_USER_ONLY */ 1056 1057 #if !defined(CONFIG_USER_ONLY) 1058 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1059 { 1060 TCGv t0 = tcg_temp_new(); 1061 1062 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1063 gen_store_spr(sprn, t0); 1064 } 1065 1066 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1067 { 1068 TCGv t0 = tcg_temp_new(); 1069 1070 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1071 gen_store_spr(sprn, t0); 1072 } 1073 1074 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1075 { 1076 TCGv t0 = tcg_temp_new(); 1077 1078 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1079 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1080 gen_store_spr(sprn, t0); 1081 } 1082 1083 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1084 { 1085 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1086 } 1087 1088 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1089 { 1090 TCGv_i32 t0 = tcg_constant_i32(sprn); 1091 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1092 } 1093 1094 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1095 { 1096 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1097 } 1098 1099 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1100 { 1101 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1102 } 1103 1104 #endif 1105 1106 #if !defined(CONFIG_USER_ONLY) 1107 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1108 { 1109 TCGv val = tcg_temp_new(); 1110 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1111 gen_store_spr(SPR_BOOKE_MAS3, val); 1112 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1113 gen_store_spr(SPR_BOOKE_MAS7, val); 1114 } 1115 1116 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1117 { 1118 TCGv mas7 = tcg_temp_new(); 1119 TCGv mas3 = tcg_temp_new(); 1120 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1121 tcg_gen_shli_tl(mas7, mas7, 32); 1122 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1123 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1124 } 1125 1126 #endif 1127 1128 #ifdef TARGET_PPC64 1129 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1130 int bit, int sprn, int cause) 1131 { 1132 TCGv_i32 t1 = tcg_constant_i32(bit); 1133 TCGv_i32 t2 = tcg_constant_i32(sprn); 1134 TCGv_i32 t3 = tcg_constant_i32(cause); 1135 1136 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1137 } 1138 1139 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1140 int bit, int sprn, int cause) 1141 { 1142 TCGv_i32 t1 = tcg_constant_i32(bit); 1143 TCGv_i32 t2 = tcg_constant_i32(sprn); 1144 TCGv_i32 t3 = tcg_constant_i32(cause); 1145 1146 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1147 } 1148 1149 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1150 { 1151 TCGv spr_up = tcg_temp_new(); 1152 TCGv spr = tcg_temp_new(); 1153 1154 gen_load_spr(spr, sprn - 1); 1155 tcg_gen_shri_tl(spr_up, spr, 32); 1156 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1157 } 1158 1159 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1160 { 1161 TCGv spr = tcg_temp_new(); 1162 1163 gen_load_spr(spr, sprn - 1); 1164 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1165 gen_store_spr(sprn - 1, spr); 1166 } 1167 1168 #if !defined(CONFIG_USER_ONLY) 1169 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1170 { 1171 TCGv hmer = tcg_temp_new(); 1172 1173 gen_load_spr(hmer, sprn); 1174 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1175 gen_store_spr(sprn, hmer); 1176 spr_store_dump_spr(sprn); 1177 } 1178 1179 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1180 { 1181 gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1182 } 1183 1184 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1185 { 1186 gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1187 } 1188 1189 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1190 { 1191 translator_io_start(&ctx->base); 1192 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1193 } 1194 #endif /* !defined(CONFIG_USER_ONLY) */ 1195 1196 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1197 { 1198 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1199 spr_read_generic(ctx, gprn, sprn); 1200 } 1201 1202 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1203 { 1204 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1205 spr_write_generic(ctx, sprn, gprn); 1206 } 1207 1208 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1209 { 1210 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1211 spr_read_generic(ctx, gprn, sprn); 1212 } 1213 1214 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1215 { 1216 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1217 spr_write_generic(ctx, sprn, gprn); 1218 } 1219 1220 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1221 { 1222 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1223 spr_read_prev_upper32(ctx, gprn, sprn); 1224 } 1225 1226 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1227 { 1228 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1229 spr_write_prev_upper32(ctx, sprn, gprn); 1230 } 1231 1232 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1233 { 1234 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1235 spr_read_generic(ctx, gprn, sprn); 1236 } 1237 1238 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1239 { 1240 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1241 spr_write_generic(ctx, sprn, gprn); 1242 } 1243 1244 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1245 { 1246 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1247 spr_read_prev_upper32(ctx, gprn, sprn); 1248 } 1249 1250 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1251 { 1252 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1253 spr_write_prev_upper32(ctx, sprn, gprn); 1254 } 1255 1256 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1257 { 1258 TCGv t0 = tcg_temp_new(); 1259 1260 /* 1261 * Access to the (H)DEXCR in problem state is done using separated 1262 * SPR indexes which are 16 below the SPR indexes which have full 1263 * access to the (H)DEXCR in privileged state. Problem state can 1264 * only read bits 32:63, bits 0:31 return 0. 1265 * 1266 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1267 */ 1268 1269 gen_load_spr(t0, sprn + 16); 1270 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1271 } 1272 #endif 1273 1274 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1275 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1276 1277 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1278 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1279 1280 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1281 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1282 1283 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1284 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1285 1286 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1287 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1288 1289 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1290 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1291 1292 typedef struct opcode_t { 1293 unsigned char opc1, opc2, opc3, opc4; 1294 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1295 unsigned char pad[4]; 1296 #endif 1297 opc_handler_t handler; 1298 const char *oname; 1299 } opcode_t; 1300 1301 static void gen_priv_opc(DisasContext *ctx) 1302 { 1303 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1304 } 1305 1306 /* Helpers for priv. check */ 1307 #define GEN_PRIV(CTX) \ 1308 do { \ 1309 gen_priv_opc(CTX); return; \ 1310 } while (0) 1311 1312 #if defined(CONFIG_USER_ONLY) 1313 #define CHK_HV(CTX) GEN_PRIV(CTX) 1314 #define CHK_SV(CTX) GEN_PRIV(CTX) 1315 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1316 #else 1317 #define CHK_HV(CTX) \ 1318 do { \ 1319 if (unlikely(ctx->pr || !ctx->hv)) {\ 1320 GEN_PRIV(CTX); \ 1321 } \ 1322 } while (0) 1323 #define CHK_SV(CTX) \ 1324 do { \ 1325 if (unlikely(ctx->pr)) { \ 1326 GEN_PRIV(CTX); \ 1327 } \ 1328 } while (0) 1329 #define CHK_HVRM(CTX) \ 1330 do { \ 1331 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1332 GEN_PRIV(CTX); \ 1333 } \ 1334 } while (0) 1335 #endif 1336 1337 #define CHK_NONE(CTX) 1338 1339 /*****************************************************************************/ 1340 /* PowerPC instructions table */ 1341 1342 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1343 { \ 1344 .opc1 = op1, \ 1345 .opc2 = op2, \ 1346 .opc3 = op3, \ 1347 .opc4 = 0xff, \ 1348 .handler = { \ 1349 .inval1 = invl, \ 1350 .type = _typ, \ 1351 .type2 = _typ2, \ 1352 .handler = &gen_##name, \ 1353 }, \ 1354 .oname = stringify(name), \ 1355 } 1356 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1357 { \ 1358 .opc1 = op1, \ 1359 .opc2 = op2, \ 1360 .opc3 = op3, \ 1361 .opc4 = 0xff, \ 1362 .handler = { \ 1363 .inval1 = invl1, \ 1364 .inval2 = invl2, \ 1365 .type = _typ, \ 1366 .type2 = _typ2, \ 1367 .handler = &gen_##name, \ 1368 }, \ 1369 .oname = stringify(name), \ 1370 } 1371 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1372 { \ 1373 .opc1 = op1, \ 1374 .opc2 = op2, \ 1375 .opc3 = op3, \ 1376 .opc4 = 0xff, \ 1377 .handler = { \ 1378 .inval1 = invl, \ 1379 .type = _typ, \ 1380 .type2 = _typ2, \ 1381 .handler = &gen_##name, \ 1382 }, \ 1383 .oname = onam, \ 1384 } 1385 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1386 { \ 1387 .opc1 = op1, \ 1388 .opc2 = op2, \ 1389 .opc3 = op3, \ 1390 .opc4 = op4, \ 1391 .handler = { \ 1392 .inval1 = invl, \ 1393 .type = _typ, \ 1394 .type2 = _typ2, \ 1395 .handler = &gen_##name, \ 1396 }, \ 1397 .oname = stringify(name), \ 1398 } 1399 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1400 { \ 1401 .opc1 = op1, \ 1402 .opc2 = op2, \ 1403 .opc3 = op3, \ 1404 .opc4 = op4, \ 1405 .handler = { \ 1406 .inval1 = invl, \ 1407 .type = _typ, \ 1408 .type2 = _typ2, \ 1409 .handler = &gen_##name, \ 1410 }, \ 1411 .oname = onam, \ 1412 } 1413 1414 /* Invalid instruction */ 1415 static void gen_invalid(DisasContext *ctx) 1416 { 1417 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1418 } 1419 1420 static opc_handler_t invalid_handler = { 1421 .inval1 = 0xFFFFFFFF, 1422 .inval2 = 0xFFFFFFFF, 1423 .type = PPC_NONE, 1424 .type2 = PPC_NONE, 1425 .handler = gen_invalid, 1426 }; 1427 1428 /*** Integer comparison ***/ 1429 1430 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1431 { 1432 TCGv t0 = tcg_temp_new(); 1433 TCGv t1 = tcg_temp_new(); 1434 TCGv_i32 t = tcg_temp_new_i32(); 1435 1436 tcg_gen_movi_tl(t0, CRF_EQ); 1437 tcg_gen_movi_tl(t1, CRF_LT); 1438 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1439 t0, arg0, arg1, t1, t0); 1440 tcg_gen_movi_tl(t1, CRF_GT); 1441 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1442 t0, arg0, arg1, t1, t0); 1443 1444 tcg_gen_trunc_tl_i32(t, t0); 1445 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1446 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1447 } 1448 1449 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1450 { 1451 TCGv t0 = tcg_constant_tl(arg1); 1452 gen_op_cmp(arg0, t0, s, crf); 1453 } 1454 1455 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1456 { 1457 TCGv t0, t1; 1458 t0 = tcg_temp_new(); 1459 t1 = tcg_temp_new(); 1460 if (s) { 1461 tcg_gen_ext32s_tl(t0, arg0); 1462 tcg_gen_ext32s_tl(t1, arg1); 1463 } else { 1464 tcg_gen_ext32u_tl(t0, arg0); 1465 tcg_gen_ext32u_tl(t1, arg1); 1466 } 1467 gen_op_cmp(t0, t1, s, crf); 1468 } 1469 1470 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1471 { 1472 TCGv t0 = tcg_constant_tl(arg1); 1473 gen_op_cmp32(arg0, t0, s, crf); 1474 } 1475 1476 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1477 { 1478 if (NARROW_MODE(ctx)) { 1479 gen_op_cmpi32(reg, 0, 1, 0); 1480 } else { 1481 gen_op_cmpi(reg, 0, 1, 0); 1482 } 1483 } 1484 1485 /* cmprb - range comparison: isupper, isaplha, islower*/ 1486 static void gen_cmprb(DisasContext *ctx) 1487 { 1488 TCGv_i32 src1 = tcg_temp_new_i32(); 1489 TCGv_i32 src2 = tcg_temp_new_i32(); 1490 TCGv_i32 src2lo = tcg_temp_new_i32(); 1491 TCGv_i32 src2hi = tcg_temp_new_i32(); 1492 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1493 1494 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1495 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1496 1497 tcg_gen_andi_i32(src1, src1, 0xFF); 1498 tcg_gen_ext8u_i32(src2lo, src2); 1499 tcg_gen_shri_i32(src2, src2, 8); 1500 tcg_gen_ext8u_i32(src2hi, src2); 1501 1502 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1503 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1504 tcg_gen_and_i32(crf, src2lo, src2hi); 1505 1506 if (ctx->opcode & 0x00200000) { 1507 tcg_gen_shri_i32(src2, src2, 8); 1508 tcg_gen_ext8u_i32(src2lo, src2); 1509 tcg_gen_shri_i32(src2, src2, 8); 1510 tcg_gen_ext8u_i32(src2hi, src2); 1511 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1512 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1513 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1514 tcg_gen_or_i32(crf, crf, src2lo); 1515 } 1516 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1517 } 1518 1519 #if defined(TARGET_PPC64) 1520 /* cmpeqb */ 1521 static void gen_cmpeqb(DisasContext *ctx) 1522 { 1523 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1524 cpu_gpr[rB(ctx->opcode)]); 1525 } 1526 #endif 1527 1528 /* isel (PowerPC 2.03 specification) */ 1529 static void gen_isel(DisasContext *ctx) 1530 { 1531 uint32_t bi = rC(ctx->opcode); 1532 uint32_t mask = 0x08 >> (bi & 0x03); 1533 TCGv t0 = tcg_temp_new(); 1534 TCGv zr; 1535 1536 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1537 tcg_gen_andi_tl(t0, t0, mask); 1538 1539 zr = tcg_constant_tl(0); 1540 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1541 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1542 cpu_gpr[rB(ctx->opcode)]); 1543 } 1544 1545 /* cmpb: PowerPC 2.05 specification */ 1546 static void gen_cmpb(DisasContext *ctx) 1547 { 1548 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549 cpu_gpr[rB(ctx->opcode)]); 1550 } 1551 1552 /*** Integer arithmetic ***/ 1553 1554 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1555 TCGv arg1, TCGv arg2, int sub) 1556 { 1557 TCGv t0 = tcg_temp_new(); 1558 1559 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1560 tcg_gen_xor_tl(t0, arg1, arg2); 1561 if (sub) { 1562 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1563 } else { 1564 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1565 } 1566 if (NARROW_MODE(ctx)) { 1567 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1568 if (is_isa300(ctx)) { 1569 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1570 } 1571 } else { 1572 if (is_isa300(ctx)) { 1573 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1574 } 1575 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1576 } 1577 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1578 } 1579 1580 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1581 TCGv res, TCGv arg0, TCGv arg1, 1582 TCGv ca32, int sub) 1583 { 1584 TCGv t0; 1585 1586 if (!is_isa300(ctx)) { 1587 return; 1588 } 1589 1590 t0 = tcg_temp_new(); 1591 if (sub) { 1592 tcg_gen_eqv_tl(t0, arg0, arg1); 1593 } else { 1594 tcg_gen_xor_tl(t0, arg0, arg1); 1595 } 1596 tcg_gen_xor_tl(t0, t0, res); 1597 tcg_gen_extract_tl(ca32, t0, 32, 1); 1598 } 1599 1600 /* Common add function */ 1601 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1602 TCGv arg2, TCGv ca, TCGv ca32, 1603 bool add_ca, bool compute_ca, 1604 bool compute_ov, bool compute_rc0) 1605 { 1606 TCGv t0 = ret; 1607 1608 if (compute_ca || compute_ov) { 1609 t0 = tcg_temp_new(); 1610 } 1611 1612 if (compute_ca) { 1613 if (NARROW_MODE(ctx)) { 1614 /* 1615 * Caution: a non-obvious corner case of the spec is that 1616 * we must produce the *entire* 64-bit addition, but 1617 * produce the carry into bit 32. 1618 */ 1619 TCGv t1 = tcg_temp_new(); 1620 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1621 tcg_gen_add_tl(t0, arg1, arg2); 1622 if (add_ca) { 1623 tcg_gen_add_tl(t0, t0, ca); 1624 } 1625 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1626 tcg_gen_extract_tl(ca, ca, 32, 1); 1627 if (is_isa300(ctx)) { 1628 tcg_gen_mov_tl(ca32, ca); 1629 } 1630 } else { 1631 TCGv zero = tcg_constant_tl(0); 1632 if (add_ca) { 1633 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1634 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1635 } else { 1636 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1637 } 1638 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1639 } 1640 } else { 1641 tcg_gen_add_tl(t0, arg1, arg2); 1642 if (add_ca) { 1643 tcg_gen_add_tl(t0, t0, ca); 1644 } 1645 } 1646 1647 if (compute_ov) { 1648 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1649 } 1650 if (unlikely(compute_rc0)) { 1651 gen_set_Rc0(ctx, t0); 1652 } 1653 1654 if (t0 != ret) { 1655 tcg_gen_mov_tl(ret, t0); 1656 } 1657 } 1658 /* Add functions with two operands */ 1659 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1660 static void glue(gen_, name)(DisasContext *ctx) \ 1661 { \ 1662 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1663 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1664 ca, glue(ca, 32), \ 1665 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1666 } 1667 /* Add functions with one operand and one immediate */ 1668 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1669 add_ca, compute_ca, compute_ov) \ 1670 static void glue(gen_, name)(DisasContext *ctx) \ 1671 { \ 1672 TCGv t0 = tcg_constant_tl(const_val); \ 1673 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1674 cpu_gpr[rA(ctx->opcode)], t0, \ 1675 ca, glue(ca, 32), \ 1676 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1677 } 1678 1679 /* add add. addo addo. */ 1680 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1681 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1682 /* addc addc. addco addco. */ 1683 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1684 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1685 /* adde adde. addeo addeo. */ 1686 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1687 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1688 /* addme addme. addmeo addmeo. */ 1689 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1690 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1691 /* addex */ 1692 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1693 /* addze addze. addzeo addzeo.*/ 1694 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1695 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1696 /* addic addic.*/ 1697 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1698 { 1699 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1700 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1701 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1702 } 1703 1704 static void gen_addic(DisasContext *ctx) 1705 { 1706 gen_op_addic(ctx, 0); 1707 } 1708 1709 static void gen_addic_(DisasContext *ctx) 1710 { 1711 gen_op_addic(ctx, 1); 1712 } 1713 1714 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1715 TCGv arg2, int sign, int compute_ov) 1716 { 1717 TCGv_i32 t0 = tcg_temp_new_i32(); 1718 TCGv_i32 t1 = tcg_temp_new_i32(); 1719 TCGv_i32 t2 = tcg_temp_new_i32(); 1720 TCGv_i32 t3 = tcg_temp_new_i32(); 1721 1722 tcg_gen_trunc_tl_i32(t0, arg1); 1723 tcg_gen_trunc_tl_i32(t1, arg2); 1724 if (sign) { 1725 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1726 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1727 tcg_gen_and_i32(t2, t2, t3); 1728 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1729 tcg_gen_or_i32(t2, t2, t3); 1730 tcg_gen_movi_i32(t3, 0); 1731 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1732 tcg_gen_div_i32(t3, t0, t1); 1733 tcg_gen_extu_i32_tl(ret, t3); 1734 } else { 1735 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1736 tcg_gen_movi_i32(t3, 0); 1737 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1738 tcg_gen_divu_i32(t3, t0, t1); 1739 tcg_gen_extu_i32_tl(ret, t3); 1740 } 1741 if (compute_ov) { 1742 tcg_gen_extu_i32_tl(cpu_ov, t2); 1743 if (is_isa300(ctx)) { 1744 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1745 } 1746 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1747 } 1748 1749 if (unlikely(Rc(ctx->opcode) != 0)) { 1750 gen_set_Rc0(ctx, ret); 1751 } 1752 } 1753 /* Div functions */ 1754 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1755 static void glue(gen_, name)(DisasContext *ctx) \ 1756 { \ 1757 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1758 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1759 sign, compute_ov); \ 1760 } 1761 /* divwu divwu. divwuo divwuo. */ 1762 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1763 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1764 /* divw divw. divwo divwo. */ 1765 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1766 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1767 1768 /* div[wd]eu[o][.] */ 1769 #define GEN_DIVE(name, hlpr, compute_ov) \ 1770 static void gen_##name(DisasContext *ctx) \ 1771 { \ 1772 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1773 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1774 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1775 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1776 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1777 } \ 1778 } 1779 1780 GEN_DIVE(divweu, divweu, 0); 1781 GEN_DIVE(divweuo, divweu, 1); 1782 GEN_DIVE(divwe, divwe, 0); 1783 GEN_DIVE(divweo, divwe, 1); 1784 1785 #if defined(TARGET_PPC64) 1786 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1787 TCGv arg2, int sign, int compute_ov) 1788 { 1789 TCGv_i64 t0 = tcg_temp_new_i64(); 1790 TCGv_i64 t1 = tcg_temp_new_i64(); 1791 TCGv_i64 t2 = tcg_temp_new_i64(); 1792 TCGv_i64 t3 = tcg_temp_new_i64(); 1793 1794 tcg_gen_mov_i64(t0, arg1); 1795 tcg_gen_mov_i64(t1, arg2); 1796 if (sign) { 1797 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1798 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1799 tcg_gen_and_i64(t2, t2, t3); 1800 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1801 tcg_gen_or_i64(t2, t2, t3); 1802 tcg_gen_movi_i64(t3, 0); 1803 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1804 tcg_gen_div_i64(ret, t0, t1); 1805 } else { 1806 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1807 tcg_gen_movi_i64(t3, 0); 1808 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1809 tcg_gen_divu_i64(ret, t0, t1); 1810 } 1811 if (compute_ov) { 1812 tcg_gen_mov_tl(cpu_ov, t2); 1813 if (is_isa300(ctx)) { 1814 tcg_gen_mov_tl(cpu_ov32, t2); 1815 } 1816 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1817 } 1818 1819 if (unlikely(Rc(ctx->opcode) != 0)) { 1820 gen_set_Rc0(ctx, ret); 1821 } 1822 } 1823 1824 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1825 static void glue(gen_, name)(DisasContext *ctx) \ 1826 { \ 1827 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1828 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1829 sign, compute_ov); \ 1830 } 1831 /* divdu divdu. divduo divduo. */ 1832 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1833 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1834 /* divd divd. divdo divdo. */ 1835 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1836 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1837 1838 GEN_DIVE(divdeu, divdeu, 0); 1839 GEN_DIVE(divdeuo, divdeu, 1); 1840 GEN_DIVE(divde, divde, 0); 1841 GEN_DIVE(divdeo, divde, 1); 1842 #endif 1843 1844 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1845 TCGv arg2, int sign) 1846 { 1847 TCGv_i32 t0 = tcg_temp_new_i32(); 1848 TCGv_i32 t1 = tcg_temp_new_i32(); 1849 1850 tcg_gen_trunc_tl_i32(t0, arg1); 1851 tcg_gen_trunc_tl_i32(t1, arg2); 1852 if (sign) { 1853 TCGv_i32 t2 = tcg_temp_new_i32(); 1854 TCGv_i32 t3 = tcg_temp_new_i32(); 1855 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1856 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1857 tcg_gen_and_i32(t2, t2, t3); 1858 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1859 tcg_gen_or_i32(t2, t2, t3); 1860 tcg_gen_movi_i32(t3, 0); 1861 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1862 tcg_gen_rem_i32(t3, t0, t1); 1863 tcg_gen_ext_i32_tl(ret, t3); 1864 } else { 1865 TCGv_i32 t2 = tcg_constant_i32(1); 1866 TCGv_i32 t3 = tcg_constant_i32(0); 1867 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1868 tcg_gen_remu_i32(t0, t0, t1); 1869 tcg_gen_extu_i32_tl(ret, t0); 1870 } 1871 } 1872 1873 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1874 static void glue(gen_, name)(DisasContext *ctx) \ 1875 { \ 1876 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1877 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1878 sign); \ 1879 } 1880 1881 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1882 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1883 1884 #if defined(TARGET_PPC64) 1885 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1886 TCGv arg2, int sign) 1887 { 1888 TCGv_i64 t0 = tcg_temp_new_i64(); 1889 TCGv_i64 t1 = tcg_temp_new_i64(); 1890 1891 tcg_gen_mov_i64(t0, arg1); 1892 tcg_gen_mov_i64(t1, arg2); 1893 if (sign) { 1894 TCGv_i64 t2 = tcg_temp_new_i64(); 1895 TCGv_i64 t3 = tcg_temp_new_i64(); 1896 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1897 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1898 tcg_gen_and_i64(t2, t2, t3); 1899 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1900 tcg_gen_or_i64(t2, t2, t3); 1901 tcg_gen_movi_i64(t3, 0); 1902 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1903 tcg_gen_rem_i64(ret, t0, t1); 1904 } else { 1905 TCGv_i64 t2 = tcg_constant_i64(1); 1906 TCGv_i64 t3 = tcg_constant_i64(0); 1907 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1908 tcg_gen_remu_i64(ret, t0, t1); 1909 } 1910 } 1911 1912 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1913 static void glue(gen_, name)(DisasContext *ctx) \ 1914 { \ 1915 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1916 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1917 sign); \ 1918 } 1919 1920 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1921 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1922 #endif 1923 1924 /* mulhw mulhw. */ 1925 static void gen_mulhw(DisasContext *ctx) 1926 { 1927 TCGv_i32 t0 = tcg_temp_new_i32(); 1928 TCGv_i32 t1 = tcg_temp_new_i32(); 1929 1930 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1931 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1932 tcg_gen_muls2_i32(t0, t1, t0, t1); 1933 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1934 if (unlikely(Rc(ctx->opcode) != 0)) { 1935 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1936 } 1937 } 1938 1939 /* mulhwu mulhwu. */ 1940 static void gen_mulhwu(DisasContext *ctx) 1941 { 1942 TCGv_i32 t0 = tcg_temp_new_i32(); 1943 TCGv_i32 t1 = tcg_temp_new_i32(); 1944 1945 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1946 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1947 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1948 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1949 if (unlikely(Rc(ctx->opcode) != 0)) { 1950 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1951 } 1952 } 1953 1954 /* mullw mullw. */ 1955 static void gen_mullw(DisasContext *ctx) 1956 { 1957 #if defined(TARGET_PPC64) 1958 TCGv_i64 t0, t1; 1959 t0 = tcg_temp_new_i64(); 1960 t1 = tcg_temp_new_i64(); 1961 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1962 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1963 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1964 #else 1965 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1966 cpu_gpr[rB(ctx->opcode)]); 1967 #endif 1968 if (unlikely(Rc(ctx->opcode) != 0)) { 1969 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1970 } 1971 } 1972 1973 /* mullwo mullwo. */ 1974 static void gen_mullwo(DisasContext *ctx) 1975 { 1976 TCGv_i32 t0 = tcg_temp_new_i32(); 1977 TCGv_i32 t1 = tcg_temp_new_i32(); 1978 1979 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1980 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1981 tcg_gen_muls2_i32(t0, t1, t0, t1); 1982 #if defined(TARGET_PPC64) 1983 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1984 #else 1985 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1986 #endif 1987 1988 tcg_gen_sari_i32(t0, t0, 31); 1989 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1990 tcg_gen_extu_i32_tl(cpu_ov, t0); 1991 if (is_isa300(ctx)) { 1992 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1993 } 1994 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1995 1996 if (unlikely(Rc(ctx->opcode) != 0)) { 1997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1998 } 1999 } 2000 2001 /* mulli */ 2002 static void gen_mulli(DisasContext *ctx) 2003 { 2004 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2005 SIMM(ctx->opcode)); 2006 } 2007 2008 #if defined(TARGET_PPC64) 2009 /* mulhd mulhd. */ 2010 static void gen_mulhd(DisasContext *ctx) 2011 { 2012 TCGv lo = tcg_temp_new(); 2013 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2014 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2015 if (unlikely(Rc(ctx->opcode) != 0)) { 2016 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2017 } 2018 } 2019 2020 /* mulhdu mulhdu. */ 2021 static void gen_mulhdu(DisasContext *ctx) 2022 { 2023 TCGv lo = tcg_temp_new(); 2024 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2025 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2026 if (unlikely(Rc(ctx->opcode) != 0)) { 2027 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2028 } 2029 } 2030 2031 /* mulld mulld. */ 2032 static void gen_mulld(DisasContext *ctx) 2033 { 2034 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2035 cpu_gpr[rB(ctx->opcode)]); 2036 if (unlikely(Rc(ctx->opcode) != 0)) { 2037 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2038 } 2039 } 2040 2041 /* mulldo mulldo. */ 2042 static void gen_mulldo(DisasContext *ctx) 2043 { 2044 TCGv_i64 t0 = tcg_temp_new_i64(); 2045 TCGv_i64 t1 = tcg_temp_new_i64(); 2046 2047 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2048 cpu_gpr[rB(ctx->opcode)]); 2049 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2050 2051 tcg_gen_sari_i64(t0, t0, 63); 2052 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2053 if (is_isa300(ctx)) { 2054 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2055 } 2056 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2057 2058 if (unlikely(Rc(ctx->opcode) != 0)) { 2059 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2060 } 2061 } 2062 #endif 2063 2064 /* Common subf function */ 2065 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2066 TCGv arg2, bool add_ca, bool compute_ca, 2067 bool compute_ov, bool compute_rc0) 2068 { 2069 TCGv t0 = ret; 2070 2071 if (compute_ca || compute_ov) { 2072 t0 = tcg_temp_new(); 2073 } 2074 2075 if (compute_ca) { 2076 /* dest = ~arg1 + arg2 [+ ca]. */ 2077 if (NARROW_MODE(ctx)) { 2078 /* 2079 * Caution: a non-obvious corner case of the spec is that 2080 * we must produce the *entire* 64-bit addition, but 2081 * produce the carry into bit 32. 2082 */ 2083 TCGv inv1 = tcg_temp_new(); 2084 TCGv t1 = tcg_temp_new(); 2085 tcg_gen_not_tl(inv1, arg1); 2086 if (add_ca) { 2087 tcg_gen_add_tl(t0, arg2, cpu_ca); 2088 } else { 2089 tcg_gen_addi_tl(t0, arg2, 1); 2090 } 2091 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2092 tcg_gen_add_tl(t0, t0, inv1); 2093 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2094 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2095 if (is_isa300(ctx)) { 2096 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2097 } 2098 } else if (add_ca) { 2099 TCGv zero, inv1 = tcg_temp_new(); 2100 tcg_gen_not_tl(inv1, arg1); 2101 zero = tcg_constant_tl(0); 2102 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2103 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2104 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2105 } else { 2106 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2107 tcg_gen_sub_tl(t0, arg2, arg1); 2108 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2109 } 2110 } else if (add_ca) { 2111 /* 2112 * Since we're ignoring carry-out, we can simplify the 2113 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2114 */ 2115 tcg_gen_sub_tl(t0, arg2, arg1); 2116 tcg_gen_add_tl(t0, t0, cpu_ca); 2117 tcg_gen_subi_tl(t0, t0, 1); 2118 } else { 2119 tcg_gen_sub_tl(t0, arg2, arg1); 2120 } 2121 2122 if (compute_ov) { 2123 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2124 } 2125 if (unlikely(compute_rc0)) { 2126 gen_set_Rc0(ctx, t0); 2127 } 2128 2129 if (t0 != ret) { 2130 tcg_gen_mov_tl(ret, t0); 2131 } 2132 } 2133 /* Sub functions with Two operands functions */ 2134 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2135 static void glue(gen_, name)(DisasContext *ctx) \ 2136 { \ 2137 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2139 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2140 } 2141 /* Sub functions with one operand and one immediate */ 2142 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2143 add_ca, compute_ca, compute_ov) \ 2144 static void glue(gen_, name)(DisasContext *ctx) \ 2145 { \ 2146 TCGv t0 = tcg_constant_tl(const_val); \ 2147 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2148 cpu_gpr[rA(ctx->opcode)], t0, \ 2149 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2150 } 2151 /* subf subf. subfo subfo. */ 2152 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2153 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2154 /* subfc subfc. subfco subfco. */ 2155 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2156 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2157 /* subfe subfe. subfeo subfo. */ 2158 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2159 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2160 /* subfme subfme. subfmeo subfmeo. */ 2161 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2162 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2163 /* subfze subfze. subfzeo subfzeo.*/ 2164 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2165 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2166 2167 /* subfic */ 2168 static void gen_subfic(DisasContext *ctx) 2169 { 2170 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2171 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2172 c, 0, 1, 0, 0); 2173 } 2174 2175 /* neg neg. nego nego. */ 2176 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2177 { 2178 TCGv zero = tcg_constant_tl(0); 2179 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2180 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2181 } 2182 2183 static void gen_neg(DisasContext *ctx) 2184 { 2185 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2186 if (unlikely(Rc(ctx->opcode))) { 2187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2188 } 2189 } 2190 2191 static void gen_nego(DisasContext *ctx) 2192 { 2193 gen_op_arith_neg(ctx, 1); 2194 } 2195 2196 /*** Integer logical ***/ 2197 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2198 static void glue(gen_, name)(DisasContext *ctx) \ 2199 { \ 2200 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2201 cpu_gpr[rB(ctx->opcode)]); \ 2202 if (unlikely(Rc(ctx->opcode) != 0)) \ 2203 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2204 } 2205 2206 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2207 static void glue(gen_, name)(DisasContext *ctx) \ 2208 { \ 2209 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2210 if (unlikely(Rc(ctx->opcode) != 0)) \ 2211 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2212 } 2213 2214 /* and & and. */ 2215 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2216 /* andc & andc. */ 2217 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2218 2219 /* andi. */ 2220 static void gen_andi_(DisasContext *ctx) 2221 { 2222 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2223 UIMM(ctx->opcode)); 2224 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2225 } 2226 2227 /* andis. */ 2228 static void gen_andis_(DisasContext *ctx) 2229 { 2230 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2231 UIMM(ctx->opcode) << 16); 2232 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2233 } 2234 2235 /* cntlzw */ 2236 static void gen_cntlzw(DisasContext *ctx) 2237 { 2238 TCGv_i32 t = tcg_temp_new_i32(); 2239 2240 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2241 tcg_gen_clzi_i32(t, t, 32); 2242 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2243 2244 if (unlikely(Rc(ctx->opcode) != 0)) { 2245 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2246 } 2247 } 2248 2249 /* cnttzw */ 2250 static void gen_cnttzw(DisasContext *ctx) 2251 { 2252 TCGv_i32 t = tcg_temp_new_i32(); 2253 2254 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2255 tcg_gen_ctzi_i32(t, t, 32); 2256 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2257 2258 if (unlikely(Rc(ctx->opcode) != 0)) { 2259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2260 } 2261 } 2262 2263 /* eqv & eqv. */ 2264 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2265 /* extsb & extsb. */ 2266 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2267 /* extsh & extsh. */ 2268 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2269 /* nand & nand. */ 2270 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2271 /* nor & nor. */ 2272 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2273 2274 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2275 static void gen_pause(DisasContext *ctx) 2276 { 2277 TCGv_i32 t0 = tcg_constant_i32(0); 2278 tcg_gen_st_i32(t0, cpu_env, 2279 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2280 2281 /* Stop translation, this gives other CPUs a chance to run */ 2282 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2283 } 2284 #endif /* defined(TARGET_PPC64) */ 2285 2286 /* or & or. */ 2287 static void gen_or(DisasContext *ctx) 2288 { 2289 int rs, ra, rb; 2290 2291 rs = rS(ctx->opcode); 2292 ra = rA(ctx->opcode); 2293 rb = rB(ctx->opcode); 2294 /* Optimisation for mr. ri case */ 2295 if (rs != ra || rs != rb) { 2296 if (rs != rb) { 2297 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2298 } else { 2299 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2300 } 2301 if (unlikely(Rc(ctx->opcode) != 0)) { 2302 gen_set_Rc0(ctx, cpu_gpr[ra]); 2303 } 2304 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2305 gen_set_Rc0(ctx, cpu_gpr[rs]); 2306 #if defined(TARGET_PPC64) 2307 } else if (rs != 0) { /* 0 is nop */ 2308 int prio = 0; 2309 2310 switch (rs) { 2311 case 1: 2312 /* Set process priority to low */ 2313 prio = 2; 2314 break; 2315 case 6: 2316 /* Set process priority to medium-low */ 2317 prio = 3; 2318 break; 2319 case 2: 2320 /* Set process priority to normal */ 2321 prio = 4; 2322 break; 2323 #if !defined(CONFIG_USER_ONLY) 2324 case 31: 2325 if (!ctx->pr) { 2326 /* Set process priority to very low */ 2327 prio = 1; 2328 } 2329 break; 2330 case 5: 2331 if (!ctx->pr) { 2332 /* Set process priority to medium-hight */ 2333 prio = 5; 2334 } 2335 break; 2336 case 3: 2337 if (!ctx->pr) { 2338 /* Set process priority to high */ 2339 prio = 6; 2340 } 2341 break; 2342 case 7: 2343 if (ctx->hv && !ctx->pr) { 2344 /* Set process priority to very high */ 2345 prio = 7; 2346 } 2347 break; 2348 #endif 2349 default: 2350 break; 2351 } 2352 if (prio) { 2353 TCGv t0 = tcg_temp_new(); 2354 gen_load_spr(t0, SPR_PPR); 2355 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2356 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2357 gen_store_spr(SPR_PPR, t0); 2358 } 2359 #if !defined(CONFIG_USER_ONLY) 2360 /* 2361 * Pause out of TCG otherwise spin loops with smt_low eat too 2362 * much CPU and the kernel hangs. This applies to all 2363 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2364 * mdoio(29), mdoom(30), and all currently undefined. 2365 */ 2366 gen_pause(ctx); 2367 #endif 2368 #endif 2369 } 2370 } 2371 /* orc & orc. */ 2372 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2373 2374 /* xor & xor. */ 2375 static void gen_xor(DisasContext *ctx) 2376 { 2377 /* Optimisation for "set to zero" case */ 2378 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2379 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2380 cpu_gpr[rB(ctx->opcode)]); 2381 } else { 2382 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2383 } 2384 if (unlikely(Rc(ctx->opcode) != 0)) { 2385 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2386 } 2387 } 2388 2389 /* ori */ 2390 static void gen_ori(DisasContext *ctx) 2391 { 2392 target_ulong uimm = UIMM(ctx->opcode); 2393 2394 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2395 return; 2396 } 2397 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2398 } 2399 2400 /* oris */ 2401 static void gen_oris(DisasContext *ctx) 2402 { 2403 target_ulong uimm = UIMM(ctx->opcode); 2404 2405 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2406 /* NOP */ 2407 return; 2408 } 2409 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2410 uimm << 16); 2411 } 2412 2413 /* xori */ 2414 static void gen_xori(DisasContext *ctx) 2415 { 2416 target_ulong uimm = UIMM(ctx->opcode); 2417 2418 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2419 /* NOP */ 2420 return; 2421 } 2422 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2423 } 2424 2425 /* xoris */ 2426 static void gen_xoris(DisasContext *ctx) 2427 { 2428 target_ulong uimm = UIMM(ctx->opcode); 2429 2430 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2431 /* NOP */ 2432 return; 2433 } 2434 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2435 uimm << 16); 2436 } 2437 2438 /* popcntb : PowerPC 2.03 specification */ 2439 static void gen_popcntb(DisasContext *ctx) 2440 { 2441 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2442 } 2443 2444 static void gen_popcntw(DisasContext *ctx) 2445 { 2446 #if defined(TARGET_PPC64) 2447 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2448 #else 2449 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2450 #endif 2451 } 2452 2453 #if defined(TARGET_PPC64) 2454 /* popcntd: PowerPC 2.06 specification */ 2455 static void gen_popcntd(DisasContext *ctx) 2456 { 2457 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2458 } 2459 #endif 2460 2461 /* prtyw: PowerPC 2.05 specification */ 2462 static void gen_prtyw(DisasContext *ctx) 2463 { 2464 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2465 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2466 TCGv t0 = tcg_temp_new(); 2467 tcg_gen_shri_tl(t0, rs, 16); 2468 tcg_gen_xor_tl(ra, rs, t0); 2469 tcg_gen_shri_tl(t0, ra, 8); 2470 tcg_gen_xor_tl(ra, ra, t0); 2471 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2472 } 2473 2474 #if defined(TARGET_PPC64) 2475 /* prtyd: PowerPC 2.05 specification */ 2476 static void gen_prtyd(DisasContext *ctx) 2477 { 2478 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2479 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2480 TCGv t0 = tcg_temp_new(); 2481 tcg_gen_shri_tl(t0, rs, 32); 2482 tcg_gen_xor_tl(ra, rs, t0); 2483 tcg_gen_shri_tl(t0, ra, 16); 2484 tcg_gen_xor_tl(ra, ra, t0); 2485 tcg_gen_shri_tl(t0, ra, 8); 2486 tcg_gen_xor_tl(ra, ra, t0); 2487 tcg_gen_andi_tl(ra, ra, 1); 2488 } 2489 #endif 2490 2491 #if defined(TARGET_PPC64) 2492 /* bpermd */ 2493 static void gen_bpermd(DisasContext *ctx) 2494 { 2495 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2496 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2497 } 2498 #endif 2499 2500 #if defined(TARGET_PPC64) 2501 /* extsw & extsw. */ 2502 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2503 2504 /* cntlzd */ 2505 static void gen_cntlzd(DisasContext *ctx) 2506 { 2507 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2508 if (unlikely(Rc(ctx->opcode) != 0)) { 2509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2510 } 2511 } 2512 2513 /* cnttzd */ 2514 static void gen_cnttzd(DisasContext *ctx) 2515 { 2516 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2517 if (unlikely(Rc(ctx->opcode) != 0)) { 2518 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2519 } 2520 } 2521 2522 /* darn */ 2523 static void gen_darn(DisasContext *ctx) 2524 { 2525 int l = L(ctx->opcode); 2526 2527 if (l > 2) { 2528 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2529 } else { 2530 translator_io_start(&ctx->base); 2531 if (l == 0) { 2532 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2533 } else { 2534 /* Return 64-bit random for both CRN and RRN */ 2535 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2536 } 2537 } 2538 } 2539 #endif 2540 2541 /*** Integer rotate ***/ 2542 2543 /* rlwimi & rlwimi. */ 2544 static void gen_rlwimi(DisasContext *ctx) 2545 { 2546 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2547 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2548 uint32_t sh = SH(ctx->opcode); 2549 uint32_t mb = MB(ctx->opcode); 2550 uint32_t me = ME(ctx->opcode); 2551 2552 if (sh == (31 - me) && mb <= me) { 2553 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2554 } else { 2555 target_ulong mask; 2556 bool mask_in_32b = true; 2557 TCGv t1; 2558 2559 #if defined(TARGET_PPC64) 2560 mb += 32; 2561 me += 32; 2562 #endif 2563 mask = MASK(mb, me); 2564 2565 #if defined(TARGET_PPC64) 2566 if (mask > 0xffffffffu) { 2567 mask_in_32b = false; 2568 } 2569 #endif 2570 t1 = tcg_temp_new(); 2571 if (mask_in_32b) { 2572 TCGv_i32 t0 = tcg_temp_new_i32(); 2573 tcg_gen_trunc_tl_i32(t0, t_rs); 2574 tcg_gen_rotli_i32(t0, t0, sh); 2575 tcg_gen_extu_i32_tl(t1, t0); 2576 } else { 2577 #if defined(TARGET_PPC64) 2578 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2579 tcg_gen_rotli_i64(t1, t1, sh); 2580 #else 2581 g_assert_not_reached(); 2582 #endif 2583 } 2584 2585 tcg_gen_andi_tl(t1, t1, mask); 2586 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2587 tcg_gen_or_tl(t_ra, t_ra, t1); 2588 } 2589 if (unlikely(Rc(ctx->opcode) != 0)) { 2590 gen_set_Rc0(ctx, t_ra); 2591 } 2592 } 2593 2594 /* rlwinm & rlwinm. */ 2595 static void gen_rlwinm(DisasContext *ctx) 2596 { 2597 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2598 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2599 int sh = SH(ctx->opcode); 2600 int mb = MB(ctx->opcode); 2601 int me = ME(ctx->opcode); 2602 int len = me - mb + 1; 2603 int rsh = (32 - sh) & 31; 2604 2605 if (sh != 0 && len > 0 && me == (31 - sh)) { 2606 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2607 } else if (me == 31 && rsh + len <= 32) { 2608 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2609 } else { 2610 target_ulong mask; 2611 bool mask_in_32b = true; 2612 #if defined(TARGET_PPC64) 2613 mb += 32; 2614 me += 32; 2615 #endif 2616 mask = MASK(mb, me); 2617 #if defined(TARGET_PPC64) 2618 if (mask > 0xffffffffu) { 2619 mask_in_32b = false; 2620 } 2621 #endif 2622 if (mask_in_32b) { 2623 if (sh == 0) { 2624 tcg_gen_andi_tl(t_ra, t_rs, mask); 2625 } else { 2626 TCGv_i32 t0 = tcg_temp_new_i32(); 2627 tcg_gen_trunc_tl_i32(t0, t_rs); 2628 tcg_gen_rotli_i32(t0, t0, sh); 2629 tcg_gen_andi_i32(t0, t0, mask); 2630 tcg_gen_extu_i32_tl(t_ra, t0); 2631 } 2632 } else { 2633 #if defined(TARGET_PPC64) 2634 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2635 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2636 tcg_gen_andi_i64(t_ra, t_ra, mask); 2637 #else 2638 g_assert_not_reached(); 2639 #endif 2640 } 2641 } 2642 if (unlikely(Rc(ctx->opcode) != 0)) { 2643 gen_set_Rc0(ctx, t_ra); 2644 } 2645 } 2646 2647 /* rlwnm & rlwnm. */ 2648 static void gen_rlwnm(DisasContext *ctx) 2649 { 2650 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2651 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2652 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2653 uint32_t mb = MB(ctx->opcode); 2654 uint32_t me = ME(ctx->opcode); 2655 target_ulong mask; 2656 bool mask_in_32b = true; 2657 2658 #if defined(TARGET_PPC64) 2659 mb += 32; 2660 me += 32; 2661 #endif 2662 mask = MASK(mb, me); 2663 2664 #if defined(TARGET_PPC64) 2665 if (mask > 0xffffffffu) { 2666 mask_in_32b = false; 2667 } 2668 #endif 2669 if (mask_in_32b) { 2670 TCGv_i32 t0 = tcg_temp_new_i32(); 2671 TCGv_i32 t1 = tcg_temp_new_i32(); 2672 tcg_gen_trunc_tl_i32(t0, t_rb); 2673 tcg_gen_trunc_tl_i32(t1, t_rs); 2674 tcg_gen_andi_i32(t0, t0, 0x1f); 2675 tcg_gen_rotl_i32(t1, t1, t0); 2676 tcg_gen_extu_i32_tl(t_ra, t1); 2677 } else { 2678 #if defined(TARGET_PPC64) 2679 TCGv_i64 t0 = tcg_temp_new_i64(); 2680 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2681 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2682 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2683 #else 2684 g_assert_not_reached(); 2685 #endif 2686 } 2687 2688 tcg_gen_andi_tl(t_ra, t_ra, mask); 2689 2690 if (unlikely(Rc(ctx->opcode) != 0)) { 2691 gen_set_Rc0(ctx, t_ra); 2692 } 2693 } 2694 2695 #if defined(TARGET_PPC64) 2696 #define GEN_PPC64_R2(name, opc1, opc2) \ 2697 static void glue(gen_, name##0)(DisasContext *ctx) \ 2698 { \ 2699 gen_##name(ctx, 0); \ 2700 } \ 2701 \ 2702 static void glue(gen_, name##1)(DisasContext *ctx) \ 2703 { \ 2704 gen_##name(ctx, 1); \ 2705 } 2706 #define GEN_PPC64_R4(name, opc1, opc2) \ 2707 static void glue(gen_, name##0)(DisasContext *ctx) \ 2708 { \ 2709 gen_##name(ctx, 0, 0); \ 2710 } \ 2711 \ 2712 static void glue(gen_, name##1)(DisasContext *ctx) \ 2713 { \ 2714 gen_##name(ctx, 0, 1); \ 2715 } \ 2716 \ 2717 static void glue(gen_, name##2)(DisasContext *ctx) \ 2718 { \ 2719 gen_##name(ctx, 1, 0); \ 2720 } \ 2721 \ 2722 static void glue(gen_, name##3)(DisasContext *ctx) \ 2723 { \ 2724 gen_##name(ctx, 1, 1); \ 2725 } 2726 2727 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2728 { 2729 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2730 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2731 int len = me - mb + 1; 2732 int rsh = (64 - sh) & 63; 2733 2734 if (sh != 0 && len > 0 && me == (63 - sh)) { 2735 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2736 } else if (me == 63 && rsh + len <= 64) { 2737 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2738 } else { 2739 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2740 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2741 } 2742 if (unlikely(Rc(ctx->opcode) != 0)) { 2743 gen_set_Rc0(ctx, t_ra); 2744 } 2745 } 2746 2747 /* rldicl - rldicl. */ 2748 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2749 { 2750 uint32_t sh, mb; 2751 2752 sh = SH(ctx->opcode) | (shn << 5); 2753 mb = MB(ctx->opcode) | (mbn << 5); 2754 gen_rldinm(ctx, mb, 63, sh); 2755 } 2756 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2757 2758 /* rldicr - rldicr. */ 2759 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2760 { 2761 uint32_t sh, me; 2762 2763 sh = SH(ctx->opcode) | (shn << 5); 2764 me = MB(ctx->opcode) | (men << 5); 2765 gen_rldinm(ctx, 0, me, sh); 2766 } 2767 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2768 2769 /* rldic - rldic. */ 2770 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2771 { 2772 uint32_t sh, mb; 2773 2774 sh = SH(ctx->opcode) | (shn << 5); 2775 mb = MB(ctx->opcode) | (mbn << 5); 2776 gen_rldinm(ctx, mb, 63 - sh, sh); 2777 } 2778 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2779 2780 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2781 { 2782 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2783 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2784 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2785 TCGv t0; 2786 2787 t0 = tcg_temp_new(); 2788 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2789 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2790 2791 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2792 if (unlikely(Rc(ctx->opcode) != 0)) { 2793 gen_set_Rc0(ctx, t_ra); 2794 } 2795 } 2796 2797 /* rldcl - rldcl. */ 2798 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2799 { 2800 uint32_t mb; 2801 2802 mb = MB(ctx->opcode) | (mbn << 5); 2803 gen_rldnm(ctx, mb, 63); 2804 } 2805 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2806 2807 /* rldcr - rldcr. */ 2808 static inline void gen_rldcr(DisasContext *ctx, int men) 2809 { 2810 uint32_t me; 2811 2812 me = MB(ctx->opcode) | (men << 5); 2813 gen_rldnm(ctx, 0, me); 2814 } 2815 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2816 2817 /* rldimi - rldimi. */ 2818 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2819 { 2820 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2821 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2822 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2823 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2824 uint32_t me = 63 - sh; 2825 2826 if (mb <= me) { 2827 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2828 } else { 2829 target_ulong mask = MASK(mb, me); 2830 TCGv t1 = tcg_temp_new(); 2831 2832 tcg_gen_rotli_tl(t1, t_rs, sh); 2833 tcg_gen_andi_tl(t1, t1, mask); 2834 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2835 tcg_gen_or_tl(t_ra, t_ra, t1); 2836 } 2837 if (unlikely(Rc(ctx->opcode) != 0)) { 2838 gen_set_Rc0(ctx, t_ra); 2839 } 2840 } 2841 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2842 #endif 2843 2844 /*** Integer shift ***/ 2845 2846 /* slw & slw. */ 2847 static void gen_slw(DisasContext *ctx) 2848 { 2849 TCGv t0, t1; 2850 2851 t0 = tcg_temp_new(); 2852 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2853 #if defined(TARGET_PPC64) 2854 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2855 tcg_gen_sari_tl(t0, t0, 0x3f); 2856 #else 2857 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2858 tcg_gen_sari_tl(t0, t0, 0x1f); 2859 #endif 2860 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2861 t1 = tcg_temp_new(); 2862 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2863 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2864 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2865 if (unlikely(Rc(ctx->opcode) != 0)) { 2866 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2867 } 2868 } 2869 2870 /* sraw & sraw. */ 2871 static void gen_sraw(DisasContext *ctx) 2872 { 2873 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2874 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2875 if (unlikely(Rc(ctx->opcode) != 0)) { 2876 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2877 } 2878 } 2879 2880 /* srawi & srawi. */ 2881 static void gen_srawi(DisasContext *ctx) 2882 { 2883 int sh = SH(ctx->opcode); 2884 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2885 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2886 if (sh == 0) { 2887 tcg_gen_ext32s_tl(dst, src); 2888 tcg_gen_movi_tl(cpu_ca, 0); 2889 if (is_isa300(ctx)) { 2890 tcg_gen_movi_tl(cpu_ca32, 0); 2891 } 2892 } else { 2893 TCGv t0; 2894 tcg_gen_ext32s_tl(dst, src); 2895 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2896 t0 = tcg_temp_new(); 2897 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2898 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2899 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2900 if (is_isa300(ctx)) { 2901 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2902 } 2903 tcg_gen_sari_tl(dst, dst, sh); 2904 } 2905 if (unlikely(Rc(ctx->opcode) != 0)) { 2906 gen_set_Rc0(ctx, dst); 2907 } 2908 } 2909 2910 /* srw & srw. */ 2911 static void gen_srw(DisasContext *ctx) 2912 { 2913 TCGv t0, t1; 2914 2915 t0 = tcg_temp_new(); 2916 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2917 #if defined(TARGET_PPC64) 2918 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2919 tcg_gen_sari_tl(t0, t0, 0x3f); 2920 #else 2921 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2922 tcg_gen_sari_tl(t0, t0, 0x1f); 2923 #endif 2924 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2925 tcg_gen_ext32u_tl(t0, t0); 2926 t1 = tcg_temp_new(); 2927 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2928 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2929 if (unlikely(Rc(ctx->opcode) != 0)) { 2930 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2931 } 2932 } 2933 2934 #if defined(TARGET_PPC64) 2935 /* sld & sld. */ 2936 static void gen_sld(DisasContext *ctx) 2937 { 2938 TCGv t0, t1; 2939 2940 t0 = tcg_temp_new(); 2941 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2942 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2943 tcg_gen_sari_tl(t0, t0, 0x3f); 2944 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2945 t1 = tcg_temp_new(); 2946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2947 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2948 if (unlikely(Rc(ctx->opcode) != 0)) { 2949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2950 } 2951 } 2952 2953 /* srad & srad. */ 2954 static void gen_srad(DisasContext *ctx) 2955 { 2956 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2957 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2958 if (unlikely(Rc(ctx->opcode) != 0)) { 2959 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2960 } 2961 } 2962 /* sradi & sradi. */ 2963 static inline void gen_sradi(DisasContext *ctx, int n) 2964 { 2965 int sh = SH(ctx->opcode) + (n << 5); 2966 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2967 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2968 if (sh == 0) { 2969 tcg_gen_mov_tl(dst, src); 2970 tcg_gen_movi_tl(cpu_ca, 0); 2971 if (is_isa300(ctx)) { 2972 tcg_gen_movi_tl(cpu_ca32, 0); 2973 } 2974 } else { 2975 TCGv t0; 2976 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2977 t0 = tcg_temp_new(); 2978 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2979 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2980 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2981 if (is_isa300(ctx)) { 2982 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2983 } 2984 tcg_gen_sari_tl(dst, src, sh); 2985 } 2986 if (unlikely(Rc(ctx->opcode) != 0)) { 2987 gen_set_Rc0(ctx, dst); 2988 } 2989 } 2990 2991 static void gen_sradi0(DisasContext *ctx) 2992 { 2993 gen_sradi(ctx, 0); 2994 } 2995 2996 static void gen_sradi1(DisasContext *ctx) 2997 { 2998 gen_sradi(ctx, 1); 2999 } 3000 3001 /* extswsli & extswsli. */ 3002 static inline void gen_extswsli(DisasContext *ctx, int n) 3003 { 3004 int sh = SH(ctx->opcode) + (n << 5); 3005 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3006 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3007 3008 tcg_gen_ext32s_tl(dst, src); 3009 tcg_gen_shli_tl(dst, dst, sh); 3010 if (unlikely(Rc(ctx->opcode) != 0)) { 3011 gen_set_Rc0(ctx, dst); 3012 } 3013 } 3014 3015 static void gen_extswsli0(DisasContext *ctx) 3016 { 3017 gen_extswsli(ctx, 0); 3018 } 3019 3020 static void gen_extswsli1(DisasContext *ctx) 3021 { 3022 gen_extswsli(ctx, 1); 3023 } 3024 3025 /* srd & srd. */ 3026 static void gen_srd(DisasContext *ctx) 3027 { 3028 TCGv t0, t1; 3029 3030 t0 = tcg_temp_new(); 3031 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3032 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3033 tcg_gen_sari_tl(t0, t0, 0x3f); 3034 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3035 t1 = tcg_temp_new(); 3036 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3037 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3038 if (unlikely(Rc(ctx->opcode) != 0)) { 3039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3040 } 3041 } 3042 #endif 3043 3044 /*** Addressing modes ***/ 3045 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3046 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3047 target_long maskl) 3048 { 3049 target_long simm = SIMM(ctx->opcode); 3050 3051 simm &= ~maskl; 3052 if (rA(ctx->opcode) == 0) { 3053 if (NARROW_MODE(ctx)) { 3054 simm = (uint32_t)simm; 3055 } 3056 tcg_gen_movi_tl(EA, simm); 3057 } else if (likely(simm != 0)) { 3058 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3059 if (NARROW_MODE(ctx)) { 3060 tcg_gen_ext32u_tl(EA, EA); 3061 } 3062 } else { 3063 if (NARROW_MODE(ctx)) { 3064 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3065 } else { 3066 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3067 } 3068 } 3069 } 3070 3071 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3072 { 3073 if (rA(ctx->opcode) == 0) { 3074 if (NARROW_MODE(ctx)) { 3075 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3076 } else { 3077 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3078 } 3079 } else { 3080 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3081 if (NARROW_MODE(ctx)) { 3082 tcg_gen_ext32u_tl(EA, EA); 3083 } 3084 } 3085 } 3086 3087 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3088 { 3089 if (rA(ctx->opcode) == 0) { 3090 tcg_gen_movi_tl(EA, 0); 3091 } else if (NARROW_MODE(ctx)) { 3092 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3093 } else { 3094 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3095 } 3096 } 3097 3098 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3099 target_long val) 3100 { 3101 tcg_gen_addi_tl(ret, arg1, val); 3102 if (NARROW_MODE(ctx)) { 3103 tcg_gen_ext32u_tl(ret, ret); 3104 } 3105 } 3106 3107 static inline void gen_align_no_le(DisasContext *ctx) 3108 { 3109 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3110 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3111 } 3112 3113 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3114 { 3115 TCGv ea = tcg_temp_new(); 3116 if (ra) { 3117 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3118 } else { 3119 tcg_gen_mov_tl(ea, displ); 3120 } 3121 if (NARROW_MODE(ctx)) { 3122 tcg_gen_ext32u_tl(ea, ea); 3123 } 3124 return ea; 3125 } 3126 3127 /*** Integer load ***/ 3128 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3129 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3130 3131 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3132 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3133 TCGv val, \ 3134 TCGv addr) \ 3135 { \ 3136 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3137 } 3138 3139 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3140 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3141 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3142 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3143 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3144 3145 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3146 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3147 3148 #define GEN_QEMU_LOAD_64(ldop, op) \ 3149 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3150 TCGv_i64 val, \ 3151 TCGv addr) \ 3152 { \ 3153 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3154 } 3155 3156 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3157 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3158 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3159 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3160 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3161 3162 #if defined(TARGET_PPC64) 3163 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3164 #endif 3165 3166 #define GEN_QEMU_STORE_TL(stop, op) \ 3167 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3168 TCGv val, \ 3169 TCGv addr) \ 3170 { \ 3171 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3172 } 3173 3174 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3175 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3176 #endif 3177 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3178 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3179 3180 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3181 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3182 3183 #define GEN_QEMU_STORE_64(stop, op) \ 3184 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3185 TCGv_i64 val, \ 3186 TCGv addr) \ 3187 { \ 3188 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3189 } 3190 3191 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3192 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3193 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3194 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3195 3196 #if defined(TARGET_PPC64) 3197 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3198 #endif 3199 3200 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3201 static void glue(gen_, name##x)(DisasContext *ctx) \ 3202 { \ 3203 TCGv EA; \ 3204 chk(ctx); \ 3205 gen_set_access_type(ctx, ACCESS_INT); \ 3206 EA = tcg_temp_new(); \ 3207 gen_addr_reg_index(ctx, EA); \ 3208 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3209 } 3210 3211 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3212 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3213 3214 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3215 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3216 3217 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3218 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3219 { \ 3220 TCGv EA; \ 3221 CHK_SV(ctx); \ 3222 gen_set_access_type(ctx, ACCESS_INT); \ 3223 EA = tcg_temp_new(); \ 3224 gen_addr_reg_index(ctx, EA); \ 3225 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3226 } 3227 3228 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3229 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3230 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3231 #if defined(TARGET_PPC64) 3232 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3233 #endif 3234 3235 #if defined(TARGET_PPC64) 3236 /* CI load/store variants */ 3237 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3238 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3239 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3240 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3241 #endif 3242 3243 /*** Integer store ***/ 3244 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3245 static void glue(gen_, name##x)(DisasContext *ctx) \ 3246 { \ 3247 TCGv EA; \ 3248 chk(ctx); \ 3249 gen_set_access_type(ctx, ACCESS_INT); \ 3250 EA = tcg_temp_new(); \ 3251 gen_addr_reg_index(ctx, EA); \ 3252 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3253 } 3254 #define GEN_STX(name, stop, opc2, opc3, type) \ 3255 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3256 3257 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3258 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3259 3260 #define GEN_STEPX(name, stop, opc2, opc3) \ 3261 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3262 { \ 3263 TCGv EA; \ 3264 CHK_SV(ctx); \ 3265 gen_set_access_type(ctx, ACCESS_INT); \ 3266 EA = tcg_temp_new(); \ 3267 gen_addr_reg_index(ctx, EA); \ 3268 tcg_gen_qemu_st_tl( \ 3269 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3270 } 3271 3272 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3273 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3274 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3275 #if defined(TARGET_PPC64) 3276 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3277 #endif 3278 3279 #if defined(TARGET_PPC64) 3280 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3281 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3282 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3283 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3284 #endif 3285 /*** Integer load and store with byte reverse ***/ 3286 3287 /* lhbrx */ 3288 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3289 3290 /* lwbrx */ 3291 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3292 3293 #if defined(TARGET_PPC64) 3294 /* ldbrx */ 3295 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3296 /* stdbrx */ 3297 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3298 #endif /* TARGET_PPC64 */ 3299 3300 /* sthbrx */ 3301 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3302 /* stwbrx */ 3303 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3304 3305 /*** Integer load and store multiple ***/ 3306 3307 /* lmw */ 3308 static void gen_lmw(DisasContext *ctx) 3309 { 3310 TCGv t0; 3311 TCGv_i32 t1; 3312 3313 if (ctx->le_mode) { 3314 gen_align_no_le(ctx); 3315 return; 3316 } 3317 gen_set_access_type(ctx, ACCESS_INT); 3318 t0 = tcg_temp_new(); 3319 t1 = tcg_constant_i32(rD(ctx->opcode)); 3320 gen_addr_imm_index(ctx, t0, 0); 3321 gen_helper_lmw(cpu_env, t0, t1); 3322 } 3323 3324 /* stmw */ 3325 static void gen_stmw(DisasContext *ctx) 3326 { 3327 TCGv t0; 3328 TCGv_i32 t1; 3329 3330 if (ctx->le_mode) { 3331 gen_align_no_le(ctx); 3332 return; 3333 } 3334 gen_set_access_type(ctx, ACCESS_INT); 3335 t0 = tcg_temp_new(); 3336 t1 = tcg_constant_i32(rS(ctx->opcode)); 3337 gen_addr_imm_index(ctx, t0, 0); 3338 gen_helper_stmw(cpu_env, t0, t1); 3339 } 3340 3341 /*** Integer load and store strings ***/ 3342 3343 /* lswi */ 3344 /* 3345 * PowerPC32 specification says we must generate an exception if rA is 3346 * in the range of registers to be loaded. In an other hand, IBM says 3347 * this is valid, but rA won't be loaded. For now, I'll follow the 3348 * spec... 3349 */ 3350 static void gen_lswi(DisasContext *ctx) 3351 { 3352 TCGv t0; 3353 TCGv_i32 t1, t2; 3354 int nb = NB(ctx->opcode); 3355 int start = rD(ctx->opcode); 3356 int ra = rA(ctx->opcode); 3357 int nr; 3358 3359 if (ctx->le_mode) { 3360 gen_align_no_le(ctx); 3361 return; 3362 } 3363 if (nb == 0) { 3364 nb = 32; 3365 } 3366 nr = DIV_ROUND_UP(nb, 4); 3367 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3368 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3369 return; 3370 } 3371 gen_set_access_type(ctx, ACCESS_INT); 3372 t0 = tcg_temp_new(); 3373 gen_addr_register(ctx, t0); 3374 t1 = tcg_constant_i32(nb); 3375 t2 = tcg_constant_i32(start); 3376 gen_helper_lsw(cpu_env, t0, t1, t2); 3377 } 3378 3379 /* lswx */ 3380 static void gen_lswx(DisasContext *ctx) 3381 { 3382 TCGv t0; 3383 TCGv_i32 t1, t2, t3; 3384 3385 if (ctx->le_mode) { 3386 gen_align_no_le(ctx); 3387 return; 3388 } 3389 gen_set_access_type(ctx, ACCESS_INT); 3390 t0 = tcg_temp_new(); 3391 gen_addr_reg_index(ctx, t0); 3392 t1 = tcg_constant_i32(rD(ctx->opcode)); 3393 t2 = tcg_constant_i32(rA(ctx->opcode)); 3394 t3 = tcg_constant_i32(rB(ctx->opcode)); 3395 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3396 } 3397 3398 /* stswi */ 3399 static void gen_stswi(DisasContext *ctx) 3400 { 3401 TCGv t0; 3402 TCGv_i32 t1, t2; 3403 int nb = NB(ctx->opcode); 3404 3405 if (ctx->le_mode) { 3406 gen_align_no_le(ctx); 3407 return; 3408 } 3409 gen_set_access_type(ctx, ACCESS_INT); 3410 t0 = tcg_temp_new(); 3411 gen_addr_register(ctx, t0); 3412 if (nb == 0) { 3413 nb = 32; 3414 } 3415 t1 = tcg_constant_i32(nb); 3416 t2 = tcg_constant_i32(rS(ctx->opcode)); 3417 gen_helper_stsw(cpu_env, t0, t1, t2); 3418 } 3419 3420 /* stswx */ 3421 static void gen_stswx(DisasContext *ctx) 3422 { 3423 TCGv t0; 3424 TCGv_i32 t1, t2; 3425 3426 if (ctx->le_mode) { 3427 gen_align_no_le(ctx); 3428 return; 3429 } 3430 gen_set_access_type(ctx, ACCESS_INT); 3431 t0 = tcg_temp_new(); 3432 gen_addr_reg_index(ctx, t0); 3433 t1 = tcg_temp_new_i32(); 3434 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3435 tcg_gen_andi_i32(t1, t1, 0x7F); 3436 t2 = tcg_constant_i32(rS(ctx->opcode)); 3437 gen_helper_stsw(cpu_env, t0, t1, t2); 3438 } 3439 3440 /*** Memory synchronisation ***/ 3441 /* eieio */ 3442 static void gen_eieio(DisasContext *ctx) 3443 { 3444 TCGBar bar = TCG_MO_ALL; 3445 3446 /* 3447 * eieio has complex semanitcs. It provides memory ordering between 3448 * operations in the set: 3449 * - loads from CI memory. 3450 * - stores to CI memory. 3451 * - stores to WT memory. 3452 * 3453 * It separately also orders memory for operations in the set: 3454 * - stores to cacheble memory. 3455 * 3456 * It also serializes instructions: 3457 * - dcbt and dcbst. 3458 * 3459 * It separately serializes: 3460 * - tlbie and tlbsync. 3461 * 3462 * And separately serializes: 3463 * - slbieg, slbiag, and slbsync. 3464 * 3465 * The end result is that CI memory ordering requires TCG_MO_ALL 3466 * and it is not possible to special-case more relaxed ordering for 3467 * cacheable accesses. TCG_BAR_SC is required to provide this 3468 * serialization. 3469 */ 3470 3471 /* 3472 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3473 * tell the CPU it is a store-forwarding barrier. 3474 */ 3475 if (ctx->opcode & 0x2000000) { 3476 /* 3477 * ISA says that "Reserved fields in instructions are ignored 3478 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3479 * as this is not an instruction software should be using, 3480 * complain to the user. 3481 */ 3482 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3483 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3484 TARGET_FMT_lx "\n", ctx->cia); 3485 } else { 3486 bar = TCG_MO_ST_LD; 3487 } 3488 } 3489 3490 tcg_gen_mb(bar | TCG_BAR_SC); 3491 } 3492 3493 #if !defined(CONFIG_USER_ONLY) 3494 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3495 { 3496 TCGv_i32 t; 3497 TCGLabel *l; 3498 3499 if (!ctx->lazy_tlb_flush) { 3500 return; 3501 } 3502 l = gen_new_label(); 3503 t = tcg_temp_new_i32(); 3504 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3505 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3506 if (global) { 3507 gen_helper_check_tlb_flush_global(cpu_env); 3508 } else { 3509 gen_helper_check_tlb_flush_local(cpu_env); 3510 } 3511 gen_set_label(l); 3512 } 3513 #else 3514 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3515 #endif 3516 3517 /* isync */ 3518 static void gen_isync(DisasContext *ctx) 3519 { 3520 /* 3521 * We need to check for a pending TLB flush. This can only happen in 3522 * kernel mode however so check MSR_PR 3523 */ 3524 if (!ctx->pr) { 3525 gen_check_tlb_flush(ctx, false); 3526 } 3527 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3528 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3529 } 3530 3531 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3532 3533 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3534 { 3535 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3536 TCGv t0 = tcg_temp_new(); 3537 3538 gen_set_access_type(ctx, ACCESS_RES); 3539 gen_addr_reg_index(ctx, t0); 3540 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3541 tcg_gen_mov_tl(cpu_reserve, t0); 3542 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3543 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3544 } 3545 3546 #define LARX(name, memop) \ 3547 static void gen_##name(DisasContext *ctx) \ 3548 { \ 3549 gen_load_locked(ctx, memop); \ 3550 } 3551 3552 /* lwarx */ 3553 LARX(lbarx, DEF_MEMOP(MO_UB)) 3554 LARX(lharx, DEF_MEMOP(MO_UW)) 3555 LARX(lwarx, DEF_MEMOP(MO_UL)) 3556 3557 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3558 TCGv EA, TCGCond cond, int addend) 3559 { 3560 TCGv t = tcg_temp_new(); 3561 TCGv t2 = tcg_temp_new(); 3562 TCGv u = tcg_temp_new(); 3563 3564 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3565 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3566 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3567 tcg_gen_addi_tl(u, t, addend); 3568 3569 /* E.g. for fetch and increment bounded... */ 3570 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3571 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3572 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3573 3574 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3575 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3576 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3577 } 3578 3579 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3580 { 3581 uint32_t gpr_FC = FC(ctx->opcode); 3582 TCGv EA = tcg_temp_new(); 3583 int rt = rD(ctx->opcode); 3584 bool need_serial; 3585 TCGv src, dst; 3586 3587 gen_addr_register(ctx, EA); 3588 dst = cpu_gpr[rt]; 3589 src = cpu_gpr[(rt + 1) & 31]; 3590 3591 need_serial = false; 3592 memop |= MO_ALIGN; 3593 switch (gpr_FC) { 3594 case 0: /* Fetch and add */ 3595 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3596 break; 3597 case 1: /* Fetch and xor */ 3598 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3599 break; 3600 case 2: /* Fetch and or */ 3601 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3602 break; 3603 case 3: /* Fetch and 'and' */ 3604 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3605 break; 3606 case 4: /* Fetch and max unsigned */ 3607 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3608 break; 3609 case 5: /* Fetch and max signed */ 3610 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3611 break; 3612 case 6: /* Fetch and min unsigned */ 3613 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3614 break; 3615 case 7: /* Fetch and min signed */ 3616 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3617 break; 3618 case 8: /* Swap */ 3619 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3620 break; 3621 3622 case 16: /* Compare and swap not equal */ 3623 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3624 need_serial = true; 3625 } else { 3626 TCGv t0 = tcg_temp_new(); 3627 TCGv t1 = tcg_temp_new(); 3628 3629 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3630 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3631 tcg_gen_mov_tl(t1, src); 3632 } else { 3633 tcg_gen_ext32u_tl(t1, src); 3634 } 3635 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3636 cpu_gpr[(rt + 2) & 31], t0); 3637 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3638 tcg_gen_mov_tl(dst, t0); 3639 } 3640 break; 3641 3642 case 24: /* Fetch and increment bounded */ 3643 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3644 need_serial = true; 3645 } else { 3646 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3647 } 3648 break; 3649 case 25: /* Fetch and increment equal */ 3650 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3651 need_serial = true; 3652 } else { 3653 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3654 } 3655 break; 3656 case 28: /* Fetch and decrement bounded */ 3657 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3658 need_serial = true; 3659 } else { 3660 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3661 } 3662 break; 3663 3664 default: 3665 /* invoke data storage error handler */ 3666 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3667 } 3668 3669 if (need_serial) { 3670 /* Restart with exclusive lock. */ 3671 gen_helper_exit_atomic(cpu_env); 3672 ctx->base.is_jmp = DISAS_NORETURN; 3673 } 3674 } 3675 3676 static void gen_lwat(DisasContext *ctx) 3677 { 3678 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3679 } 3680 3681 #ifdef TARGET_PPC64 3682 static void gen_ldat(DisasContext *ctx) 3683 { 3684 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3685 } 3686 #endif 3687 3688 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3689 { 3690 uint32_t gpr_FC = FC(ctx->opcode); 3691 TCGv EA = tcg_temp_new(); 3692 TCGv src, discard; 3693 3694 gen_addr_register(ctx, EA); 3695 src = cpu_gpr[rD(ctx->opcode)]; 3696 discard = tcg_temp_new(); 3697 3698 memop |= MO_ALIGN; 3699 switch (gpr_FC) { 3700 case 0: /* add and Store */ 3701 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3702 break; 3703 case 1: /* xor and Store */ 3704 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3705 break; 3706 case 2: /* Or and Store */ 3707 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3708 break; 3709 case 3: /* 'and' and Store */ 3710 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3711 break; 3712 case 4: /* Store max unsigned */ 3713 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3714 break; 3715 case 5: /* Store max signed */ 3716 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3717 break; 3718 case 6: /* Store min unsigned */ 3719 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3720 break; 3721 case 7: /* Store min signed */ 3722 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3723 break; 3724 case 24: /* Store twin */ 3725 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3726 /* Restart with exclusive lock. */ 3727 gen_helper_exit_atomic(cpu_env); 3728 ctx->base.is_jmp = DISAS_NORETURN; 3729 } else { 3730 TCGv t = tcg_temp_new(); 3731 TCGv t2 = tcg_temp_new(); 3732 TCGv s = tcg_temp_new(); 3733 TCGv s2 = tcg_temp_new(); 3734 TCGv ea_plus_s = tcg_temp_new(); 3735 3736 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3737 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3738 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3739 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3740 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3741 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3742 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3743 } 3744 break; 3745 default: 3746 /* invoke data storage error handler */ 3747 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3748 } 3749 } 3750 3751 static void gen_stwat(DisasContext *ctx) 3752 { 3753 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3754 } 3755 3756 #ifdef TARGET_PPC64 3757 static void gen_stdat(DisasContext *ctx) 3758 { 3759 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3760 } 3761 #endif 3762 3763 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3764 { 3765 TCGLabel *lfail; 3766 TCGv EA; 3767 TCGv cr0; 3768 TCGv t0; 3769 int rs = rS(ctx->opcode); 3770 3771 lfail = gen_new_label(); 3772 EA = tcg_temp_new(); 3773 cr0 = tcg_temp_new(); 3774 t0 = tcg_temp_new(); 3775 3776 tcg_gen_mov_tl(cr0, cpu_so); 3777 gen_set_access_type(ctx, ACCESS_RES); 3778 gen_addr_reg_index(ctx, EA); 3779 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3780 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3781 3782 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3783 cpu_gpr[rs], ctx->mem_idx, 3784 DEF_MEMOP(memop) | MO_ALIGN); 3785 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3786 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3787 tcg_gen_or_tl(cr0, cr0, t0); 3788 3789 gen_set_label(lfail); 3790 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3791 tcg_gen_movi_tl(cpu_reserve, -1); 3792 } 3793 3794 #define STCX(name, memop) \ 3795 static void gen_##name(DisasContext *ctx) \ 3796 { \ 3797 gen_conditional_store(ctx, memop); \ 3798 } 3799 3800 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3801 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3802 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3803 3804 #if defined(TARGET_PPC64) 3805 /* ldarx */ 3806 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3807 /* stdcx. */ 3808 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3809 3810 /* lqarx */ 3811 static void gen_lqarx(DisasContext *ctx) 3812 { 3813 int rd = rD(ctx->opcode); 3814 TCGv EA, hi, lo; 3815 TCGv_i128 t16; 3816 3817 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3818 (rd == rB(ctx->opcode)))) { 3819 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3820 return; 3821 } 3822 3823 gen_set_access_type(ctx, ACCESS_RES); 3824 EA = tcg_temp_new(); 3825 gen_addr_reg_index(ctx, EA); 3826 3827 /* Note that the low part is always in RD+1, even in LE mode. */ 3828 lo = cpu_gpr[rd + 1]; 3829 hi = cpu_gpr[rd]; 3830 3831 t16 = tcg_temp_new_i128(); 3832 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3833 tcg_gen_extr_i128_i64(lo, hi, t16); 3834 3835 tcg_gen_mov_tl(cpu_reserve, EA); 3836 tcg_gen_movi_tl(cpu_reserve_length, 16); 3837 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3838 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3839 } 3840 3841 /* stqcx. */ 3842 static void gen_stqcx_(DisasContext *ctx) 3843 { 3844 TCGLabel *lfail; 3845 TCGv EA, t0, t1; 3846 TCGv cr0; 3847 TCGv_i128 cmp, val; 3848 int rs = rS(ctx->opcode); 3849 3850 if (unlikely(rs & 1)) { 3851 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3852 return; 3853 } 3854 3855 lfail = gen_new_label(); 3856 EA = tcg_temp_new(); 3857 cr0 = tcg_temp_new(); 3858 3859 tcg_gen_mov_tl(cr0, cpu_so); 3860 gen_set_access_type(ctx, ACCESS_RES); 3861 gen_addr_reg_index(ctx, EA); 3862 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3863 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3864 3865 cmp = tcg_temp_new_i128(); 3866 val = tcg_temp_new_i128(); 3867 3868 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3869 3870 /* Note that the low part is always in RS+1, even in LE mode. */ 3871 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3872 3873 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3874 DEF_MEMOP(MO_128 | MO_ALIGN)); 3875 3876 t0 = tcg_temp_new(); 3877 t1 = tcg_temp_new(); 3878 tcg_gen_extr_i128_i64(t1, t0, val); 3879 3880 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3881 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3882 tcg_gen_or_tl(t0, t0, t1); 3883 3884 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3885 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3886 tcg_gen_or_tl(cr0, cr0, t0); 3887 3888 gen_set_label(lfail); 3889 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3890 tcg_gen_movi_tl(cpu_reserve, -1); 3891 } 3892 #endif /* defined(TARGET_PPC64) */ 3893 3894 /* sync */ 3895 static void gen_sync(DisasContext *ctx) 3896 { 3897 TCGBar bar = TCG_MO_ALL; 3898 uint32_t l = (ctx->opcode >> 21) & 3; 3899 3900 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3901 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3902 } 3903 3904 /* 3905 * We may need to check for a pending TLB flush. 3906 * 3907 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3908 * 3909 * Additionally, this can only happen in kernel mode however so 3910 * check MSR_PR as well. 3911 */ 3912 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3913 gen_check_tlb_flush(ctx, true); 3914 } 3915 3916 tcg_gen_mb(bar | TCG_BAR_SC); 3917 } 3918 3919 /* wait */ 3920 static void gen_wait(DisasContext *ctx) 3921 { 3922 uint32_t wc; 3923 3924 if (ctx->insns_flags & PPC_WAIT) { 3925 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3926 3927 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3928 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3929 wc = WC(ctx->opcode); 3930 } else { 3931 wc = 0; 3932 } 3933 3934 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3935 /* v3.0 defines a new 'wait' encoding. */ 3936 wc = WC(ctx->opcode); 3937 if (ctx->insns_flags2 & PPC2_ISA310) { 3938 uint32_t pl = PL(ctx->opcode); 3939 3940 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3941 if (wc == 3) { 3942 gen_invalid(ctx); 3943 return; 3944 } 3945 3946 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3947 if (pl > 0 && wc != 2) { 3948 gen_invalid(ctx); 3949 return; 3950 } 3951 3952 } else { /* ISA300 */ 3953 /* WC 1-3 are reserved */ 3954 if (wc > 0) { 3955 gen_invalid(ctx); 3956 return; 3957 } 3958 } 3959 3960 } else { 3961 warn_report("wait instruction decoded with wrong ISA flags."); 3962 gen_invalid(ctx); 3963 return; 3964 } 3965 3966 /* 3967 * wait without WC field or with WC=0 waits for an exception / interrupt 3968 * to occur. 3969 */ 3970 if (wc == 0) { 3971 TCGv_i32 t0 = tcg_constant_i32(1); 3972 tcg_gen_st_i32(t0, cpu_env, 3973 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3974 /* Stop translation, as the CPU is supposed to sleep from now */ 3975 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3976 } 3977 3978 /* 3979 * Other wait types must not just wait until an exception occurs because 3980 * ignoring their other wake-up conditions could cause a hang. 3981 * 3982 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3983 * no-ops. 3984 * 3985 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3986 * 3987 * wc=2 waits for an implementation-specific condition, such could be 3988 * always true, so it can be implemented as a no-op. 3989 * 3990 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3991 * 3992 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3993 * Reservation-loss may have implementation-specific conditions, so it 3994 * can be implemented as a no-op. 3995 * 3996 * wc=2 waits for an exception or an amount of time to pass. This 3997 * amount is implementation-specific so it can be implemented as a 3998 * no-op. 3999 * 4000 * ISA v3.1 allows for execution to resume "in the rare case of 4001 * an implementation-dependent event", so in any case software must 4002 * not depend on the architected resumption condition to become 4003 * true, so no-op implementations should be architecturally correct 4004 * (if suboptimal). 4005 */ 4006 } 4007 4008 #if defined(TARGET_PPC64) 4009 static void gen_doze(DisasContext *ctx) 4010 { 4011 #if defined(CONFIG_USER_ONLY) 4012 GEN_PRIV(ctx); 4013 #else 4014 TCGv_i32 t; 4015 4016 CHK_HV(ctx); 4017 translator_io_start(&ctx->base); 4018 t = tcg_constant_i32(PPC_PM_DOZE); 4019 gen_helper_pminsn(cpu_env, t); 4020 /* Stop translation, as the CPU is supposed to sleep from now */ 4021 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4022 #endif /* defined(CONFIG_USER_ONLY) */ 4023 } 4024 4025 static void gen_nap(DisasContext *ctx) 4026 { 4027 #if defined(CONFIG_USER_ONLY) 4028 GEN_PRIV(ctx); 4029 #else 4030 TCGv_i32 t; 4031 4032 CHK_HV(ctx); 4033 translator_io_start(&ctx->base); 4034 t = tcg_constant_i32(PPC_PM_NAP); 4035 gen_helper_pminsn(cpu_env, t); 4036 /* Stop translation, as the CPU is supposed to sleep from now */ 4037 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4038 #endif /* defined(CONFIG_USER_ONLY) */ 4039 } 4040 4041 static void gen_stop(DisasContext *ctx) 4042 { 4043 #if defined(CONFIG_USER_ONLY) 4044 GEN_PRIV(ctx); 4045 #else 4046 TCGv_i32 t; 4047 4048 CHK_HV(ctx); 4049 translator_io_start(&ctx->base); 4050 t = tcg_constant_i32(PPC_PM_STOP); 4051 gen_helper_pminsn(cpu_env, t); 4052 /* Stop translation, as the CPU is supposed to sleep from now */ 4053 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4054 #endif /* defined(CONFIG_USER_ONLY) */ 4055 } 4056 4057 static void gen_sleep(DisasContext *ctx) 4058 { 4059 #if defined(CONFIG_USER_ONLY) 4060 GEN_PRIV(ctx); 4061 #else 4062 TCGv_i32 t; 4063 4064 CHK_HV(ctx); 4065 translator_io_start(&ctx->base); 4066 t = tcg_constant_i32(PPC_PM_SLEEP); 4067 gen_helper_pminsn(cpu_env, t); 4068 /* Stop translation, as the CPU is supposed to sleep from now */ 4069 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4070 #endif /* defined(CONFIG_USER_ONLY) */ 4071 } 4072 4073 static void gen_rvwinkle(DisasContext *ctx) 4074 { 4075 #if defined(CONFIG_USER_ONLY) 4076 GEN_PRIV(ctx); 4077 #else 4078 TCGv_i32 t; 4079 4080 CHK_HV(ctx); 4081 translator_io_start(&ctx->base); 4082 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4083 gen_helper_pminsn(cpu_env, t); 4084 /* Stop translation, as the CPU is supposed to sleep from now */ 4085 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4086 #endif /* defined(CONFIG_USER_ONLY) */ 4087 } 4088 #endif /* #if defined(TARGET_PPC64) */ 4089 4090 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4091 { 4092 #if defined(TARGET_PPC64) 4093 if (ctx->has_cfar) { 4094 tcg_gen_movi_tl(cpu_cfar, nip); 4095 } 4096 #endif 4097 } 4098 4099 #if defined(TARGET_PPC64) 4100 static void pmu_count_insns(DisasContext *ctx) 4101 { 4102 /* 4103 * Do not bother calling the helper if the PMU isn't counting 4104 * instructions. 4105 */ 4106 if (!ctx->pmu_insn_cnt) { 4107 return; 4108 } 4109 4110 #if !defined(CONFIG_USER_ONLY) 4111 TCGLabel *l; 4112 TCGv t0; 4113 4114 /* 4115 * The PMU insns_inc() helper stops the internal PMU timer if a 4116 * counter overflows happens. In that case, if the guest is 4117 * running with icount and we do not handle it beforehand, 4118 * the helper can trigger a 'bad icount read'. 4119 */ 4120 translator_io_start(&ctx->base); 4121 4122 /* Avoid helper calls when only PMC5-6 are enabled. */ 4123 if (!ctx->pmc_other) { 4124 l = gen_new_label(); 4125 t0 = tcg_temp_new(); 4126 4127 gen_load_spr(t0, SPR_POWER_PMC5); 4128 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4129 gen_store_spr(SPR_POWER_PMC5, t0); 4130 /* Check for overflow, if it's enabled */ 4131 if (ctx->mmcr0_pmcjce) { 4132 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4133 gen_helper_handle_pmc5_overflow(cpu_env); 4134 } 4135 4136 gen_set_label(l); 4137 } else { 4138 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4139 } 4140 #else 4141 /* 4142 * User mode can read (but not write) PMC5 and start/stop 4143 * the PMU via MMCR0_FC. In this case just increment 4144 * PMC5 with base.num_insns. 4145 */ 4146 TCGv t0 = tcg_temp_new(); 4147 4148 gen_load_spr(t0, SPR_POWER_PMC5); 4149 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4150 gen_store_spr(SPR_POWER_PMC5, t0); 4151 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4152 } 4153 #else 4154 static void pmu_count_insns(DisasContext *ctx) 4155 { 4156 return; 4157 } 4158 #endif /* #if defined(TARGET_PPC64) */ 4159 4160 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4161 { 4162 return translator_use_goto_tb(&ctx->base, dest); 4163 } 4164 4165 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4166 { 4167 if (unlikely(ctx->singlestep_enabled)) { 4168 gen_debug_exception(ctx); 4169 } else { 4170 /* 4171 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4172 * CF_NO_GOTO_PTR is set. Count insns now. 4173 */ 4174 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4175 pmu_count_insns(ctx); 4176 } 4177 4178 tcg_gen_lookup_and_goto_ptr(); 4179 } 4180 } 4181 4182 /*** Branch ***/ 4183 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4184 { 4185 if (NARROW_MODE(ctx)) { 4186 dest = (uint32_t) dest; 4187 } 4188 if (use_goto_tb(ctx, dest)) { 4189 pmu_count_insns(ctx); 4190 tcg_gen_goto_tb(n); 4191 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4192 tcg_gen_exit_tb(ctx->base.tb, n); 4193 } else { 4194 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4195 gen_lookup_and_goto_ptr(ctx); 4196 } 4197 } 4198 4199 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4200 { 4201 if (NARROW_MODE(ctx)) { 4202 nip = (uint32_t)nip; 4203 } 4204 tcg_gen_movi_tl(cpu_lr, nip); 4205 } 4206 4207 /* b ba bl bla */ 4208 static void gen_b(DisasContext *ctx) 4209 { 4210 target_ulong li, target; 4211 4212 /* sign extend LI */ 4213 li = LI(ctx->opcode); 4214 li = (li ^ 0x02000000) - 0x02000000; 4215 if (likely(AA(ctx->opcode) == 0)) { 4216 target = ctx->cia + li; 4217 } else { 4218 target = li; 4219 } 4220 if (LK(ctx->opcode)) { 4221 gen_setlr(ctx, ctx->base.pc_next); 4222 } 4223 gen_update_cfar(ctx, ctx->cia); 4224 gen_goto_tb(ctx, 0, target); 4225 ctx->base.is_jmp = DISAS_NORETURN; 4226 } 4227 4228 #define BCOND_IM 0 4229 #define BCOND_LR 1 4230 #define BCOND_CTR 2 4231 #define BCOND_TAR 3 4232 4233 static void gen_bcond(DisasContext *ctx, int type) 4234 { 4235 uint32_t bo = BO(ctx->opcode); 4236 TCGLabel *l1; 4237 TCGv target; 4238 4239 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4240 target = tcg_temp_new(); 4241 if (type == BCOND_CTR) { 4242 tcg_gen_mov_tl(target, cpu_ctr); 4243 } else if (type == BCOND_TAR) { 4244 gen_load_spr(target, SPR_TAR); 4245 } else { 4246 tcg_gen_mov_tl(target, cpu_lr); 4247 } 4248 } else { 4249 target = NULL; 4250 } 4251 if (LK(ctx->opcode)) { 4252 gen_setlr(ctx, ctx->base.pc_next); 4253 } 4254 l1 = gen_new_label(); 4255 if ((bo & 0x4) == 0) { 4256 /* Decrement and test CTR */ 4257 TCGv temp = tcg_temp_new(); 4258 4259 if (type == BCOND_CTR) { 4260 /* 4261 * All ISAs up to v3 describe this form of bcctr as invalid but 4262 * some processors, ie. 64-bit server processors compliant with 4263 * arch 2.x, do implement a "test and decrement" logic instead, 4264 * as described in their respective UMs. This logic involves CTR 4265 * to act as both the branch target and a counter, which makes 4266 * it basically useless and thus never used in real code. 4267 * 4268 * This form was hence chosen to trigger extra micro-architectural 4269 * side-effect on real HW needed for the Spectre v2 workaround. 4270 * It is up to guests that implement such workaround, ie. linux, to 4271 * use this form in a way it just triggers the side-effect without 4272 * doing anything else harmful. 4273 */ 4274 if (unlikely(!is_book3s_arch2x(ctx))) { 4275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4276 return; 4277 } 4278 4279 if (NARROW_MODE(ctx)) { 4280 tcg_gen_ext32u_tl(temp, cpu_ctr); 4281 } else { 4282 tcg_gen_mov_tl(temp, cpu_ctr); 4283 } 4284 if (bo & 0x2) { 4285 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4286 } else { 4287 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4288 } 4289 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4290 } else { 4291 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4292 if (NARROW_MODE(ctx)) { 4293 tcg_gen_ext32u_tl(temp, cpu_ctr); 4294 } else { 4295 tcg_gen_mov_tl(temp, cpu_ctr); 4296 } 4297 if (bo & 0x2) { 4298 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4299 } else { 4300 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4301 } 4302 } 4303 } 4304 if ((bo & 0x10) == 0) { 4305 /* Test CR */ 4306 uint32_t bi = BI(ctx->opcode); 4307 uint32_t mask = 0x08 >> (bi & 0x03); 4308 TCGv_i32 temp = tcg_temp_new_i32(); 4309 4310 if (bo & 0x8) { 4311 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4312 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4313 } else { 4314 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4315 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4316 } 4317 } 4318 gen_update_cfar(ctx, ctx->cia); 4319 if (type == BCOND_IM) { 4320 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4321 if (likely(AA(ctx->opcode) == 0)) { 4322 gen_goto_tb(ctx, 0, ctx->cia + li); 4323 } else { 4324 gen_goto_tb(ctx, 0, li); 4325 } 4326 } else { 4327 if (NARROW_MODE(ctx)) { 4328 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4329 } else { 4330 tcg_gen_andi_tl(cpu_nip, target, ~3); 4331 } 4332 gen_lookup_and_goto_ptr(ctx); 4333 } 4334 if ((bo & 0x14) != 0x14) { 4335 /* fallthrough case */ 4336 gen_set_label(l1); 4337 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4338 } 4339 ctx->base.is_jmp = DISAS_NORETURN; 4340 } 4341 4342 static void gen_bc(DisasContext *ctx) 4343 { 4344 gen_bcond(ctx, BCOND_IM); 4345 } 4346 4347 static void gen_bcctr(DisasContext *ctx) 4348 { 4349 gen_bcond(ctx, BCOND_CTR); 4350 } 4351 4352 static void gen_bclr(DisasContext *ctx) 4353 { 4354 gen_bcond(ctx, BCOND_LR); 4355 } 4356 4357 static void gen_bctar(DisasContext *ctx) 4358 { 4359 gen_bcond(ctx, BCOND_TAR); 4360 } 4361 4362 /*** Condition register logical ***/ 4363 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4364 static void glue(gen_, name)(DisasContext *ctx) \ 4365 { \ 4366 uint8_t bitmask; \ 4367 int sh; \ 4368 TCGv_i32 t0, t1; \ 4369 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4370 t0 = tcg_temp_new_i32(); \ 4371 if (sh > 0) \ 4372 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4373 else if (sh < 0) \ 4374 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4375 else \ 4376 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4377 t1 = tcg_temp_new_i32(); \ 4378 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4379 if (sh > 0) \ 4380 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4381 else if (sh < 0) \ 4382 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4383 else \ 4384 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4385 tcg_op(t0, t0, t1); \ 4386 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4387 tcg_gen_andi_i32(t0, t0, bitmask); \ 4388 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4389 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4390 } 4391 4392 /* crand */ 4393 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4394 /* crandc */ 4395 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4396 /* creqv */ 4397 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4398 /* crnand */ 4399 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4400 /* crnor */ 4401 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4402 /* cror */ 4403 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4404 /* crorc */ 4405 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4406 /* crxor */ 4407 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4408 4409 /* mcrf */ 4410 static void gen_mcrf(DisasContext *ctx) 4411 { 4412 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4413 } 4414 4415 /*** System linkage ***/ 4416 4417 /* rfi (supervisor only) */ 4418 static void gen_rfi(DisasContext *ctx) 4419 { 4420 #if defined(CONFIG_USER_ONLY) 4421 GEN_PRIV(ctx); 4422 #else 4423 /* 4424 * This instruction doesn't exist anymore on 64-bit server 4425 * processors compliant with arch 2.x 4426 */ 4427 if (is_book3s_arch2x(ctx)) { 4428 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4429 return; 4430 } 4431 /* Restore CPU state */ 4432 CHK_SV(ctx); 4433 translator_io_start(&ctx->base); 4434 gen_update_cfar(ctx, ctx->cia); 4435 gen_helper_rfi(cpu_env); 4436 ctx->base.is_jmp = DISAS_EXIT; 4437 #endif 4438 } 4439 4440 #if defined(TARGET_PPC64) 4441 static void gen_rfid(DisasContext *ctx) 4442 { 4443 #if defined(CONFIG_USER_ONLY) 4444 GEN_PRIV(ctx); 4445 #else 4446 /* Restore CPU state */ 4447 CHK_SV(ctx); 4448 translator_io_start(&ctx->base); 4449 gen_update_cfar(ctx, ctx->cia); 4450 gen_helper_rfid(cpu_env); 4451 ctx->base.is_jmp = DISAS_EXIT; 4452 #endif 4453 } 4454 4455 #if !defined(CONFIG_USER_ONLY) 4456 static void gen_rfscv(DisasContext *ctx) 4457 { 4458 #if defined(CONFIG_USER_ONLY) 4459 GEN_PRIV(ctx); 4460 #else 4461 /* Restore CPU state */ 4462 CHK_SV(ctx); 4463 translator_io_start(&ctx->base); 4464 gen_update_cfar(ctx, ctx->cia); 4465 gen_helper_rfscv(cpu_env); 4466 ctx->base.is_jmp = DISAS_EXIT; 4467 #endif 4468 } 4469 #endif 4470 4471 static void gen_hrfid(DisasContext *ctx) 4472 { 4473 #if defined(CONFIG_USER_ONLY) 4474 GEN_PRIV(ctx); 4475 #else 4476 /* Restore CPU state */ 4477 CHK_HV(ctx); 4478 translator_io_start(&ctx->base); 4479 gen_helper_hrfid(cpu_env); 4480 ctx->base.is_jmp = DISAS_EXIT; 4481 #endif 4482 } 4483 #endif 4484 4485 /* sc */ 4486 #if defined(CONFIG_USER_ONLY) 4487 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4488 #else 4489 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4490 #endif 4491 static void gen_sc(DisasContext *ctx) 4492 { 4493 uint32_t lev; 4494 4495 /* 4496 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4497 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4498 * for Ultravisor which TCG does not support, so just ignore the top 6. 4499 */ 4500 lev = (ctx->opcode >> 5) & 0x1; 4501 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4502 } 4503 4504 #if defined(TARGET_PPC64) 4505 #if !defined(CONFIG_USER_ONLY) 4506 static void gen_scv(DisasContext *ctx) 4507 { 4508 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4509 4510 /* Set the PC back to the faulting instruction. */ 4511 gen_update_nip(ctx, ctx->cia); 4512 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4513 4514 ctx->base.is_jmp = DISAS_NORETURN; 4515 } 4516 #endif 4517 #endif 4518 4519 /*** Trap ***/ 4520 4521 /* Check for unconditional traps (always or never) */ 4522 static bool check_unconditional_trap(DisasContext *ctx) 4523 { 4524 /* Trap never */ 4525 if (TO(ctx->opcode) == 0) { 4526 return true; 4527 } 4528 /* Trap always */ 4529 if (TO(ctx->opcode) == 31) { 4530 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4531 return true; 4532 } 4533 return false; 4534 } 4535 4536 /* tw */ 4537 static void gen_tw(DisasContext *ctx) 4538 { 4539 TCGv_i32 t0; 4540 4541 if (check_unconditional_trap(ctx)) { 4542 return; 4543 } 4544 t0 = tcg_constant_i32(TO(ctx->opcode)); 4545 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4546 t0); 4547 } 4548 4549 /* twi */ 4550 static void gen_twi(DisasContext *ctx) 4551 { 4552 TCGv t0; 4553 TCGv_i32 t1; 4554 4555 if (check_unconditional_trap(ctx)) { 4556 return; 4557 } 4558 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4559 t1 = tcg_constant_i32(TO(ctx->opcode)); 4560 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4561 } 4562 4563 #if defined(TARGET_PPC64) 4564 /* td */ 4565 static void gen_td(DisasContext *ctx) 4566 { 4567 TCGv_i32 t0; 4568 4569 if (check_unconditional_trap(ctx)) { 4570 return; 4571 } 4572 t0 = tcg_constant_i32(TO(ctx->opcode)); 4573 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4574 t0); 4575 } 4576 4577 /* tdi */ 4578 static void gen_tdi(DisasContext *ctx) 4579 { 4580 TCGv t0; 4581 TCGv_i32 t1; 4582 4583 if (check_unconditional_trap(ctx)) { 4584 return; 4585 } 4586 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4587 t1 = tcg_constant_i32(TO(ctx->opcode)); 4588 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4589 } 4590 #endif 4591 4592 /*** Processor control ***/ 4593 4594 /* mcrxr */ 4595 static void gen_mcrxr(DisasContext *ctx) 4596 { 4597 TCGv_i32 t0 = tcg_temp_new_i32(); 4598 TCGv_i32 t1 = tcg_temp_new_i32(); 4599 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4600 4601 tcg_gen_trunc_tl_i32(t0, cpu_so); 4602 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4603 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4604 tcg_gen_shli_i32(t0, t0, 3); 4605 tcg_gen_shli_i32(t1, t1, 2); 4606 tcg_gen_shli_i32(dst, dst, 1); 4607 tcg_gen_or_i32(dst, dst, t0); 4608 tcg_gen_or_i32(dst, dst, t1); 4609 4610 tcg_gen_movi_tl(cpu_so, 0); 4611 tcg_gen_movi_tl(cpu_ov, 0); 4612 tcg_gen_movi_tl(cpu_ca, 0); 4613 } 4614 4615 #ifdef TARGET_PPC64 4616 /* mcrxrx */ 4617 static void gen_mcrxrx(DisasContext *ctx) 4618 { 4619 TCGv t0 = tcg_temp_new(); 4620 TCGv t1 = tcg_temp_new(); 4621 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4622 4623 /* copy OV and OV32 */ 4624 tcg_gen_shli_tl(t0, cpu_ov, 1); 4625 tcg_gen_or_tl(t0, t0, cpu_ov32); 4626 tcg_gen_shli_tl(t0, t0, 2); 4627 /* copy CA and CA32 */ 4628 tcg_gen_shli_tl(t1, cpu_ca, 1); 4629 tcg_gen_or_tl(t1, t1, cpu_ca32); 4630 tcg_gen_or_tl(t0, t0, t1); 4631 tcg_gen_trunc_tl_i32(dst, t0); 4632 } 4633 #endif 4634 4635 /* mfcr mfocrf */ 4636 static void gen_mfcr(DisasContext *ctx) 4637 { 4638 uint32_t crm, crn; 4639 4640 if (likely(ctx->opcode & 0x00100000)) { 4641 crm = CRM(ctx->opcode); 4642 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4643 crn = ctz32(crm); 4644 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4645 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4646 cpu_gpr[rD(ctx->opcode)], crn * 4); 4647 } 4648 } else { 4649 TCGv_i32 t0 = tcg_temp_new_i32(); 4650 tcg_gen_mov_i32(t0, cpu_crf[0]); 4651 tcg_gen_shli_i32(t0, t0, 4); 4652 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4653 tcg_gen_shli_i32(t0, t0, 4); 4654 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4655 tcg_gen_shli_i32(t0, t0, 4); 4656 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4657 tcg_gen_shli_i32(t0, t0, 4); 4658 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4659 tcg_gen_shli_i32(t0, t0, 4); 4660 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4661 tcg_gen_shli_i32(t0, t0, 4); 4662 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4663 tcg_gen_shli_i32(t0, t0, 4); 4664 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4665 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4666 } 4667 } 4668 4669 /* mfmsr */ 4670 static void gen_mfmsr(DisasContext *ctx) 4671 { 4672 CHK_SV(ctx); 4673 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4674 } 4675 4676 /* mfspr */ 4677 static inline void gen_op_mfspr(DisasContext *ctx) 4678 { 4679 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4680 uint32_t sprn = SPR(ctx->opcode); 4681 4682 #if defined(CONFIG_USER_ONLY) 4683 read_cb = ctx->spr_cb[sprn].uea_read; 4684 #else 4685 if (ctx->pr) { 4686 read_cb = ctx->spr_cb[sprn].uea_read; 4687 } else if (ctx->hv) { 4688 read_cb = ctx->spr_cb[sprn].hea_read; 4689 } else { 4690 read_cb = ctx->spr_cb[sprn].oea_read; 4691 } 4692 #endif 4693 if (likely(read_cb != NULL)) { 4694 if (likely(read_cb != SPR_NOACCESS)) { 4695 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4696 } else { 4697 /* Privilege exception */ 4698 /* 4699 * This is a hack to avoid warnings when running Linux: 4700 * this OS breaks the PowerPC virtualisation model, 4701 * allowing userland application to read the PVR 4702 */ 4703 if (sprn != SPR_PVR) { 4704 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4705 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4706 ctx->cia); 4707 } 4708 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4709 } 4710 } else { 4711 /* ISA 2.07 defines these as no-ops */ 4712 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4713 (sprn >= 808 && sprn <= 811)) { 4714 /* This is a nop */ 4715 return; 4716 } 4717 /* Not defined */ 4718 qemu_log_mask(LOG_GUEST_ERROR, 4719 "Trying to read invalid spr %d (0x%03x) at " 4720 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4721 4722 /* 4723 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4724 * generate a priv, a hv emu or a no-op 4725 */ 4726 if (sprn & 0x10) { 4727 if (ctx->pr) { 4728 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4729 } 4730 } else { 4731 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4732 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4733 } 4734 } 4735 } 4736 } 4737 4738 static void gen_mfspr(DisasContext *ctx) 4739 { 4740 gen_op_mfspr(ctx); 4741 } 4742 4743 /* mftb */ 4744 static void gen_mftb(DisasContext *ctx) 4745 { 4746 gen_op_mfspr(ctx); 4747 } 4748 4749 /* mtcrf mtocrf*/ 4750 static void gen_mtcrf(DisasContext *ctx) 4751 { 4752 uint32_t crm, crn; 4753 4754 crm = CRM(ctx->opcode); 4755 if (likely((ctx->opcode & 0x00100000))) { 4756 if (crm && ((crm & (crm - 1)) == 0)) { 4757 TCGv_i32 temp = tcg_temp_new_i32(); 4758 crn = ctz32(crm); 4759 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4760 tcg_gen_shri_i32(temp, temp, crn * 4); 4761 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4762 } 4763 } else { 4764 TCGv_i32 temp = tcg_temp_new_i32(); 4765 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4766 for (crn = 0 ; crn < 8 ; crn++) { 4767 if (crm & (1 << crn)) { 4768 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4769 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4770 } 4771 } 4772 } 4773 } 4774 4775 /* mtmsr */ 4776 #if defined(TARGET_PPC64) 4777 static void gen_mtmsrd(DisasContext *ctx) 4778 { 4779 if (unlikely(!is_book3s_arch2x(ctx))) { 4780 gen_invalid(ctx); 4781 return; 4782 } 4783 4784 CHK_SV(ctx); 4785 4786 #if !defined(CONFIG_USER_ONLY) 4787 TCGv t0, t1; 4788 target_ulong mask; 4789 4790 t0 = tcg_temp_new(); 4791 t1 = tcg_temp_new(); 4792 4793 translator_io_start(&ctx->base); 4794 4795 if (ctx->opcode & 0x00010000) { 4796 /* L=1 form only updates EE and RI */ 4797 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4798 } else { 4799 /* mtmsrd does not alter HV, S, ME, or LE */ 4800 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4801 (1ULL << MSR_HV)); 4802 /* 4803 * XXX: we need to update nip before the store if we enter 4804 * power saving mode, we will exit the loop directly from 4805 * ppc_store_msr 4806 */ 4807 gen_update_nip(ctx, ctx->base.pc_next); 4808 } 4809 4810 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4811 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4812 tcg_gen_or_tl(t0, t0, t1); 4813 4814 gen_helper_store_msr(cpu_env, t0); 4815 4816 /* Must stop the translation as machine state (may have) changed */ 4817 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4818 #endif /* !defined(CONFIG_USER_ONLY) */ 4819 } 4820 #endif /* defined(TARGET_PPC64) */ 4821 4822 static void gen_mtmsr(DisasContext *ctx) 4823 { 4824 CHK_SV(ctx); 4825 4826 #if !defined(CONFIG_USER_ONLY) 4827 TCGv t0, t1; 4828 target_ulong mask = 0xFFFFFFFF; 4829 4830 t0 = tcg_temp_new(); 4831 t1 = tcg_temp_new(); 4832 4833 translator_io_start(&ctx->base); 4834 if (ctx->opcode & 0x00010000) { 4835 /* L=1 form only updates EE and RI */ 4836 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4837 } else { 4838 /* mtmsr does not alter S, ME, or LE */ 4839 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4840 4841 /* 4842 * XXX: we need to update nip before the store if we enter 4843 * power saving mode, we will exit the loop directly from 4844 * ppc_store_msr 4845 */ 4846 gen_update_nip(ctx, ctx->base.pc_next); 4847 } 4848 4849 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4850 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4851 tcg_gen_or_tl(t0, t0, t1); 4852 4853 gen_helper_store_msr(cpu_env, t0); 4854 4855 /* Must stop the translation as machine state (may have) changed */ 4856 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4857 #endif 4858 } 4859 4860 /* mtspr */ 4861 static void gen_mtspr(DisasContext *ctx) 4862 { 4863 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4864 uint32_t sprn = SPR(ctx->opcode); 4865 4866 #if defined(CONFIG_USER_ONLY) 4867 write_cb = ctx->spr_cb[sprn].uea_write; 4868 #else 4869 if (ctx->pr) { 4870 write_cb = ctx->spr_cb[sprn].uea_write; 4871 } else if (ctx->hv) { 4872 write_cb = ctx->spr_cb[sprn].hea_write; 4873 } else { 4874 write_cb = ctx->spr_cb[sprn].oea_write; 4875 } 4876 #endif 4877 if (likely(write_cb != NULL)) { 4878 if (likely(write_cb != SPR_NOACCESS)) { 4879 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4880 } else { 4881 /* Privilege exception */ 4882 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4883 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4884 ctx->cia); 4885 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4886 } 4887 } else { 4888 /* ISA 2.07 defines these as no-ops */ 4889 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4890 (sprn >= 808 && sprn <= 811)) { 4891 /* This is a nop */ 4892 return; 4893 } 4894 4895 /* Not defined */ 4896 qemu_log_mask(LOG_GUEST_ERROR, 4897 "Trying to write invalid spr %d (0x%03x) at " 4898 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4899 4900 4901 /* 4902 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4903 * generate a priv, a hv emu or a no-op 4904 */ 4905 if (sprn & 0x10) { 4906 if (ctx->pr) { 4907 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4908 } 4909 } else { 4910 if (ctx->pr || sprn == 0) { 4911 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4912 } 4913 } 4914 } 4915 } 4916 4917 #if defined(TARGET_PPC64) 4918 /* setb */ 4919 static void gen_setb(DisasContext *ctx) 4920 { 4921 TCGv_i32 t0 = tcg_temp_new_i32(); 4922 TCGv_i32 t8 = tcg_constant_i32(8); 4923 TCGv_i32 tm1 = tcg_constant_i32(-1); 4924 int crf = crfS(ctx->opcode); 4925 4926 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4927 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4928 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4929 } 4930 #endif 4931 4932 /*** Cache management ***/ 4933 4934 /* dcbf */ 4935 static void gen_dcbf(DisasContext *ctx) 4936 { 4937 /* XXX: specification says this is treated as a load by the MMU */ 4938 TCGv t0; 4939 gen_set_access_type(ctx, ACCESS_CACHE); 4940 t0 = tcg_temp_new(); 4941 gen_addr_reg_index(ctx, t0); 4942 gen_qemu_ld8u(ctx, t0, t0); 4943 } 4944 4945 /* dcbfep (external PID dcbf) */ 4946 static void gen_dcbfep(DisasContext *ctx) 4947 { 4948 /* XXX: specification says this is treated as a load by the MMU */ 4949 TCGv t0; 4950 CHK_SV(ctx); 4951 gen_set_access_type(ctx, ACCESS_CACHE); 4952 t0 = tcg_temp_new(); 4953 gen_addr_reg_index(ctx, t0); 4954 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4955 } 4956 4957 /* dcbi (Supervisor only) */ 4958 static void gen_dcbi(DisasContext *ctx) 4959 { 4960 #if defined(CONFIG_USER_ONLY) 4961 GEN_PRIV(ctx); 4962 #else 4963 TCGv EA, val; 4964 4965 CHK_SV(ctx); 4966 EA = tcg_temp_new(); 4967 gen_set_access_type(ctx, ACCESS_CACHE); 4968 gen_addr_reg_index(ctx, EA); 4969 val = tcg_temp_new(); 4970 /* XXX: specification says this should be treated as a store by the MMU */ 4971 gen_qemu_ld8u(ctx, val, EA); 4972 gen_qemu_st8(ctx, val, EA); 4973 #endif /* defined(CONFIG_USER_ONLY) */ 4974 } 4975 4976 /* dcdst */ 4977 static void gen_dcbst(DisasContext *ctx) 4978 { 4979 /* XXX: specification say this is treated as a load by the MMU */ 4980 TCGv t0; 4981 gen_set_access_type(ctx, ACCESS_CACHE); 4982 t0 = tcg_temp_new(); 4983 gen_addr_reg_index(ctx, t0); 4984 gen_qemu_ld8u(ctx, t0, t0); 4985 } 4986 4987 /* dcbstep (dcbstep External PID version) */ 4988 static void gen_dcbstep(DisasContext *ctx) 4989 { 4990 /* XXX: specification say this is treated as a load by the MMU */ 4991 TCGv t0; 4992 gen_set_access_type(ctx, ACCESS_CACHE); 4993 t0 = tcg_temp_new(); 4994 gen_addr_reg_index(ctx, t0); 4995 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4996 } 4997 4998 /* dcbt */ 4999 static void gen_dcbt(DisasContext *ctx) 5000 { 5001 /* 5002 * interpreted as no-op 5003 * XXX: specification say this is treated as a load by the MMU but 5004 * does not generate any exception 5005 */ 5006 } 5007 5008 /* dcbtep */ 5009 static void gen_dcbtep(DisasContext *ctx) 5010 { 5011 /* 5012 * interpreted as no-op 5013 * XXX: specification say this is treated as a load by the MMU but 5014 * does not generate any exception 5015 */ 5016 } 5017 5018 /* dcbtst */ 5019 static void gen_dcbtst(DisasContext *ctx) 5020 { 5021 /* 5022 * interpreted as no-op 5023 * XXX: specification say this is treated as a load by the MMU but 5024 * does not generate any exception 5025 */ 5026 } 5027 5028 /* dcbtstep */ 5029 static void gen_dcbtstep(DisasContext *ctx) 5030 { 5031 /* 5032 * interpreted as no-op 5033 * XXX: specification say this is treated as a load by the MMU but 5034 * does not generate any exception 5035 */ 5036 } 5037 5038 /* dcbtls */ 5039 static void gen_dcbtls(DisasContext *ctx) 5040 { 5041 /* Always fails locking the cache */ 5042 TCGv t0 = tcg_temp_new(); 5043 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5044 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5045 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5046 } 5047 5048 /* dcblc */ 5049 static void gen_dcblc(DisasContext *ctx) 5050 { 5051 /* 5052 * interpreted as no-op 5053 */ 5054 } 5055 5056 /* dcbz */ 5057 static void gen_dcbz(DisasContext *ctx) 5058 { 5059 TCGv tcgv_addr; 5060 TCGv_i32 tcgv_op; 5061 5062 gen_set_access_type(ctx, ACCESS_CACHE); 5063 tcgv_addr = tcg_temp_new(); 5064 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5065 gen_addr_reg_index(ctx, tcgv_addr); 5066 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5067 } 5068 5069 /* dcbzep */ 5070 static void gen_dcbzep(DisasContext *ctx) 5071 { 5072 TCGv tcgv_addr; 5073 TCGv_i32 tcgv_op; 5074 5075 gen_set_access_type(ctx, ACCESS_CACHE); 5076 tcgv_addr = tcg_temp_new(); 5077 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5078 gen_addr_reg_index(ctx, tcgv_addr); 5079 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5080 } 5081 5082 /* dst / dstt */ 5083 static void gen_dst(DisasContext *ctx) 5084 { 5085 if (rA(ctx->opcode) == 0) { 5086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5087 } else { 5088 /* interpreted as no-op */ 5089 } 5090 } 5091 5092 /* dstst /dststt */ 5093 static void gen_dstst(DisasContext *ctx) 5094 { 5095 if (rA(ctx->opcode) == 0) { 5096 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5097 } else { 5098 /* interpreted as no-op */ 5099 } 5100 5101 } 5102 5103 /* dss / dssall */ 5104 static void gen_dss(DisasContext *ctx) 5105 { 5106 /* interpreted as no-op */ 5107 } 5108 5109 /* icbi */ 5110 static void gen_icbi(DisasContext *ctx) 5111 { 5112 TCGv t0; 5113 gen_set_access_type(ctx, ACCESS_CACHE); 5114 t0 = tcg_temp_new(); 5115 gen_addr_reg_index(ctx, t0); 5116 gen_helper_icbi(cpu_env, t0); 5117 } 5118 5119 /* icbiep */ 5120 static void gen_icbiep(DisasContext *ctx) 5121 { 5122 TCGv t0; 5123 gen_set_access_type(ctx, ACCESS_CACHE); 5124 t0 = tcg_temp_new(); 5125 gen_addr_reg_index(ctx, t0); 5126 gen_helper_icbiep(cpu_env, t0); 5127 } 5128 5129 /* Optional: */ 5130 /* dcba */ 5131 static void gen_dcba(DisasContext *ctx) 5132 { 5133 /* 5134 * interpreted as no-op 5135 * XXX: specification say this is treated as a store by the MMU 5136 * but does not generate any exception 5137 */ 5138 } 5139 5140 /*** Segment register manipulation ***/ 5141 /* Supervisor only: */ 5142 5143 /* mfsr */ 5144 static void gen_mfsr(DisasContext *ctx) 5145 { 5146 #if defined(CONFIG_USER_ONLY) 5147 GEN_PRIV(ctx); 5148 #else 5149 TCGv t0; 5150 5151 CHK_SV(ctx); 5152 t0 = tcg_constant_tl(SR(ctx->opcode)); 5153 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5154 #endif /* defined(CONFIG_USER_ONLY) */ 5155 } 5156 5157 /* mfsrin */ 5158 static void gen_mfsrin(DisasContext *ctx) 5159 { 5160 #if defined(CONFIG_USER_ONLY) 5161 GEN_PRIV(ctx); 5162 #else 5163 TCGv t0; 5164 5165 CHK_SV(ctx); 5166 t0 = tcg_temp_new(); 5167 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5168 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5169 #endif /* defined(CONFIG_USER_ONLY) */ 5170 } 5171 5172 /* mtsr */ 5173 static void gen_mtsr(DisasContext *ctx) 5174 { 5175 #if defined(CONFIG_USER_ONLY) 5176 GEN_PRIV(ctx); 5177 #else 5178 TCGv t0; 5179 5180 CHK_SV(ctx); 5181 t0 = tcg_constant_tl(SR(ctx->opcode)); 5182 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5183 #endif /* defined(CONFIG_USER_ONLY) */ 5184 } 5185 5186 /* mtsrin */ 5187 static void gen_mtsrin(DisasContext *ctx) 5188 { 5189 #if defined(CONFIG_USER_ONLY) 5190 GEN_PRIV(ctx); 5191 #else 5192 TCGv t0; 5193 CHK_SV(ctx); 5194 5195 t0 = tcg_temp_new(); 5196 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5197 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5198 #endif /* defined(CONFIG_USER_ONLY) */ 5199 } 5200 5201 #if defined(TARGET_PPC64) 5202 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5203 5204 /* mfsr */ 5205 static void gen_mfsr_64b(DisasContext *ctx) 5206 { 5207 #if defined(CONFIG_USER_ONLY) 5208 GEN_PRIV(ctx); 5209 #else 5210 TCGv t0; 5211 5212 CHK_SV(ctx); 5213 t0 = tcg_constant_tl(SR(ctx->opcode)); 5214 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5215 #endif /* defined(CONFIG_USER_ONLY) */ 5216 } 5217 5218 /* mfsrin */ 5219 static void gen_mfsrin_64b(DisasContext *ctx) 5220 { 5221 #if defined(CONFIG_USER_ONLY) 5222 GEN_PRIV(ctx); 5223 #else 5224 TCGv t0; 5225 5226 CHK_SV(ctx); 5227 t0 = tcg_temp_new(); 5228 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5229 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5230 #endif /* defined(CONFIG_USER_ONLY) */ 5231 } 5232 5233 /* mtsr */ 5234 static void gen_mtsr_64b(DisasContext *ctx) 5235 { 5236 #if defined(CONFIG_USER_ONLY) 5237 GEN_PRIV(ctx); 5238 #else 5239 TCGv t0; 5240 5241 CHK_SV(ctx); 5242 t0 = tcg_constant_tl(SR(ctx->opcode)); 5243 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5244 #endif /* defined(CONFIG_USER_ONLY) */ 5245 } 5246 5247 /* mtsrin */ 5248 static void gen_mtsrin_64b(DisasContext *ctx) 5249 { 5250 #if defined(CONFIG_USER_ONLY) 5251 GEN_PRIV(ctx); 5252 #else 5253 TCGv t0; 5254 5255 CHK_SV(ctx); 5256 t0 = tcg_temp_new(); 5257 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5258 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5259 #endif /* defined(CONFIG_USER_ONLY) */ 5260 } 5261 5262 #endif /* defined(TARGET_PPC64) */ 5263 5264 /*** Lookaside buffer management ***/ 5265 /* Optional & supervisor only: */ 5266 5267 /* tlbia */ 5268 static void gen_tlbia(DisasContext *ctx) 5269 { 5270 #if defined(CONFIG_USER_ONLY) 5271 GEN_PRIV(ctx); 5272 #else 5273 CHK_HV(ctx); 5274 5275 gen_helper_tlbia(cpu_env); 5276 #endif /* defined(CONFIG_USER_ONLY) */ 5277 } 5278 5279 /* tlbsync */ 5280 static void gen_tlbsync(DisasContext *ctx) 5281 { 5282 #if defined(CONFIG_USER_ONLY) 5283 GEN_PRIV(ctx); 5284 #else 5285 5286 if (ctx->gtse) { 5287 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5288 } else { 5289 CHK_HV(ctx); /* Else hypervisor privileged */ 5290 } 5291 5292 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5293 if (ctx->insns_flags & PPC_BOOKE) { 5294 gen_check_tlb_flush(ctx, true); 5295 } 5296 #endif /* defined(CONFIG_USER_ONLY) */ 5297 } 5298 5299 /*** External control ***/ 5300 /* Optional: */ 5301 5302 /* eciwx */ 5303 static void gen_eciwx(DisasContext *ctx) 5304 { 5305 TCGv t0; 5306 /* Should check EAR[E] ! */ 5307 gen_set_access_type(ctx, ACCESS_EXT); 5308 t0 = tcg_temp_new(); 5309 gen_addr_reg_index(ctx, t0); 5310 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5311 DEF_MEMOP(MO_UL | MO_ALIGN)); 5312 } 5313 5314 /* ecowx */ 5315 static void gen_ecowx(DisasContext *ctx) 5316 { 5317 TCGv t0; 5318 /* Should check EAR[E] ! */ 5319 gen_set_access_type(ctx, ACCESS_EXT); 5320 t0 = tcg_temp_new(); 5321 gen_addr_reg_index(ctx, t0); 5322 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5323 DEF_MEMOP(MO_UL | MO_ALIGN)); 5324 } 5325 5326 /* 602 - 603 - G2 TLB management */ 5327 5328 /* tlbld */ 5329 static void gen_tlbld_6xx(DisasContext *ctx) 5330 { 5331 #if defined(CONFIG_USER_ONLY) 5332 GEN_PRIV(ctx); 5333 #else 5334 CHK_SV(ctx); 5335 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5336 #endif /* defined(CONFIG_USER_ONLY) */ 5337 } 5338 5339 /* tlbli */ 5340 static void gen_tlbli_6xx(DisasContext *ctx) 5341 { 5342 #if defined(CONFIG_USER_ONLY) 5343 GEN_PRIV(ctx); 5344 #else 5345 CHK_SV(ctx); 5346 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5347 #endif /* defined(CONFIG_USER_ONLY) */ 5348 } 5349 5350 /* BookE specific instructions */ 5351 5352 /* XXX: not implemented on 440 ? */ 5353 static void gen_mfapidi(DisasContext *ctx) 5354 { 5355 /* XXX: TODO */ 5356 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5357 } 5358 5359 /* XXX: not implemented on 440 ? */ 5360 static void gen_tlbiva(DisasContext *ctx) 5361 { 5362 #if defined(CONFIG_USER_ONLY) 5363 GEN_PRIV(ctx); 5364 #else 5365 TCGv t0; 5366 5367 CHK_SV(ctx); 5368 t0 = tcg_temp_new(); 5369 gen_addr_reg_index(ctx, t0); 5370 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5371 #endif /* defined(CONFIG_USER_ONLY) */ 5372 } 5373 5374 /* All 405 MAC instructions are translated here */ 5375 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5376 int ra, int rb, int rt, int Rc) 5377 { 5378 TCGv t0, t1; 5379 5380 t0 = tcg_temp_new(); 5381 t1 = tcg_temp_new(); 5382 5383 switch (opc3 & 0x0D) { 5384 case 0x05: 5385 /* macchw - macchw. - macchwo - macchwo. */ 5386 /* macchws - macchws. - macchwso - macchwso. */ 5387 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5388 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5389 /* mulchw - mulchw. */ 5390 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5391 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5392 tcg_gen_ext16s_tl(t1, t1); 5393 break; 5394 case 0x04: 5395 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5396 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5397 /* mulchwu - mulchwu. */ 5398 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5399 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5400 tcg_gen_ext16u_tl(t1, t1); 5401 break; 5402 case 0x01: 5403 /* machhw - machhw. - machhwo - machhwo. */ 5404 /* machhws - machhws. - machhwso - machhwso. */ 5405 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5406 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5407 /* mulhhw - mulhhw. */ 5408 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5409 tcg_gen_ext16s_tl(t0, t0); 5410 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5411 tcg_gen_ext16s_tl(t1, t1); 5412 break; 5413 case 0x00: 5414 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5415 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5416 /* mulhhwu - mulhhwu. */ 5417 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5418 tcg_gen_ext16u_tl(t0, t0); 5419 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5420 tcg_gen_ext16u_tl(t1, t1); 5421 break; 5422 case 0x0D: 5423 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5424 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5425 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5426 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5427 /* mullhw - mullhw. */ 5428 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5429 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5430 break; 5431 case 0x0C: 5432 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5433 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5434 /* mullhwu - mullhwu. */ 5435 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5436 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5437 break; 5438 } 5439 if (opc2 & 0x04) { 5440 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5441 tcg_gen_mul_tl(t1, t0, t1); 5442 if (opc2 & 0x02) { 5443 /* nmultiply-and-accumulate (0x0E) */ 5444 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5445 } else { 5446 /* multiply-and-accumulate (0x0C) */ 5447 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5448 } 5449 5450 if (opc3 & 0x12) { 5451 /* Check overflow and/or saturate */ 5452 TCGLabel *l1 = gen_new_label(); 5453 5454 if (opc3 & 0x10) { 5455 /* Start with XER OV disabled, the most likely case */ 5456 tcg_gen_movi_tl(cpu_ov, 0); 5457 } 5458 if (opc3 & 0x01) { 5459 /* Signed */ 5460 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5461 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5462 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5463 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5464 if (opc3 & 0x02) { 5465 /* Saturate */ 5466 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5467 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5468 } 5469 } else { 5470 /* Unsigned */ 5471 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5472 if (opc3 & 0x02) { 5473 /* Saturate */ 5474 tcg_gen_movi_tl(t0, UINT32_MAX); 5475 } 5476 } 5477 if (opc3 & 0x10) { 5478 /* Check overflow */ 5479 tcg_gen_movi_tl(cpu_ov, 1); 5480 tcg_gen_movi_tl(cpu_so, 1); 5481 } 5482 gen_set_label(l1); 5483 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5484 } 5485 } else { 5486 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5487 } 5488 if (unlikely(Rc) != 0) { 5489 /* Update Rc0 */ 5490 gen_set_Rc0(ctx, cpu_gpr[rt]); 5491 } 5492 } 5493 5494 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5495 static void glue(gen_, name)(DisasContext *ctx) \ 5496 { \ 5497 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5498 rD(ctx->opcode), Rc(ctx->opcode)); \ 5499 } 5500 5501 /* macchw - macchw. */ 5502 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5503 /* macchwo - macchwo. */ 5504 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5505 /* macchws - macchws. */ 5506 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5507 /* macchwso - macchwso. */ 5508 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5509 /* macchwsu - macchwsu. */ 5510 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5511 /* macchwsuo - macchwsuo. */ 5512 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5513 /* macchwu - macchwu. */ 5514 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5515 /* macchwuo - macchwuo. */ 5516 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5517 /* machhw - machhw. */ 5518 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5519 /* machhwo - machhwo. */ 5520 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5521 /* machhws - machhws. */ 5522 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5523 /* machhwso - machhwso. */ 5524 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5525 /* machhwsu - machhwsu. */ 5526 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5527 /* machhwsuo - machhwsuo. */ 5528 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5529 /* machhwu - machhwu. */ 5530 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5531 /* machhwuo - machhwuo. */ 5532 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5533 /* maclhw - maclhw. */ 5534 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5535 /* maclhwo - maclhwo. */ 5536 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5537 /* maclhws - maclhws. */ 5538 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5539 /* maclhwso - maclhwso. */ 5540 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5541 /* maclhwu - maclhwu. */ 5542 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5543 /* maclhwuo - maclhwuo. */ 5544 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5545 /* maclhwsu - maclhwsu. */ 5546 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5547 /* maclhwsuo - maclhwsuo. */ 5548 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5549 /* nmacchw - nmacchw. */ 5550 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5551 /* nmacchwo - nmacchwo. */ 5552 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5553 /* nmacchws - nmacchws. */ 5554 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5555 /* nmacchwso - nmacchwso. */ 5556 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5557 /* nmachhw - nmachhw. */ 5558 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5559 /* nmachhwo - nmachhwo. */ 5560 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5561 /* nmachhws - nmachhws. */ 5562 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5563 /* nmachhwso - nmachhwso. */ 5564 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5565 /* nmaclhw - nmaclhw. */ 5566 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5567 /* nmaclhwo - nmaclhwo. */ 5568 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5569 /* nmaclhws - nmaclhws. */ 5570 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5571 /* nmaclhwso - nmaclhwso. */ 5572 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5573 5574 /* mulchw - mulchw. */ 5575 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5576 /* mulchwu - mulchwu. */ 5577 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5578 /* mulhhw - mulhhw. */ 5579 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5580 /* mulhhwu - mulhhwu. */ 5581 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5582 /* mullhw - mullhw. */ 5583 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5584 /* mullhwu - mullhwu. */ 5585 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5586 5587 /* mfdcr */ 5588 static void gen_mfdcr(DisasContext *ctx) 5589 { 5590 #if defined(CONFIG_USER_ONLY) 5591 GEN_PRIV(ctx); 5592 #else 5593 TCGv dcrn; 5594 5595 CHK_SV(ctx); 5596 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5597 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5598 #endif /* defined(CONFIG_USER_ONLY) */ 5599 } 5600 5601 /* mtdcr */ 5602 static void gen_mtdcr(DisasContext *ctx) 5603 { 5604 #if defined(CONFIG_USER_ONLY) 5605 GEN_PRIV(ctx); 5606 #else 5607 TCGv dcrn; 5608 5609 CHK_SV(ctx); 5610 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5611 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5612 #endif /* defined(CONFIG_USER_ONLY) */ 5613 } 5614 5615 /* mfdcrx */ 5616 /* XXX: not implemented on 440 ? */ 5617 static void gen_mfdcrx(DisasContext *ctx) 5618 { 5619 #if defined(CONFIG_USER_ONLY) 5620 GEN_PRIV(ctx); 5621 #else 5622 CHK_SV(ctx); 5623 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5624 cpu_gpr[rA(ctx->opcode)]); 5625 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5626 #endif /* defined(CONFIG_USER_ONLY) */ 5627 } 5628 5629 /* mtdcrx */ 5630 /* XXX: not implemented on 440 ? */ 5631 static void gen_mtdcrx(DisasContext *ctx) 5632 { 5633 #if defined(CONFIG_USER_ONLY) 5634 GEN_PRIV(ctx); 5635 #else 5636 CHK_SV(ctx); 5637 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5638 cpu_gpr[rS(ctx->opcode)]); 5639 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5640 #endif /* defined(CONFIG_USER_ONLY) */ 5641 } 5642 5643 /* dccci */ 5644 static void gen_dccci(DisasContext *ctx) 5645 { 5646 CHK_SV(ctx); 5647 /* interpreted as no-op */ 5648 } 5649 5650 /* dcread */ 5651 static void gen_dcread(DisasContext *ctx) 5652 { 5653 #if defined(CONFIG_USER_ONLY) 5654 GEN_PRIV(ctx); 5655 #else 5656 TCGv EA, val; 5657 5658 CHK_SV(ctx); 5659 gen_set_access_type(ctx, ACCESS_CACHE); 5660 EA = tcg_temp_new(); 5661 gen_addr_reg_index(ctx, EA); 5662 val = tcg_temp_new(); 5663 gen_qemu_ld32u(ctx, val, EA); 5664 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5665 #endif /* defined(CONFIG_USER_ONLY) */ 5666 } 5667 5668 /* icbt */ 5669 static void gen_icbt_40x(DisasContext *ctx) 5670 { 5671 /* 5672 * interpreted as no-op 5673 * XXX: specification say this is treated as a load by the MMU but 5674 * does not generate any exception 5675 */ 5676 } 5677 5678 /* iccci */ 5679 static void gen_iccci(DisasContext *ctx) 5680 { 5681 CHK_SV(ctx); 5682 /* interpreted as no-op */ 5683 } 5684 5685 /* icread */ 5686 static void gen_icread(DisasContext *ctx) 5687 { 5688 CHK_SV(ctx); 5689 /* interpreted as no-op */ 5690 } 5691 5692 /* rfci (supervisor only) */ 5693 static void gen_rfci_40x(DisasContext *ctx) 5694 { 5695 #if defined(CONFIG_USER_ONLY) 5696 GEN_PRIV(ctx); 5697 #else 5698 CHK_SV(ctx); 5699 /* Restore CPU state */ 5700 gen_helper_40x_rfci(cpu_env); 5701 ctx->base.is_jmp = DISAS_EXIT; 5702 #endif /* defined(CONFIG_USER_ONLY) */ 5703 } 5704 5705 static void gen_rfci(DisasContext *ctx) 5706 { 5707 #if defined(CONFIG_USER_ONLY) 5708 GEN_PRIV(ctx); 5709 #else 5710 CHK_SV(ctx); 5711 /* Restore CPU state */ 5712 gen_helper_rfci(cpu_env); 5713 ctx->base.is_jmp = DISAS_EXIT; 5714 #endif /* defined(CONFIG_USER_ONLY) */ 5715 } 5716 5717 /* BookE specific */ 5718 5719 /* XXX: not implemented on 440 ? */ 5720 static void gen_rfdi(DisasContext *ctx) 5721 { 5722 #if defined(CONFIG_USER_ONLY) 5723 GEN_PRIV(ctx); 5724 #else 5725 CHK_SV(ctx); 5726 /* Restore CPU state */ 5727 gen_helper_rfdi(cpu_env); 5728 ctx->base.is_jmp = DISAS_EXIT; 5729 #endif /* defined(CONFIG_USER_ONLY) */ 5730 } 5731 5732 /* XXX: not implemented on 440 ? */ 5733 static void gen_rfmci(DisasContext *ctx) 5734 { 5735 #if defined(CONFIG_USER_ONLY) 5736 GEN_PRIV(ctx); 5737 #else 5738 CHK_SV(ctx); 5739 /* Restore CPU state */ 5740 gen_helper_rfmci(cpu_env); 5741 ctx->base.is_jmp = DISAS_EXIT; 5742 #endif /* defined(CONFIG_USER_ONLY) */ 5743 } 5744 5745 /* TLB management - PowerPC 405 implementation */ 5746 5747 /* tlbre */ 5748 static void gen_tlbre_40x(DisasContext *ctx) 5749 { 5750 #if defined(CONFIG_USER_ONLY) 5751 GEN_PRIV(ctx); 5752 #else 5753 CHK_SV(ctx); 5754 switch (rB(ctx->opcode)) { 5755 case 0: 5756 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5757 cpu_gpr[rA(ctx->opcode)]); 5758 break; 5759 case 1: 5760 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5761 cpu_gpr[rA(ctx->opcode)]); 5762 break; 5763 default: 5764 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5765 break; 5766 } 5767 #endif /* defined(CONFIG_USER_ONLY) */ 5768 } 5769 5770 /* tlbsx - tlbsx. */ 5771 static void gen_tlbsx_40x(DisasContext *ctx) 5772 { 5773 #if defined(CONFIG_USER_ONLY) 5774 GEN_PRIV(ctx); 5775 #else 5776 TCGv t0; 5777 5778 CHK_SV(ctx); 5779 t0 = tcg_temp_new(); 5780 gen_addr_reg_index(ctx, t0); 5781 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5782 if (Rc(ctx->opcode)) { 5783 TCGLabel *l1 = gen_new_label(); 5784 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5785 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5786 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5787 gen_set_label(l1); 5788 } 5789 #endif /* defined(CONFIG_USER_ONLY) */ 5790 } 5791 5792 /* tlbwe */ 5793 static void gen_tlbwe_40x(DisasContext *ctx) 5794 { 5795 #if defined(CONFIG_USER_ONLY) 5796 GEN_PRIV(ctx); 5797 #else 5798 CHK_SV(ctx); 5799 5800 switch (rB(ctx->opcode)) { 5801 case 0: 5802 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5803 cpu_gpr[rS(ctx->opcode)]); 5804 break; 5805 case 1: 5806 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5807 cpu_gpr[rS(ctx->opcode)]); 5808 break; 5809 default: 5810 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5811 break; 5812 } 5813 #endif /* defined(CONFIG_USER_ONLY) */ 5814 } 5815 5816 /* TLB management - PowerPC 440 implementation */ 5817 5818 /* tlbre */ 5819 static void gen_tlbre_440(DisasContext *ctx) 5820 { 5821 #if defined(CONFIG_USER_ONLY) 5822 GEN_PRIV(ctx); 5823 #else 5824 CHK_SV(ctx); 5825 5826 switch (rB(ctx->opcode)) { 5827 case 0: 5828 case 1: 5829 case 2: 5830 { 5831 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5832 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5833 t0, cpu_gpr[rA(ctx->opcode)]); 5834 } 5835 break; 5836 default: 5837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5838 break; 5839 } 5840 #endif /* defined(CONFIG_USER_ONLY) */ 5841 } 5842 5843 /* tlbsx - tlbsx. */ 5844 static void gen_tlbsx_440(DisasContext *ctx) 5845 { 5846 #if defined(CONFIG_USER_ONLY) 5847 GEN_PRIV(ctx); 5848 #else 5849 TCGv t0; 5850 5851 CHK_SV(ctx); 5852 t0 = tcg_temp_new(); 5853 gen_addr_reg_index(ctx, t0); 5854 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5855 if (Rc(ctx->opcode)) { 5856 TCGLabel *l1 = gen_new_label(); 5857 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5858 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5859 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5860 gen_set_label(l1); 5861 } 5862 #endif /* defined(CONFIG_USER_ONLY) */ 5863 } 5864 5865 /* tlbwe */ 5866 static void gen_tlbwe_440(DisasContext *ctx) 5867 { 5868 #if defined(CONFIG_USER_ONLY) 5869 GEN_PRIV(ctx); 5870 #else 5871 CHK_SV(ctx); 5872 switch (rB(ctx->opcode)) { 5873 case 0: 5874 case 1: 5875 case 2: 5876 { 5877 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5878 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5879 cpu_gpr[rS(ctx->opcode)]); 5880 } 5881 break; 5882 default: 5883 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5884 break; 5885 } 5886 #endif /* defined(CONFIG_USER_ONLY) */ 5887 } 5888 5889 /* TLB management - PowerPC BookE 2.06 implementation */ 5890 5891 /* tlbre */ 5892 static void gen_tlbre_booke206(DisasContext *ctx) 5893 { 5894 #if defined(CONFIG_USER_ONLY) 5895 GEN_PRIV(ctx); 5896 #else 5897 CHK_SV(ctx); 5898 gen_helper_booke206_tlbre(cpu_env); 5899 #endif /* defined(CONFIG_USER_ONLY) */ 5900 } 5901 5902 /* tlbsx - tlbsx. */ 5903 static void gen_tlbsx_booke206(DisasContext *ctx) 5904 { 5905 #if defined(CONFIG_USER_ONLY) 5906 GEN_PRIV(ctx); 5907 #else 5908 TCGv t0; 5909 5910 CHK_SV(ctx); 5911 if (rA(ctx->opcode)) { 5912 t0 = tcg_temp_new(); 5913 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5914 } else { 5915 t0 = cpu_gpr[rB(ctx->opcode)]; 5916 } 5917 gen_helper_booke206_tlbsx(cpu_env, t0); 5918 #endif /* defined(CONFIG_USER_ONLY) */ 5919 } 5920 5921 /* tlbwe */ 5922 static void gen_tlbwe_booke206(DisasContext *ctx) 5923 { 5924 #if defined(CONFIG_USER_ONLY) 5925 GEN_PRIV(ctx); 5926 #else 5927 CHK_SV(ctx); 5928 gen_helper_booke206_tlbwe(cpu_env); 5929 #endif /* defined(CONFIG_USER_ONLY) */ 5930 } 5931 5932 static void gen_tlbivax_booke206(DisasContext *ctx) 5933 { 5934 #if defined(CONFIG_USER_ONLY) 5935 GEN_PRIV(ctx); 5936 #else 5937 TCGv t0; 5938 5939 CHK_SV(ctx); 5940 t0 = tcg_temp_new(); 5941 gen_addr_reg_index(ctx, t0); 5942 gen_helper_booke206_tlbivax(cpu_env, t0); 5943 #endif /* defined(CONFIG_USER_ONLY) */ 5944 } 5945 5946 static void gen_tlbilx_booke206(DisasContext *ctx) 5947 { 5948 #if defined(CONFIG_USER_ONLY) 5949 GEN_PRIV(ctx); 5950 #else 5951 TCGv t0; 5952 5953 CHK_SV(ctx); 5954 t0 = tcg_temp_new(); 5955 gen_addr_reg_index(ctx, t0); 5956 5957 switch ((ctx->opcode >> 21) & 0x3) { 5958 case 0: 5959 gen_helper_booke206_tlbilx0(cpu_env, t0); 5960 break; 5961 case 1: 5962 gen_helper_booke206_tlbilx1(cpu_env, t0); 5963 break; 5964 case 3: 5965 gen_helper_booke206_tlbilx3(cpu_env, t0); 5966 break; 5967 default: 5968 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5969 break; 5970 } 5971 #endif /* defined(CONFIG_USER_ONLY) */ 5972 } 5973 5974 /* wrtee */ 5975 static void gen_wrtee(DisasContext *ctx) 5976 { 5977 #if defined(CONFIG_USER_ONLY) 5978 GEN_PRIV(ctx); 5979 #else 5980 TCGv t0; 5981 5982 CHK_SV(ctx); 5983 t0 = tcg_temp_new(); 5984 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5985 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5986 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5987 gen_ppc_maybe_interrupt(ctx); 5988 /* 5989 * Stop translation to have a chance to raise an exception if we 5990 * just set msr_ee to 1 5991 */ 5992 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5993 #endif /* defined(CONFIG_USER_ONLY) */ 5994 } 5995 5996 /* wrteei */ 5997 static void gen_wrteei(DisasContext *ctx) 5998 { 5999 #if defined(CONFIG_USER_ONLY) 6000 GEN_PRIV(ctx); 6001 #else 6002 CHK_SV(ctx); 6003 if (ctx->opcode & 0x00008000) { 6004 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6005 gen_ppc_maybe_interrupt(ctx); 6006 /* Stop translation to have a chance to raise an exception */ 6007 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6008 } else { 6009 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6010 } 6011 #endif /* defined(CONFIG_USER_ONLY) */ 6012 } 6013 6014 /* PowerPC 440 specific instructions */ 6015 6016 /* dlmzb */ 6017 static void gen_dlmzb(DisasContext *ctx) 6018 { 6019 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6020 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6021 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6022 } 6023 6024 /* mbar replaces eieio on 440 */ 6025 static void gen_mbar(DisasContext *ctx) 6026 { 6027 /* interpreted as no-op */ 6028 } 6029 6030 /* msync replaces sync on 440 */ 6031 static void gen_msync_4xx(DisasContext *ctx) 6032 { 6033 /* Only e500 seems to treat reserved bits as invalid */ 6034 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6035 (ctx->opcode & 0x03FFF801)) { 6036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6037 } 6038 /* otherwise interpreted as no-op */ 6039 } 6040 6041 /* icbt */ 6042 static void gen_icbt_440(DisasContext *ctx) 6043 { 6044 /* 6045 * interpreted as no-op 6046 * XXX: specification say this is treated as a load by the MMU but 6047 * does not generate any exception 6048 */ 6049 } 6050 6051 #if defined(TARGET_PPC64) 6052 static void gen_maddld(DisasContext *ctx) 6053 { 6054 TCGv_i64 t1 = tcg_temp_new_i64(); 6055 6056 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6057 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6058 } 6059 6060 /* maddhd maddhdu */ 6061 static void gen_maddhd_maddhdu(DisasContext *ctx) 6062 { 6063 TCGv_i64 lo = tcg_temp_new_i64(); 6064 TCGv_i64 hi = tcg_temp_new_i64(); 6065 TCGv_i64 t1 = tcg_temp_new_i64(); 6066 6067 if (Rc(ctx->opcode)) { 6068 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6069 cpu_gpr[rB(ctx->opcode)]); 6070 tcg_gen_movi_i64(t1, 0); 6071 } else { 6072 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6073 cpu_gpr[rB(ctx->opcode)]); 6074 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6075 } 6076 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6077 cpu_gpr[rC(ctx->opcode)], t1); 6078 } 6079 #endif /* defined(TARGET_PPC64) */ 6080 6081 static void gen_tbegin(DisasContext *ctx) 6082 { 6083 if (unlikely(!ctx->tm_enabled)) { 6084 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6085 return; 6086 } 6087 gen_helper_tbegin(cpu_env); 6088 } 6089 6090 #define GEN_TM_NOOP(name) \ 6091 static inline void gen_##name(DisasContext *ctx) \ 6092 { \ 6093 if (unlikely(!ctx->tm_enabled)) { \ 6094 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6095 return; \ 6096 } \ 6097 /* \ 6098 * Because tbegin always fails in QEMU, these user \ 6099 * space instructions all have a simple implementation: \ 6100 * \ 6101 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6102 * = 0b0 || 0b00 || 0b0 \ 6103 */ \ 6104 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6105 } 6106 6107 GEN_TM_NOOP(tend); 6108 GEN_TM_NOOP(tabort); 6109 GEN_TM_NOOP(tabortwc); 6110 GEN_TM_NOOP(tabortwci); 6111 GEN_TM_NOOP(tabortdc); 6112 GEN_TM_NOOP(tabortdci); 6113 GEN_TM_NOOP(tsr); 6114 6115 static inline void gen_cp_abort(DisasContext *ctx) 6116 { 6117 /* Do Nothing */ 6118 } 6119 6120 #define GEN_CP_PASTE_NOOP(name) \ 6121 static inline void gen_##name(DisasContext *ctx) \ 6122 { \ 6123 /* \ 6124 * Generate invalid exception until we have an \ 6125 * implementation of the copy paste facility \ 6126 */ \ 6127 gen_invalid(ctx); \ 6128 } 6129 6130 GEN_CP_PASTE_NOOP(copy) 6131 GEN_CP_PASTE_NOOP(paste) 6132 6133 static void gen_tcheck(DisasContext *ctx) 6134 { 6135 if (unlikely(!ctx->tm_enabled)) { 6136 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6137 return; 6138 } 6139 /* 6140 * Because tbegin always fails, the tcheck implementation is 6141 * simple: 6142 * 6143 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6144 * = 0b1 || 0b00 || 0b0 6145 */ 6146 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6147 } 6148 6149 #if defined(CONFIG_USER_ONLY) 6150 #define GEN_TM_PRIV_NOOP(name) \ 6151 static inline void gen_##name(DisasContext *ctx) \ 6152 { \ 6153 gen_priv_opc(ctx); \ 6154 } 6155 6156 #else 6157 6158 #define GEN_TM_PRIV_NOOP(name) \ 6159 static inline void gen_##name(DisasContext *ctx) \ 6160 { \ 6161 CHK_SV(ctx); \ 6162 if (unlikely(!ctx->tm_enabled)) { \ 6163 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6164 return; \ 6165 } \ 6166 /* \ 6167 * Because tbegin always fails, the implementation is \ 6168 * simple: \ 6169 * \ 6170 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6171 * = 0b0 || 0b00 | 0b0 \ 6172 */ \ 6173 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6174 } 6175 6176 #endif 6177 6178 GEN_TM_PRIV_NOOP(treclaim); 6179 GEN_TM_PRIV_NOOP(trechkpt); 6180 6181 static inline void get_fpr(TCGv_i64 dst, int regno) 6182 { 6183 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6184 } 6185 6186 static inline void set_fpr(int regno, TCGv_i64 src) 6187 { 6188 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6189 /* 6190 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6191 * corresponding to the target FPR was undefined. However, 6192 * most (if not all) real hardware were setting the result to 0. 6193 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6194 * to be 0. 6195 */ 6196 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6197 } 6198 6199 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6200 { 6201 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6202 } 6203 6204 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6205 { 6206 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6207 } 6208 6209 /* 6210 * Helpers for decodetree used by !function for decoding arguments. 6211 */ 6212 static int times_2(DisasContext *ctx, int x) 6213 { 6214 return x * 2; 6215 } 6216 6217 static int times_4(DisasContext *ctx, int x) 6218 { 6219 return x * 4; 6220 } 6221 6222 static int times_16(DisasContext *ctx, int x) 6223 { 6224 return x * 16; 6225 } 6226 6227 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6228 { 6229 return deposit64(0xfffffffffffffe00, 3, 6, x); 6230 } 6231 6232 /* 6233 * Helpers for trans_* functions to check for specific insns flags. 6234 * Use token pasting to ensure that we use the proper flag with the 6235 * proper variable. 6236 */ 6237 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6238 do { \ 6239 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6240 return false; \ 6241 } \ 6242 } while (0) 6243 6244 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6245 do { \ 6246 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6247 return false; \ 6248 } \ 6249 } while (0) 6250 6251 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6252 #if TARGET_LONG_BITS == 32 6253 # define REQUIRE_64BIT(CTX) return false 6254 #else 6255 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6256 #endif 6257 6258 #define REQUIRE_VECTOR(CTX) \ 6259 do { \ 6260 if (unlikely(!(CTX)->altivec_enabled)) { \ 6261 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6262 return true; \ 6263 } \ 6264 } while (0) 6265 6266 #define REQUIRE_VSX(CTX) \ 6267 do { \ 6268 if (unlikely(!(CTX)->vsx_enabled)) { \ 6269 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6270 return true; \ 6271 } \ 6272 } while (0) 6273 6274 #define REQUIRE_FPU(ctx) \ 6275 do { \ 6276 if (unlikely(!(ctx)->fpu_enabled)) { \ 6277 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6278 return true; \ 6279 } \ 6280 } while (0) 6281 6282 #if !defined(CONFIG_USER_ONLY) 6283 #define REQUIRE_SV(CTX) \ 6284 do { \ 6285 if (unlikely((CTX)->pr)) { \ 6286 gen_priv_opc(CTX); \ 6287 return true; \ 6288 } \ 6289 } while (0) 6290 6291 #define REQUIRE_HV(CTX) \ 6292 do { \ 6293 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6294 gen_priv_opc(CTX); \ 6295 return true; \ 6296 } \ 6297 } while (0) 6298 #else 6299 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6300 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6301 #endif 6302 6303 /* 6304 * Helpers for implementing sets of trans_* functions. 6305 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6306 */ 6307 #define TRANS(NAME, FUNC, ...) \ 6308 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6309 { return FUNC(ctx, a, __VA_ARGS__); } 6310 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6311 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6312 { \ 6313 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6314 return FUNC(ctx, a, __VA_ARGS__); \ 6315 } 6316 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6317 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6318 { \ 6319 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6320 return FUNC(ctx, a, __VA_ARGS__); \ 6321 } 6322 6323 #define TRANS64(NAME, FUNC, ...) \ 6324 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6325 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6326 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6327 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6328 { \ 6329 REQUIRE_64BIT(ctx); \ 6330 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6331 return FUNC(ctx, a, __VA_ARGS__); \ 6332 } 6333 6334 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6335 6336 6337 #include "decode-insn32.c.inc" 6338 #include "decode-insn64.c.inc" 6339 #include "power8-pmu-regs.c.inc" 6340 6341 /* 6342 * Incorporate CIA into the constant when R=1. 6343 * Validate that when R=1, RA=0. 6344 */ 6345 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6346 { 6347 d->rt = a->rt; 6348 d->ra = a->ra; 6349 d->si = a->si; 6350 if (a->r) { 6351 if (unlikely(a->ra != 0)) { 6352 gen_invalid(ctx); 6353 return false; 6354 } 6355 d->si += ctx->cia; 6356 } 6357 return true; 6358 } 6359 6360 #include "translate/fixedpoint-impl.c.inc" 6361 6362 #include "translate/fp-impl.c.inc" 6363 6364 #include "translate/vmx-impl.c.inc" 6365 6366 #include "translate/vsx-impl.c.inc" 6367 6368 #include "translate/dfp-impl.c.inc" 6369 6370 #include "translate/spe-impl.c.inc" 6371 6372 #include "translate/branch-impl.c.inc" 6373 6374 #include "translate/processor-ctrl-impl.c.inc" 6375 6376 #include "translate/storage-ctrl-impl.c.inc" 6377 6378 /* Handles lfdp */ 6379 static void gen_dform39(DisasContext *ctx) 6380 { 6381 if ((ctx->opcode & 0x3) == 0) { 6382 if (ctx->insns_flags2 & PPC2_ISA205) { 6383 return gen_lfdp(ctx); 6384 } 6385 } 6386 return gen_invalid(ctx); 6387 } 6388 6389 /* Handles stfdp */ 6390 static void gen_dform3D(DisasContext *ctx) 6391 { 6392 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6393 /* stfdp */ 6394 if (ctx->insns_flags2 & PPC2_ISA205) { 6395 return gen_stfdp(ctx); 6396 } 6397 } 6398 return gen_invalid(ctx); 6399 } 6400 6401 #if defined(TARGET_PPC64) 6402 /* brd */ 6403 static void gen_brd(DisasContext *ctx) 6404 { 6405 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6406 } 6407 6408 /* brw */ 6409 static void gen_brw(DisasContext *ctx) 6410 { 6411 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6412 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6413 6414 } 6415 6416 /* brh */ 6417 static void gen_brh(DisasContext *ctx) 6418 { 6419 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6420 TCGv_i64 t1 = tcg_temp_new_i64(); 6421 TCGv_i64 t2 = tcg_temp_new_i64(); 6422 6423 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6424 tcg_gen_and_i64(t2, t1, mask); 6425 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6426 tcg_gen_shli_i64(t1, t1, 8); 6427 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6428 } 6429 #endif 6430 6431 static opcode_t opcodes[] = { 6432 #if defined(TARGET_PPC64) 6433 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6434 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6435 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6436 #endif 6437 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6438 #if defined(TARGET_PPC64) 6439 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6440 #endif 6441 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6442 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6443 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6444 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6446 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6447 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6448 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6449 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6450 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451 #if defined(TARGET_PPC64) 6452 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6453 #endif 6454 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6455 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6456 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6457 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6458 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6459 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6460 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6461 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6462 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6463 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6464 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6465 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6466 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6467 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6469 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6470 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6471 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6472 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6473 #if defined(TARGET_PPC64) 6474 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6475 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6476 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6477 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6478 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6479 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6480 #endif 6481 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6482 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6483 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6484 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6485 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6486 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6487 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6488 #if defined(TARGET_PPC64) 6489 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6490 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6491 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6492 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6493 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6494 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6495 PPC_NONE, PPC2_ISA300), 6496 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6497 PPC_NONE, PPC2_ISA300), 6498 #endif 6499 /* handles lfdp, lxsd, lxssp */ 6500 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6501 /* handles stfdp, stxsd, stxssp */ 6502 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6503 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6504 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6505 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6506 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6507 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6508 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6509 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6510 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6511 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6512 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6513 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6514 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6515 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6516 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6517 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6518 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6519 #if defined(TARGET_PPC64) 6520 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6521 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6522 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6523 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6524 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6525 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6526 #endif 6527 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6528 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6529 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6530 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6531 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6532 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6533 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6534 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6535 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6536 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6537 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6538 #if defined(TARGET_PPC64) 6539 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6540 #if !defined(CONFIG_USER_ONLY) 6541 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6542 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6543 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6544 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6545 #endif 6546 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6547 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6548 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6549 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6550 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6551 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6552 #endif 6553 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6554 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6555 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6556 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6557 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6558 #if defined(TARGET_PPC64) 6559 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6560 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6561 #endif 6562 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6563 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6564 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6565 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6566 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6567 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6568 #if defined(TARGET_PPC64) 6569 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6570 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6571 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6572 #endif 6573 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6574 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6575 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6576 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6577 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6578 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6579 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6580 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6581 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6582 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6583 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6584 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6585 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6586 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6587 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6588 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6589 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6590 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6591 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6592 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6593 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6594 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6595 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6596 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6597 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6598 #if defined(TARGET_PPC64) 6599 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6600 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6601 PPC_SEGMENT_64B), 6602 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6603 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6604 PPC_SEGMENT_64B), 6605 #endif 6606 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6607 /* 6608 * XXX Those instructions will need to be handled differently for 6609 * different ISA versions 6610 */ 6611 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6612 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6613 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6614 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6615 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6616 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6617 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6618 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6619 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6620 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6621 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6622 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6623 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6624 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6625 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6626 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6627 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6628 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6629 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6630 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6631 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6632 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6633 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6634 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6635 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6636 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6637 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6638 PPC_NONE, PPC2_BOOKE206), 6639 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6640 PPC_NONE, PPC2_BOOKE206), 6641 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6642 PPC_NONE, PPC2_BOOKE206), 6643 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6644 PPC_NONE, PPC2_BOOKE206), 6645 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6646 PPC_NONE, PPC2_BOOKE206), 6647 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6648 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6649 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6650 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6651 PPC_BOOKE, PPC2_BOOKE206), 6652 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6653 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6654 PPC_BOOKE, PPC2_BOOKE206), 6655 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6656 PPC_440_SPEC), 6657 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6658 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6659 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6660 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6661 #if defined(TARGET_PPC64) 6662 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6663 PPC2_ISA300), 6664 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6665 #endif 6666 6667 #undef GEN_INT_ARITH_ADD 6668 #undef GEN_INT_ARITH_ADD_CONST 6669 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6670 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6671 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6672 add_ca, compute_ca, compute_ov) \ 6673 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6674 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6675 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6676 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6677 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6678 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6679 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6680 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6681 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6682 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6683 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6684 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6685 6686 #undef GEN_INT_ARITH_DIVW 6687 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6688 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6689 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6690 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6691 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6692 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6693 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6694 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6695 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6696 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6697 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6698 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6699 6700 #if defined(TARGET_PPC64) 6701 #undef GEN_INT_ARITH_DIVD 6702 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6703 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6704 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6705 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6706 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6707 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6708 6709 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6710 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6711 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6713 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6714 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6715 6716 #undef GEN_INT_ARITH_MUL_HELPER 6717 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6718 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6719 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6720 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6721 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6722 #endif 6723 6724 #undef GEN_INT_ARITH_SUBF 6725 #undef GEN_INT_ARITH_SUBF_CONST 6726 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6727 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6728 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6729 add_ca, compute_ca, compute_ov) \ 6730 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6731 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6732 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6733 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6734 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6735 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6736 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6737 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6738 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6739 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6740 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6741 6742 #undef GEN_LOGICAL1 6743 #undef GEN_LOGICAL2 6744 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6745 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6746 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6747 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6748 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6749 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6750 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6751 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6752 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6753 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6754 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6755 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6756 #if defined(TARGET_PPC64) 6757 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6758 #endif 6759 6760 #if defined(TARGET_PPC64) 6761 #undef GEN_PPC64_R2 6762 #undef GEN_PPC64_R4 6763 #define GEN_PPC64_R2(name, opc1, opc2) \ 6764 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6765 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6766 PPC_64B) 6767 #define GEN_PPC64_R4(name, opc1, opc2) \ 6768 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6769 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6770 PPC_64B), \ 6771 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6772 PPC_64B), \ 6773 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6774 PPC_64B) 6775 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6776 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6777 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6778 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6779 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6780 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6781 #endif 6782 6783 #undef GEN_LDX_E 6784 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6785 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6786 6787 #if defined(TARGET_PPC64) 6788 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6789 6790 /* HV/P7 and later only */ 6791 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6792 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6793 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6794 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6795 #endif 6796 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6797 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6798 6799 /* External PID based load */ 6800 #undef GEN_LDEPX 6801 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6802 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6803 0x00000001, PPC_NONE, PPC2_BOOKE206), 6804 6805 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6806 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6807 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6808 #if defined(TARGET_PPC64) 6809 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6810 #endif 6811 6812 #undef GEN_STX_E 6813 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6814 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6815 6816 #if defined(TARGET_PPC64) 6817 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6818 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6819 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6820 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6821 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6822 #endif 6823 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6824 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6825 6826 #undef GEN_STEPX 6827 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6828 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6829 0x00000001, PPC_NONE, PPC2_BOOKE206), 6830 6831 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6832 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6833 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6834 #if defined(TARGET_PPC64) 6835 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6836 #endif 6837 6838 #undef GEN_CRLOGIC 6839 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6840 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6841 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6842 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6843 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6844 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6845 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6846 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6847 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6848 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6849 6850 #undef GEN_MAC_HANDLER 6851 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6852 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6853 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6854 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6855 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6856 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6857 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6858 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6859 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6860 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6861 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6862 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6863 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6864 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6865 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6866 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6867 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6868 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6869 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6870 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6871 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6872 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6873 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6874 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6875 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6876 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6877 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6878 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6879 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6880 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6881 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6882 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6883 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6884 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6885 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6886 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6887 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6888 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6889 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6890 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6891 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6892 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6893 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6894 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6895 6896 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6897 PPC_NONE, PPC2_TM), 6898 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6899 PPC_NONE, PPC2_TM), 6900 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6901 PPC_NONE, PPC2_TM), 6902 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6903 PPC_NONE, PPC2_TM), 6904 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6905 PPC_NONE, PPC2_TM), 6906 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6907 PPC_NONE, PPC2_TM), 6908 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6909 PPC_NONE, PPC2_TM), 6910 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6911 PPC_NONE, PPC2_TM), 6912 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6913 PPC_NONE, PPC2_TM), 6914 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6915 PPC_NONE, PPC2_TM), 6916 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6917 PPC_NONE, PPC2_TM), 6918 6919 #include "translate/fp-ops.c.inc" 6920 6921 #include "translate/vmx-ops.c.inc" 6922 6923 #include "translate/vsx-ops.c.inc" 6924 6925 #include "translate/spe-ops.c.inc" 6926 }; 6927 6928 /*****************************************************************************/ 6929 /* Opcode types */ 6930 enum { 6931 PPC_DIRECT = 0, /* Opcode routine */ 6932 PPC_INDIRECT = 1, /* Indirect opcode table */ 6933 }; 6934 6935 #define PPC_OPCODE_MASK 0x3 6936 6937 static inline int is_indirect_opcode(void *handler) 6938 { 6939 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6940 } 6941 6942 static inline opc_handler_t **ind_table(void *handler) 6943 { 6944 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6945 } 6946 6947 /* Instruction table creation */ 6948 /* Opcodes tables creation */ 6949 static void fill_new_table(opc_handler_t **table, int len) 6950 { 6951 int i; 6952 6953 for (i = 0; i < len; i++) { 6954 table[i] = &invalid_handler; 6955 } 6956 } 6957 6958 static int create_new_table(opc_handler_t **table, unsigned char idx) 6959 { 6960 opc_handler_t **tmp; 6961 6962 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6963 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6964 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6965 6966 return 0; 6967 } 6968 6969 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6970 opc_handler_t *handler) 6971 { 6972 if (table[idx] != &invalid_handler) { 6973 return -1; 6974 } 6975 table[idx] = handler; 6976 6977 return 0; 6978 } 6979 6980 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6981 unsigned char idx, opc_handler_t *handler) 6982 { 6983 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6984 printf("*** ERROR: opcode %02x already assigned in main " 6985 "opcode table\n", idx); 6986 return -1; 6987 } 6988 6989 return 0; 6990 } 6991 6992 static int register_ind_in_table(opc_handler_t **table, 6993 unsigned char idx1, unsigned char idx2, 6994 opc_handler_t *handler) 6995 { 6996 if (table[idx1] == &invalid_handler) { 6997 if (create_new_table(table, idx1) < 0) { 6998 printf("*** ERROR: unable to create indirect table " 6999 "idx=%02x\n", idx1); 7000 return -1; 7001 } 7002 } else { 7003 if (!is_indirect_opcode(table[idx1])) { 7004 printf("*** ERROR: idx %02x already assigned to a direct " 7005 "opcode\n", idx1); 7006 return -1; 7007 } 7008 } 7009 if (handler != NULL && 7010 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7011 printf("*** ERROR: opcode %02x already assigned in " 7012 "opcode table %02x\n", idx2, idx1); 7013 return -1; 7014 } 7015 7016 return 0; 7017 } 7018 7019 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7020 unsigned char idx1, unsigned char idx2, 7021 opc_handler_t *handler) 7022 { 7023 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7024 } 7025 7026 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7027 unsigned char idx1, unsigned char idx2, 7028 unsigned char idx3, opc_handler_t *handler) 7029 { 7030 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7031 printf("*** ERROR: unable to join indirect table idx " 7032 "[%02x-%02x]\n", idx1, idx2); 7033 return -1; 7034 } 7035 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7036 handler) < 0) { 7037 printf("*** ERROR: unable to insert opcode " 7038 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7039 return -1; 7040 } 7041 7042 return 0; 7043 } 7044 7045 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7046 unsigned char idx1, unsigned char idx2, 7047 unsigned char idx3, unsigned char idx4, 7048 opc_handler_t *handler) 7049 { 7050 opc_handler_t **table; 7051 7052 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7053 printf("*** ERROR: unable to join indirect table idx " 7054 "[%02x-%02x]\n", idx1, idx2); 7055 return -1; 7056 } 7057 table = ind_table(ppc_opcodes[idx1]); 7058 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7059 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7060 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7061 return -1; 7062 } 7063 table = ind_table(table[idx2]); 7064 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7065 printf("*** ERROR: unable to insert opcode " 7066 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7067 return -1; 7068 } 7069 return 0; 7070 } 7071 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7072 { 7073 if (insn->opc2 != 0xFF) { 7074 if (insn->opc3 != 0xFF) { 7075 if (insn->opc4 != 0xFF) { 7076 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7077 insn->opc3, insn->opc4, 7078 &insn->handler) < 0) { 7079 return -1; 7080 } 7081 } else { 7082 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7083 insn->opc3, &insn->handler) < 0) { 7084 return -1; 7085 } 7086 } 7087 } else { 7088 if (register_ind_insn(ppc_opcodes, insn->opc1, 7089 insn->opc2, &insn->handler) < 0) { 7090 return -1; 7091 } 7092 } 7093 } else { 7094 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7095 return -1; 7096 } 7097 } 7098 7099 return 0; 7100 } 7101 7102 static int test_opcode_table(opc_handler_t **table, int len) 7103 { 7104 int i, count, tmp; 7105 7106 for (i = 0, count = 0; i < len; i++) { 7107 /* Consistency fixup */ 7108 if (table[i] == NULL) { 7109 table[i] = &invalid_handler; 7110 } 7111 if (table[i] != &invalid_handler) { 7112 if (is_indirect_opcode(table[i])) { 7113 tmp = test_opcode_table(ind_table(table[i]), 7114 PPC_CPU_INDIRECT_OPCODES_LEN); 7115 if (tmp == 0) { 7116 free(table[i]); 7117 table[i] = &invalid_handler; 7118 } else { 7119 count++; 7120 } 7121 } else { 7122 count++; 7123 } 7124 } 7125 } 7126 7127 return count; 7128 } 7129 7130 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7131 { 7132 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7133 printf("*** WARNING: no opcode defined !\n"); 7134 } 7135 } 7136 7137 /*****************************************************************************/ 7138 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7139 { 7140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7141 opcode_t *opc; 7142 7143 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7144 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7145 if (((opc->handler.type & pcc->insns_flags) != 0) || 7146 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7147 if (register_insn(cpu->opcodes, opc) < 0) { 7148 error_setg(errp, "ERROR initializing PowerPC instruction " 7149 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7150 opc->opc3); 7151 return; 7152 } 7153 } 7154 } 7155 fix_opcode_tables(cpu->opcodes); 7156 fflush(stdout); 7157 fflush(stderr); 7158 } 7159 7160 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7161 { 7162 opc_handler_t **table, **table_2; 7163 int i, j, k; 7164 7165 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7166 if (cpu->opcodes[i] == &invalid_handler) { 7167 continue; 7168 } 7169 if (is_indirect_opcode(cpu->opcodes[i])) { 7170 table = ind_table(cpu->opcodes[i]); 7171 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7172 if (table[j] == &invalid_handler) { 7173 continue; 7174 } 7175 if (is_indirect_opcode(table[j])) { 7176 table_2 = ind_table(table[j]); 7177 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7178 if (table_2[k] != &invalid_handler && 7179 is_indirect_opcode(table_2[k])) { 7180 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7181 ~PPC_INDIRECT)); 7182 } 7183 } 7184 g_free((opc_handler_t *)((uintptr_t)table[j] & 7185 ~PPC_INDIRECT)); 7186 } 7187 } 7188 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7189 ~PPC_INDIRECT)); 7190 } 7191 } 7192 } 7193 7194 int ppc_fixup_cpu(PowerPCCPU *cpu) 7195 { 7196 CPUPPCState *env = &cpu->env; 7197 7198 /* 7199 * TCG doesn't (yet) emulate some groups of instructions that are 7200 * implemented on some otherwise supported CPUs (e.g. VSX and 7201 * decimal floating point instructions on POWER7). We remove 7202 * unsupported instruction groups from the cpu state's instruction 7203 * masks and hope the guest can cope. For at least the pseries 7204 * machine, the unavailability of these instructions can be 7205 * advertised to the guest via the device tree. 7206 */ 7207 if ((env->insns_flags & ~PPC_TCG_INSNS) 7208 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7209 warn_report("Disabling some instructions which are not " 7210 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7211 env->insns_flags & ~PPC_TCG_INSNS, 7212 env->insns_flags2 & ~PPC_TCG_INSNS2); 7213 } 7214 env->insns_flags &= PPC_TCG_INSNS; 7215 env->insns_flags2 &= PPC_TCG_INSNS2; 7216 return 0; 7217 } 7218 7219 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7220 { 7221 opc_handler_t **table, *handler; 7222 uint32_t inval; 7223 7224 ctx->opcode = insn; 7225 7226 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7227 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7228 ctx->le_mode ? "little" : "big"); 7229 7230 table = cpu->opcodes; 7231 handler = table[opc1(insn)]; 7232 if (is_indirect_opcode(handler)) { 7233 table = ind_table(handler); 7234 handler = table[opc2(insn)]; 7235 if (is_indirect_opcode(handler)) { 7236 table = ind_table(handler); 7237 handler = table[opc3(insn)]; 7238 if (is_indirect_opcode(handler)) { 7239 table = ind_table(handler); 7240 handler = table[opc4(insn)]; 7241 } 7242 } 7243 } 7244 7245 /* Is opcode *REALLY* valid ? */ 7246 if (unlikely(handler->handler == &gen_invalid)) { 7247 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7248 "%02x - %02x - %02x - %02x (%08x) " 7249 TARGET_FMT_lx "\n", 7250 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7251 insn, ctx->cia); 7252 return false; 7253 } 7254 7255 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7256 && Rc(insn))) { 7257 inval = handler->inval2; 7258 } else { 7259 inval = handler->inval1; 7260 } 7261 7262 if (unlikely((insn & inval) != 0)) { 7263 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7264 "%02x - %02x - %02x - %02x (%08x) " 7265 TARGET_FMT_lx "\n", insn & inval, 7266 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7267 insn, ctx->cia); 7268 return false; 7269 } 7270 7271 handler->handler(ctx); 7272 return true; 7273 } 7274 7275 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7276 { 7277 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7278 CPUPPCState *env = cs->env_ptr; 7279 uint32_t hflags = ctx->base.tb->flags; 7280 7281 ctx->spr_cb = env->spr_cb; 7282 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7283 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7284 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7285 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7286 ctx->insns_flags = env->insns_flags; 7287 ctx->insns_flags2 = env->insns_flags2; 7288 ctx->access_type = -1; 7289 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7290 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7291 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7292 ctx->flags = env->flags; 7293 #if defined(TARGET_PPC64) 7294 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7295 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7296 #endif 7297 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7298 || env->mmu_model & POWERPC_MMU_64; 7299 7300 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7301 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7302 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7303 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7304 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7305 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7306 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7307 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7308 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7309 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7310 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7311 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7312 7313 ctx->singlestep_enabled = 0; 7314 if ((hflags >> HFLAGS_SE) & 1) { 7315 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7316 ctx->base.max_insns = 1; 7317 } 7318 if ((hflags >> HFLAGS_BE) & 1) { 7319 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7320 } 7321 } 7322 7323 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7324 { 7325 } 7326 7327 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7328 { 7329 tcg_gen_insn_start(dcbase->pc_next); 7330 } 7331 7332 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7333 { 7334 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7335 return opc1(insn) == 1; 7336 } 7337 7338 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7339 { 7340 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7341 PowerPCCPU *cpu = POWERPC_CPU(cs); 7342 CPUPPCState *env = cs->env_ptr; 7343 target_ulong pc; 7344 uint32_t insn; 7345 bool ok; 7346 7347 LOG_DISAS("----------------\n"); 7348 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7349 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7350 7351 ctx->cia = pc = ctx->base.pc_next; 7352 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7353 ctx->base.pc_next = pc += 4; 7354 7355 if (!is_prefix_insn(ctx, insn)) { 7356 ok = (decode_insn32(ctx, insn) || 7357 decode_legacy(cpu, ctx, insn)); 7358 } else if ((pc & 63) == 0) { 7359 /* 7360 * Power v3.1, section 1.9 Exceptions: 7361 * attempt to execute a prefixed instruction that crosses a 7362 * 64-byte address boundary (system alignment error). 7363 */ 7364 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7365 ok = true; 7366 } else { 7367 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7368 need_byteswap(ctx)); 7369 ctx->base.pc_next = pc += 4; 7370 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7371 } 7372 if (!ok) { 7373 gen_invalid(ctx); 7374 } 7375 7376 /* End the TB when crossing a page boundary. */ 7377 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7378 ctx->base.is_jmp = DISAS_TOO_MANY; 7379 } 7380 } 7381 7382 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7383 { 7384 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7385 DisasJumpType is_jmp = ctx->base.is_jmp; 7386 target_ulong nip = ctx->base.pc_next; 7387 7388 if (is_jmp == DISAS_NORETURN) { 7389 /* We have already exited the TB. */ 7390 return; 7391 } 7392 7393 /* Honor single stepping. */ 7394 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7395 && (nip <= 0x100 || nip > 0xf00)) { 7396 switch (is_jmp) { 7397 case DISAS_TOO_MANY: 7398 case DISAS_EXIT_UPDATE: 7399 case DISAS_CHAIN_UPDATE: 7400 gen_update_nip(ctx, nip); 7401 break; 7402 case DISAS_EXIT: 7403 case DISAS_CHAIN: 7404 break; 7405 default: 7406 g_assert_not_reached(); 7407 } 7408 7409 gen_debug_exception(ctx); 7410 return; 7411 } 7412 7413 switch (is_jmp) { 7414 case DISAS_TOO_MANY: 7415 if (use_goto_tb(ctx, nip)) { 7416 pmu_count_insns(ctx); 7417 tcg_gen_goto_tb(0); 7418 gen_update_nip(ctx, nip); 7419 tcg_gen_exit_tb(ctx->base.tb, 0); 7420 break; 7421 } 7422 /* fall through */ 7423 case DISAS_CHAIN_UPDATE: 7424 gen_update_nip(ctx, nip); 7425 /* fall through */ 7426 case DISAS_CHAIN: 7427 /* 7428 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7429 * CF_NO_GOTO_PTR is set. Count insns now. 7430 */ 7431 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7432 pmu_count_insns(ctx); 7433 } 7434 7435 tcg_gen_lookup_and_goto_ptr(); 7436 break; 7437 7438 case DISAS_EXIT_UPDATE: 7439 gen_update_nip(ctx, nip); 7440 /* fall through */ 7441 case DISAS_EXIT: 7442 pmu_count_insns(ctx); 7443 tcg_gen_exit_tb(NULL, 0); 7444 break; 7445 7446 default: 7447 g_assert_not_reached(); 7448 } 7449 } 7450 7451 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7452 CPUState *cs, FILE *logfile) 7453 { 7454 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7455 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7456 } 7457 7458 static const TranslatorOps ppc_tr_ops = { 7459 .init_disas_context = ppc_tr_init_disas_context, 7460 .tb_start = ppc_tr_tb_start, 7461 .insn_start = ppc_tr_insn_start, 7462 .translate_insn = ppc_tr_translate_insn, 7463 .tb_stop = ppc_tr_tb_stop, 7464 .disas_log = ppc_tr_disas_log, 7465 }; 7466 7467 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7468 target_ulong pc, void *host_pc) 7469 { 7470 DisasContext ctx; 7471 7472 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7473 } 7474