1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 static inline bool gen_serialize(DisasContext *ctx) 238 { 239 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240 /* Restart with exclusive lock. */ 241 gen_helper_exit_atomic(cpu_env); 242 ctx->base.is_jmp = DISAS_NORETURN; 243 return false; 244 } 245 return true; 246 } 247 248 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249 static inline bool gen_serialize_core(DisasContext *ctx) 250 { 251 if (ctx->flags & POWERPC_FLAG_SMT) { 252 return gen_serialize(ctx); 253 } 254 255 return true; 256 } 257 #endif 258 259 /* SPR load/store helpers */ 260 static inline void gen_load_spr(TCGv t, int reg) 261 { 262 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 263 } 264 265 static inline void gen_store_spr(int reg, TCGv t) 266 { 267 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 268 } 269 270 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271 { 272 if (ctx->need_access_type && ctx->access_type != access_type) { 273 tcg_gen_movi_i32(cpu_access_type, access_type); 274 ctx->access_type = access_type; 275 } 276 } 277 278 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279 { 280 if (NARROW_MODE(ctx)) { 281 nip = (uint32_t)nip; 282 } 283 tcg_gen_movi_tl(cpu_nip, nip); 284 } 285 286 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287 { 288 TCGv_i32 t0, t1; 289 290 /* 291 * These are all synchronous exceptions, we set the PC back to the 292 * faulting instruction 293 */ 294 gen_update_nip(ctx, ctx->cia); 295 t0 = tcg_constant_i32(excp); 296 t1 = tcg_constant_i32(error); 297 gen_helper_raise_exception_err(cpu_env, t0, t1); 298 ctx->base.is_jmp = DISAS_NORETURN; 299 } 300 301 static void gen_exception(DisasContext *ctx, uint32_t excp) 302 { 303 TCGv_i32 t0; 304 305 /* 306 * These are all synchronous exceptions, we set the PC back to the 307 * faulting instruction 308 */ 309 gen_update_nip(ctx, ctx->cia); 310 t0 = tcg_constant_i32(excp); 311 gen_helper_raise_exception(cpu_env, t0); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316 target_ulong nip) 317 { 318 TCGv_i32 t0; 319 320 gen_update_nip(ctx, nip); 321 t0 = tcg_constant_i32(excp); 322 gen_helper_raise_exception(cpu_env, t0); 323 ctx->base.is_jmp = DISAS_NORETURN; 324 } 325 326 #if !defined(CONFIG_USER_ONLY) 327 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 328 { 329 translator_io_start(&ctx->base); 330 gen_helper_ppc_maybe_interrupt(cpu_env); 331 } 332 #endif 333 334 /* 335 * Tells the caller what is the appropriate exception to generate and prepares 336 * SPR registers for this exception. 337 * 338 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339 * POWERPC_EXCP_DEBUG (on BookE). 340 */ 341 static uint32_t gen_prep_dbgex(DisasContext *ctx) 342 { 343 if (ctx->flags & POWERPC_FLAG_DE) { 344 target_ulong dbsr = 0; 345 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 346 dbsr = DBCR0_ICMP; 347 } else { 348 /* Must have been branch */ 349 dbsr = DBCR0_BRT; 350 } 351 TCGv t0 = tcg_temp_new(); 352 gen_load_spr(t0, SPR_BOOKE_DBSR); 353 tcg_gen_ori_tl(t0, t0, dbsr); 354 gen_store_spr(SPR_BOOKE_DBSR, t0); 355 return POWERPC_EXCP_DEBUG; 356 } else { 357 return POWERPC_EXCP_TRACE; 358 } 359 } 360 361 static void gen_debug_exception(DisasContext *ctx) 362 { 363 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 364 ctx->base.is_jmp = DISAS_NORETURN; 365 } 366 367 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368 { 369 /* Will be converted to program check if needed */ 370 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371 } 372 373 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374 { 375 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376 } 377 378 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379 { 380 /* Will be converted to program check if needed */ 381 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382 } 383 384 /*****************************************************************************/ 385 /* SPR READ/WRITE CALLBACKS */ 386 387 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 388 { 389 #if 0 390 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 391 printf("ERROR: try to access SPR %d !\n", sprn); 392 #endif 393 } 394 395 /* #define PPC_DUMP_SPR_ACCESSES */ 396 397 /* 398 * Generic callbacks: 399 * do nothing but store/retrieve spr value 400 */ 401 static void spr_load_dump_spr(int sprn) 402 { 403 #ifdef PPC_DUMP_SPR_ACCESSES 404 TCGv_i32 t0 = tcg_constant_i32(sprn); 405 gen_helper_load_dump_spr(cpu_env, t0); 406 #endif 407 } 408 409 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 410 { 411 gen_load_spr(cpu_gpr[gprn], sprn); 412 spr_load_dump_spr(sprn); 413 } 414 415 static void spr_store_dump_spr(int sprn) 416 { 417 #ifdef PPC_DUMP_SPR_ACCESSES 418 TCGv_i32 t0 = tcg_constant_i32(sprn); 419 gen_helper_store_dump_spr(cpu_env, t0); 420 #endif 421 } 422 423 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 424 { 425 gen_store_spr(sprn, cpu_gpr[gprn]); 426 spr_store_dump_spr(sprn); 427 } 428 429 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 430 { 431 #ifdef TARGET_PPC64 432 TCGv t0 = tcg_temp_new(); 433 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 434 gen_store_spr(sprn, t0); 435 spr_store_dump_spr(sprn); 436 #else 437 spr_write_generic(ctx, sprn, gprn); 438 #endif 439 } 440 441 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442 { 443 /* This does not implement >1 thread */ 444 TCGv t0 = tcg_temp_new(); 445 TCGv t1 = tcg_temp_new(); 446 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448 tcg_gen_or_tl(t1, t1, t0); 449 gen_store_spr(sprn, t1); 450 } 451 452 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453 { 454 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 455 spr_write_CTRL_ST(ctx, sprn, gprn); 456 goto out; 457 } 458 459 if (!gen_serialize(ctx)) { 460 return; 461 } 462 463 gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 464 cpu_gpr[gprn]); 465 out: 466 spr_store_dump_spr(sprn); 467 468 /* 469 * SPR_CTRL writes must force a new translation block, 470 * allowing the PMU to calculate the run latch events with 471 * more accuracy. 472 */ 473 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 474 } 475 476 #if !defined(CONFIG_USER_ONLY) 477 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 478 { 479 TCGv t0 = tcg_temp_new(); 480 TCGv t1 = tcg_temp_new(); 481 gen_load_spr(t0, sprn); 482 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 483 tcg_gen_and_tl(t0, t0, t1); 484 gen_store_spr(sprn, t0); 485 } 486 487 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 488 { 489 } 490 491 #endif 492 493 /* SPR common to all PowerPC */ 494 /* XER */ 495 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 496 { 497 TCGv dst = cpu_gpr[gprn]; 498 TCGv t0 = tcg_temp_new(); 499 TCGv t1 = tcg_temp_new(); 500 TCGv t2 = tcg_temp_new(); 501 tcg_gen_mov_tl(dst, cpu_xer); 502 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 503 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 504 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 505 tcg_gen_or_tl(t0, t0, t1); 506 tcg_gen_or_tl(dst, dst, t2); 507 tcg_gen_or_tl(dst, dst, t0); 508 if (is_isa300(ctx)) { 509 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 510 tcg_gen_or_tl(dst, dst, t0); 511 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 512 tcg_gen_or_tl(dst, dst, t0); 513 } 514 } 515 516 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 517 { 518 TCGv src = cpu_gpr[gprn]; 519 /* Write all flags, while reading back check for isa300 */ 520 tcg_gen_andi_tl(cpu_xer, src, 521 ~((1u << XER_SO) | 522 (1u << XER_OV) | (1u << XER_OV32) | 523 (1u << XER_CA) | (1u << XER_CA32))); 524 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 525 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 526 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 527 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 528 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 529 } 530 531 /* LR */ 532 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 533 { 534 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 535 } 536 537 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 538 { 539 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 540 } 541 542 /* CFAR */ 543 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 544 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 545 { 546 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 547 } 548 549 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 550 { 551 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 552 } 553 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 554 555 /* CTR */ 556 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 557 { 558 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 559 } 560 561 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 562 { 563 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 564 } 565 566 /* User read access to SPR */ 567 /* USPRx */ 568 /* UMMCRx */ 569 /* UPMCx */ 570 /* USIA */ 571 /* UDECR */ 572 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 573 { 574 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 575 } 576 577 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 578 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 579 { 580 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 581 } 582 #endif 583 584 /* SPR common to all non-embedded PowerPC */ 585 /* DECR */ 586 #if !defined(CONFIG_USER_ONLY) 587 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 588 { 589 translator_io_start(&ctx->base); 590 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 591 } 592 593 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 594 { 595 translator_io_start(&ctx->base); 596 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 597 } 598 #endif 599 600 /* SPR common to all non-embedded PowerPC, except 601 */ 601 /* Time base */ 602 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 603 { 604 translator_io_start(&ctx->base); 605 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 606 } 607 608 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 609 { 610 translator_io_start(&ctx->base); 611 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 612 } 613 614 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 615 { 616 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 617 } 618 619 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 620 { 621 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 622 } 623 624 #if !defined(CONFIG_USER_ONLY) 625 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 626 { 627 translator_io_start(&ctx->base); 628 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 629 } 630 631 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 632 { 633 translator_io_start(&ctx->base); 634 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 635 } 636 637 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 638 { 639 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 640 } 641 642 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 643 { 644 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 645 } 646 647 #if defined(TARGET_PPC64) 648 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 649 { 650 translator_io_start(&ctx->base); 651 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 652 } 653 654 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 655 { 656 translator_io_start(&ctx->base); 657 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 658 } 659 660 /* HDECR */ 661 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 662 { 663 translator_io_start(&ctx->base); 664 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 665 } 666 667 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 668 { 669 translator_io_start(&ctx->base); 670 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 671 } 672 673 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 674 { 675 translator_io_start(&ctx->base); 676 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 677 } 678 679 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 680 { 681 translator_io_start(&ctx->base); 682 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 683 } 684 685 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 686 { 687 translator_io_start(&ctx->base); 688 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 689 } 690 691 #endif 692 #endif 693 694 #if !defined(CONFIG_USER_ONLY) 695 /* IBAT0U...IBAT0U */ 696 /* IBAT0L...IBAT7L */ 697 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 698 { 699 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 700 offsetof(CPUPPCState, 701 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 702 } 703 704 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 705 { 706 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 707 offsetof(CPUPPCState, 708 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 709 } 710 711 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 712 { 713 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 714 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 715 } 716 717 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 718 { 719 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 720 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 721 } 722 723 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 724 { 725 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 726 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 727 } 728 729 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 730 { 731 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 732 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 733 } 734 735 /* DBAT0U...DBAT7U */ 736 /* DBAT0L...DBAT7L */ 737 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 738 { 739 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 740 offsetof(CPUPPCState, 741 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 742 } 743 744 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 745 { 746 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 747 offsetof(CPUPPCState, 748 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 749 } 750 751 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 752 { 753 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 754 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 755 } 756 757 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 758 { 759 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 760 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 761 } 762 763 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 764 { 765 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 766 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 767 } 768 769 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 770 { 771 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 772 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 773 } 774 775 /* SDR1 */ 776 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 777 { 778 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 779 } 780 781 #if defined(TARGET_PPC64) 782 /* 64 bits PowerPC specific SPRs */ 783 /* PIDR */ 784 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 785 { 786 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 787 } 788 789 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 790 { 791 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 792 } 793 794 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 795 { 796 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 797 } 798 799 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 800 { 801 TCGv t0 = tcg_temp_new(); 802 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 803 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 804 } 805 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 806 { 807 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 808 } 809 810 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 811 { 812 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 813 } 814 815 /* DPDES */ 816 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 817 { 818 if (!gen_serialize_core(ctx)) { 819 return; 820 } 821 822 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 823 } 824 825 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 826 { 827 if (!gen_serialize_core(ctx)) { 828 return; 829 } 830 831 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 832 } 833 #endif 834 #endif 835 836 /* PowerPC 40x specific registers */ 837 #if !defined(CONFIG_USER_ONLY) 838 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 839 { 840 translator_io_start(&ctx->base); 841 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 842 } 843 844 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 845 { 846 translator_io_start(&ctx->base); 847 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 848 } 849 850 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 851 { 852 translator_io_start(&ctx->base); 853 gen_store_spr(sprn, cpu_gpr[gprn]); 854 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 855 /* We must stop translation as we may have rebooted */ 856 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 857 } 858 859 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 860 { 861 translator_io_start(&ctx->base); 862 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 863 } 864 865 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 866 { 867 translator_io_start(&ctx->base); 868 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 869 } 870 871 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 872 { 873 translator_io_start(&ctx->base); 874 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 875 } 876 877 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 878 { 879 TCGv t0 = tcg_temp_new(); 880 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 881 gen_helper_store_40x_pid(cpu_env, t0); 882 } 883 884 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 885 { 886 translator_io_start(&ctx->base); 887 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 888 } 889 890 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 891 { 892 translator_io_start(&ctx->base); 893 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 894 } 895 #endif 896 897 /* PIR */ 898 #if !defined(CONFIG_USER_ONLY) 899 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 900 { 901 TCGv t0 = tcg_temp_new(); 902 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 903 gen_store_spr(SPR_PIR, t0); 904 } 905 #endif 906 907 /* SPE specific registers */ 908 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 909 { 910 TCGv_i32 t0 = tcg_temp_new_i32(); 911 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 912 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 913 } 914 915 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 916 { 917 TCGv_i32 t0 = tcg_temp_new_i32(); 918 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 919 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 920 } 921 922 #if !defined(CONFIG_USER_ONLY) 923 /* Callback used to write the exception vector base */ 924 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 925 { 926 TCGv t0 = tcg_temp_new(); 927 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 928 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 929 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 930 gen_store_spr(sprn, t0); 931 } 932 933 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 934 { 935 int sprn_offs; 936 937 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 938 sprn_offs = sprn - SPR_BOOKE_IVOR0; 939 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 940 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 941 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 942 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 943 } else { 944 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 945 " vector 0x%03x\n", sprn); 946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 947 return; 948 } 949 950 TCGv t0 = tcg_temp_new(); 951 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 952 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 953 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 954 gen_store_spr(sprn, t0); 955 } 956 #endif 957 958 #ifdef TARGET_PPC64 959 #ifndef CONFIG_USER_ONLY 960 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 961 { 962 TCGv t0 = tcg_temp_new(); 963 TCGv t1 = tcg_temp_new(); 964 TCGv t2 = tcg_temp_new(); 965 966 /* 967 * Note, the HV=1 PR=0 case is handled earlier by simply using 968 * spr_write_generic for HV mode in the SPR table 969 */ 970 971 /* Build insertion mask into t1 based on context */ 972 if (ctx->pr) { 973 gen_load_spr(t1, SPR_UAMOR); 974 } else { 975 gen_load_spr(t1, SPR_AMOR); 976 } 977 978 /* Mask new bits into t2 */ 979 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 980 981 /* Load AMR and clear new bits in t0 */ 982 gen_load_spr(t0, SPR_AMR); 983 tcg_gen_andc_tl(t0, t0, t1); 984 985 /* Or'in new bits and write it out */ 986 tcg_gen_or_tl(t0, t0, t2); 987 gen_store_spr(SPR_AMR, t0); 988 spr_store_dump_spr(SPR_AMR); 989 } 990 991 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 992 { 993 TCGv t0 = tcg_temp_new(); 994 TCGv t1 = tcg_temp_new(); 995 TCGv t2 = tcg_temp_new(); 996 997 /* 998 * Note, the HV=1 case is handled earlier by simply using 999 * spr_write_generic for HV mode in the SPR table 1000 */ 1001 1002 /* Build insertion mask into t1 based on context */ 1003 gen_load_spr(t1, SPR_AMOR); 1004 1005 /* Mask new bits into t2 */ 1006 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1007 1008 /* Load AMR and clear new bits in t0 */ 1009 gen_load_spr(t0, SPR_UAMOR); 1010 tcg_gen_andc_tl(t0, t0, t1); 1011 1012 /* Or'in new bits and write it out */ 1013 tcg_gen_or_tl(t0, t0, t2); 1014 gen_store_spr(SPR_UAMOR, t0); 1015 spr_store_dump_spr(SPR_UAMOR); 1016 } 1017 1018 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1019 { 1020 TCGv t0 = tcg_temp_new(); 1021 TCGv t1 = tcg_temp_new(); 1022 TCGv t2 = tcg_temp_new(); 1023 1024 /* 1025 * Note, the HV=1 case is handled earlier by simply using 1026 * spr_write_generic for HV mode in the SPR table 1027 */ 1028 1029 /* Build insertion mask into t1 based on context */ 1030 gen_load_spr(t1, SPR_AMOR); 1031 1032 /* Mask new bits into t2 */ 1033 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1034 1035 /* Load AMR and clear new bits in t0 */ 1036 gen_load_spr(t0, SPR_IAMR); 1037 tcg_gen_andc_tl(t0, t0, t1); 1038 1039 /* Or'in new bits and write it out */ 1040 tcg_gen_or_tl(t0, t0, t2); 1041 gen_store_spr(SPR_IAMR, t0); 1042 spr_store_dump_spr(SPR_IAMR); 1043 } 1044 #endif 1045 #endif 1046 1047 #ifndef CONFIG_USER_ONLY 1048 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1049 { 1050 gen_helper_fixup_thrm(cpu_env); 1051 gen_load_spr(cpu_gpr[gprn], sprn); 1052 spr_load_dump_spr(sprn); 1053 } 1054 #endif /* !CONFIG_USER_ONLY */ 1055 1056 #if !defined(CONFIG_USER_ONLY) 1057 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1058 { 1059 TCGv t0 = tcg_temp_new(); 1060 1061 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1062 gen_store_spr(sprn, t0); 1063 } 1064 1065 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1066 { 1067 TCGv t0 = tcg_temp_new(); 1068 1069 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1070 gen_store_spr(sprn, t0); 1071 } 1072 1073 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1074 { 1075 TCGv t0 = tcg_temp_new(); 1076 1077 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1078 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1079 gen_store_spr(sprn, t0); 1080 } 1081 1082 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1083 { 1084 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1085 } 1086 1087 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1088 { 1089 TCGv_i32 t0 = tcg_constant_i32(sprn); 1090 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1091 } 1092 1093 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1094 { 1095 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1096 } 1097 1098 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1099 { 1100 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1101 } 1102 1103 #endif 1104 1105 #if !defined(CONFIG_USER_ONLY) 1106 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1107 { 1108 TCGv val = tcg_temp_new(); 1109 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1110 gen_store_spr(SPR_BOOKE_MAS3, val); 1111 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1112 gen_store_spr(SPR_BOOKE_MAS7, val); 1113 } 1114 1115 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1116 { 1117 TCGv mas7 = tcg_temp_new(); 1118 TCGv mas3 = tcg_temp_new(); 1119 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1120 tcg_gen_shli_tl(mas7, mas7, 32); 1121 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1122 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1123 } 1124 1125 #endif 1126 1127 #ifdef TARGET_PPC64 1128 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1129 int bit, int sprn, int cause) 1130 { 1131 TCGv_i32 t1 = tcg_constant_i32(bit); 1132 TCGv_i32 t2 = tcg_constant_i32(sprn); 1133 TCGv_i32 t3 = tcg_constant_i32(cause); 1134 1135 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1136 } 1137 1138 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1139 int bit, int sprn, int cause) 1140 { 1141 TCGv_i32 t1 = tcg_constant_i32(bit); 1142 TCGv_i32 t2 = tcg_constant_i32(sprn); 1143 TCGv_i32 t3 = tcg_constant_i32(cause); 1144 1145 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1146 } 1147 1148 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1149 { 1150 TCGv spr_up = tcg_temp_new(); 1151 TCGv spr = tcg_temp_new(); 1152 1153 gen_load_spr(spr, sprn - 1); 1154 tcg_gen_shri_tl(spr_up, spr, 32); 1155 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1156 } 1157 1158 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1159 { 1160 TCGv spr = tcg_temp_new(); 1161 1162 gen_load_spr(spr, sprn - 1); 1163 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1164 gen_store_spr(sprn - 1, spr); 1165 } 1166 1167 #if !defined(CONFIG_USER_ONLY) 1168 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1169 { 1170 TCGv hmer = tcg_temp_new(); 1171 1172 gen_load_spr(hmer, sprn); 1173 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1174 gen_store_spr(sprn, hmer); 1175 spr_store_dump_spr(sprn); 1176 } 1177 1178 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1179 { 1180 gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1181 } 1182 1183 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1184 { 1185 gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1186 } 1187 1188 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1189 { 1190 translator_io_start(&ctx->base); 1191 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1192 } 1193 #endif /* !defined(CONFIG_USER_ONLY) */ 1194 1195 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1196 { 1197 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1198 spr_read_generic(ctx, gprn, sprn); 1199 } 1200 1201 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1202 { 1203 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1204 spr_write_generic(ctx, sprn, gprn); 1205 } 1206 1207 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1208 { 1209 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1210 spr_read_generic(ctx, gprn, sprn); 1211 } 1212 1213 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1214 { 1215 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1216 spr_write_generic(ctx, sprn, gprn); 1217 } 1218 1219 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1220 { 1221 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1222 spr_read_prev_upper32(ctx, gprn, sprn); 1223 } 1224 1225 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1226 { 1227 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1228 spr_write_prev_upper32(ctx, sprn, gprn); 1229 } 1230 1231 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1232 { 1233 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1234 spr_read_generic(ctx, gprn, sprn); 1235 } 1236 1237 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1238 { 1239 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1240 spr_write_generic(ctx, sprn, gprn); 1241 } 1242 1243 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1244 { 1245 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1246 spr_read_prev_upper32(ctx, gprn, sprn); 1247 } 1248 1249 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1250 { 1251 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1252 spr_write_prev_upper32(ctx, sprn, gprn); 1253 } 1254 1255 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1256 { 1257 TCGv t0 = tcg_temp_new(); 1258 1259 /* 1260 * Access to the (H)DEXCR in problem state is done using separated 1261 * SPR indexes which are 16 below the SPR indexes which have full 1262 * access to the (H)DEXCR in privileged state. Problem state can 1263 * only read bits 32:63, bits 0:31 return 0. 1264 * 1265 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1266 */ 1267 1268 gen_load_spr(t0, sprn + 16); 1269 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1270 } 1271 #endif 1272 1273 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1274 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1275 1276 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1277 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1278 1279 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1280 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1281 1282 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1283 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1284 1285 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1286 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1287 1288 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1289 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1290 1291 typedef struct opcode_t { 1292 unsigned char opc1, opc2, opc3, opc4; 1293 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1294 unsigned char pad[4]; 1295 #endif 1296 opc_handler_t handler; 1297 const char *oname; 1298 } opcode_t; 1299 1300 static void gen_priv_opc(DisasContext *ctx) 1301 { 1302 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1303 } 1304 1305 /* Helpers for priv. check */ 1306 #define GEN_PRIV(CTX) \ 1307 do { \ 1308 gen_priv_opc(CTX); return; \ 1309 } while (0) 1310 1311 #if defined(CONFIG_USER_ONLY) 1312 #define CHK_HV(CTX) GEN_PRIV(CTX) 1313 #define CHK_SV(CTX) GEN_PRIV(CTX) 1314 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1315 #else 1316 #define CHK_HV(CTX) \ 1317 do { \ 1318 if (unlikely(ctx->pr || !ctx->hv)) {\ 1319 GEN_PRIV(CTX); \ 1320 } \ 1321 } while (0) 1322 #define CHK_SV(CTX) \ 1323 do { \ 1324 if (unlikely(ctx->pr)) { \ 1325 GEN_PRIV(CTX); \ 1326 } \ 1327 } while (0) 1328 #define CHK_HVRM(CTX) \ 1329 do { \ 1330 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1331 GEN_PRIV(CTX); \ 1332 } \ 1333 } while (0) 1334 #endif 1335 1336 #define CHK_NONE(CTX) 1337 1338 /*****************************************************************************/ 1339 /* PowerPC instructions table */ 1340 1341 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1342 { \ 1343 .opc1 = op1, \ 1344 .opc2 = op2, \ 1345 .opc3 = op3, \ 1346 .opc4 = 0xff, \ 1347 .handler = { \ 1348 .inval1 = invl, \ 1349 .type = _typ, \ 1350 .type2 = _typ2, \ 1351 .handler = &gen_##name, \ 1352 }, \ 1353 .oname = stringify(name), \ 1354 } 1355 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1356 { \ 1357 .opc1 = op1, \ 1358 .opc2 = op2, \ 1359 .opc3 = op3, \ 1360 .opc4 = 0xff, \ 1361 .handler = { \ 1362 .inval1 = invl1, \ 1363 .inval2 = invl2, \ 1364 .type = _typ, \ 1365 .type2 = _typ2, \ 1366 .handler = &gen_##name, \ 1367 }, \ 1368 .oname = stringify(name), \ 1369 } 1370 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1371 { \ 1372 .opc1 = op1, \ 1373 .opc2 = op2, \ 1374 .opc3 = op3, \ 1375 .opc4 = 0xff, \ 1376 .handler = { \ 1377 .inval1 = invl, \ 1378 .type = _typ, \ 1379 .type2 = _typ2, \ 1380 .handler = &gen_##name, \ 1381 }, \ 1382 .oname = onam, \ 1383 } 1384 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1385 { \ 1386 .opc1 = op1, \ 1387 .opc2 = op2, \ 1388 .opc3 = op3, \ 1389 .opc4 = op4, \ 1390 .handler = { \ 1391 .inval1 = invl, \ 1392 .type = _typ, \ 1393 .type2 = _typ2, \ 1394 .handler = &gen_##name, \ 1395 }, \ 1396 .oname = stringify(name), \ 1397 } 1398 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399 { \ 1400 .opc1 = op1, \ 1401 .opc2 = op2, \ 1402 .opc3 = op3, \ 1403 .opc4 = op4, \ 1404 .handler = { \ 1405 .inval1 = invl, \ 1406 .type = _typ, \ 1407 .type2 = _typ2, \ 1408 .handler = &gen_##name, \ 1409 }, \ 1410 .oname = onam, \ 1411 } 1412 1413 /* Invalid instruction */ 1414 static void gen_invalid(DisasContext *ctx) 1415 { 1416 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1417 } 1418 1419 static opc_handler_t invalid_handler = { 1420 .inval1 = 0xFFFFFFFF, 1421 .inval2 = 0xFFFFFFFF, 1422 .type = PPC_NONE, 1423 .type2 = PPC_NONE, 1424 .handler = gen_invalid, 1425 }; 1426 1427 /*** Integer comparison ***/ 1428 1429 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1430 { 1431 TCGv t0 = tcg_temp_new(); 1432 TCGv t1 = tcg_temp_new(); 1433 TCGv_i32 t = tcg_temp_new_i32(); 1434 1435 tcg_gen_movi_tl(t0, CRF_EQ); 1436 tcg_gen_movi_tl(t1, CRF_LT); 1437 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1438 t0, arg0, arg1, t1, t0); 1439 tcg_gen_movi_tl(t1, CRF_GT); 1440 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1441 t0, arg0, arg1, t1, t0); 1442 1443 tcg_gen_trunc_tl_i32(t, t0); 1444 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1445 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1446 } 1447 1448 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1449 { 1450 TCGv t0 = tcg_constant_tl(arg1); 1451 gen_op_cmp(arg0, t0, s, crf); 1452 } 1453 1454 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1455 { 1456 TCGv t0, t1; 1457 t0 = tcg_temp_new(); 1458 t1 = tcg_temp_new(); 1459 if (s) { 1460 tcg_gen_ext32s_tl(t0, arg0); 1461 tcg_gen_ext32s_tl(t1, arg1); 1462 } else { 1463 tcg_gen_ext32u_tl(t0, arg0); 1464 tcg_gen_ext32u_tl(t1, arg1); 1465 } 1466 gen_op_cmp(t0, t1, s, crf); 1467 } 1468 1469 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1470 { 1471 TCGv t0 = tcg_constant_tl(arg1); 1472 gen_op_cmp32(arg0, t0, s, crf); 1473 } 1474 1475 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1476 { 1477 if (NARROW_MODE(ctx)) { 1478 gen_op_cmpi32(reg, 0, 1, 0); 1479 } else { 1480 gen_op_cmpi(reg, 0, 1, 0); 1481 } 1482 } 1483 1484 /* cmprb - range comparison: isupper, isaplha, islower*/ 1485 static void gen_cmprb(DisasContext *ctx) 1486 { 1487 TCGv_i32 src1 = tcg_temp_new_i32(); 1488 TCGv_i32 src2 = tcg_temp_new_i32(); 1489 TCGv_i32 src2lo = tcg_temp_new_i32(); 1490 TCGv_i32 src2hi = tcg_temp_new_i32(); 1491 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1492 1493 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1494 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1495 1496 tcg_gen_andi_i32(src1, src1, 0xFF); 1497 tcg_gen_ext8u_i32(src2lo, src2); 1498 tcg_gen_shri_i32(src2, src2, 8); 1499 tcg_gen_ext8u_i32(src2hi, src2); 1500 1501 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1502 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1503 tcg_gen_and_i32(crf, src2lo, src2hi); 1504 1505 if (ctx->opcode & 0x00200000) { 1506 tcg_gen_shri_i32(src2, src2, 8); 1507 tcg_gen_ext8u_i32(src2lo, src2); 1508 tcg_gen_shri_i32(src2, src2, 8); 1509 tcg_gen_ext8u_i32(src2hi, src2); 1510 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1511 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1512 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1513 tcg_gen_or_i32(crf, crf, src2lo); 1514 } 1515 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1516 } 1517 1518 #if defined(TARGET_PPC64) 1519 /* cmpeqb */ 1520 static void gen_cmpeqb(DisasContext *ctx) 1521 { 1522 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1523 cpu_gpr[rB(ctx->opcode)]); 1524 } 1525 #endif 1526 1527 /* isel (PowerPC 2.03 specification) */ 1528 static void gen_isel(DisasContext *ctx) 1529 { 1530 uint32_t bi = rC(ctx->opcode); 1531 uint32_t mask = 0x08 >> (bi & 0x03); 1532 TCGv t0 = tcg_temp_new(); 1533 TCGv zr; 1534 1535 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1536 tcg_gen_andi_tl(t0, t0, mask); 1537 1538 zr = tcg_constant_tl(0); 1539 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1540 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1541 cpu_gpr[rB(ctx->opcode)]); 1542 } 1543 1544 /* cmpb: PowerPC 2.05 specification */ 1545 static void gen_cmpb(DisasContext *ctx) 1546 { 1547 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1548 cpu_gpr[rB(ctx->opcode)]); 1549 } 1550 1551 /*** Integer arithmetic ***/ 1552 1553 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1554 TCGv arg1, TCGv arg2, int sub) 1555 { 1556 TCGv t0 = tcg_temp_new(); 1557 1558 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1559 tcg_gen_xor_tl(t0, arg1, arg2); 1560 if (sub) { 1561 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1562 } else { 1563 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1564 } 1565 if (NARROW_MODE(ctx)) { 1566 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1567 if (is_isa300(ctx)) { 1568 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1569 } 1570 } else { 1571 if (is_isa300(ctx)) { 1572 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1573 } 1574 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1575 } 1576 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1577 } 1578 1579 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1580 TCGv res, TCGv arg0, TCGv arg1, 1581 TCGv ca32, int sub) 1582 { 1583 TCGv t0; 1584 1585 if (!is_isa300(ctx)) { 1586 return; 1587 } 1588 1589 t0 = tcg_temp_new(); 1590 if (sub) { 1591 tcg_gen_eqv_tl(t0, arg0, arg1); 1592 } else { 1593 tcg_gen_xor_tl(t0, arg0, arg1); 1594 } 1595 tcg_gen_xor_tl(t0, t0, res); 1596 tcg_gen_extract_tl(ca32, t0, 32, 1); 1597 } 1598 1599 /* Common add function */ 1600 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1601 TCGv arg2, TCGv ca, TCGv ca32, 1602 bool add_ca, bool compute_ca, 1603 bool compute_ov, bool compute_rc0) 1604 { 1605 TCGv t0 = ret; 1606 1607 if (compute_ca || compute_ov) { 1608 t0 = tcg_temp_new(); 1609 } 1610 1611 if (compute_ca) { 1612 if (NARROW_MODE(ctx)) { 1613 /* 1614 * Caution: a non-obvious corner case of the spec is that 1615 * we must produce the *entire* 64-bit addition, but 1616 * produce the carry into bit 32. 1617 */ 1618 TCGv t1 = tcg_temp_new(); 1619 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1620 tcg_gen_add_tl(t0, arg1, arg2); 1621 if (add_ca) { 1622 tcg_gen_add_tl(t0, t0, ca); 1623 } 1624 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1625 tcg_gen_extract_tl(ca, ca, 32, 1); 1626 if (is_isa300(ctx)) { 1627 tcg_gen_mov_tl(ca32, ca); 1628 } 1629 } else { 1630 TCGv zero = tcg_constant_tl(0); 1631 if (add_ca) { 1632 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1633 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1634 } else { 1635 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1636 } 1637 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1638 } 1639 } else { 1640 tcg_gen_add_tl(t0, arg1, arg2); 1641 if (add_ca) { 1642 tcg_gen_add_tl(t0, t0, ca); 1643 } 1644 } 1645 1646 if (compute_ov) { 1647 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1648 } 1649 if (unlikely(compute_rc0)) { 1650 gen_set_Rc0(ctx, t0); 1651 } 1652 1653 if (t0 != ret) { 1654 tcg_gen_mov_tl(ret, t0); 1655 } 1656 } 1657 /* Add functions with two operands */ 1658 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1659 static void glue(gen_, name)(DisasContext *ctx) \ 1660 { \ 1661 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1662 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1663 ca, glue(ca, 32), \ 1664 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1665 } 1666 /* Add functions with one operand and one immediate */ 1667 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1668 add_ca, compute_ca, compute_ov) \ 1669 static void glue(gen_, name)(DisasContext *ctx) \ 1670 { \ 1671 TCGv t0 = tcg_constant_tl(const_val); \ 1672 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1673 cpu_gpr[rA(ctx->opcode)], t0, \ 1674 ca, glue(ca, 32), \ 1675 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1676 } 1677 1678 /* add add. addo addo. */ 1679 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1680 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1681 /* addc addc. addco addco. */ 1682 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1683 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1684 /* adde adde. addeo addeo. */ 1685 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1686 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1687 /* addme addme. addmeo addmeo. */ 1688 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1689 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1690 /* addex */ 1691 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1692 /* addze addze. addzeo addzeo.*/ 1693 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1694 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1695 /* addic addic.*/ 1696 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1697 { 1698 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1699 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1700 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1701 } 1702 1703 static void gen_addic(DisasContext *ctx) 1704 { 1705 gen_op_addic(ctx, 0); 1706 } 1707 1708 static void gen_addic_(DisasContext *ctx) 1709 { 1710 gen_op_addic(ctx, 1); 1711 } 1712 1713 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1714 TCGv arg2, int sign, int compute_ov) 1715 { 1716 TCGv_i32 t0 = tcg_temp_new_i32(); 1717 TCGv_i32 t1 = tcg_temp_new_i32(); 1718 TCGv_i32 t2 = tcg_temp_new_i32(); 1719 TCGv_i32 t3 = tcg_temp_new_i32(); 1720 1721 tcg_gen_trunc_tl_i32(t0, arg1); 1722 tcg_gen_trunc_tl_i32(t1, arg2); 1723 if (sign) { 1724 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1725 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1726 tcg_gen_and_i32(t2, t2, t3); 1727 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1728 tcg_gen_or_i32(t2, t2, t3); 1729 tcg_gen_movi_i32(t3, 0); 1730 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1731 tcg_gen_div_i32(t3, t0, t1); 1732 tcg_gen_extu_i32_tl(ret, t3); 1733 } else { 1734 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1735 tcg_gen_movi_i32(t3, 0); 1736 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1737 tcg_gen_divu_i32(t3, t0, t1); 1738 tcg_gen_extu_i32_tl(ret, t3); 1739 } 1740 if (compute_ov) { 1741 tcg_gen_extu_i32_tl(cpu_ov, t2); 1742 if (is_isa300(ctx)) { 1743 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1744 } 1745 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1746 } 1747 1748 if (unlikely(Rc(ctx->opcode) != 0)) { 1749 gen_set_Rc0(ctx, ret); 1750 } 1751 } 1752 /* Div functions */ 1753 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1754 static void glue(gen_, name)(DisasContext *ctx) \ 1755 { \ 1756 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1757 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1758 sign, compute_ov); \ 1759 } 1760 /* divwu divwu. divwuo divwuo. */ 1761 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1762 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1763 /* divw divw. divwo divwo. */ 1764 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1765 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1766 1767 /* div[wd]eu[o][.] */ 1768 #define GEN_DIVE(name, hlpr, compute_ov) \ 1769 static void gen_##name(DisasContext *ctx) \ 1770 { \ 1771 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1772 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1773 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1774 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1775 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1776 } \ 1777 } 1778 1779 GEN_DIVE(divweu, divweu, 0); 1780 GEN_DIVE(divweuo, divweu, 1); 1781 GEN_DIVE(divwe, divwe, 0); 1782 GEN_DIVE(divweo, divwe, 1); 1783 1784 #if defined(TARGET_PPC64) 1785 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1786 TCGv arg2, int sign, int compute_ov) 1787 { 1788 TCGv_i64 t0 = tcg_temp_new_i64(); 1789 TCGv_i64 t1 = tcg_temp_new_i64(); 1790 TCGv_i64 t2 = tcg_temp_new_i64(); 1791 TCGv_i64 t3 = tcg_temp_new_i64(); 1792 1793 tcg_gen_mov_i64(t0, arg1); 1794 tcg_gen_mov_i64(t1, arg2); 1795 if (sign) { 1796 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1797 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1798 tcg_gen_and_i64(t2, t2, t3); 1799 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1800 tcg_gen_or_i64(t2, t2, t3); 1801 tcg_gen_movi_i64(t3, 0); 1802 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1803 tcg_gen_div_i64(ret, t0, t1); 1804 } else { 1805 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1806 tcg_gen_movi_i64(t3, 0); 1807 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1808 tcg_gen_divu_i64(ret, t0, t1); 1809 } 1810 if (compute_ov) { 1811 tcg_gen_mov_tl(cpu_ov, t2); 1812 if (is_isa300(ctx)) { 1813 tcg_gen_mov_tl(cpu_ov32, t2); 1814 } 1815 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1816 } 1817 1818 if (unlikely(Rc(ctx->opcode) != 0)) { 1819 gen_set_Rc0(ctx, ret); 1820 } 1821 } 1822 1823 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1824 static void glue(gen_, name)(DisasContext *ctx) \ 1825 { \ 1826 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1827 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1828 sign, compute_ov); \ 1829 } 1830 /* divdu divdu. divduo divduo. */ 1831 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1832 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1833 /* divd divd. divdo divdo. */ 1834 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1835 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1836 1837 GEN_DIVE(divdeu, divdeu, 0); 1838 GEN_DIVE(divdeuo, divdeu, 1); 1839 GEN_DIVE(divde, divde, 0); 1840 GEN_DIVE(divdeo, divde, 1); 1841 #endif 1842 1843 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1844 TCGv arg2, int sign) 1845 { 1846 TCGv_i32 t0 = tcg_temp_new_i32(); 1847 TCGv_i32 t1 = tcg_temp_new_i32(); 1848 1849 tcg_gen_trunc_tl_i32(t0, arg1); 1850 tcg_gen_trunc_tl_i32(t1, arg2); 1851 if (sign) { 1852 TCGv_i32 t2 = tcg_temp_new_i32(); 1853 TCGv_i32 t3 = tcg_temp_new_i32(); 1854 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1855 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1856 tcg_gen_and_i32(t2, t2, t3); 1857 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1858 tcg_gen_or_i32(t2, t2, t3); 1859 tcg_gen_movi_i32(t3, 0); 1860 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1861 tcg_gen_rem_i32(t3, t0, t1); 1862 tcg_gen_ext_i32_tl(ret, t3); 1863 } else { 1864 TCGv_i32 t2 = tcg_constant_i32(1); 1865 TCGv_i32 t3 = tcg_constant_i32(0); 1866 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1867 tcg_gen_remu_i32(t0, t0, t1); 1868 tcg_gen_extu_i32_tl(ret, t0); 1869 } 1870 } 1871 1872 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1873 static void glue(gen_, name)(DisasContext *ctx) \ 1874 { \ 1875 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1876 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1877 sign); \ 1878 } 1879 1880 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1881 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1882 1883 #if defined(TARGET_PPC64) 1884 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1885 TCGv arg2, int sign) 1886 { 1887 TCGv_i64 t0 = tcg_temp_new_i64(); 1888 TCGv_i64 t1 = tcg_temp_new_i64(); 1889 1890 tcg_gen_mov_i64(t0, arg1); 1891 tcg_gen_mov_i64(t1, arg2); 1892 if (sign) { 1893 TCGv_i64 t2 = tcg_temp_new_i64(); 1894 TCGv_i64 t3 = tcg_temp_new_i64(); 1895 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1896 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1897 tcg_gen_and_i64(t2, t2, t3); 1898 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1899 tcg_gen_or_i64(t2, t2, t3); 1900 tcg_gen_movi_i64(t3, 0); 1901 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1902 tcg_gen_rem_i64(ret, t0, t1); 1903 } else { 1904 TCGv_i64 t2 = tcg_constant_i64(1); 1905 TCGv_i64 t3 = tcg_constant_i64(0); 1906 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1907 tcg_gen_remu_i64(ret, t0, t1); 1908 } 1909 } 1910 1911 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1912 static void glue(gen_, name)(DisasContext *ctx) \ 1913 { \ 1914 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1916 sign); \ 1917 } 1918 1919 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1920 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1921 #endif 1922 1923 /* mulhw mulhw. */ 1924 static void gen_mulhw(DisasContext *ctx) 1925 { 1926 TCGv_i32 t0 = tcg_temp_new_i32(); 1927 TCGv_i32 t1 = tcg_temp_new_i32(); 1928 1929 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1930 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1931 tcg_gen_muls2_i32(t0, t1, t0, t1); 1932 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1933 if (unlikely(Rc(ctx->opcode) != 0)) { 1934 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1935 } 1936 } 1937 1938 /* mulhwu mulhwu. */ 1939 static void gen_mulhwu(DisasContext *ctx) 1940 { 1941 TCGv_i32 t0 = tcg_temp_new_i32(); 1942 TCGv_i32 t1 = tcg_temp_new_i32(); 1943 1944 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1945 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1946 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1947 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1948 if (unlikely(Rc(ctx->opcode) != 0)) { 1949 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1950 } 1951 } 1952 1953 /* mullw mullw. */ 1954 static void gen_mullw(DisasContext *ctx) 1955 { 1956 #if defined(TARGET_PPC64) 1957 TCGv_i64 t0, t1; 1958 t0 = tcg_temp_new_i64(); 1959 t1 = tcg_temp_new_i64(); 1960 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1961 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1962 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1963 #else 1964 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1965 cpu_gpr[rB(ctx->opcode)]); 1966 #endif 1967 if (unlikely(Rc(ctx->opcode) != 0)) { 1968 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1969 } 1970 } 1971 1972 /* mullwo mullwo. */ 1973 static void gen_mullwo(DisasContext *ctx) 1974 { 1975 TCGv_i32 t0 = tcg_temp_new_i32(); 1976 TCGv_i32 t1 = tcg_temp_new_i32(); 1977 1978 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1979 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1980 tcg_gen_muls2_i32(t0, t1, t0, t1); 1981 #if defined(TARGET_PPC64) 1982 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1983 #else 1984 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1985 #endif 1986 1987 tcg_gen_sari_i32(t0, t0, 31); 1988 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1989 tcg_gen_extu_i32_tl(cpu_ov, t0); 1990 if (is_isa300(ctx)) { 1991 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1992 } 1993 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1994 1995 if (unlikely(Rc(ctx->opcode) != 0)) { 1996 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1997 } 1998 } 1999 2000 /* mulli */ 2001 static void gen_mulli(DisasContext *ctx) 2002 { 2003 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2004 SIMM(ctx->opcode)); 2005 } 2006 2007 #if defined(TARGET_PPC64) 2008 /* mulhd mulhd. */ 2009 static void gen_mulhd(DisasContext *ctx) 2010 { 2011 TCGv lo = tcg_temp_new(); 2012 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2014 if (unlikely(Rc(ctx->opcode) != 0)) { 2015 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2016 } 2017 } 2018 2019 /* mulhdu mulhdu. */ 2020 static void gen_mulhdu(DisasContext *ctx) 2021 { 2022 TCGv lo = tcg_temp_new(); 2023 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2024 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2025 if (unlikely(Rc(ctx->opcode) != 0)) { 2026 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2027 } 2028 } 2029 2030 /* mulld mulld. */ 2031 static void gen_mulld(DisasContext *ctx) 2032 { 2033 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2034 cpu_gpr[rB(ctx->opcode)]); 2035 if (unlikely(Rc(ctx->opcode) != 0)) { 2036 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2037 } 2038 } 2039 2040 /* mulldo mulldo. */ 2041 static void gen_mulldo(DisasContext *ctx) 2042 { 2043 TCGv_i64 t0 = tcg_temp_new_i64(); 2044 TCGv_i64 t1 = tcg_temp_new_i64(); 2045 2046 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2047 cpu_gpr[rB(ctx->opcode)]); 2048 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2049 2050 tcg_gen_sari_i64(t0, t0, 63); 2051 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2052 if (is_isa300(ctx)) { 2053 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2054 } 2055 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2056 2057 if (unlikely(Rc(ctx->opcode) != 0)) { 2058 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2059 } 2060 } 2061 #endif 2062 2063 /* Common subf function */ 2064 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2065 TCGv arg2, bool add_ca, bool compute_ca, 2066 bool compute_ov, bool compute_rc0) 2067 { 2068 TCGv t0 = ret; 2069 2070 if (compute_ca || compute_ov) { 2071 t0 = tcg_temp_new(); 2072 } 2073 2074 if (compute_ca) { 2075 /* dest = ~arg1 + arg2 [+ ca]. */ 2076 if (NARROW_MODE(ctx)) { 2077 /* 2078 * Caution: a non-obvious corner case of the spec is that 2079 * we must produce the *entire* 64-bit addition, but 2080 * produce the carry into bit 32. 2081 */ 2082 TCGv inv1 = tcg_temp_new(); 2083 TCGv t1 = tcg_temp_new(); 2084 tcg_gen_not_tl(inv1, arg1); 2085 if (add_ca) { 2086 tcg_gen_add_tl(t0, arg2, cpu_ca); 2087 } else { 2088 tcg_gen_addi_tl(t0, arg2, 1); 2089 } 2090 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2091 tcg_gen_add_tl(t0, t0, inv1); 2092 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2093 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2094 if (is_isa300(ctx)) { 2095 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2096 } 2097 } else if (add_ca) { 2098 TCGv zero, inv1 = tcg_temp_new(); 2099 tcg_gen_not_tl(inv1, arg1); 2100 zero = tcg_constant_tl(0); 2101 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2102 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2103 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2104 } else { 2105 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2106 tcg_gen_sub_tl(t0, arg2, arg1); 2107 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2108 } 2109 } else if (add_ca) { 2110 /* 2111 * Since we're ignoring carry-out, we can simplify the 2112 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2113 */ 2114 tcg_gen_sub_tl(t0, arg2, arg1); 2115 tcg_gen_add_tl(t0, t0, cpu_ca); 2116 tcg_gen_subi_tl(t0, t0, 1); 2117 } else { 2118 tcg_gen_sub_tl(t0, arg2, arg1); 2119 } 2120 2121 if (compute_ov) { 2122 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2123 } 2124 if (unlikely(compute_rc0)) { 2125 gen_set_Rc0(ctx, t0); 2126 } 2127 2128 if (t0 != ret) { 2129 tcg_gen_mov_tl(ret, t0); 2130 } 2131 } 2132 /* Sub functions with Two operands functions */ 2133 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2134 static void glue(gen_, name)(DisasContext *ctx) \ 2135 { \ 2136 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2137 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2138 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2139 } 2140 /* Sub functions with one operand and one immediate */ 2141 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2142 add_ca, compute_ca, compute_ov) \ 2143 static void glue(gen_, name)(DisasContext *ctx) \ 2144 { \ 2145 TCGv t0 = tcg_constant_tl(const_val); \ 2146 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2147 cpu_gpr[rA(ctx->opcode)], t0, \ 2148 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2149 } 2150 /* subf subf. subfo subfo. */ 2151 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2152 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2153 /* subfc subfc. subfco subfco. */ 2154 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2155 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2156 /* subfe subfe. subfeo subfo. */ 2157 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2158 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2159 /* subfme subfme. subfmeo subfmeo. */ 2160 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2161 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2162 /* subfze subfze. subfzeo subfzeo.*/ 2163 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2164 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2165 2166 /* subfic */ 2167 static void gen_subfic(DisasContext *ctx) 2168 { 2169 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2170 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2171 c, 0, 1, 0, 0); 2172 } 2173 2174 /* neg neg. nego nego. */ 2175 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2176 { 2177 TCGv zero = tcg_constant_tl(0); 2178 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2179 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2180 } 2181 2182 static void gen_neg(DisasContext *ctx) 2183 { 2184 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2185 if (unlikely(Rc(ctx->opcode))) { 2186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2187 } 2188 } 2189 2190 static void gen_nego(DisasContext *ctx) 2191 { 2192 gen_op_arith_neg(ctx, 1); 2193 } 2194 2195 /*** Integer logical ***/ 2196 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2197 static void glue(gen_, name)(DisasContext *ctx) \ 2198 { \ 2199 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2200 cpu_gpr[rB(ctx->opcode)]); \ 2201 if (unlikely(Rc(ctx->opcode) != 0)) \ 2202 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2203 } 2204 2205 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2206 static void glue(gen_, name)(DisasContext *ctx) \ 2207 { \ 2208 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2209 if (unlikely(Rc(ctx->opcode) != 0)) \ 2210 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2211 } 2212 2213 /* and & and. */ 2214 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2215 /* andc & andc. */ 2216 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2217 2218 /* andi. */ 2219 static void gen_andi_(DisasContext *ctx) 2220 { 2221 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2222 UIMM(ctx->opcode)); 2223 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2224 } 2225 2226 /* andis. */ 2227 static void gen_andis_(DisasContext *ctx) 2228 { 2229 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2230 UIMM(ctx->opcode) << 16); 2231 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2232 } 2233 2234 /* cntlzw */ 2235 static void gen_cntlzw(DisasContext *ctx) 2236 { 2237 TCGv_i32 t = tcg_temp_new_i32(); 2238 2239 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2240 tcg_gen_clzi_i32(t, t, 32); 2241 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2242 2243 if (unlikely(Rc(ctx->opcode) != 0)) { 2244 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2245 } 2246 } 2247 2248 /* cnttzw */ 2249 static void gen_cnttzw(DisasContext *ctx) 2250 { 2251 TCGv_i32 t = tcg_temp_new_i32(); 2252 2253 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2254 tcg_gen_ctzi_i32(t, t, 32); 2255 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2256 2257 if (unlikely(Rc(ctx->opcode) != 0)) { 2258 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2259 } 2260 } 2261 2262 /* eqv & eqv. */ 2263 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2264 /* extsb & extsb. */ 2265 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2266 /* extsh & extsh. */ 2267 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2268 /* nand & nand. */ 2269 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2270 /* nor & nor. */ 2271 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2272 2273 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2274 static void gen_pause(DisasContext *ctx) 2275 { 2276 TCGv_i32 t0 = tcg_constant_i32(0); 2277 tcg_gen_st_i32(t0, cpu_env, 2278 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2279 2280 /* Stop translation, this gives other CPUs a chance to run */ 2281 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2282 } 2283 #endif /* defined(TARGET_PPC64) */ 2284 2285 /* or & or. */ 2286 static void gen_or(DisasContext *ctx) 2287 { 2288 int rs, ra, rb; 2289 2290 rs = rS(ctx->opcode); 2291 ra = rA(ctx->opcode); 2292 rb = rB(ctx->opcode); 2293 /* Optimisation for mr. ri case */ 2294 if (rs != ra || rs != rb) { 2295 if (rs != rb) { 2296 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2297 } else { 2298 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2299 } 2300 if (unlikely(Rc(ctx->opcode) != 0)) { 2301 gen_set_Rc0(ctx, cpu_gpr[ra]); 2302 } 2303 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2304 gen_set_Rc0(ctx, cpu_gpr[rs]); 2305 #if defined(TARGET_PPC64) 2306 } else if (rs != 0) { /* 0 is nop */ 2307 int prio = 0; 2308 2309 switch (rs) { 2310 case 1: 2311 /* Set process priority to low */ 2312 prio = 2; 2313 break; 2314 case 6: 2315 /* Set process priority to medium-low */ 2316 prio = 3; 2317 break; 2318 case 2: 2319 /* Set process priority to normal */ 2320 prio = 4; 2321 break; 2322 #if !defined(CONFIG_USER_ONLY) 2323 case 31: 2324 if (!ctx->pr) { 2325 /* Set process priority to very low */ 2326 prio = 1; 2327 } 2328 break; 2329 case 5: 2330 if (!ctx->pr) { 2331 /* Set process priority to medium-hight */ 2332 prio = 5; 2333 } 2334 break; 2335 case 3: 2336 if (!ctx->pr) { 2337 /* Set process priority to high */ 2338 prio = 6; 2339 } 2340 break; 2341 case 7: 2342 if (ctx->hv && !ctx->pr) { 2343 /* Set process priority to very high */ 2344 prio = 7; 2345 } 2346 break; 2347 #endif 2348 default: 2349 break; 2350 } 2351 if (prio) { 2352 TCGv t0 = tcg_temp_new(); 2353 gen_load_spr(t0, SPR_PPR); 2354 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2355 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2356 gen_store_spr(SPR_PPR, t0); 2357 } 2358 #if !defined(CONFIG_USER_ONLY) 2359 /* 2360 * Pause out of TCG otherwise spin loops with smt_low eat too 2361 * much CPU and the kernel hangs. This applies to all 2362 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2363 * mdoio(29), mdoom(30), and all currently undefined. 2364 */ 2365 gen_pause(ctx); 2366 #endif 2367 #endif 2368 } 2369 } 2370 /* orc & orc. */ 2371 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2372 2373 /* xor & xor. */ 2374 static void gen_xor(DisasContext *ctx) 2375 { 2376 /* Optimisation for "set to zero" case */ 2377 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2378 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2379 cpu_gpr[rB(ctx->opcode)]); 2380 } else { 2381 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2382 } 2383 if (unlikely(Rc(ctx->opcode) != 0)) { 2384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2385 } 2386 } 2387 2388 /* ori */ 2389 static void gen_ori(DisasContext *ctx) 2390 { 2391 target_ulong uimm = UIMM(ctx->opcode); 2392 2393 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2394 return; 2395 } 2396 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2397 } 2398 2399 /* oris */ 2400 static void gen_oris(DisasContext *ctx) 2401 { 2402 target_ulong uimm = UIMM(ctx->opcode); 2403 2404 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2405 /* NOP */ 2406 return; 2407 } 2408 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2409 uimm << 16); 2410 } 2411 2412 /* xori */ 2413 static void gen_xori(DisasContext *ctx) 2414 { 2415 target_ulong uimm = UIMM(ctx->opcode); 2416 2417 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2418 /* NOP */ 2419 return; 2420 } 2421 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2422 } 2423 2424 /* xoris */ 2425 static void gen_xoris(DisasContext *ctx) 2426 { 2427 target_ulong uimm = UIMM(ctx->opcode); 2428 2429 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2430 /* NOP */ 2431 return; 2432 } 2433 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2434 uimm << 16); 2435 } 2436 2437 /* popcntb : PowerPC 2.03 specification */ 2438 static void gen_popcntb(DisasContext *ctx) 2439 { 2440 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2441 } 2442 2443 static void gen_popcntw(DisasContext *ctx) 2444 { 2445 #if defined(TARGET_PPC64) 2446 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2447 #else 2448 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2449 #endif 2450 } 2451 2452 #if defined(TARGET_PPC64) 2453 /* popcntd: PowerPC 2.06 specification */ 2454 static void gen_popcntd(DisasContext *ctx) 2455 { 2456 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2457 } 2458 #endif 2459 2460 /* prtyw: PowerPC 2.05 specification */ 2461 static void gen_prtyw(DisasContext *ctx) 2462 { 2463 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2464 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2465 TCGv t0 = tcg_temp_new(); 2466 tcg_gen_shri_tl(t0, rs, 16); 2467 tcg_gen_xor_tl(ra, rs, t0); 2468 tcg_gen_shri_tl(t0, ra, 8); 2469 tcg_gen_xor_tl(ra, ra, t0); 2470 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2471 } 2472 2473 #if defined(TARGET_PPC64) 2474 /* prtyd: PowerPC 2.05 specification */ 2475 static void gen_prtyd(DisasContext *ctx) 2476 { 2477 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2478 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2479 TCGv t0 = tcg_temp_new(); 2480 tcg_gen_shri_tl(t0, rs, 32); 2481 tcg_gen_xor_tl(ra, rs, t0); 2482 tcg_gen_shri_tl(t0, ra, 16); 2483 tcg_gen_xor_tl(ra, ra, t0); 2484 tcg_gen_shri_tl(t0, ra, 8); 2485 tcg_gen_xor_tl(ra, ra, t0); 2486 tcg_gen_andi_tl(ra, ra, 1); 2487 } 2488 #endif 2489 2490 #if defined(TARGET_PPC64) 2491 /* bpermd */ 2492 static void gen_bpermd(DisasContext *ctx) 2493 { 2494 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2495 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2496 } 2497 #endif 2498 2499 #if defined(TARGET_PPC64) 2500 /* extsw & extsw. */ 2501 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2502 2503 /* cntlzd */ 2504 static void gen_cntlzd(DisasContext *ctx) 2505 { 2506 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2507 if (unlikely(Rc(ctx->opcode) != 0)) { 2508 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2509 } 2510 } 2511 2512 /* cnttzd */ 2513 static void gen_cnttzd(DisasContext *ctx) 2514 { 2515 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2516 if (unlikely(Rc(ctx->opcode) != 0)) { 2517 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2518 } 2519 } 2520 2521 /* darn */ 2522 static void gen_darn(DisasContext *ctx) 2523 { 2524 int l = L(ctx->opcode); 2525 2526 if (l > 2) { 2527 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2528 } else { 2529 translator_io_start(&ctx->base); 2530 if (l == 0) { 2531 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2532 } else { 2533 /* Return 64-bit random for both CRN and RRN */ 2534 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2535 } 2536 } 2537 } 2538 #endif 2539 2540 /*** Integer rotate ***/ 2541 2542 /* rlwimi & rlwimi. */ 2543 static void gen_rlwimi(DisasContext *ctx) 2544 { 2545 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2546 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2547 uint32_t sh = SH(ctx->opcode); 2548 uint32_t mb = MB(ctx->opcode); 2549 uint32_t me = ME(ctx->opcode); 2550 2551 if (sh == (31 - me) && mb <= me) { 2552 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2553 } else { 2554 target_ulong mask; 2555 bool mask_in_32b = true; 2556 TCGv t1; 2557 2558 #if defined(TARGET_PPC64) 2559 mb += 32; 2560 me += 32; 2561 #endif 2562 mask = MASK(mb, me); 2563 2564 #if defined(TARGET_PPC64) 2565 if (mask > 0xffffffffu) { 2566 mask_in_32b = false; 2567 } 2568 #endif 2569 t1 = tcg_temp_new(); 2570 if (mask_in_32b) { 2571 TCGv_i32 t0 = tcg_temp_new_i32(); 2572 tcg_gen_trunc_tl_i32(t0, t_rs); 2573 tcg_gen_rotli_i32(t0, t0, sh); 2574 tcg_gen_extu_i32_tl(t1, t0); 2575 } else { 2576 #if defined(TARGET_PPC64) 2577 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2578 tcg_gen_rotli_i64(t1, t1, sh); 2579 #else 2580 g_assert_not_reached(); 2581 #endif 2582 } 2583 2584 tcg_gen_andi_tl(t1, t1, mask); 2585 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2586 tcg_gen_or_tl(t_ra, t_ra, t1); 2587 } 2588 if (unlikely(Rc(ctx->opcode) != 0)) { 2589 gen_set_Rc0(ctx, t_ra); 2590 } 2591 } 2592 2593 /* rlwinm & rlwinm. */ 2594 static void gen_rlwinm(DisasContext *ctx) 2595 { 2596 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2597 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2598 int sh = SH(ctx->opcode); 2599 int mb = MB(ctx->opcode); 2600 int me = ME(ctx->opcode); 2601 int len = me - mb + 1; 2602 int rsh = (32 - sh) & 31; 2603 2604 if (sh != 0 && len > 0 && me == (31 - sh)) { 2605 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2606 } else if (me == 31 && rsh + len <= 32) { 2607 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2608 } else { 2609 target_ulong mask; 2610 bool mask_in_32b = true; 2611 #if defined(TARGET_PPC64) 2612 mb += 32; 2613 me += 32; 2614 #endif 2615 mask = MASK(mb, me); 2616 #if defined(TARGET_PPC64) 2617 if (mask > 0xffffffffu) { 2618 mask_in_32b = false; 2619 } 2620 #endif 2621 if (mask_in_32b) { 2622 if (sh == 0) { 2623 tcg_gen_andi_tl(t_ra, t_rs, mask); 2624 } else { 2625 TCGv_i32 t0 = tcg_temp_new_i32(); 2626 tcg_gen_trunc_tl_i32(t0, t_rs); 2627 tcg_gen_rotli_i32(t0, t0, sh); 2628 tcg_gen_andi_i32(t0, t0, mask); 2629 tcg_gen_extu_i32_tl(t_ra, t0); 2630 } 2631 } else { 2632 #if defined(TARGET_PPC64) 2633 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2634 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2635 tcg_gen_andi_i64(t_ra, t_ra, mask); 2636 #else 2637 g_assert_not_reached(); 2638 #endif 2639 } 2640 } 2641 if (unlikely(Rc(ctx->opcode) != 0)) { 2642 gen_set_Rc0(ctx, t_ra); 2643 } 2644 } 2645 2646 /* rlwnm & rlwnm. */ 2647 static void gen_rlwnm(DisasContext *ctx) 2648 { 2649 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2650 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2651 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2652 uint32_t mb = MB(ctx->opcode); 2653 uint32_t me = ME(ctx->opcode); 2654 target_ulong mask; 2655 bool mask_in_32b = true; 2656 2657 #if defined(TARGET_PPC64) 2658 mb += 32; 2659 me += 32; 2660 #endif 2661 mask = MASK(mb, me); 2662 2663 #if defined(TARGET_PPC64) 2664 if (mask > 0xffffffffu) { 2665 mask_in_32b = false; 2666 } 2667 #endif 2668 if (mask_in_32b) { 2669 TCGv_i32 t0 = tcg_temp_new_i32(); 2670 TCGv_i32 t1 = tcg_temp_new_i32(); 2671 tcg_gen_trunc_tl_i32(t0, t_rb); 2672 tcg_gen_trunc_tl_i32(t1, t_rs); 2673 tcg_gen_andi_i32(t0, t0, 0x1f); 2674 tcg_gen_rotl_i32(t1, t1, t0); 2675 tcg_gen_extu_i32_tl(t_ra, t1); 2676 } else { 2677 #if defined(TARGET_PPC64) 2678 TCGv_i64 t0 = tcg_temp_new_i64(); 2679 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2680 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2681 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2682 #else 2683 g_assert_not_reached(); 2684 #endif 2685 } 2686 2687 tcg_gen_andi_tl(t_ra, t_ra, mask); 2688 2689 if (unlikely(Rc(ctx->opcode) != 0)) { 2690 gen_set_Rc0(ctx, t_ra); 2691 } 2692 } 2693 2694 #if defined(TARGET_PPC64) 2695 #define GEN_PPC64_R2(name, opc1, opc2) \ 2696 static void glue(gen_, name##0)(DisasContext *ctx) \ 2697 { \ 2698 gen_##name(ctx, 0); \ 2699 } \ 2700 \ 2701 static void glue(gen_, name##1)(DisasContext *ctx) \ 2702 { \ 2703 gen_##name(ctx, 1); \ 2704 } 2705 #define GEN_PPC64_R4(name, opc1, opc2) \ 2706 static void glue(gen_, name##0)(DisasContext *ctx) \ 2707 { \ 2708 gen_##name(ctx, 0, 0); \ 2709 } \ 2710 \ 2711 static void glue(gen_, name##1)(DisasContext *ctx) \ 2712 { \ 2713 gen_##name(ctx, 0, 1); \ 2714 } \ 2715 \ 2716 static void glue(gen_, name##2)(DisasContext *ctx) \ 2717 { \ 2718 gen_##name(ctx, 1, 0); \ 2719 } \ 2720 \ 2721 static void glue(gen_, name##3)(DisasContext *ctx) \ 2722 { \ 2723 gen_##name(ctx, 1, 1); \ 2724 } 2725 2726 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2727 { 2728 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2729 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2730 int len = me - mb + 1; 2731 int rsh = (64 - sh) & 63; 2732 2733 if (sh != 0 && len > 0 && me == (63 - sh)) { 2734 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2735 } else if (me == 63 && rsh + len <= 64) { 2736 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2737 } else { 2738 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2739 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2740 } 2741 if (unlikely(Rc(ctx->opcode) != 0)) { 2742 gen_set_Rc0(ctx, t_ra); 2743 } 2744 } 2745 2746 /* rldicl - rldicl. */ 2747 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2748 { 2749 uint32_t sh, mb; 2750 2751 sh = SH(ctx->opcode) | (shn << 5); 2752 mb = MB(ctx->opcode) | (mbn << 5); 2753 gen_rldinm(ctx, mb, 63, sh); 2754 } 2755 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2756 2757 /* rldicr - rldicr. */ 2758 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2759 { 2760 uint32_t sh, me; 2761 2762 sh = SH(ctx->opcode) | (shn << 5); 2763 me = MB(ctx->opcode) | (men << 5); 2764 gen_rldinm(ctx, 0, me, sh); 2765 } 2766 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2767 2768 /* rldic - rldic. */ 2769 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2770 { 2771 uint32_t sh, mb; 2772 2773 sh = SH(ctx->opcode) | (shn << 5); 2774 mb = MB(ctx->opcode) | (mbn << 5); 2775 gen_rldinm(ctx, mb, 63 - sh, sh); 2776 } 2777 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2778 2779 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2780 { 2781 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2782 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2783 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2784 TCGv t0; 2785 2786 t0 = tcg_temp_new(); 2787 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2788 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2789 2790 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2791 if (unlikely(Rc(ctx->opcode) != 0)) { 2792 gen_set_Rc0(ctx, t_ra); 2793 } 2794 } 2795 2796 /* rldcl - rldcl. */ 2797 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2798 { 2799 uint32_t mb; 2800 2801 mb = MB(ctx->opcode) | (mbn << 5); 2802 gen_rldnm(ctx, mb, 63); 2803 } 2804 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2805 2806 /* rldcr - rldcr. */ 2807 static inline void gen_rldcr(DisasContext *ctx, int men) 2808 { 2809 uint32_t me; 2810 2811 me = MB(ctx->opcode) | (men << 5); 2812 gen_rldnm(ctx, 0, me); 2813 } 2814 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2815 2816 /* rldimi - rldimi. */ 2817 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2818 { 2819 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2820 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2821 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2822 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2823 uint32_t me = 63 - sh; 2824 2825 if (mb <= me) { 2826 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2827 } else { 2828 target_ulong mask = MASK(mb, me); 2829 TCGv t1 = tcg_temp_new(); 2830 2831 tcg_gen_rotli_tl(t1, t_rs, sh); 2832 tcg_gen_andi_tl(t1, t1, mask); 2833 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2834 tcg_gen_or_tl(t_ra, t_ra, t1); 2835 } 2836 if (unlikely(Rc(ctx->opcode) != 0)) { 2837 gen_set_Rc0(ctx, t_ra); 2838 } 2839 } 2840 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2841 #endif 2842 2843 /*** Integer shift ***/ 2844 2845 /* slw & slw. */ 2846 static void gen_slw(DisasContext *ctx) 2847 { 2848 TCGv t0, t1; 2849 2850 t0 = tcg_temp_new(); 2851 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2852 #if defined(TARGET_PPC64) 2853 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2854 tcg_gen_sari_tl(t0, t0, 0x3f); 2855 #else 2856 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2857 tcg_gen_sari_tl(t0, t0, 0x1f); 2858 #endif 2859 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2860 t1 = tcg_temp_new(); 2861 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2862 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2863 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2864 if (unlikely(Rc(ctx->opcode) != 0)) { 2865 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2866 } 2867 } 2868 2869 /* sraw & sraw. */ 2870 static void gen_sraw(DisasContext *ctx) 2871 { 2872 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2873 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2874 if (unlikely(Rc(ctx->opcode) != 0)) { 2875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2876 } 2877 } 2878 2879 /* srawi & srawi. */ 2880 static void gen_srawi(DisasContext *ctx) 2881 { 2882 int sh = SH(ctx->opcode); 2883 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2884 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2885 if (sh == 0) { 2886 tcg_gen_ext32s_tl(dst, src); 2887 tcg_gen_movi_tl(cpu_ca, 0); 2888 if (is_isa300(ctx)) { 2889 tcg_gen_movi_tl(cpu_ca32, 0); 2890 } 2891 } else { 2892 TCGv t0; 2893 tcg_gen_ext32s_tl(dst, src); 2894 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2895 t0 = tcg_temp_new(); 2896 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2897 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2898 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2899 if (is_isa300(ctx)) { 2900 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2901 } 2902 tcg_gen_sari_tl(dst, dst, sh); 2903 } 2904 if (unlikely(Rc(ctx->opcode) != 0)) { 2905 gen_set_Rc0(ctx, dst); 2906 } 2907 } 2908 2909 /* srw & srw. */ 2910 static void gen_srw(DisasContext *ctx) 2911 { 2912 TCGv t0, t1; 2913 2914 t0 = tcg_temp_new(); 2915 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2916 #if defined(TARGET_PPC64) 2917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2918 tcg_gen_sari_tl(t0, t0, 0x3f); 2919 #else 2920 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2921 tcg_gen_sari_tl(t0, t0, 0x1f); 2922 #endif 2923 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2924 tcg_gen_ext32u_tl(t0, t0); 2925 t1 = tcg_temp_new(); 2926 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2927 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2928 if (unlikely(Rc(ctx->opcode) != 0)) { 2929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2930 } 2931 } 2932 2933 #if defined(TARGET_PPC64) 2934 /* sld & sld. */ 2935 static void gen_sld(DisasContext *ctx) 2936 { 2937 TCGv t0, t1; 2938 2939 t0 = tcg_temp_new(); 2940 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2941 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2942 tcg_gen_sari_tl(t0, t0, 0x3f); 2943 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2944 t1 = tcg_temp_new(); 2945 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2946 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2947 if (unlikely(Rc(ctx->opcode) != 0)) { 2948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2949 } 2950 } 2951 2952 /* srad & srad. */ 2953 static void gen_srad(DisasContext *ctx) 2954 { 2955 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2956 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2957 if (unlikely(Rc(ctx->opcode) != 0)) { 2958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2959 } 2960 } 2961 /* sradi & sradi. */ 2962 static inline void gen_sradi(DisasContext *ctx, int n) 2963 { 2964 int sh = SH(ctx->opcode) + (n << 5); 2965 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2966 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2967 if (sh == 0) { 2968 tcg_gen_mov_tl(dst, src); 2969 tcg_gen_movi_tl(cpu_ca, 0); 2970 if (is_isa300(ctx)) { 2971 tcg_gen_movi_tl(cpu_ca32, 0); 2972 } 2973 } else { 2974 TCGv t0; 2975 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2976 t0 = tcg_temp_new(); 2977 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2978 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2979 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2980 if (is_isa300(ctx)) { 2981 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2982 } 2983 tcg_gen_sari_tl(dst, src, sh); 2984 } 2985 if (unlikely(Rc(ctx->opcode) != 0)) { 2986 gen_set_Rc0(ctx, dst); 2987 } 2988 } 2989 2990 static void gen_sradi0(DisasContext *ctx) 2991 { 2992 gen_sradi(ctx, 0); 2993 } 2994 2995 static void gen_sradi1(DisasContext *ctx) 2996 { 2997 gen_sradi(ctx, 1); 2998 } 2999 3000 /* extswsli & extswsli. */ 3001 static inline void gen_extswsli(DisasContext *ctx, int n) 3002 { 3003 int sh = SH(ctx->opcode) + (n << 5); 3004 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3005 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3006 3007 tcg_gen_ext32s_tl(dst, src); 3008 tcg_gen_shli_tl(dst, dst, sh); 3009 if (unlikely(Rc(ctx->opcode) != 0)) { 3010 gen_set_Rc0(ctx, dst); 3011 } 3012 } 3013 3014 static void gen_extswsli0(DisasContext *ctx) 3015 { 3016 gen_extswsli(ctx, 0); 3017 } 3018 3019 static void gen_extswsli1(DisasContext *ctx) 3020 { 3021 gen_extswsli(ctx, 1); 3022 } 3023 3024 /* srd & srd. */ 3025 static void gen_srd(DisasContext *ctx) 3026 { 3027 TCGv t0, t1; 3028 3029 t0 = tcg_temp_new(); 3030 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3031 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3032 tcg_gen_sari_tl(t0, t0, 0x3f); 3033 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3034 t1 = tcg_temp_new(); 3035 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3036 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3037 if (unlikely(Rc(ctx->opcode) != 0)) { 3038 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3039 } 3040 } 3041 #endif 3042 3043 /*** Addressing modes ***/ 3044 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3045 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3046 target_long maskl) 3047 { 3048 target_long simm = SIMM(ctx->opcode); 3049 3050 simm &= ~maskl; 3051 if (rA(ctx->opcode) == 0) { 3052 if (NARROW_MODE(ctx)) { 3053 simm = (uint32_t)simm; 3054 } 3055 tcg_gen_movi_tl(EA, simm); 3056 } else if (likely(simm != 0)) { 3057 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3058 if (NARROW_MODE(ctx)) { 3059 tcg_gen_ext32u_tl(EA, EA); 3060 } 3061 } else { 3062 if (NARROW_MODE(ctx)) { 3063 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3064 } else { 3065 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3066 } 3067 } 3068 } 3069 3070 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3071 { 3072 if (rA(ctx->opcode) == 0) { 3073 if (NARROW_MODE(ctx)) { 3074 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3075 } else { 3076 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3077 } 3078 } else { 3079 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3080 if (NARROW_MODE(ctx)) { 3081 tcg_gen_ext32u_tl(EA, EA); 3082 } 3083 } 3084 } 3085 3086 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3087 { 3088 if (rA(ctx->opcode) == 0) { 3089 tcg_gen_movi_tl(EA, 0); 3090 } else if (NARROW_MODE(ctx)) { 3091 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3092 } else { 3093 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3094 } 3095 } 3096 3097 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3098 target_long val) 3099 { 3100 tcg_gen_addi_tl(ret, arg1, val); 3101 if (NARROW_MODE(ctx)) { 3102 tcg_gen_ext32u_tl(ret, ret); 3103 } 3104 } 3105 3106 static inline void gen_align_no_le(DisasContext *ctx) 3107 { 3108 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3109 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3110 } 3111 3112 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3113 { 3114 TCGv ea = tcg_temp_new(); 3115 if (ra) { 3116 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3117 } else { 3118 tcg_gen_mov_tl(ea, displ); 3119 } 3120 if (NARROW_MODE(ctx)) { 3121 tcg_gen_ext32u_tl(ea, ea); 3122 } 3123 return ea; 3124 } 3125 3126 /*** Integer load ***/ 3127 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3128 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3129 3130 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3131 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3132 TCGv val, \ 3133 TCGv addr) \ 3134 { \ 3135 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3136 } 3137 3138 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3139 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3140 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3141 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3142 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3143 3144 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3145 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3146 3147 #define GEN_QEMU_LOAD_64(ldop, op) \ 3148 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3149 TCGv_i64 val, \ 3150 TCGv addr) \ 3151 { \ 3152 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3153 } 3154 3155 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3156 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3157 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3158 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3159 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3160 3161 #if defined(TARGET_PPC64) 3162 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3163 #endif 3164 3165 #define GEN_QEMU_STORE_TL(stop, op) \ 3166 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3167 TCGv val, \ 3168 TCGv addr) \ 3169 { \ 3170 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3171 } 3172 3173 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3174 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3175 #endif 3176 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3177 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3178 3179 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3180 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3181 3182 #define GEN_QEMU_STORE_64(stop, op) \ 3183 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3184 TCGv_i64 val, \ 3185 TCGv addr) \ 3186 { \ 3187 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3188 } 3189 3190 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3191 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3192 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3193 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3194 3195 #if defined(TARGET_PPC64) 3196 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3197 #endif 3198 3199 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3200 static void glue(gen_, name##x)(DisasContext *ctx) \ 3201 { \ 3202 TCGv EA; \ 3203 chk(ctx); \ 3204 gen_set_access_type(ctx, ACCESS_INT); \ 3205 EA = tcg_temp_new(); \ 3206 gen_addr_reg_index(ctx, EA); \ 3207 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3208 } 3209 3210 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3211 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3212 3213 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3214 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3215 3216 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3217 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3218 { \ 3219 TCGv EA; \ 3220 CHK_SV(ctx); \ 3221 gen_set_access_type(ctx, ACCESS_INT); \ 3222 EA = tcg_temp_new(); \ 3223 gen_addr_reg_index(ctx, EA); \ 3224 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3225 } 3226 3227 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3228 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3229 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3230 #if defined(TARGET_PPC64) 3231 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3232 #endif 3233 3234 #if defined(TARGET_PPC64) 3235 /* CI load/store variants */ 3236 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3237 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3238 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3239 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3240 #endif 3241 3242 /*** Integer store ***/ 3243 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3244 static void glue(gen_, name##x)(DisasContext *ctx) \ 3245 { \ 3246 TCGv EA; \ 3247 chk(ctx); \ 3248 gen_set_access_type(ctx, ACCESS_INT); \ 3249 EA = tcg_temp_new(); \ 3250 gen_addr_reg_index(ctx, EA); \ 3251 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3252 } 3253 #define GEN_STX(name, stop, opc2, opc3, type) \ 3254 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3255 3256 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3257 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3258 3259 #define GEN_STEPX(name, stop, opc2, opc3) \ 3260 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3261 { \ 3262 TCGv EA; \ 3263 CHK_SV(ctx); \ 3264 gen_set_access_type(ctx, ACCESS_INT); \ 3265 EA = tcg_temp_new(); \ 3266 gen_addr_reg_index(ctx, EA); \ 3267 tcg_gen_qemu_st_tl( \ 3268 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3269 } 3270 3271 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3272 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3273 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3274 #if defined(TARGET_PPC64) 3275 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3276 #endif 3277 3278 #if defined(TARGET_PPC64) 3279 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3280 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3281 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3282 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3283 #endif 3284 /*** Integer load and store with byte reverse ***/ 3285 3286 /* lhbrx */ 3287 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3288 3289 /* lwbrx */ 3290 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3291 3292 #if defined(TARGET_PPC64) 3293 /* ldbrx */ 3294 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3295 /* stdbrx */ 3296 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3297 #endif /* TARGET_PPC64 */ 3298 3299 /* sthbrx */ 3300 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3301 /* stwbrx */ 3302 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3303 3304 /*** Integer load and store multiple ***/ 3305 3306 /* lmw */ 3307 static void gen_lmw(DisasContext *ctx) 3308 { 3309 TCGv t0; 3310 TCGv_i32 t1; 3311 3312 if (ctx->le_mode) { 3313 gen_align_no_le(ctx); 3314 return; 3315 } 3316 gen_set_access_type(ctx, ACCESS_INT); 3317 t0 = tcg_temp_new(); 3318 t1 = tcg_constant_i32(rD(ctx->opcode)); 3319 gen_addr_imm_index(ctx, t0, 0); 3320 gen_helper_lmw(cpu_env, t0, t1); 3321 } 3322 3323 /* stmw */ 3324 static void gen_stmw(DisasContext *ctx) 3325 { 3326 TCGv t0; 3327 TCGv_i32 t1; 3328 3329 if (ctx->le_mode) { 3330 gen_align_no_le(ctx); 3331 return; 3332 } 3333 gen_set_access_type(ctx, ACCESS_INT); 3334 t0 = tcg_temp_new(); 3335 t1 = tcg_constant_i32(rS(ctx->opcode)); 3336 gen_addr_imm_index(ctx, t0, 0); 3337 gen_helper_stmw(cpu_env, t0, t1); 3338 } 3339 3340 /*** Integer load and store strings ***/ 3341 3342 /* lswi */ 3343 /* 3344 * PowerPC32 specification says we must generate an exception if rA is 3345 * in the range of registers to be loaded. In an other hand, IBM says 3346 * this is valid, but rA won't be loaded. For now, I'll follow the 3347 * spec... 3348 */ 3349 static void gen_lswi(DisasContext *ctx) 3350 { 3351 TCGv t0; 3352 TCGv_i32 t1, t2; 3353 int nb = NB(ctx->opcode); 3354 int start = rD(ctx->opcode); 3355 int ra = rA(ctx->opcode); 3356 int nr; 3357 3358 if (ctx->le_mode) { 3359 gen_align_no_le(ctx); 3360 return; 3361 } 3362 if (nb == 0) { 3363 nb = 32; 3364 } 3365 nr = DIV_ROUND_UP(nb, 4); 3366 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3367 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3368 return; 3369 } 3370 gen_set_access_type(ctx, ACCESS_INT); 3371 t0 = tcg_temp_new(); 3372 gen_addr_register(ctx, t0); 3373 t1 = tcg_constant_i32(nb); 3374 t2 = tcg_constant_i32(start); 3375 gen_helper_lsw(cpu_env, t0, t1, t2); 3376 } 3377 3378 /* lswx */ 3379 static void gen_lswx(DisasContext *ctx) 3380 { 3381 TCGv t0; 3382 TCGv_i32 t1, t2, t3; 3383 3384 if (ctx->le_mode) { 3385 gen_align_no_le(ctx); 3386 return; 3387 } 3388 gen_set_access_type(ctx, ACCESS_INT); 3389 t0 = tcg_temp_new(); 3390 gen_addr_reg_index(ctx, t0); 3391 t1 = tcg_constant_i32(rD(ctx->opcode)); 3392 t2 = tcg_constant_i32(rA(ctx->opcode)); 3393 t3 = tcg_constant_i32(rB(ctx->opcode)); 3394 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3395 } 3396 3397 /* stswi */ 3398 static void gen_stswi(DisasContext *ctx) 3399 { 3400 TCGv t0; 3401 TCGv_i32 t1, t2; 3402 int nb = NB(ctx->opcode); 3403 3404 if (ctx->le_mode) { 3405 gen_align_no_le(ctx); 3406 return; 3407 } 3408 gen_set_access_type(ctx, ACCESS_INT); 3409 t0 = tcg_temp_new(); 3410 gen_addr_register(ctx, t0); 3411 if (nb == 0) { 3412 nb = 32; 3413 } 3414 t1 = tcg_constant_i32(nb); 3415 t2 = tcg_constant_i32(rS(ctx->opcode)); 3416 gen_helper_stsw(cpu_env, t0, t1, t2); 3417 } 3418 3419 /* stswx */ 3420 static void gen_stswx(DisasContext *ctx) 3421 { 3422 TCGv t0; 3423 TCGv_i32 t1, t2; 3424 3425 if (ctx->le_mode) { 3426 gen_align_no_le(ctx); 3427 return; 3428 } 3429 gen_set_access_type(ctx, ACCESS_INT); 3430 t0 = tcg_temp_new(); 3431 gen_addr_reg_index(ctx, t0); 3432 t1 = tcg_temp_new_i32(); 3433 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3434 tcg_gen_andi_i32(t1, t1, 0x7F); 3435 t2 = tcg_constant_i32(rS(ctx->opcode)); 3436 gen_helper_stsw(cpu_env, t0, t1, t2); 3437 } 3438 3439 /*** Memory synchronisation ***/ 3440 /* eieio */ 3441 static void gen_eieio(DisasContext *ctx) 3442 { 3443 TCGBar bar = TCG_MO_ALL; 3444 3445 /* 3446 * eieio has complex semanitcs. It provides memory ordering between 3447 * operations in the set: 3448 * - loads from CI memory. 3449 * - stores to CI memory. 3450 * - stores to WT memory. 3451 * 3452 * It separately also orders memory for operations in the set: 3453 * - stores to cacheble memory. 3454 * 3455 * It also serializes instructions: 3456 * - dcbt and dcbst. 3457 * 3458 * It separately serializes: 3459 * - tlbie and tlbsync. 3460 * 3461 * And separately serializes: 3462 * - slbieg, slbiag, and slbsync. 3463 * 3464 * The end result is that CI memory ordering requires TCG_MO_ALL 3465 * and it is not possible to special-case more relaxed ordering for 3466 * cacheable accesses. TCG_BAR_SC is required to provide this 3467 * serialization. 3468 */ 3469 3470 /* 3471 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3472 * tell the CPU it is a store-forwarding barrier. 3473 */ 3474 if (ctx->opcode & 0x2000000) { 3475 /* 3476 * ISA says that "Reserved fields in instructions are ignored 3477 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3478 * as this is not an instruction software should be using, 3479 * complain to the user. 3480 */ 3481 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3482 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3483 TARGET_FMT_lx "\n", ctx->cia); 3484 } else { 3485 bar = TCG_MO_ST_LD; 3486 } 3487 } 3488 3489 tcg_gen_mb(bar | TCG_BAR_SC); 3490 } 3491 3492 #if !defined(CONFIG_USER_ONLY) 3493 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3494 { 3495 TCGv_i32 t; 3496 TCGLabel *l; 3497 3498 if (!ctx->lazy_tlb_flush) { 3499 return; 3500 } 3501 l = gen_new_label(); 3502 t = tcg_temp_new_i32(); 3503 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3504 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3505 if (global) { 3506 gen_helper_check_tlb_flush_global(cpu_env); 3507 } else { 3508 gen_helper_check_tlb_flush_local(cpu_env); 3509 } 3510 gen_set_label(l); 3511 } 3512 #else 3513 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3514 #endif 3515 3516 /* isync */ 3517 static void gen_isync(DisasContext *ctx) 3518 { 3519 /* 3520 * We need to check for a pending TLB flush. This can only happen in 3521 * kernel mode however so check MSR_PR 3522 */ 3523 if (!ctx->pr) { 3524 gen_check_tlb_flush(ctx, false); 3525 } 3526 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3527 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3528 } 3529 3530 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3531 3532 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3533 { 3534 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3535 TCGv t0 = tcg_temp_new(); 3536 3537 gen_set_access_type(ctx, ACCESS_RES); 3538 gen_addr_reg_index(ctx, t0); 3539 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3540 tcg_gen_mov_tl(cpu_reserve, t0); 3541 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3542 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3543 } 3544 3545 #define LARX(name, memop) \ 3546 static void gen_##name(DisasContext *ctx) \ 3547 { \ 3548 gen_load_locked(ctx, memop); \ 3549 } 3550 3551 /* lwarx */ 3552 LARX(lbarx, DEF_MEMOP(MO_UB)) 3553 LARX(lharx, DEF_MEMOP(MO_UW)) 3554 LARX(lwarx, DEF_MEMOP(MO_UL)) 3555 3556 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3557 TCGv EA, TCGCond cond, int addend) 3558 { 3559 TCGv t = tcg_temp_new(); 3560 TCGv t2 = tcg_temp_new(); 3561 TCGv u = tcg_temp_new(); 3562 3563 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3564 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3565 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3566 tcg_gen_addi_tl(u, t, addend); 3567 3568 /* E.g. for fetch and increment bounded... */ 3569 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3570 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3571 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3572 3573 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3574 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3575 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3576 } 3577 3578 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3579 { 3580 uint32_t gpr_FC = FC(ctx->opcode); 3581 TCGv EA = tcg_temp_new(); 3582 int rt = rD(ctx->opcode); 3583 bool need_serial; 3584 TCGv src, dst; 3585 3586 gen_addr_register(ctx, EA); 3587 dst = cpu_gpr[rt]; 3588 src = cpu_gpr[(rt + 1) & 31]; 3589 3590 need_serial = false; 3591 memop |= MO_ALIGN; 3592 switch (gpr_FC) { 3593 case 0: /* Fetch and add */ 3594 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3595 break; 3596 case 1: /* Fetch and xor */ 3597 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3598 break; 3599 case 2: /* Fetch and or */ 3600 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3601 break; 3602 case 3: /* Fetch and 'and' */ 3603 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3604 break; 3605 case 4: /* Fetch and max unsigned */ 3606 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3607 break; 3608 case 5: /* Fetch and max signed */ 3609 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3610 break; 3611 case 6: /* Fetch and min unsigned */ 3612 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3613 break; 3614 case 7: /* Fetch and min signed */ 3615 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3616 break; 3617 case 8: /* Swap */ 3618 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3619 break; 3620 3621 case 16: /* Compare and swap not equal */ 3622 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3623 need_serial = true; 3624 } else { 3625 TCGv t0 = tcg_temp_new(); 3626 TCGv t1 = tcg_temp_new(); 3627 3628 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3629 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3630 tcg_gen_mov_tl(t1, src); 3631 } else { 3632 tcg_gen_ext32u_tl(t1, src); 3633 } 3634 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3635 cpu_gpr[(rt + 2) & 31], t0); 3636 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3637 tcg_gen_mov_tl(dst, t0); 3638 } 3639 break; 3640 3641 case 24: /* Fetch and increment bounded */ 3642 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3643 need_serial = true; 3644 } else { 3645 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3646 } 3647 break; 3648 case 25: /* Fetch and increment equal */ 3649 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3650 need_serial = true; 3651 } else { 3652 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3653 } 3654 break; 3655 case 28: /* Fetch and decrement bounded */ 3656 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3657 need_serial = true; 3658 } else { 3659 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3660 } 3661 break; 3662 3663 default: 3664 /* invoke data storage error handler */ 3665 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3666 } 3667 3668 if (need_serial) { 3669 /* Restart with exclusive lock. */ 3670 gen_helper_exit_atomic(cpu_env); 3671 ctx->base.is_jmp = DISAS_NORETURN; 3672 } 3673 } 3674 3675 static void gen_lwat(DisasContext *ctx) 3676 { 3677 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3678 } 3679 3680 #ifdef TARGET_PPC64 3681 static void gen_ldat(DisasContext *ctx) 3682 { 3683 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3684 } 3685 #endif 3686 3687 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3688 { 3689 uint32_t gpr_FC = FC(ctx->opcode); 3690 TCGv EA = tcg_temp_new(); 3691 TCGv src, discard; 3692 3693 gen_addr_register(ctx, EA); 3694 src = cpu_gpr[rD(ctx->opcode)]; 3695 discard = tcg_temp_new(); 3696 3697 memop |= MO_ALIGN; 3698 switch (gpr_FC) { 3699 case 0: /* add and Store */ 3700 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3701 break; 3702 case 1: /* xor and Store */ 3703 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3704 break; 3705 case 2: /* Or and Store */ 3706 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3707 break; 3708 case 3: /* 'and' and Store */ 3709 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3710 break; 3711 case 4: /* Store max unsigned */ 3712 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3713 break; 3714 case 5: /* Store max signed */ 3715 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3716 break; 3717 case 6: /* Store min unsigned */ 3718 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3719 break; 3720 case 7: /* Store min signed */ 3721 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3722 break; 3723 case 24: /* Store twin */ 3724 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3725 /* Restart with exclusive lock. */ 3726 gen_helper_exit_atomic(cpu_env); 3727 ctx->base.is_jmp = DISAS_NORETURN; 3728 } else { 3729 TCGv t = tcg_temp_new(); 3730 TCGv t2 = tcg_temp_new(); 3731 TCGv s = tcg_temp_new(); 3732 TCGv s2 = tcg_temp_new(); 3733 TCGv ea_plus_s = tcg_temp_new(); 3734 3735 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3736 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3737 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3738 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3739 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3740 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3741 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3742 } 3743 break; 3744 default: 3745 /* invoke data storage error handler */ 3746 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3747 } 3748 } 3749 3750 static void gen_stwat(DisasContext *ctx) 3751 { 3752 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3753 } 3754 3755 #ifdef TARGET_PPC64 3756 static void gen_stdat(DisasContext *ctx) 3757 { 3758 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3759 } 3760 #endif 3761 3762 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3763 { 3764 TCGLabel *lfail; 3765 TCGv EA; 3766 TCGv cr0; 3767 TCGv t0; 3768 int rs = rS(ctx->opcode); 3769 3770 lfail = gen_new_label(); 3771 EA = tcg_temp_new(); 3772 cr0 = tcg_temp_new(); 3773 t0 = tcg_temp_new(); 3774 3775 tcg_gen_mov_tl(cr0, cpu_so); 3776 gen_set_access_type(ctx, ACCESS_RES); 3777 gen_addr_reg_index(ctx, EA); 3778 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3779 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3780 3781 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3782 cpu_gpr[rs], ctx->mem_idx, 3783 DEF_MEMOP(memop) | MO_ALIGN); 3784 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3785 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3786 tcg_gen_or_tl(cr0, cr0, t0); 3787 3788 gen_set_label(lfail); 3789 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3790 tcg_gen_movi_tl(cpu_reserve, -1); 3791 } 3792 3793 #define STCX(name, memop) \ 3794 static void gen_##name(DisasContext *ctx) \ 3795 { \ 3796 gen_conditional_store(ctx, memop); \ 3797 } 3798 3799 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3800 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3801 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3802 3803 #if defined(TARGET_PPC64) 3804 /* ldarx */ 3805 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3806 /* stdcx. */ 3807 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3808 3809 /* lqarx */ 3810 static void gen_lqarx(DisasContext *ctx) 3811 { 3812 int rd = rD(ctx->opcode); 3813 TCGv EA, hi, lo; 3814 TCGv_i128 t16; 3815 3816 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3817 (rd == rB(ctx->opcode)))) { 3818 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3819 return; 3820 } 3821 3822 gen_set_access_type(ctx, ACCESS_RES); 3823 EA = tcg_temp_new(); 3824 gen_addr_reg_index(ctx, EA); 3825 3826 /* Note that the low part is always in RD+1, even in LE mode. */ 3827 lo = cpu_gpr[rd + 1]; 3828 hi = cpu_gpr[rd]; 3829 3830 t16 = tcg_temp_new_i128(); 3831 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3832 tcg_gen_extr_i128_i64(lo, hi, t16); 3833 3834 tcg_gen_mov_tl(cpu_reserve, EA); 3835 tcg_gen_movi_tl(cpu_reserve_length, 16); 3836 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3837 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3838 } 3839 3840 /* stqcx. */ 3841 static void gen_stqcx_(DisasContext *ctx) 3842 { 3843 TCGLabel *lfail; 3844 TCGv EA, t0, t1; 3845 TCGv cr0; 3846 TCGv_i128 cmp, val; 3847 int rs = rS(ctx->opcode); 3848 3849 if (unlikely(rs & 1)) { 3850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3851 return; 3852 } 3853 3854 lfail = gen_new_label(); 3855 EA = tcg_temp_new(); 3856 cr0 = tcg_temp_new(); 3857 3858 tcg_gen_mov_tl(cr0, cpu_so); 3859 gen_set_access_type(ctx, ACCESS_RES); 3860 gen_addr_reg_index(ctx, EA); 3861 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3862 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3863 3864 cmp = tcg_temp_new_i128(); 3865 val = tcg_temp_new_i128(); 3866 3867 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3868 3869 /* Note that the low part is always in RS+1, even in LE mode. */ 3870 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3871 3872 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3873 DEF_MEMOP(MO_128 | MO_ALIGN)); 3874 3875 t0 = tcg_temp_new(); 3876 t1 = tcg_temp_new(); 3877 tcg_gen_extr_i128_i64(t1, t0, val); 3878 3879 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3880 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3881 tcg_gen_or_tl(t0, t0, t1); 3882 3883 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3884 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3885 tcg_gen_or_tl(cr0, cr0, t0); 3886 3887 gen_set_label(lfail); 3888 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3889 tcg_gen_movi_tl(cpu_reserve, -1); 3890 } 3891 #endif /* defined(TARGET_PPC64) */ 3892 3893 /* sync */ 3894 static void gen_sync(DisasContext *ctx) 3895 { 3896 TCGBar bar = TCG_MO_ALL; 3897 uint32_t l = (ctx->opcode >> 21) & 3; 3898 3899 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3900 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3901 } 3902 3903 /* 3904 * We may need to check for a pending TLB flush. 3905 * 3906 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3907 * 3908 * Additionally, this can only happen in kernel mode however so 3909 * check MSR_PR as well. 3910 */ 3911 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3912 gen_check_tlb_flush(ctx, true); 3913 } 3914 3915 tcg_gen_mb(bar | TCG_BAR_SC); 3916 } 3917 3918 /* wait */ 3919 static void gen_wait(DisasContext *ctx) 3920 { 3921 uint32_t wc; 3922 3923 if (ctx->insns_flags & PPC_WAIT) { 3924 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3925 3926 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3927 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3928 wc = WC(ctx->opcode); 3929 } else { 3930 wc = 0; 3931 } 3932 3933 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3934 /* v3.0 defines a new 'wait' encoding. */ 3935 wc = WC(ctx->opcode); 3936 if (ctx->insns_flags2 & PPC2_ISA310) { 3937 uint32_t pl = PL(ctx->opcode); 3938 3939 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3940 if (wc == 3) { 3941 gen_invalid(ctx); 3942 return; 3943 } 3944 3945 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3946 if (pl > 0 && wc != 2) { 3947 gen_invalid(ctx); 3948 return; 3949 } 3950 3951 } else { /* ISA300 */ 3952 /* WC 1-3 are reserved */ 3953 if (wc > 0) { 3954 gen_invalid(ctx); 3955 return; 3956 } 3957 } 3958 3959 } else { 3960 warn_report("wait instruction decoded with wrong ISA flags."); 3961 gen_invalid(ctx); 3962 return; 3963 } 3964 3965 /* 3966 * wait without WC field or with WC=0 waits for an exception / interrupt 3967 * to occur. 3968 */ 3969 if (wc == 0) { 3970 TCGv_i32 t0 = tcg_constant_i32(1); 3971 tcg_gen_st_i32(t0, cpu_env, 3972 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3973 /* Stop translation, as the CPU is supposed to sleep from now */ 3974 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3975 } 3976 3977 /* 3978 * Other wait types must not just wait until an exception occurs because 3979 * ignoring their other wake-up conditions could cause a hang. 3980 * 3981 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3982 * no-ops. 3983 * 3984 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3985 * 3986 * wc=2 waits for an implementation-specific condition, such could be 3987 * always true, so it can be implemented as a no-op. 3988 * 3989 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3990 * 3991 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3992 * Reservation-loss may have implementation-specific conditions, so it 3993 * can be implemented as a no-op. 3994 * 3995 * wc=2 waits for an exception or an amount of time to pass. This 3996 * amount is implementation-specific so it can be implemented as a 3997 * no-op. 3998 * 3999 * ISA v3.1 allows for execution to resume "in the rare case of 4000 * an implementation-dependent event", so in any case software must 4001 * not depend on the architected resumption condition to become 4002 * true, so no-op implementations should be architecturally correct 4003 * (if suboptimal). 4004 */ 4005 } 4006 4007 #if defined(TARGET_PPC64) 4008 static void gen_doze(DisasContext *ctx) 4009 { 4010 #if defined(CONFIG_USER_ONLY) 4011 GEN_PRIV(ctx); 4012 #else 4013 TCGv_i32 t; 4014 4015 CHK_HV(ctx); 4016 translator_io_start(&ctx->base); 4017 t = tcg_constant_i32(PPC_PM_DOZE); 4018 gen_helper_pminsn(cpu_env, t); 4019 /* Stop translation, as the CPU is supposed to sleep from now */ 4020 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4021 #endif /* defined(CONFIG_USER_ONLY) */ 4022 } 4023 4024 static void gen_nap(DisasContext *ctx) 4025 { 4026 #if defined(CONFIG_USER_ONLY) 4027 GEN_PRIV(ctx); 4028 #else 4029 TCGv_i32 t; 4030 4031 CHK_HV(ctx); 4032 translator_io_start(&ctx->base); 4033 t = tcg_constant_i32(PPC_PM_NAP); 4034 gen_helper_pminsn(cpu_env, t); 4035 /* Stop translation, as the CPU is supposed to sleep from now */ 4036 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4037 #endif /* defined(CONFIG_USER_ONLY) */ 4038 } 4039 4040 static void gen_stop(DisasContext *ctx) 4041 { 4042 #if defined(CONFIG_USER_ONLY) 4043 GEN_PRIV(ctx); 4044 #else 4045 TCGv_i32 t; 4046 4047 CHK_HV(ctx); 4048 translator_io_start(&ctx->base); 4049 t = tcg_constant_i32(PPC_PM_STOP); 4050 gen_helper_pminsn(cpu_env, t); 4051 /* Stop translation, as the CPU is supposed to sleep from now */ 4052 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4053 #endif /* defined(CONFIG_USER_ONLY) */ 4054 } 4055 4056 static void gen_sleep(DisasContext *ctx) 4057 { 4058 #if defined(CONFIG_USER_ONLY) 4059 GEN_PRIV(ctx); 4060 #else 4061 TCGv_i32 t; 4062 4063 CHK_HV(ctx); 4064 translator_io_start(&ctx->base); 4065 t = tcg_constant_i32(PPC_PM_SLEEP); 4066 gen_helper_pminsn(cpu_env, t); 4067 /* Stop translation, as the CPU is supposed to sleep from now */ 4068 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4069 #endif /* defined(CONFIG_USER_ONLY) */ 4070 } 4071 4072 static void gen_rvwinkle(DisasContext *ctx) 4073 { 4074 #if defined(CONFIG_USER_ONLY) 4075 GEN_PRIV(ctx); 4076 #else 4077 TCGv_i32 t; 4078 4079 CHK_HV(ctx); 4080 translator_io_start(&ctx->base); 4081 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4082 gen_helper_pminsn(cpu_env, t); 4083 /* Stop translation, as the CPU is supposed to sleep from now */ 4084 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4085 #endif /* defined(CONFIG_USER_ONLY) */ 4086 } 4087 #endif /* #if defined(TARGET_PPC64) */ 4088 4089 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4090 { 4091 #if defined(TARGET_PPC64) 4092 if (ctx->has_cfar) { 4093 tcg_gen_movi_tl(cpu_cfar, nip); 4094 } 4095 #endif 4096 } 4097 4098 #if defined(TARGET_PPC64) 4099 static void pmu_count_insns(DisasContext *ctx) 4100 { 4101 /* 4102 * Do not bother calling the helper if the PMU isn't counting 4103 * instructions. 4104 */ 4105 if (!ctx->pmu_insn_cnt) { 4106 return; 4107 } 4108 4109 #if !defined(CONFIG_USER_ONLY) 4110 TCGLabel *l; 4111 TCGv t0; 4112 4113 /* 4114 * The PMU insns_inc() helper stops the internal PMU timer if a 4115 * counter overflows happens. In that case, if the guest is 4116 * running with icount and we do not handle it beforehand, 4117 * the helper can trigger a 'bad icount read'. 4118 */ 4119 translator_io_start(&ctx->base); 4120 4121 /* Avoid helper calls when only PMC5-6 are enabled. */ 4122 if (!ctx->pmc_other) { 4123 l = gen_new_label(); 4124 t0 = tcg_temp_new(); 4125 4126 gen_load_spr(t0, SPR_POWER_PMC5); 4127 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4128 gen_store_spr(SPR_POWER_PMC5, t0); 4129 /* Check for overflow, if it's enabled */ 4130 if (ctx->mmcr0_pmcjce) { 4131 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4132 gen_helper_handle_pmc5_overflow(cpu_env); 4133 } 4134 4135 gen_set_label(l); 4136 } else { 4137 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4138 } 4139 #else 4140 /* 4141 * User mode can read (but not write) PMC5 and start/stop 4142 * the PMU via MMCR0_FC. In this case just increment 4143 * PMC5 with base.num_insns. 4144 */ 4145 TCGv t0 = tcg_temp_new(); 4146 4147 gen_load_spr(t0, SPR_POWER_PMC5); 4148 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4149 gen_store_spr(SPR_POWER_PMC5, t0); 4150 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4151 } 4152 #else 4153 static void pmu_count_insns(DisasContext *ctx) 4154 { 4155 return; 4156 } 4157 #endif /* #if defined(TARGET_PPC64) */ 4158 4159 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4160 { 4161 return translator_use_goto_tb(&ctx->base, dest); 4162 } 4163 4164 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4165 { 4166 if (unlikely(ctx->singlestep_enabled)) { 4167 gen_debug_exception(ctx); 4168 } else { 4169 /* 4170 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4171 * CF_NO_GOTO_PTR is set. Count insns now. 4172 */ 4173 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4174 pmu_count_insns(ctx); 4175 } 4176 4177 tcg_gen_lookup_and_goto_ptr(); 4178 } 4179 } 4180 4181 /*** Branch ***/ 4182 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4183 { 4184 if (NARROW_MODE(ctx)) { 4185 dest = (uint32_t) dest; 4186 } 4187 if (use_goto_tb(ctx, dest)) { 4188 pmu_count_insns(ctx); 4189 tcg_gen_goto_tb(n); 4190 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4191 tcg_gen_exit_tb(ctx->base.tb, n); 4192 } else { 4193 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4194 gen_lookup_and_goto_ptr(ctx); 4195 } 4196 } 4197 4198 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4199 { 4200 if (NARROW_MODE(ctx)) { 4201 nip = (uint32_t)nip; 4202 } 4203 tcg_gen_movi_tl(cpu_lr, nip); 4204 } 4205 4206 /* b ba bl bla */ 4207 static void gen_b(DisasContext *ctx) 4208 { 4209 target_ulong li, target; 4210 4211 /* sign extend LI */ 4212 li = LI(ctx->opcode); 4213 li = (li ^ 0x02000000) - 0x02000000; 4214 if (likely(AA(ctx->opcode) == 0)) { 4215 target = ctx->cia + li; 4216 } else { 4217 target = li; 4218 } 4219 if (LK(ctx->opcode)) { 4220 gen_setlr(ctx, ctx->base.pc_next); 4221 } 4222 gen_update_cfar(ctx, ctx->cia); 4223 gen_goto_tb(ctx, 0, target); 4224 ctx->base.is_jmp = DISAS_NORETURN; 4225 } 4226 4227 #define BCOND_IM 0 4228 #define BCOND_LR 1 4229 #define BCOND_CTR 2 4230 #define BCOND_TAR 3 4231 4232 static void gen_bcond(DisasContext *ctx, int type) 4233 { 4234 uint32_t bo = BO(ctx->opcode); 4235 TCGLabel *l1; 4236 TCGv target; 4237 4238 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4239 target = tcg_temp_new(); 4240 if (type == BCOND_CTR) { 4241 tcg_gen_mov_tl(target, cpu_ctr); 4242 } else if (type == BCOND_TAR) { 4243 gen_load_spr(target, SPR_TAR); 4244 } else { 4245 tcg_gen_mov_tl(target, cpu_lr); 4246 } 4247 } else { 4248 target = NULL; 4249 } 4250 if (LK(ctx->opcode)) { 4251 gen_setlr(ctx, ctx->base.pc_next); 4252 } 4253 l1 = gen_new_label(); 4254 if ((bo & 0x4) == 0) { 4255 /* Decrement and test CTR */ 4256 TCGv temp = tcg_temp_new(); 4257 4258 if (type == BCOND_CTR) { 4259 /* 4260 * All ISAs up to v3 describe this form of bcctr as invalid but 4261 * some processors, ie. 64-bit server processors compliant with 4262 * arch 2.x, do implement a "test and decrement" logic instead, 4263 * as described in their respective UMs. This logic involves CTR 4264 * to act as both the branch target and a counter, which makes 4265 * it basically useless and thus never used in real code. 4266 * 4267 * This form was hence chosen to trigger extra micro-architectural 4268 * side-effect on real HW needed for the Spectre v2 workaround. 4269 * It is up to guests that implement such workaround, ie. linux, to 4270 * use this form in a way it just triggers the side-effect without 4271 * doing anything else harmful. 4272 */ 4273 if (unlikely(!is_book3s_arch2x(ctx))) { 4274 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4275 return; 4276 } 4277 4278 if (NARROW_MODE(ctx)) { 4279 tcg_gen_ext32u_tl(temp, cpu_ctr); 4280 } else { 4281 tcg_gen_mov_tl(temp, cpu_ctr); 4282 } 4283 if (bo & 0x2) { 4284 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4285 } else { 4286 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4287 } 4288 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4289 } else { 4290 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4291 if (NARROW_MODE(ctx)) { 4292 tcg_gen_ext32u_tl(temp, cpu_ctr); 4293 } else { 4294 tcg_gen_mov_tl(temp, cpu_ctr); 4295 } 4296 if (bo & 0x2) { 4297 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4298 } else { 4299 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4300 } 4301 } 4302 } 4303 if ((bo & 0x10) == 0) { 4304 /* Test CR */ 4305 uint32_t bi = BI(ctx->opcode); 4306 uint32_t mask = 0x08 >> (bi & 0x03); 4307 TCGv_i32 temp = tcg_temp_new_i32(); 4308 4309 if (bo & 0x8) { 4310 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4311 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4312 } else { 4313 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4314 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4315 } 4316 } 4317 gen_update_cfar(ctx, ctx->cia); 4318 if (type == BCOND_IM) { 4319 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4320 if (likely(AA(ctx->opcode) == 0)) { 4321 gen_goto_tb(ctx, 0, ctx->cia + li); 4322 } else { 4323 gen_goto_tb(ctx, 0, li); 4324 } 4325 } else { 4326 if (NARROW_MODE(ctx)) { 4327 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4328 } else { 4329 tcg_gen_andi_tl(cpu_nip, target, ~3); 4330 } 4331 gen_lookup_and_goto_ptr(ctx); 4332 } 4333 if ((bo & 0x14) != 0x14) { 4334 /* fallthrough case */ 4335 gen_set_label(l1); 4336 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4337 } 4338 ctx->base.is_jmp = DISAS_NORETURN; 4339 } 4340 4341 static void gen_bc(DisasContext *ctx) 4342 { 4343 gen_bcond(ctx, BCOND_IM); 4344 } 4345 4346 static void gen_bcctr(DisasContext *ctx) 4347 { 4348 gen_bcond(ctx, BCOND_CTR); 4349 } 4350 4351 static void gen_bclr(DisasContext *ctx) 4352 { 4353 gen_bcond(ctx, BCOND_LR); 4354 } 4355 4356 static void gen_bctar(DisasContext *ctx) 4357 { 4358 gen_bcond(ctx, BCOND_TAR); 4359 } 4360 4361 /*** Condition register logical ***/ 4362 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4363 static void glue(gen_, name)(DisasContext *ctx) \ 4364 { \ 4365 uint8_t bitmask; \ 4366 int sh; \ 4367 TCGv_i32 t0, t1; \ 4368 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4369 t0 = tcg_temp_new_i32(); \ 4370 if (sh > 0) \ 4371 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4372 else if (sh < 0) \ 4373 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4374 else \ 4375 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4376 t1 = tcg_temp_new_i32(); \ 4377 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4378 if (sh > 0) \ 4379 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4380 else if (sh < 0) \ 4381 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4382 else \ 4383 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4384 tcg_op(t0, t0, t1); \ 4385 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4386 tcg_gen_andi_i32(t0, t0, bitmask); \ 4387 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4388 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4389 } 4390 4391 /* crand */ 4392 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4393 /* crandc */ 4394 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4395 /* creqv */ 4396 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4397 /* crnand */ 4398 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4399 /* crnor */ 4400 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4401 /* cror */ 4402 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4403 /* crorc */ 4404 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4405 /* crxor */ 4406 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4407 4408 /* mcrf */ 4409 static void gen_mcrf(DisasContext *ctx) 4410 { 4411 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4412 } 4413 4414 /*** System linkage ***/ 4415 4416 /* rfi (supervisor only) */ 4417 static void gen_rfi(DisasContext *ctx) 4418 { 4419 #if defined(CONFIG_USER_ONLY) 4420 GEN_PRIV(ctx); 4421 #else 4422 /* 4423 * This instruction doesn't exist anymore on 64-bit server 4424 * processors compliant with arch 2.x 4425 */ 4426 if (is_book3s_arch2x(ctx)) { 4427 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4428 return; 4429 } 4430 /* Restore CPU state */ 4431 CHK_SV(ctx); 4432 translator_io_start(&ctx->base); 4433 gen_update_cfar(ctx, ctx->cia); 4434 gen_helper_rfi(cpu_env); 4435 ctx->base.is_jmp = DISAS_EXIT; 4436 #endif 4437 } 4438 4439 #if defined(TARGET_PPC64) 4440 static void gen_rfid(DisasContext *ctx) 4441 { 4442 #if defined(CONFIG_USER_ONLY) 4443 GEN_PRIV(ctx); 4444 #else 4445 /* Restore CPU state */ 4446 CHK_SV(ctx); 4447 translator_io_start(&ctx->base); 4448 gen_update_cfar(ctx, ctx->cia); 4449 gen_helper_rfid(cpu_env); 4450 ctx->base.is_jmp = DISAS_EXIT; 4451 #endif 4452 } 4453 4454 #if !defined(CONFIG_USER_ONLY) 4455 static void gen_rfscv(DisasContext *ctx) 4456 { 4457 #if defined(CONFIG_USER_ONLY) 4458 GEN_PRIV(ctx); 4459 #else 4460 /* Restore CPU state */ 4461 CHK_SV(ctx); 4462 translator_io_start(&ctx->base); 4463 gen_update_cfar(ctx, ctx->cia); 4464 gen_helper_rfscv(cpu_env); 4465 ctx->base.is_jmp = DISAS_EXIT; 4466 #endif 4467 } 4468 #endif 4469 4470 static void gen_hrfid(DisasContext *ctx) 4471 { 4472 #if defined(CONFIG_USER_ONLY) 4473 GEN_PRIV(ctx); 4474 #else 4475 /* Restore CPU state */ 4476 CHK_HV(ctx); 4477 translator_io_start(&ctx->base); 4478 gen_helper_hrfid(cpu_env); 4479 ctx->base.is_jmp = DISAS_EXIT; 4480 #endif 4481 } 4482 #endif 4483 4484 /* sc */ 4485 #if defined(CONFIG_USER_ONLY) 4486 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4487 #else 4488 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4489 #endif 4490 static void gen_sc(DisasContext *ctx) 4491 { 4492 uint32_t lev; 4493 4494 /* 4495 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4496 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4497 * for Ultravisor which TCG does not support, so just ignore the top 6. 4498 */ 4499 lev = (ctx->opcode >> 5) & 0x1; 4500 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4501 } 4502 4503 #if defined(TARGET_PPC64) 4504 #if !defined(CONFIG_USER_ONLY) 4505 static void gen_scv(DisasContext *ctx) 4506 { 4507 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4508 4509 /* Set the PC back to the faulting instruction. */ 4510 gen_update_nip(ctx, ctx->cia); 4511 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4512 4513 ctx->base.is_jmp = DISAS_NORETURN; 4514 } 4515 #endif 4516 #endif 4517 4518 /*** Trap ***/ 4519 4520 /* Check for unconditional traps (always or never) */ 4521 static bool check_unconditional_trap(DisasContext *ctx) 4522 { 4523 /* Trap never */ 4524 if (TO(ctx->opcode) == 0) { 4525 return true; 4526 } 4527 /* Trap always */ 4528 if (TO(ctx->opcode) == 31) { 4529 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4530 return true; 4531 } 4532 return false; 4533 } 4534 4535 /* tw */ 4536 static void gen_tw(DisasContext *ctx) 4537 { 4538 TCGv_i32 t0; 4539 4540 if (check_unconditional_trap(ctx)) { 4541 return; 4542 } 4543 t0 = tcg_constant_i32(TO(ctx->opcode)); 4544 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4545 t0); 4546 } 4547 4548 /* twi */ 4549 static void gen_twi(DisasContext *ctx) 4550 { 4551 TCGv t0; 4552 TCGv_i32 t1; 4553 4554 if (check_unconditional_trap(ctx)) { 4555 return; 4556 } 4557 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4558 t1 = tcg_constant_i32(TO(ctx->opcode)); 4559 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4560 } 4561 4562 #if defined(TARGET_PPC64) 4563 /* td */ 4564 static void gen_td(DisasContext *ctx) 4565 { 4566 TCGv_i32 t0; 4567 4568 if (check_unconditional_trap(ctx)) { 4569 return; 4570 } 4571 t0 = tcg_constant_i32(TO(ctx->opcode)); 4572 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4573 t0); 4574 } 4575 4576 /* tdi */ 4577 static void gen_tdi(DisasContext *ctx) 4578 { 4579 TCGv t0; 4580 TCGv_i32 t1; 4581 4582 if (check_unconditional_trap(ctx)) { 4583 return; 4584 } 4585 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4586 t1 = tcg_constant_i32(TO(ctx->opcode)); 4587 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4588 } 4589 #endif 4590 4591 /*** Processor control ***/ 4592 4593 /* mcrxr */ 4594 static void gen_mcrxr(DisasContext *ctx) 4595 { 4596 TCGv_i32 t0 = tcg_temp_new_i32(); 4597 TCGv_i32 t1 = tcg_temp_new_i32(); 4598 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4599 4600 tcg_gen_trunc_tl_i32(t0, cpu_so); 4601 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4602 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4603 tcg_gen_shli_i32(t0, t0, 3); 4604 tcg_gen_shli_i32(t1, t1, 2); 4605 tcg_gen_shli_i32(dst, dst, 1); 4606 tcg_gen_or_i32(dst, dst, t0); 4607 tcg_gen_or_i32(dst, dst, t1); 4608 4609 tcg_gen_movi_tl(cpu_so, 0); 4610 tcg_gen_movi_tl(cpu_ov, 0); 4611 tcg_gen_movi_tl(cpu_ca, 0); 4612 } 4613 4614 #ifdef TARGET_PPC64 4615 /* mcrxrx */ 4616 static void gen_mcrxrx(DisasContext *ctx) 4617 { 4618 TCGv t0 = tcg_temp_new(); 4619 TCGv t1 = tcg_temp_new(); 4620 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4621 4622 /* copy OV and OV32 */ 4623 tcg_gen_shli_tl(t0, cpu_ov, 1); 4624 tcg_gen_or_tl(t0, t0, cpu_ov32); 4625 tcg_gen_shli_tl(t0, t0, 2); 4626 /* copy CA and CA32 */ 4627 tcg_gen_shli_tl(t1, cpu_ca, 1); 4628 tcg_gen_or_tl(t1, t1, cpu_ca32); 4629 tcg_gen_or_tl(t0, t0, t1); 4630 tcg_gen_trunc_tl_i32(dst, t0); 4631 } 4632 #endif 4633 4634 /* mfcr mfocrf */ 4635 static void gen_mfcr(DisasContext *ctx) 4636 { 4637 uint32_t crm, crn; 4638 4639 if (likely(ctx->opcode & 0x00100000)) { 4640 crm = CRM(ctx->opcode); 4641 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4642 crn = ctz32(crm); 4643 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4644 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4645 cpu_gpr[rD(ctx->opcode)], crn * 4); 4646 } 4647 } else { 4648 TCGv_i32 t0 = tcg_temp_new_i32(); 4649 tcg_gen_mov_i32(t0, cpu_crf[0]); 4650 tcg_gen_shli_i32(t0, t0, 4); 4651 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4652 tcg_gen_shli_i32(t0, t0, 4); 4653 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4654 tcg_gen_shli_i32(t0, t0, 4); 4655 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4656 tcg_gen_shli_i32(t0, t0, 4); 4657 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4658 tcg_gen_shli_i32(t0, t0, 4); 4659 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4660 tcg_gen_shli_i32(t0, t0, 4); 4661 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4662 tcg_gen_shli_i32(t0, t0, 4); 4663 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4664 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4665 } 4666 } 4667 4668 /* mfmsr */ 4669 static void gen_mfmsr(DisasContext *ctx) 4670 { 4671 CHK_SV(ctx); 4672 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4673 } 4674 4675 /* mfspr */ 4676 static inline void gen_op_mfspr(DisasContext *ctx) 4677 { 4678 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4679 uint32_t sprn = SPR(ctx->opcode); 4680 4681 #if defined(CONFIG_USER_ONLY) 4682 read_cb = ctx->spr_cb[sprn].uea_read; 4683 #else 4684 if (ctx->pr) { 4685 read_cb = ctx->spr_cb[sprn].uea_read; 4686 } else if (ctx->hv) { 4687 read_cb = ctx->spr_cb[sprn].hea_read; 4688 } else { 4689 read_cb = ctx->spr_cb[sprn].oea_read; 4690 } 4691 #endif 4692 if (likely(read_cb != NULL)) { 4693 if (likely(read_cb != SPR_NOACCESS)) { 4694 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4695 } else { 4696 /* Privilege exception */ 4697 /* 4698 * This is a hack to avoid warnings when running Linux: 4699 * this OS breaks the PowerPC virtualisation model, 4700 * allowing userland application to read the PVR 4701 */ 4702 if (sprn != SPR_PVR) { 4703 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4704 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4705 ctx->cia); 4706 } 4707 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4708 } 4709 } else { 4710 /* ISA 2.07 defines these as no-ops */ 4711 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4712 (sprn >= 808 && sprn <= 811)) { 4713 /* This is a nop */ 4714 return; 4715 } 4716 /* Not defined */ 4717 qemu_log_mask(LOG_GUEST_ERROR, 4718 "Trying to read invalid spr %d (0x%03x) at " 4719 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4720 4721 /* 4722 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4723 * generate a priv, a hv emu or a no-op 4724 */ 4725 if (sprn & 0x10) { 4726 if (ctx->pr) { 4727 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4728 } 4729 } else { 4730 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4731 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4732 } 4733 } 4734 } 4735 } 4736 4737 static void gen_mfspr(DisasContext *ctx) 4738 { 4739 gen_op_mfspr(ctx); 4740 } 4741 4742 /* mftb */ 4743 static void gen_mftb(DisasContext *ctx) 4744 { 4745 gen_op_mfspr(ctx); 4746 } 4747 4748 /* mtcrf mtocrf*/ 4749 static void gen_mtcrf(DisasContext *ctx) 4750 { 4751 uint32_t crm, crn; 4752 4753 crm = CRM(ctx->opcode); 4754 if (likely((ctx->opcode & 0x00100000))) { 4755 if (crm && ((crm & (crm - 1)) == 0)) { 4756 TCGv_i32 temp = tcg_temp_new_i32(); 4757 crn = ctz32(crm); 4758 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4759 tcg_gen_shri_i32(temp, temp, crn * 4); 4760 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4761 } 4762 } else { 4763 TCGv_i32 temp = tcg_temp_new_i32(); 4764 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4765 for (crn = 0 ; crn < 8 ; crn++) { 4766 if (crm & (1 << crn)) { 4767 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4768 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4769 } 4770 } 4771 } 4772 } 4773 4774 /* mtmsr */ 4775 #if defined(TARGET_PPC64) 4776 static void gen_mtmsrd(DisasContext *ctx) 4777 { 4778 if (unlikely(!is_book3s_arch2x(ctx))) { 4779 gen_invalid(ctx); 4780 return; 4781 } 4782 4783 CHK_SV(ctx); 4784 4785 #if !defined(CONFIG_USER_ONLY) 4786 TCGv t0, t1; 4787 target_ulong mask; 4788 4789 t0 = tcg_temp_new(); 4790 t1 = tcg_temp_new(); 4791 4792 translator_io_start(&ctx->base); 4793 4794 if (ctx->opcode & 0x00010000) { 4795 /* L=1 form only updates EE and RI */ 4796 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4797 } else { 4798 /* mtmsrd does not alter HV, S, ME, or LE */ 4799 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4800 (1ULL << MSR_HV)); 4801 /* 4802 * XXX: we need to update nip before the store if we enter 4803 * power saving mode, we will exit the loop directly from 4804 * ppc_store_msr 4805 */ 4806 gen_update_nip(ctx, ctx->base.pc_next); 4807 } 4808 4809 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4810 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4811 tcg_gen_or_tl(t0, t0, t1); 4812 4813 gen_helper_store_msr(cpu_env, t0); 4814 4815 /* Must stop the translation as machine state (may have) changed */ 4816 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4817 #endif /* !defined(CONFIG_USER_ONLY) */ 4818 } 4819 #endif /* defined(TARGET_PPC64) */ 4820 4821 static void gen_mtmsr(DisasContext *ctx) 4822 { 4823 CHK_SV(ctx); 4824 4825 #if !defined(CONFIG_USER_ONLY) 4826 TCGv t0, t1; 4827 target_ulong mask = 0xFFFFFFFF; 4828 4829 t0 = tcg_temp_new(); 4830 t1 = tcg_temp_new(); 4831 4832 translator_io_start(&ctx->base); 4833 if (ctx->opcode & 0x00010000) { 4834 /* L=1 form only updates EE and RI */ 4835 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4836 } else { 4837 /* mtmsr does not alter S, ME, or LE */ 4838 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4839 4840 /* 4841 * XXX: we need to update nip before the store if we enter 4842 * power saving mode, we will exit the loop directly from 4843 * ppc_store_msr 4844 */ 4845 gen_update_nip(ctx, ctx->base.pc_next); 4846 } 4847 4848 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4849 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4850 tcg_gen_or_tl(t0, t0, t1); 4851 4852 gen_helper_store_msr(cpu_env, t0); 4853 4854 /* Must stop the translation as machine state (may have) changed */ 4855 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4856 #endif 4857 } 4858 4859 /* mtspr */ 4860 static void gen_mtspr(DisasContext *ctx) 4861 { 4862 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4863 uint32_t sprn = SPR(ctx->opcode); 4864 4865 #if defined(CONFIG_USER_ONLY) 4866 write_cb = ctx->spr_cb[sprn].uea_write; 4867 #else 4868 if (ctx->pr) { 4869 write_cb = ctx->spr_cb[sprn].uea_write; 4870 } else if (ctx->hv) { 4871 write_cb = ctx->spr_cb[sprn].hea_write; 4872 } else { 4873 write_cb = ctx->spr_cb[sprn].oea_write; 4874 } 4875 #endif 4876 if (likely(write_cb != NULL)) { 4877 if (likely(write_cb != SPR_NOACCESS)) { 4878 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4879 } else { 4880 /* Privilege exception */ 4881 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4882 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4883 ctx->cia); 4884 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4885 } 4886 } else { 4887 /* ISA 2.07 defines these as no-ops */ 4888 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4889 (sprn >= 808 && sprn <= 811)) { 4890 /* This is a nop */ 4891 return; 4892 } 4893 4894 /* Not defined */ 4895 qemu_log_mask(LOG_GUEST_ERROR, 4896 "Trying to write invalid spr %d (0x%03x) at " 4897 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4898 4899 4900 /* 4901 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4902 * generate a priv, a hv emu or a no-op 4903 */ 4904 if (sprn & 0x10) { 4905 if (ctx->pr) { 4906 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4907 } 4908 } else { 4909 if (ctx->pr || sprn == 0) { 4910 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4911 } 4912 } 4913 } 4914 } 4915 4916 #if defined(TARGET_PPC64) 4917 /* setb */ 4918 static void gen_setb(DisasContext *ctx) 4919 { 4920 TCGv_i32 t0 = tcg_temp_new_i32(); 4921 TCGv_i32 t8 = tcg_constant_i32(8); 4922 TCGv_i32 tm1 = tcg_constant_i32(-1); 4923 int crf = crfS(ctx->opcode); 4924 4925 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4926 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4927 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4928 } 4929 #endif 4930 4931 /*** Cache management ***/ 4932 4933 /* dcbf */ 4934 static void gen_dcbf(DisasContext *ctx) 4935 { 4936 /* XXX: specification says this is treated as a load by the MMU */ 4937 TCGv t0; 4938 gen_set_access_type(ctx, ACCESS_CACHE); 4939 t0 = tcg_temp_new(); 4940 gen_addr_reg_index(ctx, t0); 4941 gen_qemu_ld8u(ctx, t0, t0); 4942 } 4943 4944 /* dcbfep (external PID dcbf) */ 4945 static void gen_dcbfep(DisasContext *ctx) 4946 { 4947 /* XXX: specification says this is treated as a load by the MMU */ 4948 TCGv t0; 4949 CHK_SV(ctx); 4950 gen_set_access_type(ctx, ACCESS_CACHE); 4951 t0 = tcg_temp_new(); 4952 gen_addr_reg_index(ctx, t0); 4953 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4954 } 4955 4956 /* dcbi (Supervisor only) */ 4957 static void gen_dcbi(DisasContext *ctx) 4958 { 4959 #if defined(CONFIG_USER_ONLY) 4960 GEN_PRIV(ctx); 4961 #else 4962 TCGv EA, val; 4963 4964 CHK_SV(ctx); 4965 EA = tcg_temp_new(); 4966 gen_set_access_type(ctx, ACCESS_CACHE); 4967 gen_addr_reg_index(ctx, EA); 4968 val = tcg_temp_new(); 4969 /* XXX: specification says this should be treated as a store by the MMU */ 4970 gen_qemu_ld8u(ctx, val, EA); 4971 gen_qemu_st8(ctx, val, EA); 4972 #endif /* defined(CONFIG_USER_ONLY) */ 4973 } 4974 4975 /* dcdst */ 4976 static void gen_dcbst(DisasContext *ctx) 4977 { 4978 /* XXX: specification say this is treated as a load by the MMU */ 4979 TCGv t0; 4980 gen_set_access_type(ctx, ACCESS_CACHE); 4981 t0 = tcg_temp_new(); 4982 gen_addr_reg_index(ctx, t0); 4983 gen_qemu_ld8u(ctx, t0, t0); 4984 } 4985 4986 /* dcbstep (dcbstep External PID version) */ 4987 static void gen_dcbstep(DisasContext *ctx) 4988 { 4989 /* XXX: specification say this is treated as a load by the MMU */ 4990 TCGv t0; 4991 gen_set_access_type(ctx, ACCESS_CACHE); 4992 t0 = tcg_temp_new(); 4993 gen_addr_reg_index(ctx, t0); 4994 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4995 } 4996 4997 /* dcbt */ 4998 static void gen_dcbt(DisasContext *ctx) 4999 { 5000 /* 5001 * interpreted as no-op 5002 * XXX: specification say this is treated as a load by the MMU but 5003 * does not generate any exception 5004 */ 5005 } 5006 5007 /* dcbtep */ 5008 static void gen_dcbtep(DisasContext *ctx) 5009 { 5010 /* 5011 * interpreted as no-op 5012 * XXX: specification say this is treated as a load by the MMU but 5013 * does not generate any exception 5014 */ 5015 } 5016 5017 /* dcbtst */ 5018 static void gen_dcbtst(DisasContext *ctx) 5019 { 5020 /* 5021 * interpreted as no-op 5022 * XXX: specification say this is treated as a load by the MMU but 5023 * does not generate any exception 5024 */ 5025 } 5026 5027 /* dcbtstep */ 5028 static void gen_dcbtstep(DisasContext *ctx) 5029 { 5030 /* 5031 * interpreted as no-op 5032 * XXX: specification say this is treated as a load by the MMU but 5033 * does not generate any exception 5034 */ 5035 } 5036 5037 /* dcbtls */ 5038 static void gen_dcbtls(DisasContext *ctx) 5039 { 5040 /* Always fails locking the cache */ 5041 TCGv t0 = tcg_temp_new(); 5042 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5043 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5044 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5045 } 5046 5047 /* dcblc */ 5048 static void gen_dcblc(DisasContext *ctx) 5049 { 5050 /* 5051 * interpreted as no-op 5052 */ 5053 } 5054 5055 /* dcbz */ 5056 static void gen_dcbz(DisasContext *ctx) 5057 { 5058 TCGv tcgv_addr; 5059 TCGv_i32 tcgv_op; 5060 5061 gen_set_access_type(ctx, ACCESS_CACHE); 5062 tcgv_addr = tcg_temp_new(); 5063 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5064 gen_addr_reg_index(ctx, tcgv_addr); 5065 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5066 } 5067 5068 /* dcbzep */ 5069 static void gen_dcbzep(DisasContext *ctx) 5070 { 5071 TCGv tcgv_addr; 5072 TCGv_i32 tcgv_op; 5073 5074 gen_set_access_type(ctx, ACCESS_CACHE); 5075 tcgv_addr = tcg_temp_new(); 5076 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5077 gen_addr_reg_index(ctx, tcgv_addr); 5078 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5079 } 5080 5081 /* dst / dstt */ 5082 static void gen_dst(DisasContext *ctx) 5083 { 5084 if (rA(ctx->opcode) == 0) { 5085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5086 } else { 5087 /* interpreted as no-op */ 5088 } 5089 } 5090 5091 /* dstst /dststt */ 5092 static void gen_dstst(DisasContext *ctx) 5093 { 5094 if (rA(ctx->opcode) == 0) { 5095 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5096 } else { 5097 /* interpreted as no-op */ 5098 } 5099 5100 } 5101 5102 /* dss / dssall */ 5103 static void gen_dss(DisasContext *ctx) 5104 { 5105 /* interpreted as no-op */ 5106 } 5107 5108 /* icbi */ 5109 static void gen_icbi(DisasContext *ctx) 5110 { 5111 TCGv t0; 5112 gen_set_access_type(ctx, ACCESS_CACHE); 5113 t0 = tcg_temp_new(); 5114 gen_addr_reg_index(ctx, t0); 5115 gen_helper_icbi(cpu_env, t0); 5116 } 5117 5118 /* icbiep */ 5119 static void gen_icbiep(DisasContext *ctx) 5120 { 5121 TCGv t0; 5122 gen_set_access_type(ctx, ACCESS_CACHE); 5123 t0 = tcg_temp_new(); 5124 gen_addr_reg_index(ctx, t0); 5125 gen_helper_icbiep(cpu_env, t0); 5126 } 5127 5128 /* Optional: */ 5129 /* dcba */ 5130 static void gen_dcba(DisasContext *ctx) 5131 { 5132 /* 5133 * interpreted as no-op 5134 * XXX: specification say this is treated as a store by the MMU 5135 * but does not generate any exception 5136 */ 5137 } 5138 5139 /*** Segment register manipulation ***/ 5140 /* Supervisor only: */ 5141 5142 /* mfsr */ 5143 static void gen_mfsr(DisasContext *ctx) 5144 { 5145 #if defined(CONFIG_USER_ONLY) 5146 GEN_PRIV(ctx); 5147 #else 5148 TCGv t0; 5149 5150 CHK_SV(ctx); 5151 t0 = tcg_constant_tl(SR(ctx->opcode)); 5152 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5153 #endif /* defined(CONFIG_USER_ONLY) */ 5154 } 5155 5156 /* mfsrin */ 5157 static void gen_mfsrin(DisasContext *ctx) 5158 { 5159 #if defined(CONFIG_USER_ONLY) 5160 GEN_PRIV(ctx); 5161 #else 5162 TCGv t0; 5163 5164 CHK_SV(ctx); 5165 t0 = tcg_temp_new(); 5166 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5167 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5168 #endif /* defined(CONFIG_USER_ONLY) */ 5169 } 5170 5171 /* mtsr */ 5172 static void gen_mtsr(DisasContext *ctx) 5173 { 5174 #if defined(CONFIG_USER_ONLY) 5175 GEN_PRIV(ctx); 5176 #else 5177 TCGv t0; 5178 5179 CHK_SV(ctx); 5180 t0 = tcg_constant_tl(SR(ctx->opcode)); 5181 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5182 #endif /* defined(CONFIG_USER_ONLY) */ 5183 } 5184 5185 /* mtsrin */ 5186 static void gen_mtsrin(DisasContext *ctx) 5187 { 5188 #if defined(CONFIG_USER_ONLY) 5189 GEN_PRIV(ctx); 5190 #else 5191 TCGv t0; 5192 CHK_SV(ctx); 5193 5194 t0 = tcg_temp_new(); 5195 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5196 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5197 #endif /* defined(CONFIG_USER_ONLY) */ 5198 } 5199 5200 #if defined(TARGET_PPC64) 5201 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5202 5203 /* mfsr */ 5204 static void gen_mfsr_64b(DisasContext *ctx) 5205 { 5206 #if defined(CONFIG_USER_ONLY) 5207 GEN_PRIV(ctx); 5208 #else 5209 TCGv t0; 5210 5211 CHK_SV(ctx); 5212 t0 = tcg_constant_tl(SR(ctx->opcode)); 5213 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5214 #endif /* defined(CONFIG_USER_ONLY) */ 5215 } 5216 5217 /* mfsrin */ 5218 static void gen_mfsrin_64b(DisasContext *ctx) 5219 { 5220 #if defined(CONFIG_USER_ONLY) 5221 GEN_PRIV(ctx); 5222 #else 5223 TCGv t0; 5224 5225 CHK_SV(ctx); 5226 t0 = tcg_temp_new(); 5227 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5228 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5229 #endif /* defined(CONFIG_USER_ONLY) */ 5230 } 5231 5232 /* mtsr */ 5233 static void gen_mtsr_64b(DisasContext *ctx) 5234 { 5235 #if defined(CONFIG_USER_ONLY) 5236 GEN_PRIV(ctx); 5237 #else 5238 TCGv t0; 5239 5240 CHK_SV(ctx); 5241 t0 = tcg_constant_tl(SR(ctx->opcode)); 5242 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5243 #endif /* defined(CONFIG_USER_ONLY) */ 5244 } 5245 5246 /* mtsrin */ 5247 static void gen_mtsrin_64b(DisasContext *ctx) 5248 { 5249 #if defined(CONFIG_USER_ONLY) 5250 GEN_PRIV(ctx); 5251 #else 5252 TCGv t0; 5253 5254 CHK_SV(ctx); 5255 t0 = tcg_temp_new(); 5256 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5257 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5258 #endif /* defined(CONFIG_USER_ONLY) */ 5259 } 5260 5261 #endif /* defined(TARGET_PPC64) */ 5262 5263 /*** Lookaside buffer management ***/ 5264 /* Optional & supervisor only: */ 5265 5266 /* tlbia */ 5267 static void gen_tlbia(DisasContext *ctx) 5268 { 5269 #if defined(CONFIG_USER_ONLY) 5270 GEN_PRIV(ctx); 5271 #else 5272 CHK_HV(ctx); 5273 5274 gen_helper_tlbia(cpu_env); 5275 #endif /* defined(CONFIG_USER_ONLY) */ 5276 } 5277 5278 /* tlbsync */ 5279 static void gen_tlbsync(DisasContext *ctx) 5280 { 5281 #if defined(CONFIG_USER_ONLY) 5282 GEN_PRIV(ctx); 5283 #else 5284 5285 if (ctx->gtse) { 5286 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5287 } else { 5288 CHK_HV(ctx); /* Else hypervisor privileged */ 5289 } 5290 5291 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5292 if (ctx->insns_flags & PPC_BOOKE) { 5293 gen_check_tlb_flush(ctx, true); 5294 } 5295 #endif /* defined(CONFIG_USER_ONLY) */ 5296 } 5297 5298 /*** External control ***/ 5299 /* Optional: */ 5300 5301 /* eciwx */ 5302 static void gen_eciwx(DisasContext *ctx) 5303 { 5304 TCGv t0; 5305 /* Should check EAR[E] ! */ 5306 gen_set_access_type(ctx, ACCESS_EXT); 5307 t0 = tcg_temp_new(); 5308 gen_addr_reg_index(ctx, t0); 5309 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5310 DEF_MEMOP(MO_UL | MO_ALIGN)); 5311 } 5312 5313 /* ecowx */ 5314 static void gen_ecowx(DisasContext *ctx) 5315 { 5316 TCGv t0; 5317 /* Should check EAR[E] ! */ 5318 gen_set_access_type(ctx, ACCESS_EXT); 5319 t0 = tcg_temp_new(); 5320 gen_addr_reg_index(ctx, t0); 5321 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5322 DEF_MEMOP(MO_UL | MO_ALIGN)); 5323 } 5324 5325 /* 602 - 603 - G2 TLB management */ 5326 5327 /* tlbld */ 5328 static void gen_tlbld_6xx(DisasContext *ctx) 5329 { 5330 #if defined(CONFIG_USER_ONLY) 5331 GEN_PRIV(ctx); 5332 #else 5333 CHK_SV(ctx); 5334 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5335 #endif /* defined(CONFIG_USER_ONLY) */ 5336 } 5337 5338 /* tlbli */ 5339 static void gen_tlbli_6xx(DisasContext *ctx) 5340 { 5341 #if defined(CONFIG_USER_ONLY) 5342 GEN_PRIV(ctx); 5343 #else 5344 CHK_SV(ctx); 5345 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5346 #endif /* defined(CONFIG_USER_ONLY) */ 5347 } 5348 5349 /* BookE specific instructions */ 5350 5351 /* XXX: not implemented on 440 ? */ 5352 static void gen_mfapidi(DisasContext *ctx) 5353 { 5354 /* XXX: TODO */ 5355 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5356 } 5357 5358 /* XXX: not implemented on 440 ? */ 5359 static void gen_tlbiva(DisasContext *ctx) 5360 { 5361 #if defined(CONFIG_USER_ONLY) 5362 GEN_PRIV(ctx); 5363 #else 5364 TCGv t0; 5365 5366 CHK_SV(ctx); 5367 t0 = tcg_temp_new(); 5368 gen_addr_reg_index(ctx, t0); 5369 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5370 #endif /* defined(CONFIG_USER_ONLY) */ 5371 } 5372 5373 /* All 405 MAC instructions are translated here */ 5374 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5375 int ra, int rb, int rt, int Rc) 5376 { 5377 TCGv t0, t1; 5378 5379 t0 = tcg_temp_new(); 5380 t1 = tcg_temp_new(); 5381 5382 switch (opc3 & 0x0D) { 5383 case 0x05: 5384 /* macchw - macchw. - macchwo - macchwo. */ 5385 /* macchws - macchws. - macchwso - macchwso. */ 5386 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5387 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5388 /* mulchw - mulchw. */ 5389 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5390 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5391 tcg_gen_ext16s_tl(t1, t1); 5392 break; 5393 case 0x04: 5394 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5395 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5396 /* mulchwu - mulchwu. */ 5397 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5398 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5399 tcg_gen_ext16u_tl(t1, t1); 5400 break; 5401 case 0x01: 5402 /* machhw - machhw. - machhwo - machhwo. */ 5403 /* machhws - machhws. - machhwso - machhwso. */ 5404 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5405 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5406 /* mulhhw - mulhhw. */ 5407 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5408 tcg_gen_ext16s_tl(t0, t0); 5409 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5410 tcg_gen_ext16s_tl(t1, t1); 5411 break; 5412 case 0x00: 5413 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5414 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5415 /* mulhhwu - mulhhwu. */ 5416 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5417 tcg_gen_ext16u_tl(t0, t0); 5418 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5419 tcg_gen_ext16u_tl(t1, t1); 5420 break; 5421 case 0x0D: 5422 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5423 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5424 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5425 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5426 /* mullhw - mullhw. */ 5427 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5428 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5429 break; 5430 case 0x0C: 5431 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5432 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5433 /* mullhwu - mullhwu. */ 5434 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5435 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5436 break; 5437 } 5438 if (opc2 & 0x04) { 5439 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5440 tcg_gen_mul_tl(t1, t0, t1); 5441 if (opc2 & 0x02) { 5442 /* nmultiply-and-accumulate (0x0E) */ 5443 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5444 } else { 5445 /* multiply-and-accumulate (0x0C) */ 5446 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5447 } 5448 5449 if (opc3 & 0x12) { 5450 /* Check overflow and/or saturate */ 5451 TCGLabel *l1 = gen_new_label(); 5452 5453 if (opc3 & 0x10) { 5454 /* Start with XER OV disabled, the most likely case */ 5455 tcg_gen_movi_tl(cpu_ov, 0); 5456 } 5457 if (opc3 & 0x01) { 5458 /* Signed */ 5459 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5460 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5461 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5462 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5463 if (opc3 & 0x02) { 5464 /* Saturate */ 5465 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5466 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5467 } 5468 } else { 5469 /* Unsigned */ 5470 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5471 if (opc3 & 0x02) { 5472 /* Saturate */ 5473 tcg_gen_movi_tl(t0, UINT32_MAX); 5474 } 5475 } 5476 if (opc3 & 0x10) { 5477 /* Check overflow */ 5478 tcg_gen_movi_tl(cpu_ov, 1); 5479 tcg_gen_movi_tl(cpu_so, 1); 5480 } 5481 gen_set_label(l1); 5482 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5483 } 5484 } else { 5485 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5486 } 5487 if (unlikely(Rc) != 0) { 5488 /* Update Rc0 */ 5489 gen_set_Rc0(ctx, cpu_gpr[rt]); 5490 } 5491 } 5492 5493 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5494 static void glue(gen_, name)(DisasContext *ctx) \ 5495 { \ 5496 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5497 rD(ctx->opcode), Rc(ctx->opcode)); \ 5498 } 5499 5500 /* macchw - macchw. */ 5501 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5502 /* macchwo - macchwo. */ 5503 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5504 /* macchws - macchws. */ 5505 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5506 /* macchwso - macchwso. */ 5507 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5508 /* macchwsu - macchwsu. */ 5509 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5510 /* macchwsuo - macchwsuo. */ 5511 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5512 /* macchwu - macchwu. */ 5513 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5514 /* macchwuo - macchwuo. */ 5515 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5516 /* machhw - machhw. */ 5517 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5518 /* machhwo - machhwo. */ 5519 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5520 /* machhws - machhws. */ 5521 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5522 /* machhwso - machhwso. */ 5523 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5524 /* machhwsu - machhwsu. */ 5525 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5526 /* machhwsuo - machhwsuo. */ 5527 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5528 /* machhwu - machhwu. */ 5529 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5530 /* machhwuo - machhwuo. */ 5531 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5532 /* maclhw - maclhw. */ 5533 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5534 /* maclhwo - maclhwo. */ 5535 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5536 /* maclhws - maclhws. */ 5537 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5538 /* maclhwso - maclhwso. */ 5539 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5540 /* maclhwu - maclhwu. */ 5541 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5542 /* maclhwuo - maclhwuo. */ 5543 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5544 /* maclhwsu - maclhwsu. */ 5545 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5546 /* maclhwsuo - maclhwsuo. */ 5547 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5548 /* nmacchw - nmacchw. */ 5549 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5550 /* nmacchwo - nmacchwo. */ 5551 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5552 /* nmacchws - nmacchws. */ 5553 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5554 /* nmacchwso - nmacchwso. */ 5555 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5556 /* nmachhw - nmachhw. */ 5557 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5558 /* nmachhwo - nmachhwo. */ 5559 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5560 /* nmachhws - nmachhws. */ 5561 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5562 /* nmachhwso - nmachhwso. */ 5563 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5564 /* nmaclhw - nmaclhw. */ 5565 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5566 /* nmaclhwo - nmaclhwo. */ 5567 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5568 /* nmaclhws - nmaclhws. */ 5569 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5570 /* nmaclhwso - nmaclhwso. */ 5571 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5572 5573 /* mulchw - mulchw. */ 5574 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5575 /* mulchwu - mulchwu. */ 5576 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5577 /* mulhhw - mulhhw. */ 5578 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5579 /* mulhhwu - mulhhwu. */ 5580 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5581 /* mullhw - mullhw. */ 5582 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5583 /* mullhwu - mullhwu. */ 5584 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5585 5586 /* mfdcr */ 5587 static void gen_mfdcr(DisasContext *ctx) 5588 { 5589 #if defined(CONFIG_USER_ONLY) 5590 GEN_PRIV(ctx); 5591 #else 5592 TCGv dcrn; 5593 5594 CHK_SV(ctx); 5595 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5596 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5597 #endif /* defined(CONFIG_USER_ONLY) */ 5598 } 5599 5600 /* mtdcr */ 5601 static void gen_mtdcr(DisasContext *ctx) 5602 { 5603 #if defined(CONFIG_USER_ONLY) 5604 GEN_PRIV(ctx); 5605 #else 5606 TCGv dcrn; 5607 5608 CHK_SV(ctx); 5609 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5610 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5611 #endif /* defined(CONFIG_USER_ONLY) */ 5612 } 5613 5614 /* mfdcrx */ 5615 /* XXX: not implemented on 440 ? */ 5616 static void gen_mfdcrx(DisasContext *ctx) 5617 { 5618 #if defined(CONFIG_USER_ONLY) 5619 GEN_PRIV(ctx); 5620 #else 5621 CHK_SV(ctx); 5622 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5623 cpu_gpr[rA(ctx->opcode)]); 5624 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5625 #endif /* defined(CONFIG_USER_ONLY) */ 5626 } 5627 5628 /* mtdcrx */ 5629 /* XXX: not implemented on 440 ? */ 5630 static void gen_mtdcrx(DisasContext *ctx) 5631 { 5632 #if defined(CONFIG_USER_ONLY) 5633 GEN_PRIV(ctx); 5634 #else 5635 CHK_SV(ctx); 5636 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5637 cpu_gpr[rS(ctx->opcode)]); 5638 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5639 #endif /* defined(CONFIG_USER_ONLY) */ 5640 } 5641 5642 /* dccci */ 5643 static void gen_dccci(DisasContext *ctx) 5644 { 5645 CHK_SV(ctx); 5646 /* interpreted as no-op */ 5647 } 5648 5649 /* dcread */ 5650 static void gen_dcread(DisasContext *ctx) 5651 { 5652 #if defined(CONFIG_USER_ONLY) 5653 GEN_PRIV(ctx); 5654 #else 5655 TCGv EA, val; 5656 5657 CHK_SV(ctx); 5658 gen_set_access_type(ctx, ACCESS_CACHE); 5659 EA = tcg_temp_new(); 5660 gen_addr_reg_index(ctx, EA); 5661 val = tcg_temp_new(); 5662 gen_qemu_ld32u(ctx, val, EA); 5663 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5664 #endif /* defined(CONFIG_USER_ONLY) */ 5665 } 5666 5667 /* icbt */ 5668 static void gen_icbt_40x(DisasContext *ctx) 5669 { 5670 /* 5671 * interpreted as no-op 5672 * XXX: specification say this is treated as a load by the MMU but 5673 * does not generate any exception 5674 */ 5675 } 5676 5677 /* iccci */ 5678 static void gen_iccci(DisasContext *ctx) 5679 { 5680 CHK_SV(ctx); 5681 /* interpreted as no-op */ 5682 } 5683 5684 /* icread */ 5685 static void gen_icread(DisasContext *ctx) 5686 { 5687 CHK_SV(ctx); 5688 /* interpreted as no-op */ 5689 } 5690 5691 /* rfci (supervisor only) */ 5692 static void gen_rfci_40x(DisasContext *ctx) 5693 { 5694 #if defined(CONFIG_USER_ONLY) 5695 GEN_PRIV(ctx); 5696 #else 5697 CHK_SV(ctx); 5698 /* Restore CPU state */ 5699 gen_helper_40x_rfci(cpu_env); 5700 ctx->base.is_jmp = DISAS_EXIT; 5701 #endif /* defined(CONFIG_USER_ONLY) */ 5702 } 5703 5704 static void gen_rfci(DisasContext *ctx) 5705 { 5706 #if defined(CONFIG_USER_ONLY) 5707 GEN_PRIV(ctx); 5708 #else 5709 CHK_SV(ctx); 5710 /* Restore CPU state */ 5711 gen_helper_rfci(cpu_env); 5712 ctx->base.is_jmp = DISAS_EXIT; 5713 #endif /* defined(CONFIG_USER_ONLY) */ 5714 } 5715 5716 /* BookE specific */ 5717 5718 /* XXX: not implemented on 440 ? */ 5719 static void gen_rfdi(DisasContext *ctx) 5720 { 5721 #if defined(CONFIG_USER_ONLY) 5722 GEN_PRIV(ctx); 5723 #else 5724 CHK_SV(ctx); 5725 /* Restore CPU state */ 5726 gen_helper_rfdi(cpu_env); 5727 ctx->base.is_jmp = DISAS_EXIT; 5728 #endif /* defined(CONFIG_USER_ONLY) */ 5729 } 5730 5731 /* XXX: not implemented on 440 ? */ 5732 static void gen_rfmci(DisasContext *ctx) 5733 { 5734 #if defined(CONFIG_USER_ONLY) 5735 GEN_PRIV(ctx); 5736 #else 5737 CHK_SV(ctx); 5738 /* Restore CPU state */ 5739 gen_helper_rfmci(cpu_env); 5740 ctx->base.is_jmp = DISAS_EXIT; 5741 #endif /* defined(CONFIG_USER_ONLY) */ 5742 } 5743 5744 /* TLB management - PowerPC 405 implementation */ 5745 5746 /* tlbre */ 5747 static void gen_tlbre_40x(DisasContext *ctx) 5748 { 5749 #if defined(CONFIG_USER_ONLY) 5750 GEN_PRIV(ctx); 5751 #else 5752 CHK_SV(ctx); 5753 switch (rB(ctx->opcode)) { 5754 case 0: 5755 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5756 cpu_gpr[rA(ctx->opcode)]); 5757 break; 5758 case 1: 5759 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5760 cpu_gpr[rA(ctx->opcode)]); 5761 break; 5762 default: 5763 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5764 break; 5765 } 5766 #endif /* defined(CONFIG_USER_ONLY) */ 5767 } 5768 5769 /* tlbsx - tlbsx. */ 5770 static void gen_tlbsx_40x(DisasContext *ctx) 5771 { 5772 #if defined(CONFIG_USER_ONLY) 5773 GEN_PRIV(ctx); 5774 #else 5775 TCGv t0; 5776 5777 CHK_SV(ctx); 5778 t0 = tcg_temp_new(); 5779 gen_addr_reg_index(ctx, t0); 5780 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5781 if (Rc(ctx->opcode)) { 5782 TCGLabel *l1 = gen_new_label(); 5783 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5784 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5785 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5786 gen_set_label(l1); 5787 } 5788 #endif /* defined(CONFIG_USER_ONLY) */ 5789 } 5790 5791 /* tlbwe */ 5792 static void gen_tlbwe_40x(DisasContext *ctx) 5793 { 5794 #if defined(CONFIG_USER_ONLY) 5795 GEN_PRIV(ctx); 5796 #else 5797 CHK_SV(ctx); 5798 5799 switch (rB(ctx->opcode)) { 5800 case 0: 5801 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5802 cpu_gpr[rS(ctx->opcode)]); 5803 break; 5804 case 1: 5805 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5806 cpu_gpr[rS(ctx->opcode)]); 5807 break; 5808 default: 5809 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5810 break; 5811 } 5812 #endif /* defined(CONFIG_USER_ONLY) */ 5813 } 5814 5815 /* TLB management - PowerPC 440 implementation */ 5816 5817 /* tlbre */ 5818 static void gen_tlbre_440(DisasContext *ctx) 5819 { 5820 #if defined(CONFIG_USER_ONLY) 5821 GEN_PRIV(ctx); 5822 #else 5823 CHK_SV(ctx); 5824 5825 switch (rB(ctx->opcode)) { 5826 case 0: 5827 case 1: 5828 case 2: 5829 { 5830 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5831 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5832 t0, cpu_gpr[rA(ctx->opcode)]); 5833 } 5834 break; 5835 default: 5836 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5837 break; 5838 } 5839 #endif /* defined(CONFIG_USER_ONLY) */ 5840 } 5841 5842 /* tlbsx - tlbsx. */ 5843 static void gen_tlbsx_440(DisasContext *ctx) 5844 { 5845 #if defined(CONFIG_USER_ONLY) 5846 GEN_PRIV(ctx); 5847 #else 5848 TCGv t0; 5849 5850 CHK_SV(ctx); 5851 t0 = tcg_temp_new(); 5852 gen_addr_reg_index(ctx, t0); 5853 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5854 if (Rc(ctx->opcode)) { 5855 TCGLabel *l1 = gen_new_label(); 5856 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5857 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5858 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5859 gen_set_label(l1); 5860 } 5861 #endif /* defined(CONFIG_USER_ONLY) */ 5862 } 5863 5864 /* tlbwe */ 5865 static void gen_tlbwe_440(DisasContext *ctx) 5866 { 5867 #if defined(CONFIG_USER_ONLY) 5868 GEN_PRIV(ctx); 5869 #else 5870 CHK_SV(ctx); 5871 switch (rB(ctx->opcode)) { 5872 case 0: 5873 case 1: 5874 case 2: 5875 { 5876 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5877 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5878 cpu_gpr[rS(ctx->opcode)]); 5879 } 5880 break; 5881 default: 5882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5883 break; 5884 } 5885 #endif /* defined(CONFIG_USER_ONLY) */ 5886 } 5887 5888 /* TLB management - PowerPC BookE 2.06 implementation */ 5889 5890 /* tlbre */ 5891 static void gen_tlbre_booke206(DisasContext *ctx) 5892 { 5893 #if defined(CONFIG_USER_ONLY) 5894 GEN_PRIV(ctx); 5895 #else 5896 CHK_SV(ctx); 5897 gen_helper_booke206_tlbre(cpu_env); 5898 #endif /* defined(CONFIG_USER_ONLY) */ 5899 } 5900 5901 /* tlbsx - tlbsx. */ 5902 static void gen_tlbsx_booke206(DisasContext *ctx) 5903 { 5904 #if defined(CONFIG_USER_ONLY) 5905 GEN_PRIV(ctx); 5906 #else 5907 TCGv t0; 5908 5909 CHK_SV(ctx); 5910 if (rA(ctx->opcode)) { 5911 t0 = tcg_temp_new(); 5912 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5913 } else { 5914 t0 = cpu_gpr[rB(ctx->opcode)]; 5915 } 5916 gen_helper_booke206_tlbsx(cpu_env, t0); 5917 #endif /* defined(CONFIG_USER_ONLY) */ 5918 } 5919 5920 /* tlbwe */ 5921 static void gen_tlbwe_booke206(DisasContext *ctx) 5922 { 5923 #if defined(CONFIG_USER_ONLY) 5924 GEN_PRIV(ctx); 5925 #else 5926 CHK_SV(ctx); 5927 gen_helper_booke206_tlbwe(cpu_env); 5928 #endif /* defined(CONFIG_USER_ONLY) */ 5929 } 5930 5931 static void gen_tlbivax_booke206(DisasContext *ctx) 5932 { 5933 #if defined(CONFIG_USER_ONLY) 5934 GEN_PRIV(ctx); 5935 #else 5936 TCGv t0; 5937 5938 CHK_SV(ctx); 5939 t0 = tcg_temp_new(); 5940 gen_addr_reg_index(ctx, t0); 5941 gen_helper_booke206_tlbivax(cpu_env, t0); 5942 #endif /* defined(CONFIG_USER_ONLY) */ 5943 } 5944 5945 static void gen_tlbilx_booke206(DisasContext *ctx) 5946 { 5947 #if defined(CONFIG_USER_ONLY) 5948 GEN_PRIV(ctx); 5949 #else 5950 TCGv t0; 5951 5952 CHK_SV(ctx); 5953 t0 = tcg_temp_new(); 5954 gen_addr_reg_index(ctx, t0); 5955 5956 switch ((ctx->opcode >> 21) & 0x3) { 5957 case 0: 5958 gen_helper_booke206_tlbilx0(cpu_env, t0); 5959 break; 5960 case 1: 5961 gen_helper_booke206_tlbilx1(cpu_env, t0); 5962 break; 5963 case 3: 5964 gen_helper_booke206_tlbilx3(cpu_env, t0); 5965 break; 5966 default: 5967 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5968 break; 5969 } 5970 #endif /* defined(CONFIG_USER_ONLY) */ 5971 } 5972 5973 /* wrtee */ 5974 static void gen_wrtee(DisasContext *ctx) 5975 { 5976 #if defined(CONFIG_USER_ONLY) 5977 GEN_PRIV(ctx); 5978 #else 5979 TCGv t0; 5980 5981 CHK_SV(ctx); 5982 t0 = tcg_temp_new(); 5983 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5984 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5985 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5986 gen_ppc_maybe_interrupt(ctx); 5987 /* 5988 * Stop translation to have a chance to raise an exception if we 5989 * just set msr_ee to 1 5990 */ 5991 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5992 #endif /* defined(CONFIG_USER_ONLY) */ 5993 } 5994 5995 /* wrteei */ 5996 static void gen_wrteei(DisasContext *ctx) 5997 { 5998 #if defined(CONFIG_USER_ONLY) 5999 GEN_PRIV(ctx); 6000 #else 6001 CHK_SV(ctx); 6002 if (ctx->opcode & 0x00008000) { 6003 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6004 gen_ppc_maybe_interrupt(ctx); 6005 /* Stop translation to have a chance to raise an exception */ 6006 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6007 } else { 6008 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6009 } 6010 #endif /* defined(CONFIG_USER_ONLY) */ 6011 } 6012 6013 /* PowerPC 440 specific instructions */ 6014 6015 /* dlmzb */ 6016 static void gen_dlmzb(DisasContext *ctx) 6017 { 6018 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6019 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6020 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6021 } 6022 6023 /* mbar replaces eieio on 440 */ 6024 static void gen_mbar(DisasContext *ctx) 6025 { 6026 /* interpreted as no-op */ 6027 } 6028 6029 /* msync replaces sync on 440 */ 6030 static void gen_msync_4xx(DisasContext *ctx) 6031 { 6032 /* Only e500 seems to treat reserved bits as invalid */ 6033 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6034 (ctx->opcode & 0x03FFF801)) { 6035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6036 } 6037 /* otherwise interpreted as no-op */ 6038 } 6039 6040 /* icbt */ 6041 static void gen_icbt_440(DisasContext *ctx) 6042 { 6043 /* 6044 * interpreted as no-op 6045 * XXX: specification say this is treated as a load by the MMU but 6046 * does not generate any exception 6047 */ 6048 } 6049 6050 #if defined(TARGET_PPC64) 6051 static void gen_maddld(DisasContext *ctx) 6052 { 6053 TCGv_i64 t1 = tcg_temp_new_i64(); 6054 6055 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6056 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6057 } 6058 6059 /* maddhd maddhdu */ 6060 static void gen_maddhd_maddhdu(DisasContext *ctx) 6061 { 6062 TCGv_i64 lo = tcg_temp_new_i64(); 6063 TCGv_i64 hi = tcg_temp_new_i64(); 6064 TCGv_i64 t1 = tcg_temp_new_i64(); 6065 6066 if (Rc(ctx->opcode)) { 6067 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6068 cpu_gpr[rB(ctx->opcode)]); 6069 tcg_gen_movi_i64(t1, 0); 6070 } else { 6071 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6072 cpu_gpr[rB(ctx->opcode)]); 6073 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6074 } 6075 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6076 cpu_gpr[rC(ctx->opcode)], t1); 6077 } 6078 #endif /* defined(TARGET_PPC64) */ 6079 6080 static void gen_tbegin(DisasContext *ctx) 6081 { 6082 if (unlikely(!ctx->tm_enabled)) { 6083 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6084 return; 6085 } 6086 gen_helper_tbegin(cpu_env); 6087 } 6088 6089 #define GEN_TM_NOOP(name) \ 6090 static inline void gen_##name(DisasContext *ctx) \ 6091 { \ 6092 if (unlikely(!ctx->tm_enabled)) { \ 6093 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6094 return; \ 6095 } \ 6096 /* \ 6097 * Because tbegin always fails in QEMU, these user \ 6098 * space instructions all have a simple implementation: \ 6099 * \ 6100 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6101 * = 0b0 || 0b00 || 0b0 \ 6102 */ \ 6103 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6104 } 6105 6106 GEN_TM_NOOP(tend); 6107 GEN_TM_NOOP(tabort); 6108 GEN_TM_NOOP(tabortwc); 6109 GEN_TM_NOOP(tabortwci); 6110 GEN_TM_NOOP(tabortdc); 6111 GEN_TM_NOOP(tabortdci); 6112 GEN_TM_NOOP(tsr); 6113 6114 static inline void gen_cp_abort(DisasContext *ctx) 6115 { 6116 /* Do Nothing */ 6117 } 6118 6119 #define GEN_CP_PASTE_NOOP(name) \ 6120 static inline void gen_##name(DisasContext *ctx) \ 6121 { \ 6122 /* \ 6123 * Generate invalid exception until we have an \ 6124 * implementation of the copy paste facility \ 6125 */ \ 6126 gen_invalid(ctx); \ 6127 } 6128 6129 GEN_CP_PASTE_NOOP(copy) 6130 GEN_CP_PASTE_NOOP(paste) 6131 6132 static void gen_tcheck(DisasContext *ctx) 6133 { 6134 if (unlikely(!ctx->tm_enabled)) { 6135 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6136 return; 6137 } 6138 /* 6139 * Because tbegin always fails, the tcheck implementation is 6140 * simple: 6141 * 6142 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6143 * = 0b1 || 0b00 || 0b0 6144 */ 6145 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6146 } 6147 6148 #if defined(CONFIG_USER_ONLY) 6149 #define GEN_TM_PRIV_NOOP(name) \ 6150 static inline void gen_##name(DisasContext *ctx) \ 6151 { \ 6152 gen_priv_opc(ctx); \ 6153 } 6154 6155 #else 6156 6157 #define GEN_TM_PRIV_NOOP(name) \ 6158 static inline void gen_##name(DisasContext *ctx) \ 6159 { \ 6160 CHK_SV(ctx); \ 6161 if (unlikely(!ctx->tm_enabled)) { \ 6162 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6163 return; \ 6164 } \ 6165 /* \ 6166 * Because tbegin always fails, the implementation is \ 6167 * simple: \ 6168 * \ 6169 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6170 * = 0b0 || 0b00 | 0b0 \ 6171 */ \ 6172 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6173 } 6174 6175 #endif 6176 6177 GEN_TM_PRIV_NOOP(treclaim); 6178 GEN_TM_PRIV_NOOP(trechkpt); 6179 6180 static inline void get_fpr(TCGv_i64 dst, int regno) 6181 { 6182 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6183 } 6184 6185 static inline void set_fpr(int regno, TCGv_i64 src) 6186 { 6187 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6188 /* 6189 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6190 * corresponding to the target FPR was undefined. However, 6191 * most (if not all) real hardware were setting the result to 0. 6192 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6193 * to be 0. 6194 */ 6195 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6196 } 6197 6198 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6199 { 6200 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6201 } 6202 6203 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6204 { 6205 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6206 } 6207 6208 /* 6209 * Helpers for decodetree used by !function for decoding arguments. 6210 */ 6211 static int times_2(DisasContext *ctx, int x) 6212 { 6213 return x * 2; 6214 } 6215 6216 static int times_4(DisasContext *ctx, int x) 6217 { 6218 return x * 4; 6219 } 6220 6221 static int times_16(DisasContext *ctx, int x) 6222 { 6223 return x * 16; 6224 } 6225 6226 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6227 { 6228 return deposit64(0xfffffffffffffe00, 3, 6, x); 6229 } 6230 6231 /* 6232 * Helpers for trans_* functions to check for specific insns flags. 6233 * Use token pasting to ensure that we use the proper flag with the 6234 * proper variable. 6235 */ 6236 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6237 do { \ 6238 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6239 return false; \ 6240 } \ 6241 } while (0) 6242 6243 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6244 do { \ 6245 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6246 return false; \ 6247 } \ 6248 } while (0) 6249 6250 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6251 #if TARGET_LONG_BITS == 32 6252 # define REQUIRE_64BIT(CTX) return false 6253 #else 6254 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6255 #endif 6256 6257 #define REQUIRE_VECTOR(CTX) \ 6258 do { \ 6259 if (unlikely(!(CTX)->altivec_enabled)) { \ 6260 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6261 return true; \ 6262 } \ 6263 } while (0) 6264 6265 #define REQUIRE_VSX(CTX) \ 6266 do { \ 6267 if (unlikely(!(CTX)->vsx_enabled)) { \ 6268 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6269 return true; \ 6270 } \ 6271 } while (0) 6272 6273 #define REQUIRE_FPU(ctx) \ 6274 do { \ 6275 if (unlikely(!(ctx)->fpu_enabled)) { \ 6276 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6277 return true; \ 6278 } \ 6279 } while (0) 6280 6281 #if !defined(CONFIG_USER_ONLY) 6282 #define REQUIRE_SV(CTX) \ 6283 do { \ 6284 if (unlikely((CTX)->pr)) { \ 6285 gen_priv_opc(CTX); \ 6286 return true; \ 6287 } \ 6288 } while (0) 6289 6290 #define REQUIRE_HV(CTX) \ 6291 do { \ 6292 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6293 gen_priv_opc(CTX); \ 6294 return true; \ 6295 } \ 6296 } while (0) 6297 #else 6298 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6299 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6300 #endif 6301 6302 /* 6303 * Helpers for implementing sets of trans_* functions. 6304 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6305 */ 6306 #define TRANS(NAME, FUNC, ...) \ 6307 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6308 { return FUNC(ctx, a, __VA_ARGS__); } 6309 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6310 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6311 { \ 6312 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6313 return FUNC(ctx, a, __VA_ARGS__); \ 6314 } 6315 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6316 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6317 { \ 6318 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6319 return FUNC(ctx, a, __VA_ARGS__); \ 6320 } 6321 6322 #define TRANS64(NAME, FUNC, ...) \ 6323 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6324 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6325 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6326 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6327 { \ 6328 REQUIRE_64BIT(ctx); \ 6329 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6330 return FUNC(ctx, a, __VA_ARGS__); \ 6331 } 6332 6333 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6334 6335 6336 #include "decode-insn32.c.inc" 6337 #include "decode-insn64.c.inc" 6338 #include "power8-pmu-regs.c.inc" 6339 6340 /* 6341 * Incorporate CIA into the constant when R=1. 6342 * Validate that when R=1, RA=0. 6343 */ 6344 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6345 { 6346 d->rt = a->rt; 6347 d->ra = a->ra; 6348 d->si = a->si; 6349 if (a->r) { 6350 if (unlikely(a->ra != 0)) { 6351 gen_invalid(ctx); 6352 return false; 6353 } 6354 d->si += ctx->cia; 6355 } 6356 return true; 6357 } 6358 6359 #include "translate/fixedpoint-impl.c.inc" 6360 6361 #include "translate/fp-impl.c.inc" 6362 6363 #include "translate/vmx-impl.c.inc" 6364 6365 #include "translate/vsx-impl.c.inc" 6366 6367 #include "translate/dfp-impl.c.inc" 6368 6369 #include "translate/spe-impl.c.inc" 6370 6371 #include "translate/branch-impl.c.inc" 6372 6373 #include "translate/processor-ctrl-impl.c.inc" 6374 6375 #include "translate/storage-ctrl-impl.c.inc" 6376 6377 /* Handles lfdp */ 6378 static void gen_dform39(DisasContext *ctx) 6379 { 6380 if ((ctx->opcode & 0x3) == 0) { 6381 if (ctx->insns_flags2 & PPC2_ISA205) { 6382 return gen_lfdp(ctx); 6383 } 6384 } 6385 return gen_invalid(ctx); 6386 } 6387 6388 /* Handles stfdp */ 6389 static void gen_dform3D(DisasContext *ctx) 6390 { 6391 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6392 /* stfdp */ 6393 if (ctx->insns_flags2 & PPC2_ISA205) { 6394 return gen_stfdp(ctx); 6395 } 6396 } 6397 return gen_invalid(ctx); 6398 } 6399 6400 #if defined(TARGET_PPC64) 6401 /* brd */ 6402 static void gen_brd(DisasContext *ctx) 6403 { 6404 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6405 } 6406 6407 /* brw */ 6408 static void gen_brw(DisasContext *ctx) 6409 { 6410 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6411 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6412 6413 } 6414 6415 /* brh */ 6416 static void gen_brh(DisasContext *ctx) 6417 { 6418 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6419 TCGv_i64 t1 = tcg_temp_new_i64(); 6420 TCGv_i64 t2 = tcg_temp_new_i64(); 6421 6422 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6423 tcg_gen_and_i64(t2, t1, mask); 6424 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6425 tcg_gen_shli_i64(t1, t1, 8); 6426 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6427 } 6428 #endif 6429 6430 static opcode_t opcodes[] = { 6431 #if defined(TARGET_PPC64) 6432 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6433 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6434 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6435 #endif 6436 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6437 #if defined(TARGET_PPC64) 6438 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6439 #endif 6440 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6441 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6442 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6443 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6446 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6447 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6448 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6449 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450 #if defined(TARGET_PPC64) 6451 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6452 #endif 6453 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6454 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6455 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6456 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6457 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6458 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6459 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6460 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6461 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6462 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6463 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6464 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6465 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6466 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6467 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6469 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6470 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6471 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6472 #if defined(TARGET_PPC64) 6473 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6474 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6475 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6476 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6477 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6478 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6479 #endif 6480 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6481 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6482 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6483 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6484 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6485 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6486 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6487 #if defined(TARGET_PPC64) 6488 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6489 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6490 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6491 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6492 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6493 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6494 PPC_NONE, PPC2_ISA300), 6495 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6496 PPC_NONE, PPC2_ISA300), 6497 #endif 6498 /* handles lfdp, lxsd, lxssp */ 6499 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6500 /* handles stfdp, stxsd, stxssp */ 6501 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6502 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6503 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6504 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6505 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6506 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6507 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6508 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6509 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6510 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6511 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6512 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6513 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6514 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6515 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6516 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6517 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6518 #if defined(TARGET_PPC64) 6519 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6520 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6521 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6522 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6523 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6524 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6525 #endif 6526 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6527 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6528 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6529 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6530 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6531 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6532 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6533 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6534 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6535 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6536 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6537 #if defined(TARGET_PPC64) 6538 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6539 #if !defined(CONFIG_USER_ONLY) 6540 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6541 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6542 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6543 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6544 #endif 6545 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6546 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6547 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6548 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6549 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6550 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6551 #endif 6552 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6553 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6554 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6555 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6556 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6557 #if defined(TARGET_PPC64) 6558 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6559 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6560 #endif 6561 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6562 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6563 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6564 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6565 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6566 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6567 #if defined(TARGET_PPC64) 6568 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6569 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6570 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6571 #endif 6572 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6573 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6574 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6575 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6576 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6577 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6578 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6579 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6580 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6581 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6582 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6583 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6584 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6585 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6586 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6587 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6588 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6589 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6590 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6591 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6592 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6593 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6594 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6595 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6596 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6597 #if defined(TARGET_PPC64) 6598 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6599 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6600 PPC_SEGMENT_64B), 6601 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6602 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6603 PPC_SEGMENT_64B), 6604 #endif 6605 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6606 /* 6607 * XXX Those instructions will need to be handled differently for 6608 * different ISA versions 6609 */ 6610 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6611 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6612 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6613 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6614 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6615 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6616 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6617 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6618 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6619 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6620 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6621 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6622 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6623 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6624 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6625 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6626 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6627 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6628 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6629 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6630 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6631 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6632 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6633 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6634 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6635 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6636 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6637 PPC_NONE, PPC2_BOOKE206), 6638 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6639 PPC_NONE, PPC2_BOOKE206), 6640 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6641 PPC_NONE, PPC2_BOOKE206), 6642 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6643 PPC_NONE, PPC2_BOOKE206), 6644 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6645 PPC_NONE, PPC2_BOOKE206), 6646 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6647 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6648 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6649 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6650 PPC_BOOKE, PPC2_BOOKE206), 6651 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6652 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6653 PPC_BOOKE, PPC2_BOOKE206), 6654 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6655 PPC_440_SPEC), 6656 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6657 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6658 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6659 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6660 #if defined(TARGET_PPC64) 6661 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6662 PPC2_ISA300), 6663 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6664 #endif 6665 6666 #undef GEN_INT_ARITH_ADD 6667 #undef GEN_INT_ARITH_ADD_CONST 6668 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6669 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6670 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6671 add_ca, compute_ca, compute_ov) \ 6672 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6673 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6674 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6675 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6676 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6677 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6678 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6679 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6680 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6681 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6682 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6683 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6684 6685 #undef GEN_INT_ARITH_DIVW 6686 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6687 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6688 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6689 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6690 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6691 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6692 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6693 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6694 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6695 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6696 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6697 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6698 6699 #if defined(TARGET_PPC64) 6700 #undef GEN_INT_ARITH_DIVD 6701 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6702 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6703 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6704 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6705 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6706 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6707 6708 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6709 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6710 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6711 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6713 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6714 6715 #undef GEN_INT_ARITH_MUL_HELPER 6716 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6717 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6718 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6719 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6720 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6721 #endif 6722 6723 #undef GEN_INT_ARITH_SUBF 6724 #undef GEN_INT_ARITH_SUBF_CONST 6725 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6726 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6727 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6728 add_ca, compute_ca, compute_ov) \ 6729 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6730 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6731 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6732 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6733 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6734 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6735 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6736 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6737 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6738 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6739 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6740 6741 #undef GEN_LOGICAL1 6742 #undef GEN_LOGICAL2 6743 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6744 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6745 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6746 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6747 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6748 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6749 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6750 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6751 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6752 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6753 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6754 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6755 #if defined(TARGET_PPC64) 6756 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6757 #endif 6758 6759 #if defined(TARGET_PPC64) 6760 #undef GEN_PPC64_R2 6761 #undef GEN_PPC64_R4 6762 #define GEN_PPC64_R2(name, opc1, opc2) \ 6763 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6764 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6765 PPC_64B) 6766 #define GEN_PPC64_R4(name, opc1, opc2) \ 6767 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6768 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6769 PPC_64B), \ 6770 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6771 PPC_64B), \ 6772 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6773 PPC_64B) 6774 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6775 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6776 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6777 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6778 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6779 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6780 #endif 6781 6782 #undef GEN_LDX_E 6783 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6784 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6785 6786 #if defined(TARGET_PPC64) 6787 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6788 6789 /* HV/P7 and later only */ 6790 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6791 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6792 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6793 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6794 #endif 6795 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6796 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6797 6798 /* External PID based load */ 6799 #undef GEN_LDEPX 6800 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6801 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6802 0x00000001, PPC_NONE, PPC2_BOOKE206), 6803 6804 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6805 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6806 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6807 #if defined(TARGET_PPC64) 6808 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6809 #endif 6810 6811 #undef GEN_STX_E 6812 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6813 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6814 6815 #if defined(TARGET_PPC64) 6816 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6817 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6818 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6819 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6820 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6821 #endif 6822 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6823 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6824 6825 #undef GEN_STEPX 6826 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6827 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6828 0x00000001, PPC_NONE, PPC2_BOOKE206), 6829 6830 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6831 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6832 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6833 #if defined(TARGET_PPC64) 6834 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6835 #endif 6836 6837 #undef GEN_CRLOGIC 6838 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6839 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6840 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6841 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6842 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6843 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6844 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6845 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6846 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6847 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6848 6849 #undef GEN_MAC_HANDLER 6850 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6851 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6852 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6853 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6854 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6855 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6856 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6857 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6858 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6859 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6860 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6861 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6862 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6863 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6864 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6865 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6866 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6867 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6868 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6869 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6870 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6871 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6872 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6873 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6874 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6875 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6876 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6877 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6878 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6879 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6880 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6881 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6882 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6883 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6884 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6885 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6886 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6887 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6888 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6889 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6890 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6891 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6892 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6893 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6894 6895 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6896 PPC_NONE, PPC2_TM), 6897 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6898 PPC_NONE, PPC2_TM), 6899 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6900 PPC_NONE, PPC2_TM), 6901 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6902 PPC_NONE, PPC2_TM), 6903 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6904 PPC_NONE, PPC2_TM), 6905 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6906 PPC_NONE, PPC2_TM), 6907 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6908 PPC_NONE, PPC2_TM), 6909 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6910 PPC_NONE, PPC2_TM), 6911 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6912 PPC_NONE, PPC2_TM), 6913 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6914 PPC_NONE, PPC2_TM), 6915 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6916 PPC_NONE, PPC2_TM), 6917 6918 #include "translate/fp-ops.c.inc" 6919 6920 #include "translate/vmx-ops.c.inc" 6921 6922 #include "translate/vsx-ops.c.inc" 6923 6924 #include "translate/spe-ops.c.inc" 6925 }; 6926 6927 /*****************************************************************************/ 6928 /* Opcode types */ 6929 enum { 6930 PPC_DIRECT = 0, /* Opcode routine */ 6931 PPC_INDIRECT = 1, /* Indirect opcode table */ 6932 }; 6933 6934 #define PPC_OPCODE_MASK 0x3 6935 6936 static inline int is_indirect_opcode(void *handler) 6937 { 6938 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6939 } 6940 6941 static inline opc_handler_t **ind_table(void *handler) 6942 { 6943 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6944 } 6945 6946 /* Instruction table creation */ 6947 /* Opcodes tables creation */ 6948 static void fill_new_table(opc_handler_t **table, int len) 6949 { 6950 int i; 6951 6952 for (i = 0; i < len; i++) { 6953 table[i] = &invalid_handler; 6954 } 6955 } 6956 6957 static int create_new_table(opc_handler_t **table, unsigned char idx) 6958 { 6959 opc_handler_t **tmp; 6960 6961 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6962 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6963 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6964 6965 return 0; 6966 } 6967 6968 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6969 opc_handler_t *handler) 6970 { 6971 if (table[idx] != &invalid_handler) { 6972 return -1; 6973 } 6974 table[idx] = handler; 6975 6976 return 0; 6977 } 6978 6979 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6980 unsigned char idx, opc_handler_t *handler) 6981 { 6982 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6983 printf("*** ERROR: opcode %02x already assigned in main " 6984 "opcode table\n", idx); 6985 return -1; 6986 } 6987 6988 return 0; 6989 } 6990 6991 static int register_ind_in_table(opc_handler_t **table, 6992 unsigned char idx1, unsigned char idx2, 6993 opc_handler_t *handler) 6994 { 6995 if (table[idx1] == &invalid_handler) { 6996 if (create_new_table(table, idx1) < 0) { 6997 printf("*** ERROR: unable to create indirect table " 6998 "idx=%02x\n", idx1); 6999 return -1; 7000 } 7001 } else { 7002 if (!is_indirect_opcode(table[idx1])) { 7003 printf("*** ERROR: idx %02x already assigned to a direct " 7004 "opcode\n", idx1); 7005 return -1; 7006 } 7007 } 7008 if (handler != NULL && 7009 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7010 printf("*** ERROR: opcode %02x already assigned in " 7011 "opcode table %02x\n", idx2, idx1); 7012 return -1; 7013 } 7014 7015 return 0; 7016 } 7017 7018 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7019 unsigned char idx1, unsigned char idx2, 7020 opc_handler_t *handler) 7021 { 7022 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7023 } 7024 7025 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7026 unsigned char idx1, unsigned char idx2, 7027 unsigned char idx3, opc_handler_t *handler) 7028 { 7029 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7030 printf("*** ERROR: unable to join indirect table idx " 7031 "[%02x-%02x]\n", idx1, idx2); 7032 return -1; 7033 } 7034 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7035 handler) < 0) { 7036 printf("*** ERROR: unable to insert opcode " 7037 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7038 return -1; 7039 } 7040 7041 return 0; 7042 } 7043 7044 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7045 unsigned char idx1, unsigned char idx2, 7046 unsigned char idx3, unsigned char idx4, 7047 opc_handler_t *handler) 7048 { 7049 opc_handler_t **table; 7050 7051 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7052 printf("*** ERROR: unable to join indirect table idx " 7053 "[%02x-%02x]\n", idx1, idx2); 7054 return -1; 7055 } 7056 table = ind_table(ppc_opcodes[idx1]); 7057 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7058 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7059 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7060 return -1; 7061 } 7062 table = ind_table(table[idx2]); 7063 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7064 printf("*** ERROR: unable to insert opcode " 7065 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7066 return -1; 7067 } 7068 return 0; 7069 } 7070 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7071 { 7072 if (insn->opc2 != 0xFF) { 7073 if (insn->opc3 != 0xFF) { 7074 if (insn->opc4 != 0xFF) { 7075 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7076 insn->opc3, insn->opc4, 7077 &insn->handler) < 0) { 7078 return -1; 7079 } 7080 } else { 7081 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7082 insn->opc3, &insn->handler) < 0) { 7083 return -1; 7084 } 7085 } 7086 } else { 7087 if (register_ind_insn(ppc_opcodes, insn->opc1, 7088 insn->opc2, &insn->handler) < 0) { 7089 return -1; 7090 } 7091 } 7092 } else { 7093 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7094 return -1; 7095 } 7096 } 7097 7098 return 0; 7099 } 7100 7101 static int test_opcode_table(opc_handler_t **table, int len) 7102 { 7103 int i, count, tmp; 7104 7105 for (i = 0, count = 0; i < len; i++) { 7106 /* Consistency fixup */ 7107 if (table[i] == NULL) { 7108 table[i] = &invalid_handler; 7109 } 7110 if (table[i] != &invalid_handler) { 7111 if (is_indirect_opcode(table[i])) { 7112 tmp = test_opcode_table(ind_table(table[i]), 7113 PPC_CPU_INDIRECT_OPCODES_LEN); 7114 if (tmp == 0) { 7115 free(table[i]); 7116 table[i] = &invalid_handler; 7117 } else { 7118 count++; 7119 } 7120 } else { 7121 count++; 7122 } 7123 } 7124 } 7125 7126 return count; 7127 } 7128 7129 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7130 { 7131 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7132 printf("*** WARNING: no opcode defined !\n"); 7133 } 7134 } 7135 7136 /*****************************************************************************/ 7137 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7138 { 7139 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7140 opcode_t *opc; 7141 7142 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7143 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7144 if (((opc->handler.type & pcc->insns_flags) != 0) || 7145 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7146 if (register_insn(cpu->opcodes, opc) < 0) { 7147 error_setg(errp, "ERROR initializing PowerPC instruction " 7148 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7149 opc->opc3); 7150 return; 7151 } 7152 } 7153 } 7154 fix_opcode_tables(cpu->opcodes); 7155 fflush(stdout); 7156 fflush(stderr); 7157 } 7158 7159 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7160 { 7161 opc_handler_t **table, **table_2; 7162 int i, j, k; 7163 7164 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7165 if (cpu->opcodes[i] == &invalid_handler) { 7166 continue; 7167 } 7168 if (is_indirect_opcode(cpu->opcodes[i])) { 7169 table = ind_table(cpu->opcodes[i]); 7170 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7171 if (table[j] == &invalid_handler) { 7172 continue; 7173 } 7174 if (is_indirect_opcode(table[j])) { 7175 table_2 = ind_table(table[j]); 7176 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7177 if (table_2[k] != &invalid_handler && 7178 is_indirect_opcode(table_2[k])) { 7179 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7180 ~PPC_INDIRECT)); 7181 } 7182 } 7183 g_free((opc_handler_t *)((uintptr_t)table[j] & 7184 ~PPC_INDIRECT)); 7185 } 7186 } 7187 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7188 ~PPC_INDIRECT)); 7189 } 7190 } 7191 } 7192 7193 int ppc_fixup_cpu(PowerPCCPU *cpu) 7194 { 7195 CPUPPCState *env = &cpu->env; 7196 7197 /* 7198 * TCG doesn't (yet) emulate some groups of instructions that are 7199 * implemented on some otherwise supported CPUs (e.g. VSX and 7200 * decimal floating point instructions on POWER7). We remove 7201 * unsupported instruction groups from the cpu state's instruction 7202 * masks and hope the guest can cope. For at least the pseries 7203 * machine, the unavailability of these instructions can be 7204 * advertised to the guest via the device tree. 7205 */ 7206 if ((env->insns_flags & ~PPC_TCG_INSNS) 7207 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7208 warn_report("Disabling some instructions which are not " 7209 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7210 env->insns_flags & ~PPC_TCG_INSNS, 7211 env->insns_flags2 & ~PPC_TCG_INSNS2); 7212 } 7213 env->insns_flags &= PPC_TCG_INSNS; 7214 env->insns_flags2 &= PPC_TCG_INSNS2; 7215 return 0; 7216 } 7217 7218 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7219 { 7220 opc_handler_t **table, *handler; 7221 uint32_t inval; 7222 7223 ctx->opcode = insn; 7224 7225 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7226 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7227 ctx->le_mode ? "little" : "big"); 7228 7229 table = cpu->opcodes; 7230 handler = table[opc1(insn)]; 7231 if (is_indirect_opcode(handler)) { 7232 table = ind_table(handler); 7233 handler = table[opc2(insn)]; 7234 if (is_indirect_opcode(handler)) { 7235 table = ind_table(handler); 7236 handler = table[opc3(insn)]; 7237 if (is_indirect_opcode(handler)) { 7238 table = ind_table(handler); 7239 handler = table[opc4(insn)]; 7240 } 7241 } 7242 } 7243 7244 /* Is opcode *REALLY* valid ? */ 7245 if (unlikely(handler->handler == &gen_invalid)) { 7246 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7247 "%02x - %02x - %02x - %02x (%08x) " 7248 TARGET_FMT_lx "\n", 7249 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7250 insn, ctx->cia); 7251 return false; 7252 } 7253 7254 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7255 && Rc(insn))) { 7256 inval = handler->inval2; 7257 } else { 7258 inval = handler->inval1; 7259 } 7260 7261 if (unlikely((insn & inval) != 0)) { 7262 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7263 "%02x - %02x - %02x - %02x (%08x) " 7264 TARGET_FMT_lx "\n", insn & inval, 7265 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7266 insn, ctx->cia); 7267 return false; 7268 } 7269 7270 handler->handler(ctx); 7271 return true; 7272 } 7273 7274 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7275 { 7276 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7277 CPUPPCState *env = cs->env_ptr; 7278 uint32_t hflags = ctx->base.tb->flags; 7279 7280 ctx->spr_cb = env->spr_cb; 7281 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7282 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7283 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7284 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7285 ctx->insns_flags = env->insns_flags; 7286 ctx->insns_flags2 = env->insns_flags2; 7287 ctx->access_type = -1; 7288 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7289 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7290 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7291 ctx->flags = env->flags; 7292 #if defined(TARGET_PPC64) 7293 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7294 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7295 #endif 7296 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7297 || env->mmu_model & POWERPC_MMU_64; 7298 7299 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7300 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7301 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7302 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7303 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7304 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7305 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7306 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7307 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7308 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7309 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7310 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7311 7312 ctx->singlestep_enabled = 0; 7313 if ((hflags >> HFLAGS_SE) & 1) { 7314 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7315 ctx->base.max_insns = 1; 7316 } 7317 if ((hflags >> HFLAGS_BE) & 1) { 7318 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7319 } 7320 } 7321 7322 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7323 { 7324 } 7325 7326 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7327 { 7328 tcg_gen_insn_start(dcbase->pc_next); 7329 } 7330 7331 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7332 { 7333 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7334 return opc1(insn) == 1; 7335 } 7336 7337 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7338 { 7339 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7340 PowerPCCPU *cpu = POWERPC_CPU(cs); 7341 CPUPPCState *env = cs->env_ptr; 7342 target_ulong pc; 7343 uint32_t insn; 7344 bool ok; 7345 7346 LOG_DISAS("----------------\n"); 7347 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7348 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7349 7350 ctx->cia = pc = ctx->base.pc_next; 7351 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7352 ctx->base.pc_next = pc += 4; 7353 7354 if (!is_prefix_insn(ctx, insn)) { 7355 ok = (decode_insn32(ctx, insn) || 7356 decode_legacy(cpu, ctx, insn)); 7357 } else if ((pc & 63) == 0) { 7358 /* 7359 * Power v3.1, section 1.9 Exceptions: 7360 * attempt to execute a prefixed instruction that crosses a 7361 * 64-byte address boundary (system alignment error). 7362 */ 7363 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7364 ok = true; 7365 } else { 7366 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7367 need_byteswap(ctx)); 7368 ctx->base.pc_next = pc += 4; 7369 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7370 } 7371 if (!ok) { 7372 gen_invalid(ctx); 7373 } 7374 7375 /* End the TB when crossing a page boundary. */ 7376 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7377 ctx->base.is_jmp = DISAS_TOO_MANY; 7378 } 7379 } 7380 7381 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7382 { 7383 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7384 DisasJumpType is_jmp = ctx->base.is_jmp; 7385 target_ulong nip = ctx->base.pc_next; 7386 7387 if (is_jmp == DISAS_NORETURN) { 7388 /* We have already exited the TB. */ 7389 return; 7390 } 7391 7392 /* Honor single stepping. */ 7393 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7394 && (nip <= 0x100 || nip > 0xf00)) { 7395 switch (is_jmp) { 7396 case DISAS_TOO_MANY: 7397 case DISAS_EXIT_UPDATE: 7398 case DISAS_CHAIN_UPDATE: 7399 gen_update_nip(ctx, nip); 7400 break; 7401 case DISAS_EXIT: 7402 case DISAS_CHAIN: 7403 break; 7404 default: 7405 g_assert_not_reached(); 7406 } 7407 7408 gen_debug_exception(ctx); 7409 return; 7410 } 7411 7412 switch (is_jmp) { 7413 case DISAS_TOO_MANY: 7414 if (use_goto_tb(ctx, nip)) { 7415 pmu_count_insns(ctx); 7416 tcg_gen_goto_tb(0); 7417 gen_update_nip(ctx, nip); 7418 tcg_gen_exit_tb(ctx->base.tb, 0); 7419 break; 7420 } 7421 /* fall through */ 7422 case DISAS_CHAIN_UPDATE: 7423 gen_update_nip(ctx, nip); 7424 /* fall through */ 7425 case DISAS_CHAIN: 7426 /* 7427 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7428 * CF_NO_GOTO_PTR is set. Count insns now. 7429 */ 7430 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7431 pmu_count_insns(ctx); 7432 } 7433 7434 tcg_gen_lookup_and_goto_ptr(); 7435 break; 7436 7437 case DISAS_EXIT_UPDATE: 7438 gen_update_nip(ctx, nip); 7439 /* fall through */ 7440 case DISAS_EXIT: 7441 pmu_count_insns(ctx); 7442 tcg_gen_exit_tb(NULL, 0); 7443 break; 7444 7445 default: 7446 g_assert_not_reached(); 7447 } 7448 } 7449 7450 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7451 CPUState *cs, FILE *logfile) 7452 { 7453 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7454 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7455 } 7456 7457 static const TranslatorOps ppc_tr_ops = { 7458 .init_disas_context = ppc_tr_init_disas_context, 7459 .tb_start = ppc_tr_tb_start, 7460 .insn_start = ppc_tr_insn_start, 7461 .translate_insn = ppc_tr_translate_insn, 7462 .tb_stop = ppc_tr_tb_stop, 7463 .disas_log = ppc_tr_disas_log, 7464 }; 7465 7466 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7467 target_ulong pc, void *host_pc) 7468 { 7469 DisasContext ctx; 7470 7471 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7472 } 7473