1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "exec/translator.h" 36 #include "exec/log.h" 37 #include "qemu/atomic128.h" 38 #include "spr_common.h" 39 #include "power8-pmu.h" 40 41 #include "qemu/qemu-print.h" 42 #include "qapi/error.h" 43 44 #define HELPER_H "helper.h" 45 #include "exec/helper-info.c.inc" 46 #undef HELPER_H 47 48 #define CPU_SINGLE_STEP 0x1 49 #define CPU_BRANCH_STEP 0x2 50 51 /* Include definitions for instructions classes and implementations flags */ 52 /* #define PPC_DEBUG_DISAS */ 53 54 #ifdef PPC_DEBUG_DISAS 55 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56 #else 57 # define LOG_DISAS(...) do { } while (0) 58 #endif 59 /*****************************************************************************/ 60 /* Code translation helpers */ 61 62 /* global register indexes */ 63 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64 + 10 * 4 + 22 * 5 /* SPE GPRh */ 65 + 8 * 5 /* CRF */]; 66 static TCGv cpu_gpr[32]; 67 static TCGv cpu_gprh[32]; 68 static TCGv_i32 cpu_crf[8]; 69 static TCGv cpu_nip; 70 static TCGv cpu_msr; 71 static TCGv cpu_ctr; 72 static TCGv cpu_lr; 73 #if defined(TARGET_PPC64) 74 static TCGv cpu_cfar; 75 #endif 76 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77 static TCGv cpu_reserve; 78 static TCGv cpu_reserve_length; 79 static TCGv cpu_reserve_val; 80 static TCGv cpu_reserve_val2; 81 static TCGv cpu_fpscr; 82 static TCGv_i32 cpu_access_type; 83 84 void ppc_translate_init(void) 85 { 86 int i; 87 char *p; 88 size_t cpu_reg_names_size; 89 90 p = cpu_reg_names; 91 cpu_reg_names_size = sizeof(cpu_reg_names); 92 93 for (i = 0; i < 8; i++) { 94 snprintf(p, cpu_reg_names_size, "crf%d", i); 95 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96 offsetof(CPUPPCState, crf[i]), p); 97 p += 5; 98 cpu_reg_names_size -= 5; 99 } 100 101 for (i = 0; i < 32; i++) { 102 snprintf(p, cpu_reg_names_size, "r%d", i); 103 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gpr[i]), p); 105 p += (i < 10) ? 3 : 4; 106 cpu_reg_names_size -= (i < 10) ? 3 : 4; 107 snprintf(p, cpu_reg_names_size, "r%dH", i); 108 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109 offsetof(CPUPPCState, gprh[i]), p); 110 p += (i < 10) ? 4 : 5; 111 cpu_reg_names_size -= (i < 10) ? 4 : 5; 112 } 113 114 cpu_nip = tcg_global_mem_new(cpu_env, 115 offsetof(CPUPPCState, nip), "nip"); 116 117 cpu_msr = tcg_global_mem_new(cpu_env, 118 offsetof(CPUPPCState, msr), "msr"); 119 120 cpu_ctr = tcg_global_mem_new(cpu_env, 121 offsetof(CPUPPCState, ctr), "ctr"); 122 123 cpu_lr = tcg_global_mem_new(cpu_env, 124 offsetof(CPUPPCState, lr), "lr"); 125 126 #if defined(TARGET_PPC64) 127 cpu_cfar = tcg_global_mem_new(cpu_env, 128 offsetof(CPUPPCState, cfar), "cfar"); 129 #endif 130 131 cpu_xer = tcg_global_mem_new(cpu_env, 132 offsetof(CPUPPCState, xer), "xer"); 133 cpu_so = tcg_global_mem_new(cpu_env, 134 offsetof(CPUPPCState, so), "SO"); 135 cpu_ov = tcg_global_mem_new(cpu_env, 136 offsetof(CPUPPCState, ov), "OV"); 137 cpu_ca = tcg_global_mem_new(cpu_env, 138 offsetof(CPUPPCState, ca), "CA"); 139 cpu_ov32 = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, ov32), "OV32"); 141 cpu_ca32 = tcg_global_mem_new(cpu_env, 142 offsetof(CPUPPCState, ca32), "CA32"); 143 144 cpu_reserve = tcg_global_mem_new(cpu_env, 145 offsetof(CPUPPCState, reserve_addr), 146 "reserve_addr"); 147 cpu_reserve_length = tcg_global_mem_new(cpu_env, 148 offsetof(CPUPPCState, 149 reserve_length), 150 "reserve_length"); 151 cpu_reserve_val = tcg_global_mem_new(cpu_env, 152 offsetof(CPUPPCState, reserve_val), 153 "reserve_val"); 154 cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 158 cpu_fpscr = tcg_global_mem_new(cpu_env, 159 offsetof(CPUPPCState, fpscr), "fpscr"); 160 161 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162 offsetof(CPUPPCState, access_type), 163 "access_type"); 164 } 165 166 /* internal defines */ 167 struct DisasContext { 168 DisasContextBase base; 169 target_ulong cia; /* current instruction address */ 170 uint32_t opcode; 171 /* Routine used to access memory */ 172 bool pr, hv, dr, le_mode; 173 bool lazy_tlb_flush; 174 bool need_access_type; 175 int mem_idx; 176 int access_type; 177 /* Translation flags */ 178 MemOp default_tcg_memop_mask; 179 #if defined(TARGET_PPC64) 180 bool sf_mode; 181 bool has_cfar; 182 #endif 183 bool fpu_enabled; 184 bool altivec_enabled; 185 bool vsx_enabled; 186 bool spe_enabled; 187 bool tm_enabled; 188 bool gtse; 189 bool hr; 190 bool mmcr0_pmcc0; 191 bool mmcr0_pmcc1; 192 bool mmcr0_pmcjce; 193 bool pmc_other; 194 bool pmu_insn_cnt; 195 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196 int singlestep_enabled; 197 uint32_t flags; 198 uint64_t insns_flags; 199 uint64_t insns_flags2; 200 }; 201 202 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206 207 /* Return true iff byteswap is needed in a scalar memop */ 208 static inline bool need_byteswap(const DisasContext *ctx) 209 { 210 #if TARGET_BIG_ENDIAN 211 return ctx->le_mode; 212 #else 213 return !ctx->le_mode; 214 #endif 215 } 216 217 /* True when active word size < size of target_long. */ 218 #ifdef TARGET_PPC64 219 # define NARROW_MODE(C) (!(C)->sf_mode) 220 #else 221 # define NARROW_MODE(C) 0 222 #endif 223 224 struct opc_handler_t { 225 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226 uint32_t inval1; 227 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228 uint32_t inval2; 229 /* instruction type */ 230 uint64_t type; 231 /* extended instruction type */ 232 uint64_t type2; 233 /* handler */ 234 void (*handler)(DisasContext *ctx); 235 }; 236 237 static inline bool gen_serialize(DisasContext *ctx) 238 { 239 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240 /* Restart with exclusive lock. */ 241 gen_helper_exit_atomic(cpu_env); 242 ctx->base.is_jmp = DISAS_NORETURN; 243 return false; 244 } 245 return true; 246 } 247 248 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249 static inline bool gen_serialize_core(DisasContext *ctx) 250 { 251 if (ctx->flags & POWERPC_FLAG_SMT) { 252 return gen_serialize(ctx); 253 } 254 255 return true; 256 } 257 #endif 258 259 /* SPR load/store helpers */ 260 static inline void gen_load_spr(TCGv t, int reg) 261 { 262 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 263 } 264 265 static inline void gen_store_spr(int reg, TCGv t) 266 { 267 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 268 } 269 270 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271 { 272 if (ctx->need_access_type && ctx->access_type != access_type) { 273 tcg_gen_movi_i32(cpu_access_type, access_type); 274 ctx->access_type = access_type; 275 } 276 } 277 278 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279 { 280 if (NARROW_MODE(ctx)) { 281 nip = (uint32_t)nip; 282 } 283 tcg_gen_movi_tl(cpu_nip, nip); 284 } 285 286 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287 { 288 TCGv_i32 t0, t1; 289 290 /* 291 * These are all synchronous exceptions, we set the PC back to the 292 * faulting instruction 293 */ 294 gen_update_nip(ctx, ctx->cia); 295 t0 = tcg_constant_i32(excp); 296 t1 = tcg_constant_i32(error); 297 gen_helper_raise_exception_err(cpu_env, t0, t1); 298 ctx->base.is_jmp = DISAS_NORETURN; 299 } 300 301 static void gen_exception(DisasContext *ctx, uint32_t excp) 302 { 303 TCGv_i32 t0; 304 305 /* 306 * These are all synchronous exceptions, we set the PC back to the 307 * faulting instruction 308 */ 309 gen_update_nip(ctx, ctx->cia); 310 t0 = tcg_constant_i32(excp); 311 gen_helper_raise_exception(cpu_env, t0); 312 ctx->base.is_jmp = DISAS_NORETURN; 313 } 314 315 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316 target_ulong nip) 317 { 318 TCGv_i32 t0; 319 320 gen_update_nip(ctx, nip); 321 t0 = tcg_constant_i32(excp); 322 gen_helper_raise_exception(cpu_env, t0); 323 ctx->base.is_jmp = DISAS_NORETURN; 324 } 325 326 #if !defined(CONFIG_USER_ONLY) 327 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 328 { 329 translator_io_start(&ctx->base); 330 gen_helper_ppc_maybe_interrupt(cpu_env); 331 } 332 #endif 333 334 /* 335 * Tells the caller what is the appropriate exception to generate and prepares 336 * SPR registers for this exception. 337 * 338 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339 * POWERPC_EXCP_DEBUG (on BookE). 340 */ 341 static uint32_t gen_prep_dbgex(DisasContext *ctx) 342 { 343 if (ctx->flags & POWERPC_FLAG_DE) { 344 target_ulong dbsr = 0; 345 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 346 dbsr = DBCR0_ICMP; 347 } else { 348 /* Must have been branch */ 349 dbsr = DBCR0_BRT; 350 } 351 TCGv t0 = tcg_temp_new(); 352 gen_load_spr(t0, SPR_BOOKE_DBSR); 353 tcg_gen_ori_tl(t0, t0, dbsr); 354 gen_store_spr(SPR_BOOKE_DBSR, t0); 355 return POWERPC_EXCP_DEBUG; 356 } else { 357 return POWERPC_EXCP_TRACE; 358 } 359 } 360 361 static void gen_debug_exception(DisasContext *ctx) 362 { 363 gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 364 ctx->base.is_jmp = DISAS_NORETURN; 365 } 366 367 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368 { 369 /* Will be converted to program check if needed */ 370 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371 } 372 373 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374 { 375 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376 } 377 378 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379 { 380 /* Will be converted to program check if needed */ 381 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382 } 383 384 /*****************************************************************************/ 385 /* SPR READ/WRITE CALLBACKS */ 386 387 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 388 { 389 #if 0 390 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 391 printf("ERROR: try to access SPR %d !\n", sprn); 392 #endif 393 } 394 395 /* #define PPC_DUMP_SPR_ACCESSES */ 396 397 /* 398 * Generic callbacks: 399 * do nothing but store/retrieve spr value 400 */ 401 static void spr_load_dump_spr(int sprn) 402 { 403 #ifdef PPC_DUMP_SPR_ACCESSES 404 TCGv_i32 t0 = tcg_constant_i32(sprn); 405 gen_helper_load_dump_spr(cpu_env, t0); 406 #endif 407 } 408 409 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 410 { 411 gen_load_spr(cpu_gpr[gprn], sprn); 412 spr_load_dump_spr(sprn); 413 } 414 415 static void spr_store_dump_spr(int sprn) 416 { 417 #ifdef PPC_DUMP_SPR_ACCESSES 418 TCGv_i32 t0 = tcg_constant_i32(sprn); 419 gen_helper_store_dump_spr(cpu_env, t0); 420 #endif 421 } 422 423 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 424 { 425 gen_store_spr(sprn, cpu_gpr[gprn]); 426 spr_store_dump_spr(sprn); 427 } 428 429 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 430 { 431 #ifdef TARGET_PPC64 432 TCGv t0 = tcg_temp_new(); 433 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 434 gen_store_spr(sprn, t0); 435 spr_store_dump_spr(sprn); 436 #else 437 spr_write_generic(ctx, sprn, gprn); 438 #endif 439 } 440 441 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442 { 443 /* This does not implement >1 thread */ 444 TCGv t0 = tcg_temp_new(); 445 TCGv t1 = tcg_temp_new(); 446 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448 tcg_gen_or_tl(t1, t1, t0); 449 gen_store_spr(sprn, t1); 450 } 451 452 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453 { 454 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 455 spr_write_CTRL_ST(ctx, sprn, gprn); 456 goto out; 457 } 458 459 if (!gen_serialize(ctx)) { 460 return; 461 } 462 463 gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 464 cpu_gpr[gprn]); 465 out: 466 spr_store_dump_spr(sprn); 467 468 /* 469 * SPR_CTRL writes must force a new translation block, 470 * allowing the PMU to calculate the run latch events with 471 * more accuracy. 472 */ 473 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 474 } 475 476 #if !defined(CONFIG_USER_ONLY) 477 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 478 { 479 TCGv t0 = tcg_temp_new(); 480 TCGv t1 = tcg_temp_new(); 481 gen_load_spr(t0, sprn); 482 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 483 tcg_gen_and_tl(t0, t0, t1); 484 gen_store_spr(sprn, t0); 485 } 486 487 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 488 { 489 } 490 491 #endif 492 493 /* SPR common to all PowerPC */ 494 /* XER */ 495 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 496 { 497 TCGv dst = cpu_gpr[gprn]; 498 TCGv t0 = tcg_temp_new(); 499 TCGv t1 = tcg_temp_new(); 500 TCGv t2 = tcg_temp_new(); 501 tcg_gen_mov_tl(dst, cpu_xer); 502 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 503 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 504 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 505 tcg_gen_or_tl(t0, t0, t1); 506 tcg_gen_or_tl(dst, dst, t2); 507 tcg_gen_or_tl(dst, dst, t0); 508 if (is_isa300(ctx)) { 509 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 510 tcg_gen_or_tl(dst, dst, t0); 511 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 512 tcg_gen_or_tl(dst, dst, t0); 513 } 514 } 515 516 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 517 { 518 TCGv src = cpu_gpr[gprn]; 519 /* Write all flags, while reading back check for isa300 */ 520 tcg_gen_andi_tl(cpu_xer, src, 521 ~((1u << XER_SO) | 522 (1u << XER_OV) | (1u << XER_OV32) | 523 (1u << XER_CA) | (1u << XER_CA32))); 524 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 525 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 526 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 527 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 528 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 529 } 530 531 /* LR */ 532 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 533 { 534 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 535 } 536 537 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 538 { 539 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 540 } 541 542 /* CFAR */ 543 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 544 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 545 { 546 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 547 } 548 549 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 550 { 551 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 552 } 553 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 554 555 /* CTR */ 556 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 557 { 558 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 559 } 560 561 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 562 { 563 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 564 } 565 566 /* User read access to SPR */ 567 /* USPRx */ 568 /* UMMCRx */ 569 /* UPMCx */ 570 /* USIA */ 571 /* UDECR */ 572 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 573 { 574 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 575 } 576 577 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 578 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 579 { 580 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 581 } 582 #endif 583 584 /* SPR common to all non-embedded PowerPC */ 585 /* DECR */ 586 #if !defined(CONFIG_USER_ONLY) 587 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 588 { 589 translator_io_start(&ctx->base); 590 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 591 } 592 593 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 594 { 595 translator_io_start(&ctx->base); 596 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 597 } 598 #endif 599 600 /* SPR common to all non-embedded PowerPC, except 601 */ 601 /* Time base */ 602 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 603 { 604 translator_io_start(&ctx->base); 605 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 606 } 607 608 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 609 { 610 translator_io_start(&ctx->base); 611 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 612 } 613 614 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 615 { 616 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 617 } 618 619 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 620 { 621 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 622 } 623 624 #if !defined(CONFIG_USER_ONLY) 625 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 626 { 627 translator_io_start(&ctx->base); 628 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 629 } 630 631 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 632 { 633 translator_io_start(&ctx->base); 634 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 635 } 636 637 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 638 { 639 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 640 } 641 642 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 643 { 644 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 645 } 646 647 #if defined(TARGET_PPC64) 648 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 649 { 650 translator_io_start(&ctx->base); 651 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 652 } 653 654 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 655 { 656 translator_io_start(&ctx->base); 657 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 658 } 659 660 /* HDECR */ 661 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 662 { 663 translator_io_start(&ctx->base); 664 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 665 } 666 667 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 668 { 669 translator_io_start(&ctx->base); 670 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 671 } 672 673 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 674 { 675 translator_io_start(&ctx->base); 676 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 677 } 678 679 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 680 { 681 translator_io_start(&ctx->base); 682 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 683 } 684 685 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 686 { 687 translator_io_start(&ctx->base); 688 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 689 } 690 691 #endif 692 #endif 693 694 #if !defined(CONFIG_USER_ONLY) 695 /* IBAT0U...IBAT0U */ 696 /* IBAT0L...IBAT7L */ 697 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 698 { 699 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 700 offsetof(CPUPPCState, 701 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 702 } 703 704 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 705 { 706 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 707 offsetof(CPUPPCState, 708 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 709 } 710 711 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 712 { 713 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 714 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 715 } 716 717 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 718 { 719 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 720 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 721 } 722 723 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 724 { 725 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 726 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 727 } 728 729 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 730 { 731 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 732 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 733 } 734 735 /* DBAT0U...DBAT7U */ 736 /* DBAT0L...DBAT7L */ 737 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 738 { 739 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 740 offsetof(CPUPPCState, 741 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 742 } 743 744 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 745 { 746 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 747 offsetof(CPUPPCState, 748 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 749 } 750 751 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 752 { 753 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 754 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 755 } 756 757 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 758 { 759 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 760 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 761 } 762 763 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 764 { 765 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 766 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 767 } 768 769 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 770 { 771 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 772 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 773 } 774 775 /* SDR1 */ 776 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 777 { 778 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 779 } 780 781 #if defined(TARGET_PPC64) 782 /* 64 bits PowerPC specific SPRs */ 783 /* PIDR */ 784 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 785 { 786 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 787 } 788 789 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 790 { 791 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 792 } 793 794 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 795 { 796 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 797 } 798 799 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 800 { 801 TCGv t0 = tcg_temp_new(); 802 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 803 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 804 } 805 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 806 { 807 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 808 } 809 810 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 811 { 812 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 813 } 814 815 /* DPDES */ 816 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 817 { 818 if (!gen_serialize_core(ctx)) { 819 return; 820 } 821 822 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 823 } 824 825 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 826 { 827 if (!gen_serialize_core(ctx)) { 828 return; 829 } 830 831 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 832 } 833 #endif 834 #endif 835 836 /* PowerPC 40x specific registers */ 837 #if !defined(CONFIG_USER_ONLY) 838 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 839 { 840 translator_io_start(&ctx->base); 841 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 842 } 843 844 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 845 { 846 translator_io_start(&ctx->base); 847 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 848 } 849 850 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 851 { 852 translator_io_start(&ctx->base); 853 gen_store_spr(sprn, cpu_gpr[gprn]); 854 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 855 /* We must stop translation as we may have rebooted */ 856 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 857 } 858 859 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 860 { 861 translator_io_start(&ctx->base); 862 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 863 } 864 865 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 866 { 867 translator_io_start(&ctx->base); 868 gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 869 } 870 871 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 872 { 873 translator_io_start(&ctx->base); 874 gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 875 } 876 877 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 878 { 879 TCGv t0 = tcg_temp_new(); 880 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 881 gen_helper_store_40x_pid(cpu_env, t0); 882 } 883 884 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 885 { 886 translator_io_start(&ctx->base); 887 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 888 } 889 890 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 891 { 892 translator_io_start(&ctx->base); 893 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 894 } 895 #endif 896 897 /* PIR */ 898 #if !defined(CONFIG_USER_ONLY) 899 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 900 { 901 TCGv t0 = tcg_temp_new(); 902 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 903 gen_store_spr(SPR_PIR, t0); 904 } 905 #endif 906 907 /* SPE specific registers */ 908 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 909 { 910 TCGv_i32 t0 = tcg_temp_new_i32(); 911 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 912 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 913 } 914 915 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 916 { 917 TCGv_i32 t0 = tcg_temp_new_i32(); 918 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 919 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 920 } 921 922 #if !defined(CONFIG_USER_ONLY) 923 /* Callback used to write the exception vector base */ 924 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 925 { 926 TCGv t0 = tcg_temp_new(); 927 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 928 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 929 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 930 gen_store_spr(sprn, t0); 931 } 932 933 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 934 { 935 int sprn_offs; 936 937 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 938 sprn_offs = sprn - SPR_BOOKE_IVOR0; 939 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 940 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 941 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 942 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 943 } else { 944 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 945 " vector 0x%03x\n", sprn); 946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 947 return; 948 } 949 950 TCGv t0 = tcg_temp_new(); 951 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 952 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 953 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 954 gen_store_spr(sprn, t0); 955 } 956 #endif 957 958 #ifdef TARGET_PPC64 959 #ifndef CONFIG_USER_ONLY 960 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 961 { 962 TCGv t0 = tcg_temp_new(); 963 TCGv t1 = tcg_temp_new(); 964 TCGv t2 = tcg_temp_new(); 965 966 /* 967 * Note, the HV=1 PR=0 case is handled earlier by simply using 968 * spr_write_generic for HV mode in the SPR table 969 */ 970 971 /* Build insertion mask into t1 based on context */ 972 if (ctx->pr) { 973 gen_load_spr(t1, SPR_UAMOR); 974 } else { 975 gen_load_spr(t1, SPR_AMOR); 976 } 977 978 /* Mask new bits into t2 */ 979 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 980 981 /* Load AMR and clear new bits in t0 */ 982 gen_load_spr(t0, SPR_AMR); 983 tcg_gen_andc_tl(t0, t0, t1); 984 985 /* Or'in new bits and write it out */ 986 tcg_gen_or_tl(t0, t0, t2); 987 gen_store_spr(SPR_AMR, t0); 988 spr_store_dump_spr(SPR_AMR); 989 } 990 991 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 992 { 993 TCGv t0 = tcg_temp_new(); 994 TCGv t1 = tcg_temp_new(); 995 TCGv t2 = tcg_temp_new(); 996 997 /* 998 * Note, the HV=1 case is handled earlier by simply using 999 * spr_write_generic for HV mode in the SPR table 1000 */ 1001 1002 /* Build insertion mask into t1 based on context */ 1003 gen_load_spr(t1, SPR_AMOR); 1004 1005 /* Mask new bits into t2 */ 1006 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1007 1008 /* Load AMR and clear new bits in t0 */ 1009 gen_load_spr(t0, SPR_UAMOR); 1010 tcg_gen_andc_tl(t0, t0, t1); 1011 1012 /* Or'in new bits and write it out */ 1013 tcg_gen_or_tl(t0, t0, t2); 1014 gen_store_spr(SPR_UAMOR, t0); 1015 spr_store_dump_spr(SPR_UAMOR); 1016 } 1017 1018 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1019 { 1020 TCGv t0 = tcg_temp_new(); 1021 TCGv t1 = tcg_temp_new(); 1022 TCGv t2 = tcg_temp_new(); 1023 1024 /* 1025 * Note, the HV=1 case is handled earlier by simply using 1026 * spr_write_generic for HV mode in the SPR table 1027 */ 1028 1029 /* Build insertion mask into t1 based on context */ 1030 gen_load_spr(t1, SPR_AMOR); 1031 1032 /* Mask new bits into t2 */ 1033 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1034 1035 /* Load AMR and clear new bits in t0 */ 1036 gen_load_spr(t0, SPR_IAMR); 1037 tcg_gen_andc_tl(t0, t0, t1); 1038 1039 /* Or'in new bits and write it out */ 1040 tcg_gen_or_tl(t0, t0, t2); 1041 gen_store_spr(SPR_IAMR, t0); 1042 spr_store_dump_spr(SPR_IAMR); 1043 } 1044 #endif 1045 #endif 1046 1047 #ifndef CONFIG_USER_ONLY 1048 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1049 { 1050 gen_helper_fixup_thrm(cpu_env); 1051 gen_load_spr(cpu_gpr[gprn], sprn); 1052 spr_load_dump_spr(sprn); 1053 } 1054 #endif /* !CONFIG_USER_ONLY */ 1055 1056 #if !defined(CONFIG_USER_ONLY) 1057 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1058 { 1059 TCGv t0 = tcg_temp_new(); 1060 1061 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1062 gen_store_spr(sprn, t0); 1063 } 1064 1065 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1066 { 1067 TCGv t0 = tcg_temp_new(); 1068 1069 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1070 gen_store_spr(sprn, t0); 1071 } 1072 1073 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1074 { 1075 TCGv t0 = tcg_temp_new(); 1076 1077 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1078 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1079 gen_store_spr(sprn, t0); 1080 } 1081 1082 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1083 { 1084 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1085 } 1086 1087 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1088 { 1089 TCGv_i32 t0 = tcg_constant_i32(sprn); 1090 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1091 } 1092 1093 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1094 { 1095 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1096 } 1097 1098 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1099 { 1100 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1101 } 1102 1103 #endif 1104 1105 #if !defined(CONFIG_USER_ONLY) 1106 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1107 { 1108 TCGv val = tcg_temp_new(); 1109 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1110 gen_store_spr(SPR_BOOKE_MAS3, val); 1111 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1112 gen_store_spr(SPR_BOOKE_MAS7, val); 1113 } 1114 1115 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1116 { 1117 TCGv mas7 = tcg_temp_new(); 1118 TCGv mas3 = tcg_temp_new(); 1119 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1120 tcg_gen_shli_tl(mas7, mas7, 32); 1121 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1122 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1123 } 1124 1125 #endif 1126 1127 #ifdef TARGET_PPC64 1128 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1129 int bit, int sprn, int cause) 1130 { 1131 TCGv_i32 t1 = tcg_constant_i32(bit); 1132 TCGv_i32 t2 = tcg_constant_i32(sprn); 1133 TCGv_i32 t3 = tcg_constant_i32(cause); 1134 1135 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1136 } 1137 1138 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1139 int bit, int sprn, int cause) 1140 { 1141 TCGv_i32 t1 = tcg_constant_i32(bit); 1142 TCGv_i32 t2 = tcg_constant_i32(sprn); 1143 TCGv_i32 t3 = tcg_constant_i32(cause); 1144 1145 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1146 } 1147 1148 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1149 { 1150 TCGv spr_up = tcg_temp_new(); 1151 TCGv spr = tcg_temp_new(); 1152 1153 gen_load_spr(spr, sprn - 1); 1154 tcg_gen_shri_tl(spr_up, spr, 32); 1155 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1156 } 1157 1158 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1159 { 1160 TCGv spr = tcg_temp_new(); 1161 1162 gen_load_spr(spr, sprn - 1); 1163 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1164 gen_store_spr(sprn - 1, spr); 1165 } 1166 1167 #if !defined(CONFIG_USER_ONLY) 1168 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1169 { 1170 TCGv hmer = tcg_temp_new(); 1171 1172 gen_load_spr(hmer, sprn); 1173 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1174 gen_store_spr(sprn, hmer); 1175 spr_store_dump_spr(sprn); 1176 } 1177 1178 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1179 { 1180 gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1181 } 1182 1183 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1184 { 1185 gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1186 } 1187 1188 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1189 { 1190 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1191 } 1192 #endif /* !defined(CONFIG_USER_ONLY) */ 1193 1194 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1195 { 1196 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1197 spr_read_generic(ctx, gprn, sprn); 1198 } 1199 1200 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1201 { 1202 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1203 spr_write_generic(ctx, sprn, gprn); 1204 } 1205 1206 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1207 { 1208 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1209 spr_read_generic(ctx, gprn, sprn); 1210 } 1211 1212 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1213 { 1214 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1215 spr_write_generic(ctx, sprn, gprn); 1216 } 1217 1218 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1219 { 1220 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1221 spr_read_prev_upper32(ctx, gprn, sprn); 1222 } 1223 1224 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1225 { 1226 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1227 spr_write_prev_upper32(ctx, sprn, gprn); 1228 } 1229 1230 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1231 { 1232 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1233 spr_read_generic(ctx, gprn, sprn); 1234 } 1235 1236 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1237 { 1238 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1239 spr_write_generic(ctx, sprn, gprn); 1240 } 1241 1242 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1243 { 1244 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1245 spr_read_prev_upper32(ctx, gprn, sprn); 1246 } 1247 1248 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1249 { 1250 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1251 spr_write_prev_upper32(ctx, sprn, gprn); 1252 } 1253 1254 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1255 { 1256 TCGv t0 = tcg_temp_new(); 1257 1258 /* 1259 * Access to the (H)DEXCR in problem state is done using separated 1260 * SPR indexes which are 16 below the SPR indexes which have full 1261 * access to the (H)DEXCR in privileged state. Problem state can 1262 * only read bits 32:63, bits 0:31 return 0. 1263 * 1264 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1265 */ 1266 1267 gen_load_spr(t0, sprn + 16); 1268 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1269 } 1270 #endif 1271 1272 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1273 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1274 1275 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1276 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1277 1278 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1279 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1280 1281 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1282 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1283 1284 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1285 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1286 1287 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1288 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1289 1290 typedef struct opcode_t { 1291 unsigned char opc1, opc2, opc3, opc4; 1292 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1293 unsigned char pad[4]; 1294 #endif 1295 opc_handler_t handler; 1296 const char *oname; 1297 } opcode_t; 1298 1299 static void gen_priv_opc(DisasContext *ctx) 1300 { 1301 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1302 } 1303 1304 /* Helpers for priv. check */ 1305 #define GEN_PRIV(CTX) \ 1306 do { \ 1307 gen_priv_opc(CTX); return; \ 1308 } while (0) 1309 1310 #if defined(CONFIG_USER_ONLY) 1311 #define CHK_HV(CTX) GEN_PRIV(CTX) 1312 #define CHK_SV(CTX) GEN_PRIV(CTX) 1313 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1314 #else 1315 #define CHK_HV(CTX) \ 1316 do { \ 1317 if (unlikely(ctx->pr || !ctx->hv)) {\ 1318 GEN_PRIV(CTX); \ 1319 } \ 1320 } while (0) 1321 #define CHK_SV(CTX) \ 1322 do { \ 1323 if (unlikely(ctx->pr)) { \ 1324 GEN_PRIV(CTX); \ 1325 } \ 1326 } while (0) 1327 #define CHK_HVRM(CTX) \ 1328 do { \ 1329 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1330 GEN_PRIV(CTX); \ 1331 } \ 1332 } while (0) 1333 #endif 1334 1335 #define CHK_NONE(CTX) 1336 1337 /*****************************************************************************/ 1338 /* PowerPC instructions table */ 1339 1340 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1341 { \ 1342 .opc1 = op1, \ 1343 .opc2 = op2, \ 1344 .opc3 = op3, \ 1345 .opc4 = 0xff, \ 1346 .handler = { \ 1347 .inval1 = invl, \ 1348 .type = _typ, \ 1349 .type2 = _typ2, \ 1350 .handler = &gen_##name, \ 1351 }, \ 1352 .oname = stringify(name), \ 1353 } 1354 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1355 { \ 1356 .opc1 = op1, \ 1357 .opc2 = op2, \ 1358 .opc3 = op3, \ 1359 .opc4 = 0xff, \ 1360 .handler = { \ 1361 .inval1 = invl1, \ 1362 .inval2 = invl2, \ 1363 .type = _typ, \ 1364 .type2 = _typ2, \ 1365 .handler = &gen_##name, \ 1366 }, \ 1367 .oname = stringify(name), \ 1368 } 1369 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1370 { \ 1371 .opc1 = op1, \ 1372 .opc2 = op2, \ 1373 .opc3 = op3, \ 1374 .opc4 = 0xff, \ 1375 .handler = { \ 1376 .inval1 = invl, \ 1377 .type = _typ, \ 1378 .type2 = _typ2, \ 1379 .handler = &gen_##name, \ 1380 }, \ 1381 .oname = onam, \ 1382 } 1383 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1384 { \ 1385 .opc1 = op1, \ 1386 .opc2 = op2, \ 1387 .opc3 = op3, \ 1388 .opc4 = op4, \ 1389 .handler = { \ 1390 .inval1 = invl, \ 1391 .type = _typ, \ 1392 .type2 = _typ2, \ 1393 .handler = &gen_##name, \ 1394 }, \ 1395 .oname = stringify(name), \ 1396 } 1397 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1398 { \ 1399 .opc1 = op1, \ 1400 .opc2 = op2, \ 1401 .opc3 = op3, \ 1402 .opc4 = op4, \ 1403 .handler = { \ 1404 .inval1 = invl, \ 1405 .type = _typ, \ 1406 .type2 = _typ2, \ 1407 .handler = &gen_##name, \ 1408 }, \ 1409 .oname = onam, \ 1410 } 1411 1412 /* Invalid instruction */ 1413 static void gen_invalid(DisasContext *ctx) 1414 { 1415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1416 } 1417 1418 static opc_handler_t invalid_handler = { 1419 .inval1 = 0xFFFFFFFF, 1420 .inval2 = 0xFFFFFFFF, 1421 .type = PPC_NONE, 1422 .type2 = PPC_NONE, 1423 .handler = gen_invalid, 1424 }; 1425 1426 /*** Integer comparison ***/ 1427 1428 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1429 { 1430 TCGv t0 = tcg_temp_new(); 1431 TCGv t1 = tcg_temp_new(); 1432 TCGv_i32 t = tcg_temp_new_i32(); 1433 1434 tcg_gen_movi_tl(t0, CRF_EQ); 1435 tcg_gen_movi_tl(t1, CRF_LT); 1436 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1437 t0, arg0, arg1, t1, t0); 1438 tcg_gen_movi_tl(t1, CRF_GT); 1439 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1440 t0, arg0, arg1, t1, t0); 1441 1442 tcg_gen_trunc_tl_i32(t, t0); 1443 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1444 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1445 } 1446 1447 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1448 { 1449 TCGv t0 = tcg_constant_tl(arg1); 1450 gen_op_cmp(arg0, t0, s, crf); 1451 } 1452 1453 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1454 { 1455 TCGv t0, t1; 1456 t0 = tcg_temp_new(); 1457 t1 = tcg_temp_new(); 1458 if (s) { 1459 tcg_gen_ext32s_tl(t0, arg0); 1460 tcg_gen_ext32s_tl(t1, arg1); 1461 } else { 1462 tcg_gen_ext32u_tl(t0, arg0); 1463 tcg_gen_ext32u_tl(t1, arg1); 1464 } 1465 gen_op_cmp(t0, t1, s, crf); 1466 } 1467 1468 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1469 { 1470 TCGv t0 = tcg_constant_tl(arg1); 1471 gen_op_cmp32(arg0, t0, s, crf); 1472 } 1473 1474 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1475 { 1476 if (NARROW_MODE(ctx)) { 1477 gen_op_cmpi32(reg, 0, 1, 0); 1478 } else { 1479 gen_op_cmpi(reg, 0, 1, 0); 1480 } 1481 } 1482 1483 /* cmprb - range comparison: isupper, isaplha, islower*/ 1484 static void gen_cmprb(DisasContext *ctx) 1485 { 1486 TCGv_i32 src1 = tcg_temp_new_i32(); 1487 TCGv_i32 src2 = tcg_temp_new_i32(); 1488 TCGv_i32 src2lo = tcg_temp_new_i32(); 1489 TCGv_i32 src2hi = tcg_temp_new_i32(); 1490 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1491 1492 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1493 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1494 1495 tcg_gen_andi_i32(src1, src1, 0xFF); 1496 tcg_gen_ext8u_i32(src2lo, src2); 1497 tcg_gen_shri_i32(src2, src2, 8); 1498 tcg_gen_ext8u_i32(src2hi, src2); 1499 1500 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1501 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1502 tcg_gen_and_i32(crf, src2lo, src2hi); 1503 1504 if (ctx->opcode & 0x00200000) { 1505 tcg_gen_shri_i32(src2, src2, 8); 1506 tcg_gen_ext8u_i32(src2lo, src2); 1507 tcg_gen_shri_i32(src2, src2, 8); 1508 tcg_gen_ext8u_i32(src2hi, src2); 1509 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1510 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1511 tcg_gen_and_i32(src2lo, src2lo, src2hi); 1512 tcg_gen_or_i32(crf, crf, src2lo); 1513 } 1514 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1515 } 1516 1517 #if defined(TARGET_PPC64) 1518 /* cmpeqb */ 1519 static void gen_cmpeqb(DisasContext *ctx) 1520 { 1521 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1522 cpu_gpr[rB(ctx->opcode)]); 1523 } 1524 #endif 1525 1526 /* isel (PowerPC 2.03 specification) */ 1527 static void gen_isel(DisasContext *ctx) 1528 { 1529 uint32_t bi = rC(ctx->opcode); 1530 uint32_t mask = 0x08 >> (bi & 0x03); 1531 TCGv t0 = tcg_temp_new(); 1532 TCGv zr; 1533 1534 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1535 tcg_gen_andi_tl(t0, t0, mask); 1536 1537 zr = tcg_constant_tl(0); 1538 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1539 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1540 cpu_gpr[rB(ctx->opcode)]); 1541 } 1542 1543 /* cmpb: PowerPC 2.05 specification */ 1544 static void gen_cmpb(DisasContext *ctx) 1545 { 1546 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1547 cpu_gpr[rB(ctx->opcode)]); 1548 } 1549 1550 /*** Integer arithmetic ***/ 1551 1552 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1553 TCGv arg1, TCGv arg2, int sub) 1554 { 1555 TCGv t0 = tcg_temp_new(); 1556 1557 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1558 tcg_gen_xor_tl(t0, arg1, arg2); 1559 if (sub) { 1560 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1561 } else { 1562 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1563 } 1564 if (NARROW_MODE(ctx)) { 1565 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1566 if (is_isa300(ctx)) { 1567 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1568 } 1569 } else { 1570 if (is_isa300(ctx)) { 1571 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1572 } 1573 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1574 } 1575 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1576 } 1577 1578 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1579 TCGv res, TCGv arg0, TCGv arg1, 1580 TCGv ca32, int sub) 1581 { 1582 TCGv t0; 1583 1584 if (!is_isa300(ctx)) { 1585 return; 1586 } 1587 1588 t0 = tcg_temp_new(); 1589 if (sub) { 1590 tcg_gen_eqv_tl(t0, arg0, arg1); 1591 } else { 1592 tcg_gen_xor_tl(t0, arg0, arg1); 1593 } 1594 tcg_gen_xor_tl(t0, t0, res); 1595 tcg_gen_extract_tl(ca32, t0, 32, 1); 1596 } 1597 1598 /* Common add function */ 1599 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1600 TCGv arg2, TCGv ca, TCGv ca32, 1601 bool add_ca, bool compute_ca, 1602 bool compute_ov, bool compute_rc0) 1603 { 1604 TCGv t0 = ret; 1605 1606 if (compute_ca || compute_ov) { 1607 t0 = tcg_temp_new(); 1608 } 1609 1610 if (compute_ca) { 1611 if (NARROW_MODE(ctx)) { 1612 /* 1613 * Caution: a non-obvious corner case of the spec is that 1614 * we must produce the *entire* 64-bit addition, but 1615 * produce the carry into bit 32. 1616 */ 1617 TCGv t1 = tcg_temp_new(); 1618 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1619 tcg_gen_add_tl(t0, arg1, arg2); 1620 if (add_ca) { 1621 tcg_gen_add_tl(t0, t0, ca); 1622 } 1623 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1624 tcg_gen_extract_tl(ca, ca, 32, 1); 1625 if (is_isa300(ctx)) { 1626 tcg_gen_mov_tl(ca32, ca); 1627 } 1628 } else { 1629 TCGv zero = tcg_constant_tl(0); 1630 if (add_ca) { 1631 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1632 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1633 } else { 1634 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1635 } 1636 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1637 } 1638 } else { 1639 tcg_gen_add_tl(t0, arg1, arg2); 1640 if (add_ca) { 1641 tcg_gen_add_tl(t0, t0, ca); 1642 } 1643 } 1644 1645 if (compute_ov) { 1646 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1647 } 1648 if (unlikely(compute_rc0)) { 1649 gen_set_Rc0(ctx, t0); 1650 } 1651 1652 if (t0 != ret) { 1653 tcg_gen_mov_tl(ret, t0); 1654 } 1655 } 1656 /* Add functions with two operands */ 1657 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1658 static void glue(gen_, name)(DisasContext *ctx) \ 1659 { \ 1660 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1661 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1662 ca, glue(ca, 32), \ 1663 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1664 } 1665 /* Add functions with one operand and one immediate */ 1666 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1667 add_ca, compute_ca, compute_ov) \ 1668 static void glue(gen_, name)(DisasContext *ctx) \ 1669 { \ 1670 TCGv t0 = tcg_constant_tl(const_val); \ 1671 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1672 cpu_gpr[rA(ctx->opcode)], t0, \ 1673 ca, glue(ca, 32), \ 1674 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1675 } 1676 1677 /* add add. addo addo. */ 1678 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 1679 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1680 /* addc addc. addco addco. */ 1681 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 1682 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1683 /* adde adde. addeo addeo. */ 1684 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 1685 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1686 /* addme addme. addmeo addmeo. */ 1687 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 1688 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 1689 /* addex */ 1690 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1691 /* addze addze. addzeo addzeo.*/ 1692 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 1693 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1694 /* addic addic.*/ 1695 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1696 { 1697 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1698 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1699 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1700 } 1701 1702 static void gen_addic(DisasContext *ctx) 1703 { 1704 gen_op_addic(ctx, 0); 1705 } 1706 1707 static void gen_addic_(DisasContext *ctx) 1708 { 1709 gen_op_addic(ctx, 1); 1710 } 1711 1712 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1713 TCGv arg2, int sign, int compute_ov) 1714 { 1715 TCGv_i32 t0 = tcg_temp_new_i32(); 1716 TCGv_i32 t1 = tcg_temp_new_i32(); 1717 TCGv_i32 t2 = tcg_temp_new_i32(); 1718 TCGv_i32 t3 = tcg_temp_new_i32(); 1719 1720 tcg_gen_trunc_tl_i32(t0, arg1); 1721 tcg_gen_trunc_tl_i32(t1, arg2); 1722 if (sign) { 1723 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1724 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1725 tcg_gen_and_i32(t2, t2, t3); 1726 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1727 tcg_gen_or_i32(t2, t2, t3); 1728 tcg_gen_movi_i32(t3, 0); 1729 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1730 tcg_gen_div_i32(t3, t0, t1); 1731 tcg_gen_extu_i32_tl(ret, t3); 1732 } else { 1733 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1734 tcg_gen_movi_i32(t3, 0); 1735 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1736 tcg_gen_divu_i32(t3, t0, t1); 1737 tcg_gen_extu_i32_tl(ret, t3); 1738 } 1739 if (compute_ov) { 1740 tcg_gen_extu_i32_tl(cpu_ov, t2); 1741 if (is_isa300(ctx)) { 1742 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1743 } 1744 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1745 } 1746 1747 if (unlikely(Rc(ctx->opcode) != 0)) { 1748 gen_set_Rc0(ctx, ret); 1749 } 1750 } 1751 /* Div functions */ 1752 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1753 static void glue(gen_, name)(DisasContext *ctx) \ 1754 { \ 1755 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1756 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1757 sign, compute_ov); \ 1758 } 1759 /* divwu divwu. divwuo divwuo. */ 1760 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1761 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1762 /* divw divw. divwo divwo. */ 1763 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1764 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1765 1766 /* div[wd]eu[o][.] */ 1767 #define GEN_DIVE(name, hlpr, compute_ov) \ 1768 static void gen_##name(DisasContext *ctx) \ 1769 { \ 1770 TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1771 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1772 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1773 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1774 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1775 } \ 1776 } 1777 1778 GEN_DIVE(divweu, divweu, 0); 1779 GEN_DIVE(divweuo, divweu, 1); 1780 GEN_DIVE(divwe, divwe, 0); 1781 GEN_DIVE(divweo, divwe, 1); 1782 1783 #if defined(TARGET_PPC64) 1784 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1785 TCGv arg2, int sign, int compute_ov) 1786 { 1787 TCGv_i64 t0 = tcg_temp_new_i64(); 1788 TCGv_i64 t1 = tcg_temp_new_i64(); 1789 TCGv_i64 t2 = tcg_temp_new_i64(); 1790 TCGv_i64 t3 = tcg_temp_new_i64(); 1791 1792 tcg_gen_mov_i64(t0, arg1); 1793 tcg_gen_mov_i64(t1, arg2); 1794 if (sign) { 1795 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1796 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1797 tcg_gen_and_i64(t2, t2, t3); 1798 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1799 tcg_gen_or_i64(t2, t2, t3); 1800 tcg_gen_movi_i64(t3, 0); 1801 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1802 tcg_gen_div_i64(ret, t0, t1); 1803 } else { 1804 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1805 tcg_gen_movi_i64(t3, 0); 1806 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1807 tcg_gen_divu_i64(ret, t0, t1); 1808 } 1809 if (compute_ov) { 1810 tcg_gen_mov_tl(cpu_ov, t2); 1811 if (is_isa300(ctx)) { 1812 tcg_gen_mov_tl(cpu_ov32, t2); 1813 } 1814 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1815 } 1816 1817 if (unlikely(Rc(ctx->opcode) != 0)) { 1818 gen_set_Rc0(ctx, ret); 1819 } 1820 } 1821 1822 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1823 static void glue(gen_, name)(DisasContext *ctx) \ 1824 { \ 1825 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1826 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1827 sign, compute_ov); \ 1828 } 1829 /* divdu divdu. divduo divduo. */ 1830 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1831 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1832 /* divd divd. divdo divdo. */ 1833 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1834 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1835 1836 GEN_DIVE(divdeu, divdeu, 0); 1837 GEN_DIVE(divdeuo, divdeu, 1); 1838 GEN_DIVE(divde, divde, 0); 1839 GEN_DIVE(divdeo, divde, 1); 1840 #endif 1841 1842 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1843 TCGv arg2, int sign) 1844 { 1845 TCGv_i32 t0 = tcg_temp_new_i32(); 1846 TCGv_i32 t1 = tcg_temp_new_i32(); 1847 1848 tcg_gen_trunc_tl_i32(t0, arg1); 1849 tcg_gen_trunc_tl_i32(t1, arg2); 1850 if (sign) { 1851 TCGv_i32 t2 = tcg_temp_new_i32(); 1852 TCGv_i32 t3 = tcg_temp_new_i32(); 1853 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1854 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1855 tcg_gen_and_i32(t2, t2, t3); 1856 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1857 tcg_gen_or_i32(t2, t2, t3); 1858 tcg_gen_movi_i32(t3, 0); 1859 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1860 tcg_gen_rem_i32(t3, t0, t1); 1861 tcg_gen_ext_i32_tl(ret, t3); 1862 } else { 1863 TCGv_i32 t2 = tcg_constant_i32(1); 1864 TCGv_i32 t3 = tcg_constant_i32(0); 1865 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1866 tcg_gen_remu_i32(t0, t0, t1); 1867 tcg_gen_extu_i32_tl(ret, t0); 1868 } 1869 } 1870 1871 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1872 static void glue(gen_, name)(DisasContext *ctx) \ 1873 { \ 1874 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1875 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1876 sign); \ 1877 } 1878 1879 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1880 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1881 1882 #if defined(TARGET_PPC64) 1883 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1884 TCGv arg2, int sign) 1885 { 1886 TCGv_i64 t0 = tcg_temp_new_i64(); 1887 TCGv_i64 t1 = tcg_temp_new_i64(); 1888 1889 tcg_gen_mov_i64(t0, arg1); 1890 tcg_gen_mov_i64(t1, arg2); 1891 if (sign) { 1892 TCGv_i64 t2 = tcg_temp_new_i64(); 1893 TCGv_i64 t3 = tcg_temp_new_i64(); 1894 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1895 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1896 tcg_gen_and_i64(t2, t2, t3); 1897 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1898 tcg_gen_or_i64(t2, t2, t3); 1899 tcg_gen_movi_i64(t3, 0); 1900 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1901 tcg_gen_rem_i64(ret, t0, t1); 1902 } else { 1903 TCGv_i64 t2 = tcg_constant_i64(1); 1904 TCGv_i64 t3 = tcg_constant_i64(0); 1905 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1906 tcg_gen_remu_i64(ret, t0, t1); 1907 } 1908 } 1909 1910 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1911 static void glue(gen_, name)(DisasContext *ctx) \ 1912 { \ 1913 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1914 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1915 sign); \ 1916 } 1917 1918 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1919 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1920 #endif 1921 1922 /* mulhw mulhw. */ 1923 static void gen_mulhw(DisasContext *ctx) 1924 { 1925 TCGv_i32 t0 = tcg_temp_new_i32(); 1926 TCGv_i32 t1 = tcg_temp_new_i32(); 1927 1928 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1929 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1930 tcg_gen_muls2_i32(t0, t1, t0, t1); 1931 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1932 if (unlikely(Rc(ctx->opcode) != 0)) { 1933 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1934 } 1935 } 1936 1937 /* mulhwu mulhwu. */ 1938 static void gen_mulhwu(DisasContext *ctx) 1939 { 1940 TCGv_i32 t0 = tcg_temp_new_i32(); 1941 TCGv_i32 t1 = tcg_temp_new_i32(); 1942 1943 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1944 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1945 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1946 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1947 if (unlikely(Rc(ctx->opcode) != 0)) { 1948 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1949 } 1950 } 1951 1952 /* mullw mullw. */ 1953 static void gen_mullw(DisasContext *ctx) 1954 { 1955 #if defined(TARGET_PPC64) 1956 TCGv_i64 t0, t1; 1957 t0 = tcg_temp_new_i64(); 1958 t1 = tcg_temp_new_i64(); 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1960 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1961 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1962 #else 1963 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1964 cpu_gpr[rB(ctx->opcode)]); 1965 #endif 1966 if (unlikely(Rc(ctx->opcode) != 0)) { 1967 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1968 } 1969 } 1970 1971 /* mullwo mullwo. */ 1972 static void gen_mullwo(DisasContext *ctx) 1973 { 1974 TCGv_i32 t0 = tcg_temp_new_i32(); 1975 TCGv_i32 t1 = tcg_temp_new_i32(); 1976 1977 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1978 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1979 tcg_gen_muls2_i32(t0, t1, t0, t1); 1980 #if defined(TARGET_PPC64) 1981 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1982 #else 1983 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1984 #endif 1985 1986 tcg_gen_sari_i32(t0, t0, 31); 1987 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1988 tcg_gen_extu_i32_tl(cpu_ov, t0); 1989 if (is_isa300(ctx)) { 1990 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1991 } 1992 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1993 1994 if (unlikely(Rc(ctx->opcode) != 0)) { 1995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1996 } 1997 } 1998 1999 /* mulli */ 2000 static void gen_mulli(DisasContext *ctx) 2001 { 2002 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2003 SIMM(ctx->opcode)); 2004 } 2005 2006 #if defined(TARGET_PPC64) 2007 /* mulhd mulhd. */ 2008 static void gen_mulhd(DisasContext *ctx) 2009 { 2010 TCGv lo = tcg_temp_new(); 2011 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2012 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2013 if (unlikely(Rc(ctx->opcode) != 0)) { 2014 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2015 } 2016 } 2017 2018 /* mulhdu mulhdu. */ 2019 static void gen_mulhdu(DisasContext *ctx) 2020 { 2021 TCGv lo = tcg_temp_new(); 2022 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2023 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2024 if (unlikely(Rc(ctx->opcode) != 0)) { 2025 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2026 } 2027 } 2028 2029 /* mulld mulld. */ 2030 static void gen_mulld(DisasContext *ctx) 2031 { 2032 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2033 cpu_gpr[rB(ctx->opcode)]); 2034 if (unlikely(Rc(ctx->opcode) != 0)) { 2035 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2036 } 2037 } 2038 2039 /* mulldo mulldo. */ 2040 static void gen_mulldo(DisasContext *ctx) 2041 { 2042 TCGv_i64 t0 = tcg_temp_new_i64(); 2043 TCGv_i64 t1 = tcg_temp_new_i64(); 2044 2045 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2046 cpu_gpr[rB(ctx->opcode)]); 2047 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2048 2049 tcg_gen_sari_i64(t0, t0, 63); 2050 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 2051 if (is_isa300(ctx)) { 2052 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 2053 } 2054 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2055 2056 if (unlikely(Rc(ctx->opcode) != 0)) { 2057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2058 } 2059 } 2060 #endif 2061 2062 /* Common subf function */ 2063 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2064 TCGv arg2, bool add_ca, bool compute_ca, 2065 bool compute_ov, bool compute_rc0) 2066 { 2067 TCGv t0 = ret; 2068 2069 if (compute_ca || compute_ov) { 2070 t0 = tcg_temp_new(); 2071 } 2072 2073 if (compute_ca) { 2074 /* dest = ~arg1 + arg2 [+ ca]. */ 2075 if (NARROW_MODE(ctx)) { 2076 /* 2077 * Caution: a non-obvious corner case of the spec is that 2078 * we must produce the *entire* 64-bit addition, but 2079 * produce the carry into bit 32. 2080 */ 2081 TCGv inv1 = tcg_temp_new(); 2082 TCGv t1 = tcg_temp_new(); 2083 tcg_gen_not_tl(inv1, arg1); 2084 if (add_ca) { 2085 tcg_gen_add_tl(t0, arg2, cpu_ca); 2086 } else { 2087 tcg_gen_addi_tl(t0, arg2, 1); 2088 } 2089 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2090 tcg_gen_add_tl(t0, t0, inv1); 2091 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2092 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 2093 if (is_isa300(ctx)) { 2094 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2095 } 2096 } else if (add_ca) { 2097 TCGv zero, inv1 = tcg_temp_new(); 2098 tcg_gen_not_tl(inv1, arg1); 2099 zero = tcg_constant_tl(0); 2100 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2101 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 2102 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2103 } else { 2104 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2105 tcg_gen_sub_tl(t0, arg2, arg1); 2106 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2107 } 2108 } else if (add_ca) { 2109 /* 2110 * Since we're ignoring carry-out, we can simplify the 2111 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2112 */ 2113 tcg_gen_sub_tl(t0, arg2, arg1); 2114 tcg_gen_add_tl(t0, t0, cpu_ca); 2115 tcg_gen_subi_tl(t0, t0, 1); 2116 } else { 2117 tcg_gen_sub_tl(t0, arg2, arg1); 2118 } 2119 2120 if (compute_ov) { 2121 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2122 } 2123 if (unlikely(compute_rc0)) { 2124 gen_set_Rc0(ctx, t0); 2125 } 2126 2127 if (t0 != ret) { 2128 tcg_gen_mov_tl(ret, t0); 2129 } 2130 } 2131 /* Sub functions with Two operands functions */ 2132 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2133 static void glue(gen_, name)(DisasContext *ctx) \ 2134 { \ 2135 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2136 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2137 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2138 } 2139 /* Sub functions with one operand and one immediate */ 2140 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2141 add_ca, compute_ca, compute_ov) \ 2142 static void glue(gen_, name)(DisasContext *ctx) \ 2143 { \ 2144 TCGv t0 = tcg_constant_tl(const_val); \ 2145 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2146 cpu_gpr[rA(ctx->opcode)], t0, \ 2147 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2148 } 2149 /* subf subf. subfo subfo. */ 2150 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2151 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2152 /* subfc subfc. subfco subfco. */ 2153 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2154 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2155 /* subfe subfe. subfeo subfo. */ 2156 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2157 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2158 /* subfme subfme. subfmeo subfmeo. */ 2159 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2160 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2161 /* subfze subfze. subfzeo subfzeo.*/ 2162 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2163 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2164 2165 /* subfic */ 2166 static void gen_subfic(DisasContext *ctx) 2167 { 2168 TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2169 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2170 c, 0, 1, 0, 0); 2171 } 2172 2173 /* neg neg. nego nego. */ 2174 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2175 { 2176 TCGv zero = tcg_constant_tl(0); 2177 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2178 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2179 } 2180 2181 static void gen_neg(DisasContext *ctx) 2182 { 2183 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2184 if (unlikely(Rc(ctx->opcode))) { 2185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2186 } 2187 } 2188 2189 static void gen_nego(DisasContext *ctx) 2190 { 2191 gen_op_arith_neg(ctx, 1); 2192 } 2193 2194 /*** Integer logical ***/ 2195 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2196 static void glue(gen_, name)(DisasContext *ctx) \ 2197 { \ 2198 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2199 cpu_gpr[rB(ctx->opcode)]); \ 2200 if (unlikely(Rc(ctx->opcode) != 0)) \ 2201 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2202 } 2203 2204 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2205 static void glue(gen_, name)(DisasContext *ctx) \ 2206 { \ 2207 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2208 if (unlikely(Rc(ctx->opcode) != 0)) \ 2209 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2210 } 2211 2212 /* and & and. */ 2213 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2214 /* andc & andc. */ 2215 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2216 2217 /* andi. */ 2218 static void gen_andi_(DisasContext *ctx) 2219 { 2220 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2221 UIMM(ctx->opcode)); 2222 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2223 } 2224 2225 /* andis. */ 2226 static void gen_andis_(DisasContext *ctx) 2227 { 2228 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2229 UIMM(ctx->opcode) << 16); 2230 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2231 } 2232 2233 /* cntlzw */ 2234 static void gen_cntlzw(DisasContext *ctx) 2235 { 2236 TCGv_i32 t = tcg_temp_new_i32(); 2237 2238 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2239 tcg_gen_clzi_i32(t, t, 32); 2240 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2241 2242 if (unlikely(Rc(ctx->opcode) != 0)) { 2243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2244 } 2245 } 2246 2247 /* cnttzw */ 2248 static void gen_cnttzw(DisasContext *ctx) 2249 { 2250 TCGv_i32 t = tcg_temp_new_i32(); 2251 2252 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 2253 tcg_gen_ctzi_i32(t, t, 32); 2254 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 2255 2256 if (unlikely(Rc(ctx->opcode) != 0)) { 2257 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2258 } 2259 } 2260 2261 /* eqv & eqv. */ 2262 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2263 /* extsb & extsb. */ 2264 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2265 /* extsh & extsh. */ 2266 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2267 /* nand & nand. */ 2268 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2269 /* nor & nor. */ 2270 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2271 2272 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2273 static void gen_pause(DisasContext *ctx) 2274 { 2275 TCGv_i32 t0 = tcg_constant_i32(0); 2276 tcg_gen_st_i32(t0, cpu_env, 2277 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2278 2279 /* Stop translation, this gives other CPUs a chance to run */ 2280 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2281 } 2282 #endif /* defined(TARGET_PPC64) */ 2283 2284 /* or & or. */ 2285 static void gen_or(DisasContext *ctx) 2286 { 2287 int rs, ra, rb; 2288 2289 rs = rS(ctx->opcode); 2290 ra = rA(ctx->opcode); 2291 rb = rB(ctx->opcode); 2292 /* Optimisation for mr. ri case */ 2293 if (rs != ra || rs != rb) { 2294 if (rs != rb) { 2295 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2296 } else { 2297 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2298 } 2299 if (unlikely(Rc(ctx->opcode) != 0)) { 2300 gen_set_Rc0(ctx, cpu_gpr[ra]); 2301 } 2302 } else if (unlikely(Rc(ctx->opcode) != 0)) { 2303 gen_set_Rc0(ctx, cpu_gpr[rs]); 2304 #if defined(TARGET_PPC64) 2305 } else if (rs != 0) { /* 0 is nop */ 2306 int prio = 0; 2307 2308 switch (rs) { 2309 case 1: 2310 /* Set process priority to low */ 2311 prio = 2; 2312 break; 2313 case 6: 2314 /* Set process priority to medium-low */ 2315 prio = 3; 2316 break; 2317 case 2: 2318 /* Set process priority to normal */ 2319 prio = 4; 2320 break; 2321 #if !defined(CONFIG_USER_ONLY) 2322 case 31: 2323 if (!ctx->pr) { 2324 /* Set process priority to very low */ 2325 prio = 1; 2326 } 2327 break; 2328 case 5: 2329 if (!ctx->pr) { 2330 /* Set process priority to medium-hight */ 2331 prio = 5; 2332 } 2333 break; 2334 case 3: 2335 if (!ctx->pr) { 2336 /* Set process priority to high */ 2337 prio = 6; 2338 } 2339 break; 2340 case 7: 2341 if (ctx->hv && !ctx->pr) { 2342 /* Set process priority to very high */ 2343 prio = 7; 2344 } 2345 break; 2346 #endif 2347 default: 2348 break; 2349 } 2350 if (prio) { 2351 TCGv t0 = tcg_temp_new(); 2352 gen_load_spr(t0, SPR_PPR); 2353 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2354 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2355 gen_store_spr(SPR_PPR, t0); 2356 } 2357 #if !defined(CONFIG_USER_ONLY) 2358 /* 2359 * Pause out of TCG otherwise spin loops with smt_low eat too 2360 * much CPU and the kernel hangs. This applies to all 2361 * encodings other than no-op, e.g., miso(rs=26), yield(27), 2362 * mdoio(29), mdoom(30), and all currently undefined. 2363 */ 2364 gen_pause(ctx); 2365 #endif 2366 #endif 2367 } 2368 } 2369 /* orc & orc. */ 2370 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2371 2372 /* xor & xor. */ 2373 static void gen_xor(DisasContext *ctx) 2374 { 2375 /* Optimisation for "set to zero" case */ 2376 if (rS(ctx->opcode) != rB(ctx->opcode)) { 2377 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2378 cpu_gpr[rB(ctx->opcode)]); 2379 } else { 2380 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2381 } 2382 if (unlikely(Rc(ctx->opcode) != 0)) { 2383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2384 } 2385 } 2386 2387 /* ori */ 2388 static void gen_ori(DisasContext *ctx) 2389 { 2390 target_ulong uimm = UIMM(ctx->opcode); 2391 2392 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2393 return; 2394 } 2395 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2396 } 2397 2398 /* oris */ 2399 static void gen_oris(DisasContext *ctx) 2400 { 2401 target_ulong uimm = UIMM(ctx->opcode); 2402 2403 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2404 /* NOP */ 2405 return; 2406 } 2407 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2408 uimm << 16); 2409 } 2410 2411 /* xori */ 2412 static void gen_xori(DisasContext *ctx) 2413 { 2414 target_ulong uimm = UIMM(ctx->opcode); 2415 2416 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2417 /* NOP */ 2418 return; 2419 } 2420 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2421 } 2422 2423 /* xoris */ 2424 static void gen_xoris(DisasContext *ctx) 2425 { 2426 target_ulong uimm = UIMM(ctx->opcode); 2427 2428 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2429 /* NOP */ 2430 return; 2431 } 2432 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2433 uimm << 16); 2434 } 2435 2436 /* popcntb : PowerPC 2.03 specification */ 2437 static void gen_popcntb(DisasContext *ctx) 2438 { 2439 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2440 } 2441 2442 static void gen_popcntw(DisasContext *ctx) 2443 { 2444 #if defined(TARGET_PPC64) 2445 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2446 #else 2447 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2448 #endif 2449 } 2450 2451 #if defined(TARGET_PPC64) 2452 /* popcntd: PowerPC 2.06 specification */ 2453 static void gen_popcntd(DisasContext *ctx) 2454 { 2455 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2456 } 2457 #endif 2458 2459 /* prtyw: PowerPC 2.05 specification */ 2460 static void gen_prtyw(DisasContext *ctx) 2461 { 2462 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2463 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2464 TCGv t0 = tcg_temp_new(); 2465 tcg_gen_shri_tl(t0, rs, 16); 2466 tcg_gen_xor_tl(ra, rs, t0); 2467 tcg_gen_shri_tl(t0, ra, 8); 2468 tcg_gen_xor_tl(ra, ra, t0); 2469 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2470 } 2471 2472 #if defined(TARGET_PPC64) 2473 /* prtyd: PowerPC 2.05 specification */ 2474 static void gen_prtyd(DisasContext *ctx) 2475 { 2476 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2477 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2478 TCGv t0 = tcg_temp_new(); 2479 tcg_gen_shri_tl(t0, rs, 32); 2480 tcg_gen_xor_tl(ra, rs, t0); 2481 tcg_gen_shri_tl(t0, ra, 16); 2482 tcg_gen_xor_tl(ra, ra, t0); 2483 tcg_gen_shri_tl(t0, ra, 8); 2484 tcg_gen_xor_tl(ra, ra, t0); 2485 tcg_gen_andi_tl(ra, ra, 1); 2486 } 2487 #endif 2488 2489 #if defined(TARGET_PPC64) 2490 /* bpermd */ 2491 static void gen_bpermd(DisasContext *ctx) 2492 { 2493 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2494 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2495 } 2496 #endif 2497 2498 #if defined(TARGET_PPC64) 2499 /* extsw & extsw. */ 2500 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2501 2502 /* cntlzd */ 2503 static void gen_cntlzd(DisasContext *ctx) 2504 { 2505 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2506 if (unlikely(Rc(ctx->opcode) != 0)) { 2507 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2508 } 2509 } 2510 2511 /* cnttzd */ 2512 static void gen_cnttzd(DisasContext *ctx) 2513 { 2514 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2515 if (unlikely(Rc(ctx->opcode) != 0)) { 2516 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2517 } 2518 } 2519 2520 /* darn */ 2521 static void gen_darn(DisasContext *ctx) 2522 { 2523 int l = L(ctx->opcode); 2524 2525 if (l > 2) { 2526 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 2527 } else { 2528 translator_io_start(&ctx->base); 2529 if (l == 0) { 2530 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 2531 } else { 2532 /* Return 64-bit random for both CRN and RRN */ 2533 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 2534 } 2535 } 2536 } 2537 #endif 2538 2539 /*** Integer rotate ***/ 2540 2541 /* rlwimi & rlwimi. */ 2542 static void gen_rlwimi(DisasContext *ctx) 2543 { 2544 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2545 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2546 uint32_t sh = SH(ctx->opcode); 2547 uint32_t mb = MB(ctx->opcode); 2548 uint32_t me = ME(ctx->opcode); 2549 2550 if (sh == (31 - me) && mb <= me) { 2551 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2552 } else { 2553 target_ulong mask; 2554 bool mask_in_32b = true; 2555 TCGv t1; 2556 2557 #if defined(TARGET_PPC64) 2558 mb += 32; 2559 me += 32; 2560 #endif 2561 mask = MASK(mb, me); 2562 2563 #if defined(TARGET_PPC64) 2564 if (mask > 0xffffffffu) { 2565 mask_in_32b = false; 2566 } 2567 #endif 2568 t1 = tcg_temp_new(); 2569 if (mask_in_32b) { 2570 TCGv_i32 t0 = tcg_temp_new_i32(); 2571 tcg_gen_trunc_tl_i32(t0, t_rs); 2572 tcg_gen_rotli_i32(t0, t0, sh); 2573 tcg_gen_extu_i32_tl(t1, t0); 2574 } else { 2575 #if defined(TARGET_PPC64) 2576 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2577 tcg_gen_rotli_i64(t1, t1, sh); 2578 #else 2579 g_assert_not_reached(); 2580 #endif 2581 } 2582 2583 tcg_gen_andi_tl(t1, t1, mask); 2584 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2585 tcg_gen_or_tl(t_ra, t_ra, t1); 2586 } 2587 if (unlikely(Rc(ctx->opcode) != 0)) { 2588 gen_set_Rc0(ctx, t_ra); 2589 } 2590 } 2591 2592 /* rlwinm & rlwinm. */ 2593 static void gen_rlwinm(DisasContext *ctx) 2594 { 2595 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2596 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2597 int sh = SH(ctx->opcode); 2598 int mb = MB(ctx->opcode); 2599 int me = ME(ctx->opcode); 2600 int len = me - mb + 1; 2601 int rsh = (32 - sh) & 31; 2602 2603 if (sh != 0 && len > 0 && me == (31 - sh)) { 2604 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2605 } else if (me == 31 && rsh + len <= 32) { 2606 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2607 } else { 2608 target_ulong mask; 2609 bool mask_in_32b = true; 2610 #if defined(TARGET_PPC64) 2611 mb += 32; 2612 me += 32; 2613 #endif 2614 mask = MASK(mb, me); 2615 #if defined(TARGET_PPC64) 2616 if (mask > 0xffffffffu) { 2617 mask_in_32b = false; 2618 } 2619 #endif 2620 if (mask_in_32b) { 2621 if (sh == 0) { 2622 tcg_gen_andi_tl(t_ra, t_rs, mask); 2623 } else { 2624 TCGv_i32 t0 = tcg_temp_new_i32(); 2625 tcg_gen_trunc_tl_i32(t0, t_rs); 2626 tcg_gen_rotli_i32(t0, t0, sh); 2627 tcg_gen_andi_i32(t0, t0, mask); 2628 tcg_gen_extu_i32_tl(t_ra, t0); 2629 } 2630 } else { 2631 #if defined(TARGET_PPC64) 2632 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2633 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2634 tcg_gen_andi_i64(t_ra, t_ra, mask); 2635 #else 2636 g_assert_not_reached(); 2637 #endif 2638 } 2639 } 2640 if (unlikely(Rc(ctx->opcode) != 0)) { 2641 gen_set_Rc0(ctx, t_ra); 2642 } 2643 } 2644 2645 /* rlwnm & rlwnm. */ 2646 static void gen_rlwnm(DisasContext *ctx) 2647 { 2648 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2649 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2650 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2651 uint32_t mb = MB(ctx->opcode); 2652 uint32_t me = ME(ctx->opcode); 2653 target_ulong mask; 2654 bool mask_in_32b = true; 2655 2656 #if defined(TARGET_PPC64) 2657 mb += 32; 2658 me += 32; 2659 #endif 2660 mask = MASK(mb, me); 2661 2662 #if defined(TARGET_PPC64) 2663 if (mask > 0xffffffffu) { 2664 mask_in_32b = false; 2665 } 2666 #endif 2667 if (mask_in_32b) { 2668 TCGv_i32 t0 = tcg_temp_new_i32(); 2669 TCGv_i32 t1 = tcg_temp_new_i32(); 2670 tcg_gen_trunc_tl_i32(t0, t_rb); 2671 tcg_gen_trunc_tl_i32(t1, t_rs); 2672 tcg_gen_andi_i32(t0, t0, 0x1f); 2673 tcg_gen_rotl_i32(t1, t1, t0); 2674 tcg_gen_extu_i32_tl(t_ra, t1); 2675 } else { 2676 #if defined(TARGET_PPC64) 2677 TCGv_i64 t0 = tcg_temp_new_i64(); 2678 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2679 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2680 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2681 #else 2682 g_assert_not_reached(); 2683 #endif 2684 } 2685 2686 tcg_gen_andi_tl(t_ra, t_ra, mask); 2687 2688 if (unlikely(Rc(ctx->opcode) != 0)) { 2689 gen_set_Rc0(ctx, t_ra); 2690 } 2691 } 2692 2693 #if defined(TARGET_PPC64) 2694 #define GEN_PPC64_R2(name, opc1, opc2) \ 2695 static void glue(gen_, name##0)(DisasContext *ctx) \ 2696 { \ 2697 gen_##name(ctx, 0); \ 2698 } \ 2699 \ 2700 static void glue(gen_, name##1)(DisasContext *ctx) \ 2701 { \ 2702 gen_##name(ctx, 1); \ 2703 } 2704 #define GEN_PPC64_R4(name, opc1, opc2) \ 2705 static void glue(gen_, name##0)(DisasContext *ctx) \ 2706 { \ 2707 gen_##name(ctx, 0, 0); \ 2708 } \ 2709 \ 2710 static void glue(gen_, name##1)(DisasContext *ctx) \ 2711 { \ 2712 gen_##name(ctx, 0, 1); \ 2713 } \ 2714 \ 2715 static void glue(gen_, name##2)(DisasContext *ctx) \ 2716 { \ 2717 gen_##name(ctx, 1, 0); \ 2718 } \ 2719 \ 2720 static void glue(gen_, name##3)(DisasContext *ctx) \ 2721 { \ 2722 gen_##name(ctx, 1, 1); \ 2723 } 2724 2725 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2726 { 2727 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2728 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2729 int len = me - mb + 1; 2730 int rsh = (64 - sh) & 63; 2731 2732 if (sh != 0 && len > 0 && me == (63 - sh)) { 2733 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2734 } else if (me == 63 && rsh + len <= 64) { 2735 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2736 } else { 2737 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2738 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2739 } 2740 if (unlikely(Rc(ctx->opcode) != 0)) { 2741 gen_set_Rc0(ctx, t_ra); 2742 } 2743 } 2744 2745 /* rldicl - rldicl. */ 2746 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2747 { 2748 uint32_t sh, mb; 2749 2750 sh = SH(ctx->opcode) | (shn << 5); 2751 mb = MB(ctx->opcode) | (mbn << 5); 2752 gen_rldinm(ctx, mb, 63, sh); 2753 } 2754 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2755 2756 /* rldicr - rldicr. */ 2757 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2758 { 2759 uint32_t sh, me; 2760 2761 sh = SH(ctx->opcode) | (shn << 5); 2762 me = MB(ctx->opcode) | (men << 5); 2763 gen_rldinm(ctx, 0, me, sh); 2764 } 2765 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2766 2767 /* rldic - rldic. */ 2768 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2769 { 2770 uint32_t sh, mb; 2771 2772 sh = SH(ctx->opcode) | (shn << 5); 2773 mb = MB(ctx->opcode) | (mbn << 5); 2774 gen_rldinm(ctx, mb, 63 - sh, sh); 2775 } 2776 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2777 2778 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2779 { 2780 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2781 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2782 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2783 TCGv t0; 2784 2785 t0 = tcg_temp_new(); 2786 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2787 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2788 2789 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2790 if (unlikely(Rc(ctx->opcode) != 0)) { 2791 gen_set_Rc0(ctx, t_ra); 2792 } 2793 } 2794 2795 /* rldcl - rldcl. */ 2796 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2797 { 2798 uint32_t mb; 2799 2800 mb = MB(ctx->opcode) | (mbn << 5); 2801 gen_rldnm(ctx, mb, 63); 2802 } 2803 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2804 2805 /* rldcr - rldcr. */ 2806 static inline void gen_rldcr(DisasContext *ctx, int men) 2807 { 2808 uint32_t me; 2809 2810 me = MB(ctx->opcode) | (men << 5); 2811 gen_rldnm(ctx, 0, me); 2812 } 2813 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2814 2815 /* rldimi - rldimi. */ 2816 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2817 { 2818 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2819 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2820 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2821 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2822 uint32_t me = 63 - sh; 2823 2824 if (mb <= me) { 2825 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2826 } else { 2827 target_ulong mask = MASK(mb, me); 2828 TCGv t1 = tcg_temp_new(); 2829 2830 tcg_gen_rotli_tl(t1, t_rs, sh); 2831 tcg_gen_andi_tl(t1, t1, mask); 2832 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2833 tcg_gen_or_tl(t_ra, t_ra, t1); 2834 } 2835 if (unlikely(Rc(ctx->opcode) != 0)) { 2836 gen_set_Rc0(ctx, t_ra); 2837 } 2838 } 2839 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2840 #endif 2841 2842 /*** Integer shift ***/ 2843 2844 /* slw & slw. */ 2845 static void gen_slw(DisasContext *ctx) 2846 { 2847 TCGv t0, t1; 2848 2849 t0 = tcg_temp_new(); 2850 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2851 #if defined(TARGET_PPC64) 2852 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2853 tcg_gen_sari_tl(t0, t0, 0x3f); 2854 #else 2855 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2856 tcg_gen_sari_tl(t0, t0, 0x1f); 2857 #endif 2858 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2859 t1 = tcg_temp_new(); 2860 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2861 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2862 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2863 if (unlikely(Rc(ctx->opcode) != 0)) { 2864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2865 } 2866 } 2867 2868 /* sraw & sraw. */ 2869 static void gen_sraw(DisasContext *ctx) 2870 { 2871 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2872 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2873 if (unlikely(Rc(ctx->opcode) != 0)) { 2874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2875 } 2876 } 2877 2878 /* srawi & srawi. */ 2879 static void gen_srawi(DisasContext *ctx) 2880 { 2881 int sh = SH(ctx->opcode); 2882 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2883 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2884 if (sh == 0) { 2885 tcg_gen_ext32s_tl(dst, src); 2886 tcg_gen_movi_tl(cpu_ca, 0); 2887 if (is_isa300(ctx)) { 2888 tcg_gen_movi_tl(cpu_ca32, 0); 2889 } 2890 } else { 2891 TCGv t0; 2892 tcg_gen_ext32s_tl(dst, src); 2893 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2894 t0 = tcg_temp_new(); 2895 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2896 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2897 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2898 if (is_isa300(ctx)) { 2899 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2900 } 2901 tcg_gen_sari_tl(dst, dst, sh); 2902 } 2903 if (unlikely(Rc(ctx->opcode) != 0)) { 2904 gen_set_Rc0(ctx, dst); 2905 } 2906 } 2907 2908 /* srw & srw. */ 2909 static void gen_srw(DisasContext *ctx) 2910 { 2911 TCGv t0, t1; 2912 2913 t0 = tcg_temp_new(); 2914 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2915 #if defined(TARGET_PPC64) 2916 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2917 tcg_gen_sari_tl(t0, t0, 0x3f); 2918 #else 2919 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2920 tcg_gen_sari_tl(t0, t0, 0x1f); 2921 #endif 2922 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2923 tcg_gen_ext32u_tl(t0, t0); 2924 t1 = tcg_temp_new(); 2925 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2926 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2927 if (unlikely(Rc(ctx->opcode) != 0)) { 2928 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2929 } 2930 } 2931 2932 #if defined(TARGET_PPC64) 2933 /* sld & sld. */ 2934 static void gen_sld(DisasContext *ctx) 2935 { 2936 TCGv t0, t1; 2937 2938 t0 = tcg_temp_new(); 2939 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2940 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2941 tcg_gen_sari_tl(t0, t0, 0x3f); 2942 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2943 t1 = tcg_temp_new(); 2944 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2945 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2946 if (unlikely(Rc(ctx->opcode) != 0)) { 2947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2948 } 2949 } 2950 2951 /* srad & srad. */ 2952 static void gen_srad(DisasContext *ctx) 2953 { 2954 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2955 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2956 if (unlikely(Rc(ctx->opcode) != 0)) { 2957 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2958 } 2959 } 2960 /* sradi & sradi. */ 2961 static inline void gen_sradi(DisasContext *ctx, int n) 2962 { 2963 int sh = SH(ctx->opcode) + (n << 5); 2964 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2965 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2966 if (sh == 0) { 2967 tcg_gen_mov_tl(dst, src); 2968 tcg_gen_movi_tl(cpu_ca, 0); 2969 if (is_isa300(ctx)) { 2970 tcg_gen_movi_tl(cpu_ca32, 0); 2971 } 2972 } else { 2973 TCGv t0; 2974 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2975 t0 = tcg_temp_new(); 2976 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2977 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2979 if (is_isa300(ctx)) { 2980 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2981 } 2982 tcg_gen_sari_tl(dst, src, sh); 2983 } 2984 if (unlikely(Rc(ctx->opcode) != 0)) { 2985 gen_set_Rc0(ctx, dst); 2986 } 2987 } 2988 2989 static void gen_sradi0(DisasContext *ctx) 2990 { 2991 gen_sradi(ctx, 0); 2992 } 2993 2994 static void gen_sradi1(DisasContext *ctx) 2995 { 2996 gen_sradi(ctx, 1); 2997 } 2998 2999 /* extswsli & extswsli. */ 3000 static inline void gen_extswsli(DisasContext *ctx, int n) 3001 { 3002 int sh = SH(ctx->opcode) + (n << 5); 3003 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3004 TCGv src = cpu_gpr[rS(ctx->opcode)]; 3005 3006 tcg_gen_ext32s_tl(dst, src); 3007 tcg_gen_shli_tl(dst, dst, sh); 3008 if (unlikely(Rc(ctx->opcode) != 0)) { 3009 gen_set_Rc0(ctx, dst); 3010 } 3011 } 3012 3013 static void gen_extswsli0(DisasContext *ctx) 3014 { 3015 gen_extswsli(ctx, 0); 3016 } 3017 3018 static void gen_extswsli1(DisasContext *ctx) 3019 { 3020 gen_extswsli(ctx, 1); 3021 } 3022 3023 /* srd & srd. */ 3024 static void gen_srd(DisasContext *ctx) 3025 { 3026 TCGv t0, t1; 3027 3028 t0 = tcg_temp_new(); 3029 /* AND rS with a mask that is 0 when rB >= 0x40 */ 3030 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3031 tcg_gen_sari_tl(t0, t0, 0x3f); 3032 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3033 t1 = tcg_temp_new(); 3034 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3035 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3036 if (unlikely(Rc(ctx->opcode) != 0)) { 3037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3038 } 3039 } 3040 #endif 3041 3042 /*** Addressing modes ***/ 3043 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3044 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3045 target_long maskl) 3046 { 3047 target_long simm = SIMM(ctx->opcode); 3048 3049 simm &= ~maskl; 3050 if (rA(ctx->opcode) == 0) { 3051 if (NARROW_MODE(ctx)) { 3052 simm = (uint32_t)simm; 3053 } 3054 tcg_gen_movi_tl(EA, simm); 3055 } else if (likely(simm != 0)) { 3056 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3057 if (NARROW_MODE(ctx)) { 3058 tcg_gen_ext32u_tl(EA, EA); 3059 } 3060 } else { 3061 if (NARROW_MODE(ctx)) { 3062 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3063 } else { 3064 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3065 } 3066 } 3067 } 3068 3069 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3070 { 3071 if (rA(ctx->opcode) == 0) { 3072 if (NARROW_MODE(ctx)) { 3073 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3074 } else { 3075 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3076 } 3077 } else { 3078 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3079 if (NARROW_MODE(ctx)) { 3080 tcg_gen_ext32u_tl(EA, EA); 3081 } 3082 } 3083 } 3084 3085 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3086 { 3087 if (rA(ctx->opcode) == 0) { 3088 tcg_gen_movi_tl(EA, 0); 3089 } else if (NARROW_MODE(ctx)) { 3090 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3091 } else { 3092 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3093 } 3094 } 3095 3096 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3097 target_long val) 3098 { 3099 tcg_gen_addi_tl(ret, arg1, val); 3100 if (NARROW_MODE(ctx)) { 3101 tcg_gen_ext32u_tl(ret, ret); 3102 } 3103 } 3104 3105 static inline void gen_align_no_le(DisasContext *ctx) 3106 { 3107 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3108 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3109 } 3110 3111 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3112 { 3113 TCGv ea = tcg_temp_new(); 3114 if (ra) { 3115 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3116 } else { 3117 tcg_gen_mov_tl(ea, displ); 3118 } 3119 if (NARROW_MODE(ctx)) { 3120 tcg_gen_ext32u_tl(ea, ea); 3121 } 3122 return ea; 3123 } 3124 3125 /*** Integer load ***/ 3126 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3127 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3128 3129 #define GEN_QEMU_LOAD_TL(ldop, op) \ 3130 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3131 TCGv val, \ 3132 TCGv addr) \ 3133 { \ 3134 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3135 } 3136 3137 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3138 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3139 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3140 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3141 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3142 3143 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3144 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3145 3146 #define GEN_QEMU_LOAD_64(ldop, op) \ 3147 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3148 TCGv_i64 val, \ 3149 TCGv addr) \ 3150 { \ 3151 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3152 } 3153 3154 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3155 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3156 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3157 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3158 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3159 3160 #if defined(TARGET_PPC64) 3161 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3162 #endif 3163 3164 #define GEN_QEMU_STORE_TL(stop, op) \ 3165 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3166 TCGv val, \ 3167 TCGv addr) \ 3168 { \ 3169 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3170 } 3171 3172 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3173 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3174 #endif 3175 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3176 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3177 3178 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3179 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3180 3181 #define GEN_QEMU_STORE_64(stop, op) \ 3182 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3183 TCGv_i64 val, \ 3184 TCGv addr) \ 3185 { \ 3186 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3187 } 3188 3189 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3190 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3191 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3192 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3193 3194 #if defined(TARGET_PPC64) 3195 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3196 #endif 3197 3198 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3199 static void glue(gen_, name##x)(DisasContext *ctx) \ 3200 { \ 3201 TCGv EA; \ 3202 chk(ctx); \ 3203 gen_set_access_type(ctx, ACCESS_INT); \ 3204 EA = tcg_temp_new(); \ 3205 gen_addr_reg_index(ctx, EA); \ 3206 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3207 } 3208 3209 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3210 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3211 3212 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3213 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3214 3215 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 3216 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3217 { \ 3218 TCGv EA; \ 3219 CHK_SV(ctx); \ 3220 gen_set_access_type(ctx, ACCESS_INT); \ 3221 EA = tcg_temp_new(); \ 3222 gen_addr_reg_index(ctx, EA); \ 3223 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 3224 } 3225 3226 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 3227 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 3228 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 3229 #if defined(TARGET_PPC64) 3230 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 3231 #endif 3232 3233 #if defined(TARGET_PPC64) 3234 /* CI load/store variants */ 3235 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3236 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3237 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3238 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3239 #endif 3240 3241 /*** Integer store ***/ 3242 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3243 static void glue(gen_, name##x)(DisasContext *ctx) \ 3244 { \ 3245 TCGv EA; \ 3246 chk(ctx); \ 3247 gen_set_access_type(ctx, ACCESS_INT); \ 3248 EA = tcg_temp_new(); \ 3249 gen_addr_reg_index(ctx, EA); \ 3250 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3251 } 3252 #define GEN_STX(name, stop, opc2, opc3, type) \ 3253 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3254 3255 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3256 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3257 3258 #define GEN_STEPX(name, stop, opc2, opc3) \ 3259 static void glue(gen_, name##epx)(DisasContext *ctx) \ 3260 { \ 3261 TCGv EA; \ 3262 CHK_SV(ctx); \ 3263 gen_set_access_type(ctx, ACCESS_INT); \ 3264 EA = tcg_temp_new(); \ 3265 gen_addr_reg_index(ctx, EA); \ 3266 tcg_gen_qemu_st_tl( \ 3267 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 3268 } 3269 3270 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 3271 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 3272 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 3273 #if defined(TARGET_PPC64) 3274 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 3275 #endif 3276 3277 #if defined(TARGET_PPC64) 3278 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3279 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3280 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3281 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3282 #endif 3283 /*** Integer load and store with byte reverse ***/ 3284 3285 /* lhbrx */ 3286 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3287 3288 /* lwbrx */ 3289 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3290 3291 #if defined(TARGET_PPC64) 3292 /* ldbrx */ 3293 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3294 /* stdbrx */ 3295 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3296 #endif /* TARGET_PPC64 */ 3297 3298 /* sthbrx */ 3299 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3300 /* stwbrx */ 3301 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3302 3303 /*** Integer load and store multiple ***/ 3304 3305 /* lmw */ 3306 static void gen_lmw(DisasContext *ctx) 3307 { 3308 TCGv t0; 3309 TCGv_i32 t1; 3310 3311 if (ctx->le_mode) { 3312 gen_align_no_le(ctx); 3313 return; 3314 } 3315 gen_set_access_type(ctx, ACCESS_INT); 3316 t0 = tcg_temp_new(); 3317 t1 = tcg_constant_i32(rD(ctx->opcode)); 3318 gen_addr_imm_index(ctx, t0, 0); 3319 gen_helper_lmw(cpu_env, t0, t1); 3320 } 3321 3322 /* stmw */ 3323 static void gen_stmw(DisasContext *ctx) 3324 { 3325 TCGv t0; 3326 TCGv_i32 t1; 3327 3328 if (ctx->le_mode) { 3329 gen_align_no_le(ctx); 3330 return; 3331 } 3332 gen_set_access_type(ctx, ACCESS_INT); 3333 t0 = tcg_temp_new(); 3334 t1 = tcg_constant_i32(rS(ctx->opcode)); 3335 gen_addr_imm_index(ctx, t0, 0); 3336 gen_helper_stmw(cpu_env, t0, t1); 3337 } 3338 3339 /*** Integer load and store strings ***/ 3340 3341 /* lswi */ 3342 /* 3343 * PowerPC32 specification says we must generate an exception if rA is 3344 * in the range of registers to be loaded. In an other hand, IBM says 3345 * this is valid, but rA won't be loaded. For now, I'll follow the 3346 * spec... 3347 */ 3348 static void gen_lswi(DisasContext *ctx) 3349 { 3350 TCGv t0; 3351 TCGv_i32 t1, t2; 3352 int nb = NB(ctx->opcode); 3353 int start = rD(ctx->opcode); 3354 int ra = rA(ctx->opcode); 3355 int nr; 3356 3357 if (ctx->le_mode) { 3358 gen_align_no_le(ctx); 3359 return; 3360 } 3361 if (nb == 0) { 3362 nb = 32; 3363 } 3364 nr = DIV_ROUND_UP(nb, 4); 3365 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3366 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3367 return; 3368 } 3369 gen_set_access_type(ctx, ACCESS_INT); 3370 t0 = tcg_temp_new(); 3371 gen_addr_register(ctx, t0); 3372 t1 = tcg_constant_i32(nb); 3373 t2 = tcg_constant_i32(start); 3374 gen_helper_lsw(cpu_env, t0, t1, t2); 3375 } 3376 3377 /* lswx */ 3378 static void gen_lswx(DisasContext *ctx) 3379 { 3380 TCGv t0; 3381 TCGv_i32 t1, t2, t3; 3382 3383 if (ctx->le_mode) { 3384 gen_align_no_le(ctx); 3385 return; 3386 } 3387 gen_set_access_type(ctx, ACCESS_INT); 3388 t0 = tcg_temp_new(); 3389 gen_addr_reg_index(ctx, t0); 3390 t1 = tcg_constant_i32(rD(ctx->opcode)); 3391 t2 = tcg_constant_i32(rA(ctx->opcode)); 3392 t3 = tcg_constant_i32(rB(ctx->opcode)); 3393 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3394 } 3395 3396 /* stswi */ 3397 static void gen_stswi(DisasContext *ctx) 3398 { 3399 TCGv t0; 3400 TCGv_i32 t1, t2; 3401 int nb = NB(ctx->opcode); 3402 3403 if (ctx->le_mode) { 3404 gen_align_no_le(ctx); 3405 return; 3406 } 3407 gen_set_access_type(ctx, ACCESS_INT); 3408 t0 = tcg_temp_new(); 3409 gen_addr_register(ctx, t0); 3410 if (nb == 0) { 3411 nb = 32; 3412 } 3413 t1 = tcg_constant_i32(nb); 3414 t2 = tcg_constant_i32(rS(ctx->opcode)); 3415 gen_helper_stsw(cpu_env, t0, t1, t2); 3416 } 3417 3418 /* stswx */ 3419 static void gen_stswx(DisasContext *ctx) 3420 { 3421 TCGv t0; 3422 TCGv_i32 t1, t2; 3423 3424 if (ctx->le_mode) { 3425 gen_align_no_le(ctx); 3426 return; 3427 } 3428 gen_set_access_type(ctx, ACCESS_INT); 3429 t0 = tcg_temp_new(); 3430 gen_addr_reg_index(ctx, t0); 3431 t1 = tcg_temp_new_i32(); 3432 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3433 tcg_gen_andi_i32(t1, t1, 0x7F); 3434 t2 = tcg_constant_i32(rS(ctx->opcode)); 3435 gen_helper_stsw(cpu_env, t0, t1, t2); 3436 } 3437 3438 /*** Memory synchronisation ***/ 3439 /* eieio */ 3440 static void gen_eieio(DisasContext *ctx) 3441 { 3442 TCGBar bar = TCG_MO_ALL; 3443 3444 /* 3445 * eieio has complex semanitcs. It provides memory ordering between 3446 * operations in the set: 3447 * - loads from CI memory. 3448 * - stores to CI memory. 3449 * - stores to WT memory. 3450 * 3451 * It separately also orders memory for operations in the set: 3452 * - stores to cacheble memory. 3453 * 3454 * It also serializes instructions: 3455 * - dcbt and dcbst. 3456 * 3457 * It separately serializes: 3458 * - tlbie and tlbsync. 3459 * 3460 * And separately serializes: 3461 * - slbieg, slbiag, and slbsync. 3462 * 3463 * The end result is that CI memory ordering requires TCG_MO_ALL 3464 * and it is not possible to special-case more relaxed ordering for 3465 * cacheable accesses. TCG_BAR_SC is required to provide this 3466 * serialization. 3467 */ 3468 3469 /* 3470 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3471 * tell the CPU it is a store-forwarding barrier. 3472 */ 3473 if (ctx->opcode & 0x2000000) { 3474 /* 3475 * ISA says that "Reserved fields in instructions are ignored 3476 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3477 * as this is not an instruction software should be using, 3478 * complain to the user. 3479 */ 3480 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3481 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3482 TARGET_FMT_lx "\n", ctx->cia); 3483 } else { 3484 bar = TCG_MO_ST_LD; 3485 } 3486 } 3487 3488 tcg_gen_mb(bar | TCG_BAR_SC); 3489 } 3490 3491 #if !defined(CONFIG_USER_ONLY) 3492 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3493 { 3494 TCGv_i32 t; 3495 TCGLabel *l; 3496 3497 if (!ctx->lazy_tlb_flush) { 3498 return; 3499 } 3500 l = gen_new_label(); 3501 t = tcg_temp_new_i32(); 3502 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3503 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3504 if (global) { 3505 gen_helper_check_tlb_flush_global(cpu_env); 3506 } else { 3507 gen_helper_check_tlb_flush_local(cpu_env); 3508 } 3509 gen_set_label(l); 3510 } 3511 #else 3512 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3513 #endif 3514 3515 /* isync */ 3516 static void gen_isync(DisasContext *ctx) 3517 { 3518 /* 3519 * We need to check for a pending TLB flush. This can only happen in 3520 * kernel mode however so check MSR_PR 3521 */ 3522 if (!ctx->pr) { 3523 gen_check_tlb_flush(ctx, false); 3524 } 3525 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3526 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3527 } 3528 3529 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3530 3531 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3532 { 3533 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3534 TCGv t0 = tcg_temp_new(); 3535 3536 gen_set_access_type(ctx, ACCESS_RES); 3537 gen_addr_reg_index(ctx, t0); 3538 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3539 tcg_gen_mov_tl(cpu_reserve, t0); 3540 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 3541 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3542 } 3543 3544 #define LARX(name, memop) \ 3545 static void gen_##name(DisasContext *ctx) \ 3546 { \ 3547 gen_load_locked(ctx, memop); \ 3548 } 3549 3550 /* lwarx */ 3551 LARX(lbarx, DEF_MEMOP(MO_UB)) 3552 LARX(lharx, DEF_MEMOP(MO_UW)) 3553 LARX(lwarx, DEF_MEMOP(MO_UL)) 3554 3555 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3556 TCGv EA, TCGCond cond, int addend) 3557 { 3558 TCGv t = tcg_temp_new(); 3559 TCGv t2 = tcg_temp_new(); 3560 TCGv u = tcg_temp_new(); 3561 3562 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3563 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3564 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3565 tcg_gen_addi_tl(u, t, addend); 3566 3567 /* E.g. for fetch and increment bounded... */ 3568 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3569 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3570 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3571 3572 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3573 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3574 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3575 } 3576 3577 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3578 { 3579 uint32_t gpr_FC = FC(ctx->opcode); 3580 TCGv EA = tcg_temp_new(); 3581 int rt = rD(ctx->opcode); 3582 bool need_serial; 3583 TCGv src, dst; 3584 3585 gen_addr_register(ctx, EA); 3586 dst = cpu_gpr[rt]; 3587 src = cpu_gpr[(rt + 1) & 31]; 3588 3589 need_serial = false; 3590 memop |= MO_ALIGN; 3591 switch (gpr_FC) { 3592 case 0: /* Fetch and add */ 3593 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3594 break; 3595 case 1: /* Fetch and xor */ 3596 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3597 break; 3598 case 2: /* Fetch and or */ 3599 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3600 break; 3601 case 3: /* Fetch and 'and' */ 3602 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3603 break; 3604 case 4: /* Fetch and max unsigned */ 3605 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3606 break; 3607 case 5: /* Fetch and max signed */ 3608 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3609 break; 3610 case 6: /* Fetch and min unsigned */ 3611 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3612 break; 3613 case 7: /* Fetch and min signed */ 3614 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3615 break; 3616 case 8: /* Swap */ 3617 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3618 break; 3619 3620 case 16: /* Compare and swap not equal */ 3621 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3622 need_serial = true; 3623 } else { 3624 TCGv t0 = tcg_temp_new(); 3625 TCGv t1 = tcg_temp_new(); 3626 3627 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3628 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3629 tcg_gen_mov_tl(t1, src); 3630 } else { 3631 tcg_gen_ext32u_tl(t1, src); 3632 } 3633 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3634 cpu_gpr[(rt + 2) & 31], t0); 3635 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3636 tcg_gen_mov_tl(dst, t0); 3637 } 3638 break; 3639 3640 case 24: /* Fetch and increment bounded */ 3641 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3642 need_serial = true; 3643 } else { 3644 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3645 } 3646 break; 3647 case 25: /* Fetch and increment equal */ 3648 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3649 need_serial = true; 3650 } else { 3651 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3652 } 3653 break; 3654 case 28: /* Fetch and decrement bounded */ 3655 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3656 need_serial = true; 3657 } else { 3658 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3659 } 3660 break; 3661 3662 default: 3663 /* invoke data storage error handler */ 3664 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3665 } 3666 3667 if (need_serial) { 3668 /* Restart with exclusive lock. */ 3669 gen_helper_exit_atomic(cpu_env); 3670 ctx->base.is_jmp = DISAS_NORETURN; 3671 } 3672 } 3673 3674 static void gen_lwat(DisasContext *ctx) 3675 { 3676 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3677 } 3678 3679 #ifdef TARGET_PPC64 3680 static void gen_ldat(DisasContext *ctx) 3681 { 3682 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3683 } 3684 #endif 3685 3686 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3687 { 3688 uint32_t gpr_FC = FC(ctx->opcode); 3689 TCGv EA = tcg_temp_new(); 3690 TCGv src, discard; 3691 3692 gen_addr_register(ctx, EA); 3693 src = cpu_gpr[rD(ctx->opcode)]; 3694 discard = tcg_temp_new(); 3695 3696 memop |= MO_ALIGN; 3697 switch (gpr_FC) { 3698 case 0: /* add and Store */ 3699 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3700 break; 3701 case 1: /* xor and Store */ 3702 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3703 break; 3704 case 2: /* Or and Store */ 3705 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3706 break; 3707 case 3: /* 'and' and Store */ 3708 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3709 break; 3710 case 4: /* Store max unsigned */ 3711 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3712 break; 3713 case 5: /* Store max signed */ 3714 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3715 break; 3716 case 6: /* Store min unsigned */ 3717 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3718 break; 3719 case 7: /* Store min signed */ 3720 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3721 break; 3722 case 24: /* Store twin */ 3723 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3724 /* Restart with exclusive lock. */ 3725 gen_helper_exit_atomic(cpu_env); 3726 ctx->base.is_jmp = DISAS_NORETURN; 3727 } else { 3728 TCGv t = tcg_temp_new(); 3729 TCGv t2 = tcg_temp_new(); 3730 TCGv s = tcg_temp_new(); 3731 TCGv s2 = tcg_temp_new(); 3732 TCGv ea_plus_s = tcg_temp_new(); 3733 3734 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3735 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3736 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3737 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3738 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3739 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3740 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3741 } 3742 break; 3743 default: 3744 /* invoke data storage error handler */ 3745 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3746 } 3747 } 3748 3749 static void gen_stwat(DisasContext *ctx) 3750 { 3751 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3752 } 3753 3754 #ifdef TARGET_PPC64 3755 static void gen_stdat(DisasContext *ctx) 3756 { 3757 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3758 } 3759 #endif 3760 3761 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3762 { 3763 TCGLabel *lfail; 3764 TCGv EA; 3765 TCGv cr0; 3766 TCGv t0; 3767 int rs = rS(ctx->opcode); 3768 3769 lfail = gen_new_label(); 3770 EA = tcg_temp_new(); 3771 cr0 = tcg_temp_new(); 3772 t0 = tcg_temp_new(); 3773 3774 tcg_gen_mov_tl(cr0, cpu_so); 3775 gen_set_access_type(ctx, ACCESS_RES); 3776 gen_addr_reg_index(ctx, EA); 3777 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3778 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3779 3780 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3781 cpu_gpr[rs], ctx->mem_idx, 3782 DEF_MEMOP(memop) | MO_ALIGN); 3783 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3784 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3785 tcg_gen_or_tl(cr0, cr0, t0); 3786 3787 gen_set_label(lfail); 3788 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3789 tcg_gen_movi_tl(cpu_reserve, -1); 3790 } 3791 3792 #define STCX(name, memop) \ 3793 static void gen_##name(DisasContext *ctx) \ 3794 { \ 3795 gen_conditional_store(ctx, memop); \ 3796 } 3797 3798 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3799 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3800 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3801 3802 #if defined(TARGET_PPC64) 3803 /* ldarx */ 3804 LARX(ldarx, DEF_MEMOP(MO_UQ)) 3805 /* stdcx. */ 3806 STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3807 3808 /* lqarx */ 3809 static void gen_lqarx(DisasContext *ctx) 3810 { 3811 int rd = rD(ctx->opcode); 3812 TCGv EA, hi, lo; 3813 TCGv_i128 t16; 3814 3815 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3816 (rd == rB(ctx->opcode)))) { 3817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3818 return; 3819 } 3820 3821 gen_set_access_type(ctx, ACCESS_RES); 3822 EA = tcg_temp_new(); 3823 gen_addr_reg_index(ctx, EA); 3824 3825 /* Note that the low part is always in RD+1, even in LE mode. */ 3826 lo = cpu_gpr[rd + 1]; 3827 hi = cpu_gpr[rd]; 3828 3829 t16 = tcg_temp_new_i128(); 3830 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3831 tcg_gen_extr_i128_i64(lo, hi, t16); 3832 3833 tcg_gen_mov_tl(cpu_reserve, EA); 3834 tcg_gen_movi_tl(cpu_reserve_length, 16); 3835 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3836 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3837 } 3838 3839 /* stqcx. */ 3840 static void gen_stqcx_(DisasContext *ctx) 3841 { 3842 TCGLabel *lfail; 3843 TCGv EA, t0, t1; 3844 TCGv cr0; 3845 TCGv_i128 cmp, val; 3846 int rs = rS(ctx->opcode); 3847 3848 if (unlikely(rs & 1)) { 3849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3850 return; 3851 } 3852 3853 lfail = gen_new_label(); 3854 EA = tcg_temp_new(); 3855 cr0 = tcg_temp_new(); 3856 3857 tcg_gen_mov_tl(cr0, cpu_so); 3858 gen_set_access_type(ctx, ACCESS_RES); 3859 gen_addr_reg_index(ctx, EA); 3860 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3861 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3862 3863 cmp = tcg_temp_new_i128(); 3864 val = tcg_temp_new_i128(); 3865 3866 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3867 3868 /* Note that the low part is always in RS+1, even in LE mode. */ 3869 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3870 3871 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3872 DEF_MEMOP(MO_128 | MO_ALIGN)); 3873 3874 t0 = tcg_temp_new(); 3875 t1 = tcg_temp_new(); 3876 tcg_gen_extr_i128_i64(t1, t0, val); 3877 3878 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3879 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3880 tcg_gen_or_tl(t0, t0, t1); 3881 3882 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3883 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3884 tcg_gen_or_tl(cr0, cr0, t0); 3885 3886 gen_set_label(lfail); 3887 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3888 tcg_gen_movi_tl(cpu_reserve, -1); 3889 } 3890 #endif /* defined(TARGET_PPC64) */ 3891 3892 /* sync */ 3893 static void gen_sync(DisasContext *ctx) 3894 { 3895 TCGBar bar = TCG_MO_ALL; 3896 uint32_t l = (ctx->opcode >> 21) & 3; 3897 3898 if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 3899 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 3900 } 3901 3902 /* 3903 * We may need to check for a pending TLB flush. 3904 * 3905 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3906 * 3907 * Additionally, this can only happen in kernel mode however so 3908 * check MSR_PR as well. 3909 */ 3910 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3911 gen_check_tlb_flush(ctx, true); 3912 } 3913 3914 tcg_gen_mb(bar | TCG_BAR_SC); 3915 } 3916 3917 /* wait */ 3918 static void gen_wait(DisasContext *ctx) 3919 { 3920 uint32_t wc; 3921 3922 if (ctx->insns_flags & PPC_WAIT) { 3923 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3924 3925 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3926 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3927 wc = WC(ctx->opcode); 3928 } else { 3929 wc = 0; 3930 } 3931 3932 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3933 /* v3.0 defines a new 'wait' encoding. */ 3934 wc = WC(ctx->opcode); 3935 if (ctx->insns_flags2 & PPC2_ISA310) { 3936 uint32_t pl = PL(ctx->opcode); 3937 3938 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3939 if (wc == 3) { 3940 gen_invalid(ctx); 3941 return; 3942 } 3943 3944 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3945 if (pl > 0 && wc != 2) { 3946 gen_invalid(ctx); 3947 return; 3948 } 3949 3950 } else { /* ISA300 */ 3951 /* WC 1-3 are reserved */ 3952 if (wc > 0) { 3953 gen_invalid(ctx); 3954 return; 3955 } 3956 } 3957 3958 } else { 3959 warn_report("wait instruction decoded with wrong ISA flags."); 3960 gen_invalid(ctx); 3961 return; 3962 } 3963 3964 /* 3965 * wait without WC field or with WC=0 waits for an exception / interrupt 3966 * to occur. 3967 */ 3968 if (wc == 0) { 3969 TCGv_i32 t0 = tcg_constant_i32(1); 3970 tcg_gen_st_i32(t0, cpu_env, 3971 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3972 /* Stop translation, as the CPU is supposed to sleep from now */ 3973 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3974 } 3975 3976 /* 3977 * Other wait types must not just wait until an exception occurs because 3978 * ignoring their other wake-up conditions could cause a hang. 3979 * 3980 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3981 * no-ops. 3982 * 3983 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3984 * 3985 * wc=2 waits for an implementation-specific condition, such could be 3986 * always true, so it can be implemented as a no-op. 3987 * 3988 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3989 * 3990 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3991 * Reservation-loss may have implementation-specific conditions, so it 3992 * can be implemented as a no-op. 3993 * 3994 * wc=2 waits for an exception or an amount of time to pass. This 3995 * amount is implementation-specific so it can be implemented as a 3996 * no-op. 3997 * 3998 * ISA v3.1 allows for execution to resume "in the rare case of 3999 * an implementation-dependent event", so in any case software must 4000 * not depend on the architected resumption condition to become 4001 * true, so no-op implementations should be architecturally correct 4002 * (if suboptimal). 4003 */ 4004 } 4005 4006 #if defined(TARGET_PPC64) 4007 static void gen_doze(DisasContext *ctx) 4008 { 4009 #if defined(CONFIG_USER_ONLY) 4010 GEN_PRIV(ctx); 4011 #else 4012 TCGv_i32 t; 4013 4014 CHK_HV(ctx); 4015 t = tcg_constant_i32(PPC_PM_DOZE); 4016 gen_helper_pminsn(cpu_env, t); 4017 /* Stop translation, as the CPU is supposed to sleep from now */ 4018 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4019 #endif /* defined(CONFIG_USER_ONLY) */ 4020 } 4021 4022 static void gen_nap(DisasContext *ctx) 4023 { 4024 #if defined(CONFIG_USER_ONLY) 4025 GEN_PRIV(ctx); 4026 #else 4027 TCGv_i32 t; 4028 4029 CHK_HV(ctx); 4030 t = tcg_constant_i32(PPC_PM_NAP); 4031 gen_helper_pminsn(cpu_env, t); 4032 /* Stop translation, as the CPU is supposed to sleep from now */ 4033 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4034 #endif /* defined(CONFIG_USER_ONLY) */ 4035 } 4036 4037 static void gen_stop(DisasContext *ctx) 4038 { 4039 #if defined(CONFIG_USER_ONLY) 4040 GEN_PRIV(ctx); 4041 #else 4042 TCGv_i32 t; 4043 4044 CHK_HV(ctx); 4045 t = tcg_constant_i32(PPC_PM_STOP); 4046 gen_helper_pminsn(cpu_env, t); 4047 /* Stop translation, as the CPU is supposed to sleep from now */ 4048 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4049 #endif /* defined(CONFIG_USER_ONLY) */ 4050 } 4051 4052 static void gen_sleep(DisasContext *ctx) 4053 { 4054 #if defined(CONFIG_USER_ONLY) 4055 GEN_PRIV(ctx); 4056 #else 4057 TCGv_i32 t; 4058 4059 CHK_HV(ctx); 4060 t = tcg_constant_i32(PPC_PM_SLEEP); 4061 gen_helper_pminsn(cpu_env, t); 4062 /* Stop translation, as the CPU is supposed to sleep from now */ 4063 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4064 #endif /* defined(CONFIG_USER_ONLY) */ 4065 } 4066 4067 static void gen_rvwinkle(DisasContext *ctx) 4068 { 4069 #if defined(CONFIG_USER_ONLY) 4070 GEN_PRIV(ctx); 4071 #else 4072 TCGv_i32 t; 4073 4074 CHK_HV(ctx); 4075 t = tcg_constant_i32(PPC_PM_RVWINKLE); 4076 gen_helper_pminsn(cpu_env, t); 4077 /* Stop translation, as the CPU is supposed to sleep from now */ 4078 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4079 #endif /* defined(CONFIG_USER_ONLY) */ 4080 } 4081 #endif /* #if defined(TARGET_PPC64) */ 4082 4083 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4084 { 4085 #if defined(TARGET_PPC64) 4086 if (ctx->has_cfar) { 4087 tcg_gen_movi_tl(cpu_cfar, nip); 4088 } 4089 #endif 4090 } 4091 4092 #if defined(TARGET_PPC64) 4093 static void pmu_count_insns(DisasContext *ctx) 4094 { 4095 /* 4096 * Do not bother calling the helper if the PMU isn't counting 4097 * instructions. 4098 */ 4099 if (!ctx->pmu_insn_cnt) { 4100 return; 4101 } 4102 4103 #if !defined(CONFIG_USER_ONLY) 4104 TCGLabel *l; 4105 TCGv t0; 4106 4107 /* 4108 * The PMU insns_inc() helper stops the internal PMU timer if a 4109 * counter overflows happens. In that case, if the guest is 4110 * running with icount and we do not handle it beforehand, 4111 * the helper can trigger a 'bad icount read'. 4112 */ 4113 translator_io_start(&ctx->base); 4114 4115 /* Avoid helper calls when only PMC5-6 are enabled. */ 4116 if (!ctx->pmc_other) { 4117 l = gen_new_label(); 4118 t0 = tcg_temp_new(); 4119 4120 gen_load_spr(t0, SPR_POWER_PMC5); 4121 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4122 gen_store_spr(SPR_POWER_PMC5, t0); 4123 /* Check for overflow, if it's enabled */ 4124 if (ctx->mmcr0_pmcjce) { 4125 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4126 gen_helper_handle_pmc5_overflow(cpu_env); 4127 } 4128 4129 gen_set_label(l); 4130 } else { 4131 gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4132 } 4133 #else 4134 /* 4135 * User mode can read (but not write) PMC5 and start/stop 4136 * the PMU via MMCR0_FC. In this case just increment 4137 * PMC5 with base.num_insns. 4138 */ 4139 TCGv t0 = tcg_temp_new(); 4140 4141 gen_load_spr(t0, SPR_POWER_PMC5); 4142 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4143 gen_store_spr(SPR_POWER_PMC5, t0); 4144 #endif /* #if !defined(CONFIG_USER_ONLY) */ 4145 } 4146 #else 4147 static void pmu_count_insns(DisasContext *ctx) 4148 { 4149 return; 4150 } 4151 #endif /* #if defined(TARGET_PPC64) */ 4152 4153 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4154 { 4155 return translator_use_goto_tb(&ctx->base, dest); 4156 } 4157 4158 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 4159 { 4160 if (unlikely(ctx->singlestep_enabled)) { 4161 gen_debug_exception(ctx); 4162 } else { 4163 /* 4164 * tcg_gen_lookup_and_goto_ptr will exit the TB if 4165 * CF_NO_GOTO_PTR is set. Count insns now. 4166 */ 4167 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 4168 pmu_count_insns(ctx); 4169 } 4170 4171 tcg_gen_lookup_and_goto_ptr(); 4172 } 4173 } 4174 4175 /*** Branch ***/ 4176 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4177 { 4178 if (NARROW_MODE(ctx)) { 4179 dest = (uint32_t) dest; 4180 } 4181 if (use_goto_tb(ctx, dest)) { 4182 pmu_count_insns(ctx); 4183 tcg_gen_goto_tb(n); 4184 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4185 tcg_gen_exit_tb(ctx->base.tb, n); 4186 } else { 4187 tcg_gen_movi_tl(cpu_nip, dest & ~3); 4188 gen_lookup_and_goto_ptr(ctx); 4189 } 4190 } 4191 4192 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4193 { 4194 if (NARROW_MODE(ctx)) { 4195 nip = (uint32_t)nip; 4196 } 4197 tcg_gen_movi_tl(cpu_lr, nip); 4198 } 4199 4200 /* b ba bl bla */ 4201 static void gen_b(DisasContext *ctx) 4202 { 4203 target_ulong li, target; 4204 4205 /* sign extend LI */ 4206 li = LI(ctx->opcode); 4207 li = (li ^ 0x02000000) - 0x02000000; 4208 if (likely(AA(ctx->opcode) == 0)) { 4209 target = ctx->cia + li; 4210 } else { 4211 target = li; 4212 } 4213 if (LK(ctx->opcode)) { 4214 gen_setlr(ctx, ctx->base.pc_next); 4215 } 4216 gen_update_cfar(ctx, ctx->cia); 4217 gen_goto_tb(ctx, 0, target); 4218 ctx->base.is_jmp = DISAS_NORETURN; 4219 } 4220 4221 #define BCOND_IM 0 4222 #define BCOND_LR 1 4223 #define BCOND_CTR 2 4224 #define BCOND_TAR 3 4225 4226 static void gen_bcond(DisasContext *ctx, int type) 4227 { 4228 uint32_t bo = BO(ctx->opcode); 4229 TCGLabel *l1; 4230 TCGv target; 4231 4232 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4233 target = tcg_temp_new(); 4234 if (type == BCOND_CTR) { 4235 tcg_gen_mov_tl(target, cpu_ctr); 4236 } else if (type == BCOND_TAR) { 4237 gen_load_spr(target, SPR_TAR); 4238 } else { 4239 tcg_gen_mov_tl(target, cpu_lr); 4240 } 4241 } else { 4242 target = NULL; 4243 } 4244 if (LK(ctx->opcode)) { 4245 gen_setlr(ctx, ctx->base.pc_next); 4246 } 4247 l1 = gen_new_label(); 4248 if ((bo & 0x4) == 0) { 4249 /* Decrement and test CTR */ 4250 TCGv temp = tcg_temp_new(); 4251 4252 if (type == BCOND_CTR) { 4253 /* 4254 * All ISAs up to v3 describe this form of bcctr as invalid but 4255 * some processors, ie. 64-bit server processors compliant with 4256 * arch 2.x, do implement a "test and decrement" logic instead, 4257 * as described in their respective UMs. This logic involves CTR 4258 * to act as both the branch target and a counter, which makes 4259 * it basically useless and thus never used in real code. 4260 * 4261 * This form was hence chosen to trigger extra micro-architectural 4262 * side-effect on real HW needed for the Spectre v2 workaround. 4263 * It is up to guests that implement such workaround, ie. linux, to 4264 * use this form in a way it just triggers the side-effect without 4265 * doing anything else harmful. 4266 */ 4267 if (unlikely(!is_book3s_arch2x(ctx))) { 4268 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4269 return; 4270 } 4271 4272 if (NARROW_MODE(ctx)) { 4273 tcg_gen_ext32u_tl(temp, cpu_ctr); 4274 } else { 4275 tcg_gen_mov_tl(temp, cpu_ctr); 4276 } 4277 if (bo & 0x2) { 4278 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4279 } else { 4280 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4281 } 4282 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4283 } else { 4284 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4285 if (NARROW_MODE(ctx)) { 4286 tcg_gen_ext32u_tl(temp, cpu_ctr); 4287 } else { 4288 tcg_gen_mov_tl(temp, cpu_ctr); 4289 } 4290 if (bo & 0x2) { 4291 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4292 } else { 4293 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4294 } 4295 } 4296 } 4297 if ((bo & 0x10) == 0) { 4298 /* Test CR */ 4299 uint32_t bi = BI(ctx->opcode); 4300 uint32_t mask = 0x08 >> (bi & 0x03); 4301 TCGv_i32 temp = tcg_temp_new_i32(); 4302 4303 if (bo & 0x8) { 4304 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4305 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4306 } else { 4307 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4308 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4309 } 4310 } 4311 gen_update_cfar(ctx, ctx->cia); 4312 if (type == BCOND_IM) { 4313 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4314 if (likely(AA(ctx->opcode) == 0)) { 4315 gen_goto_tb(ctx, 0, ctx->cia + li); 4316 } else { 4317 gen_goto_tb(ctx, 0, li); 4318 } 4319 } else { 4320 if (NARROW_MODE(ctx)) { 4321 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4322 } else { 4323 tcg_gen_andi_tl(cpu_nip, target, ~3); 4324 } 4325 gen_lookup_and_goto_ptr(ctx); 4326 } 4327 if ((bo & 0x14) != 0x14) { 4328 /* fallthrough case */ 4329 gen_set_label(l1); 4330 gen_goto_tb(ctx, 1, ctx->base.pc_next); 4331 } 4332 ctx->base.is_jmp = DISAS_NORETURN; 4333 } 4334 4335 static void gen_bc(DisasContext *ctx) 4336 { 4337 gen_bcond(ctx, BCOND_IM); 4338 } 4339 4340 static void gen_bcctr(DisasContext *ctx) 4341 { 4342 gen_bcond(ctx, BCOND_CTR); 4343 } 4344 4345 static void gen_bclr(DisasContext *ctx) 4346 { 4347 gen_bcond(ctx, BCOND_LR); 4348 } 4349 4350 static void gen_bctar(DisasContext *ctx) 4351 { 4352 gen_bcond(ctx, BCOND_TAR); 4353 } 4354 4355 /*** Condition register logical ***/ 4356 #define GEN_CRLOGIC(name, tcg_op, opc) \ 4357 static void glue(gen_, name)(DisasContext *ctx) \ 4358 { \ 4359 uint8_t bitmask; \ 4360 int sh; \ 4361 TCGv_i32 t0, t1; \ 4362 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4363 t0 = tcg_temp_new_i32(); \ 4364 if (sh > 0) \ 4365 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4366 else if (sh < 0) \ 4367 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4368 else \ 4369 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4370 t1 = tcg_temp_new_i32(); \ 4371 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4372 if (sh > 0) \ 4373 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4374 else if (sh < 0) \ 4375 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4376 else \ 4377 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4378 tcg_op(t0, t0, t1); \ 4379 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4380 tcg_gen_andi_i32(t0, t0, bitmask); \ 4381 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4382 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4383 } 4384 4385 /* crand */ 4386 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4387 /* crandc */ 4388 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4389 /* creqv */ 4390 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4391 /* crnand */ 4392 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4393 /* crnor */ 4394 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4395 /* cror */ 4396 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4397 /* crorc */ 4398 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4399 /* crxor */ 4400 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4401 4402 /* mcrf */ 4403 static void gen_mcrf(DisasContext *ctx) 4404 { 4405 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4406 } 4407 4408 /*** System linkage ***/ 4409 4410 /* rfi (supervisor only) */ 4411 static void gen_rfi(DisasContext *ctx) 4412 { 4413 #if defined(CONFIG_USER_ONLY) 4414 GEN_PRIV(ctx); 4415 #else 4416 /* 4417 * This instruction doesn't exist anymore on 64-bit server 4418 * processors compliant with arch 2.x 4419 */ 4420 if (is_book3s_arch2x(ctx)) { 4421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4422 return; 4423 } 4424 /* Restore CPU state */ 4425 CHK_SV(ctx); 4426 translator_io_start(&ctx->base); 4427 gen_update_cfar(ctx, ctx->cia); 4428 gen_helper_rfi(cpu_env); 4429 ctx->base.is_jmp = DISAS_EXIT; 4430 #endif 4431 } 4432 4433 #if defined(TARGET_PPC64) 4434 static void gen_rfid(DisasContext *ctx) 4435 { 4436 #if defined(CONFIG_USER_ONLY) 4437 GEN_PRIV(ctx); 4438 #else 4439 /* Restore CPU state */ 4440 CHK_SV(ctx); 4441 translator_io_start(&ctx->base); 4442 gen_update_cfar(ctx, ctx->cia); 4443 gen_helper_rfid(cpu_env); 4444 ctx->base.is_jmp = DISAS_EXIT; 4445 #endif 4446 } 4447 4448 #if !defined(CONFIG_USER_ONLY) 4449 static void gen_rfscv(DisasContext *ctx) 4450 { 4451 #if defined(CONFIG_USER_ONLY) 4452 GEN_PRIV(ctx); 4453 #else 4454 /* Restore CPU state */ 4455 CHK_SV(ctx); 4456 translator_io_start(&ctx->base); 4457 gen_update_cfar(ctx, ctx->cia); 4458 gen_helper_rfscv(cpu_env); 4459 ctx->base.is_jmp = DISAS_EXIT; 4460 #endif 4461 } 4462 #endif 4463 4464 static void gen_hrfid(DisasContext *ctx) 4465 { 4466 #if defined(CONFIG_USER_ONLY) 4467 GEN_PRIV(ctx); 4468 #else 4469 /* Restore CPU state */ 4470 CHK_HV(ctx); 4471 gen_helper_hrfid(cpu_env); 4472 ctx->base.is_jmp = DISAS_EXIT; 4473 #endif 4474 } 4475 #endif 4476 4477 /* sc */ 4478 #if defined(CONFIG_USER_ONLY) 4479 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4480 #else 4481 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4482 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4483 #endif 4484 static void gen_sc(DisasContext *ctx) 4485 { 4486 uint32_t lev; 4487 4488 /* 4489 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4490 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4491 * for Ultravisor which TCG does not support, so just ignore the top 6. 4492 */ 4493 lev = (ctx->opcode >> 5) & 0x1; 4494 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4495 } 4496 4497 #if defined(TARGET_PPC64) 4498 #if !defined(CONFIG_USER_ONLY) 4499 static void gen_scv(DisasContext *ctx) 4500 { 4501 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4502 4503 /* Set the PC back to the faulting instruction. */ 4504 gen_update_nip(ctx, ctx->cia); 4505 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4506 4507 ctx->base.is_jmp = DISAS_NORETURN; 4508 } 4509 #endif 4510 #endif 4511 4512 /*** Trap ***/ 4513 4514 /* Check for unconditional traps (always or never) */ 4515 static bool check_unconditional_trap(DisasContext *ctx) 4516 { 4517 /* Trap never */ 4518 if (TO(ctx->opcode) == 0) { 4519 return true; 4520 } 4521 /* Trap always */ 4522 if (TO(ctx->opcode) == 31) { 4523 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4524 return true; 4525 } 4526 return false; 4527 } 4528 4529 /* tw */ 4530 static void gen_tw(DisasContext *ctx) 4531 { 4532 TCGv_i32 t0; 4533 4534 if (check_unconditional_trap(ctx)) { 4535 return; 4536 } 4537 t0 = tcg_constant_i32(TO(ctx->opcode)); 4538 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4539 t0); 4540 } 4541 4542 /* twi */ 4543 static void gen_twi(DisasContext *ctx) 4544 { 4545 TCGv t0; 4546 TCGv_i32 t1; 4547 4548 if (check_unconditional_trap(ctx)) { 4549 return; 4550 } 4551 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4552 t1 = tcg_constant_i32(TO(ctx->opcode)); 4553 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4554 } 4555 4556 #if defined(TARGET_PPC64) 4557 /* td */ 4558 static void gen_td(DisasContext *ctx) 4559 { 4560 TCGv_i32 t0; 4561 4562 if (check_unconditional_trap(ctx)) { 4563 return; 4564 } 4565 t0 = tcg_constant_i32(TO(ctx->opcode)); 4566 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4567 t0); 4568 } 4569 4570 /* tdi */ 4571 static void gen_tdi(DisasContext *ctx) 4572 { 4573 TCGv t0; 4574 TCGv_i32 t1; 4575 4576 if (check_unconditional_trap(ctx)) { 4577 return; 4578 } 4579 t0 = tcg_constant_tl(SIMM(ctx->opcode)); 4580 t1 = tcg_constant_i32(TO(ctx->opcode)); 4581 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4582 } 4583 #endif 4584 4585 /*** Processor control ***/ 4586 4587 /* mcrxr */ 4588 static void gen_mcrxr(DisasContext *ctx) 4589 { 4590 TCGv_i32 t0 = tcg_temp_new_i32(); 4591 TCGv_i32 t1 = tcg_temp_new_i32(); 4592 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4593 4594 tcg_gen_trunc_tl_i32(t0, cpu_so); 4595 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4596 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4597 tcg_gen_shli_i32(t0, t0, 3); 4598 tcg_gen_shli_i32(t1, t1, 2); 4599 tcg_gen_shli_i32(dst, dst, 1); 4600 tcg_gen_or_i32(dst, dst, t0); 4601 tcg_gen_or_i32(dst, dst, t1); 4602 4603 tcg_gen_movi_tl(cpu_so, 0); 4604 tcg_gen_movi_tl(cpu_ov, 0); 4605 tcg_gen_movi_tl(cpu_ca, 0); 4606 } 4607 4608 #ifdef TARGET_PPC64 4609 /* mcrxrx */ 4610 static void gen_mcrxrx(DisasContext *ctx) 4611 { 4612 TCGv t0 = tcg_temp_new(); 4613 TCGv t1 = tcg_temp_new(); 4614 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4615 4616 /* copy OV and OV32 */ 4617 tcg_gen_shli_tl(t0, cpu_ov, 1); 4618 tcg_gen_or_tl(t0, t0, cpu_ov32); 4619 tcg_gen_shli_tl(t0, t0, 2); 4620 /* copy CA and CA32 */ 4621 tcg_gen_shli_tl(t1, cpu_ca, 1); 4622 tcg_gen_or_tl(t1, t1, cpu_ca32); 4623 tcg_gen_or_tl(t0, t0, t1); 4624 tcg_gen_trunc_tl_i32(dst, t0); 4625 } 4626 #endif 4627 4628 /* mfcr mfocrf */ 4629 static void gen_mfcr(DisasContext *ctx) 4630 { 4631 uint32_t crm, crn; 4632 4633 if (likely(ctx->opcode & 0x00100000)) { 4634 crm = CRM(ctx->opcode); 4635 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4636 crn = ctz32(crm); 4637 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4638 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4639 cpu_gpr[rD(ctx->opcode)], crn * 4); 4640 } 4641 } else { 4642 TCGv_i32 t0 = tcg_temp_new_i32(); 4643 tcg_gen_mov_i32(t0, cpu_crf[0]); 4644 tcg_gen_shli_i32(t0, t0, 4); 4645 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4646 tcg_gen_shli_i32(t0, t0, 4); 4647 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4648 tcg_gen_shli_i32(t0, t0, 4); 4649 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4650 tcg_gen_shli_i32(t0, t0, 4); 4651 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4652 tcg_gen_shli_i32(t0, t0, 4); 4653 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4654 tcg_gen_shli_i32(t0, t0, 4); 4655 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4656 tcg_gen_shli_i32(t0, t0, 4); 4657 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4658 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4659 } 4660 } 4661 4662 /* mfmsr */ 4663 static void gen_mfmsr(DisasContext *ctx) 4664 { 4665 CHK_SV(ctx); 4666 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4667 } 4668 4669 /* mfspr */ 4670 static inline void gen_op_mfspr(DisasContext *ctx) 4671 { 4672 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4673 uint32_t sprn = SPR(ctx->opcode); 4674 4675 #if defined(CONFIG_USER_ONLY) 4676 read_cb = ctx->spr_cb[sprn].uea_read; 4677 #else 4678 if (ctx->pr) { 4679 read_cb = ctx->spr_cb[sprn].uea_read; 4680 } else if (ctx->hv) { 4681 read_cb = ctx->spr_cb[sprn].hea_read; 4682 } else { 4683 read_cb = ctx->spr_cb[sprn].oea_read; 4684 } 4685 #endif 4686 if (likely(read_cb != NULL)) { 4687 if (likely(read_cb != SPR_NOACCESS)) { 4688 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4689 } else { 4690 /* Privilege exception */ 4691 /* 4692 * This is a hack to avoid warnings when running Linux: 4693 * this OS breaks the PowerPC virtualisation model, 4694 * allowing userland application to read the PVR 4695 */ 4696 if (sprn != SPR_PVR) { 4697 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4698 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4699 ctx->cia); 4700 } 4701 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4702 } 4703 } else { 4704 /* ISA 2.07 defines these as no-ops */ 4705 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4706 (sprn >= 808 && sprn <= 811)) { 4707 /* This is a nop */ 4708 return; 4709 } 4710 /* Not defined */ 4711 qemu_log_mask(LOG_GUEST_ERROR, 4712 "Trying to read invalid spr %d (0x%03x) at " 4713 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4714 4715 /* 4716 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4717 * generate a priv, a hv emu or a no-op 4718 */ 4719 if (sprn & 0x10) { 4720 if (ctx->pr) { 4721 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4722 } 4723 } else { 4724 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4725 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4726 } 4727 } 4728 } 4729 } 4730 4731 static void gen_mfspr(DisasContext *ctx) 4732 { 4733 gen_op_mfspr(ctx); 4734 } 4735 4736 /* mftb */ 4737 static void gen_mftb(DisasContext *ctx) 4738 { 4739 gen_op_mfspr(ctx); 4740 } 4741 4742 /* mtcrf mtocrf*/ 4743 static void gen_mtcrf(DisasContext *ctx) 4744 { 4745 uint32_t crm, crn; 4746 4747 crm = CRM(ctx->opcode); 4748 if (likely((ctx->opcode & 0x00100000))) { 4749 if (crm && ((crm & (crm - 1)) == 0)) { 4750 TCGv_i32 temp = tcg_temp_new_i32(); 4751 crn = ctz32(crm); 4752 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4753 tcg_gen_shri_i32(temp, temp, crn * 4); 4754 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4755 } 4756 } else { 4757 TCGv_i32 temp = tcg_temp_new_i32(); 4758 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4759 for (crn = 0 ; crn < 8 ; crn++) { 4760 if (crm & (1 << crn)) { 4761 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4762 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4763 } 4764 } 4765 } 4766 } 4767 4768 /* mtmsr */ 4769 #if defined(TARGET_PPC64) 4770 static void gen_mtmsrd(DisasContext *ctx) 4771 { 4772 if (unlikely(!is_book3s_arch2x(ctx))) { 4773 gen_invalid(ctx); 4774 return; 4775 } 4776 4777 CHK_SV(ctx); 4778 4779 #if !defined(CONFIG_USER_ONLY) 4780 TCGv t0, t1; 4781 target_ulong mask; 4782 4783 t0 = tcg_temp_new(); 4784 t1 = tcg_temp_new(); 4785 4786 translator_io_start(&ctx->base); 4787 4788 if (ctx->opcode & 0x00010000) { 4789 /* L=1 form only updates EE and RI */ 4790 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4791 } else { 4792 /* mtmsrd does not alter HV, S, ME, or LE */ 4793 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4794 (1ULL << MSR_HV)); 4795 /* 4796 * XXX: we need to update nip before the store if we enter 4797 * power saving mode, we will exit the loop directly from 4798 * ppc_store_msr 4799 */ 4800 gen_update_nip(ctx, ctx->base.pc_next); 4801 } 4802 4803 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4804 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4805 tcg_gen_or_tl(t0, t0, t1); 4806 4807 gen_helper_store_msr(cpu_env, t0); 4808 4809 /* Must stop the translation as machine state (may have) changed */ 4810 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4811 #endif /* !defined(CONFIG_USER_ONLY) */ 4812 } 4813 #endif /* defined(TARGET_PPC64) */ 4814 4815 static void gen_mtmsr(DisasContext *ctx) 4816 { 4817 CHK_SV(ctx); 4818 4819 #if !defined(CONFIG_USER_ONLY) 4820 TCGv t0, t1; 4821 target_ulong mask = 0xFFFFFFFF; 4822 4823 t0 = tcg_temp_new(); 4824 t1 = tcg_temp_new(); 4825 4826 translator_io_start(&ctx->base); 4827 if (ctx->opcode & 0x00010000) { 4828 /* L=1 form only updates EE and RI */ 4829 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4830 } else { 4831 /* mtmsr does not alter S, ME, or LE */ 4832 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4833 4834 /* 4835 * XXX: we need to update nip before the store if we enter 4836 * power saving mode, we will exit the loop directly from 4837 * ppc_store_msr 4838 */ 4839 gen_update_nip(ctx, ctx->base.pc_next); 4840 } 4841 4842 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4843 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4844 tcg_gen_or_tl(t0, t0, t1); 4845 4846 gen_helper_store_msr(cpu_env, t0); 4847 4848 /* Must stop the translation as machine state (may have) changed */ 4849 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4850 #endif 4851 } 4852 4853 /* mtspr */ 4854 static void gen_mtspr(DisasContext *ctx) 4855 { 4856 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4857 uint32_t sprn = SPR(ctx->opcode); 4858 4859 #if defined(CONFIG_USER_ONLY) 4860 write_cb = ctx->spr_cb[sprn].uea_write; 4861 #else 4862 if (ctx->pr) { 4863 write_cb = ctx->spr_cb[sprn].uea_write; 4864 } else if (ctx->hv) { 4865 write_cb = ctx->spr_cb[sprn].hea_write; 4866 } else { 4867 write_cb = ctx->spr_cb[sprn].oea_write; 4868 } 4869 #endif 4870 if (likely(write_cb != NULL)) { 4871 if (likely(write_cb != SPR_NOACCESS)) { 4872 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4873 } else { 4874 /* Privilege exception */ 4875 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4876 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4877 ctx->cia); 4878 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4879 } 4880 } else { 4881 /* ISA 2.07 defines these as no-ops */ 4882 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4883 (sprn >= 808 && sprn <= 811)) { 4884 /* This is a nop */ 4885 return; 4886 } 4887 4888 /* Not defined */ 4889 qemu_log_mask(LOG_GUEST_ERROR, 4890 "Trying to write invalid spr %d (0x%03x) at " 4891 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4892 4893 4894 /* 4895 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4896 * generate a priv, a hv emu or a no-op 4897 */ 4898 if (sprn & 0x10) { 4899 if (ctx->pr) { 4900 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4901 } 4902 } else { 4903 if (ctx->pr || sprn == 0) { 4904 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4905 } 4906 } 4907 } 4908 } 4909 4910 #if defined(TARGET_PPC64) 4911 /* setb */ 4912 static void gen_setb(DisasContext *ctx) 4913 { 4914 TCGv_i32 t0 = tcg_temp_new_i32(); 4915 TCGv_i32 t8 = tcg_constant_i32(8); 4916 TCGv_i32 tm1 = tcg_constant_i32(-1); 4917 int crf = crfS(ctx->opcode); 4918 4919 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4920 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4921 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4922 } 4923 #endif 4924 4925 /*** Cache management ***/ 4926 4927 /* dcbf */ 4928 static void gen_dcbf(DisasContext *ctx) 4929 { 4930 /* XXX: specification says this is treated as a load by the MMU */ 4931 TCGv t0; 4932 gen_set_access_type(ctx, ACCESS_CACHE); 4933 t0 = tcg_temp_new(); 4934 gen_addr_reg_index(ctx, t0); 4935 gen_qemu_ld8u(ctx, t0, t0); 4936 } 4937 4938 /* dcbfep (external PID dcbf) */ 4939 static void gen_dcbfep(DisasContext *ctx) 4940 { 4941 /* XXX: specification says this is treated as a load by the MMU */ 4942 TCGv t0; 4943 CHK_SV(ctx); 4944 gen_set_access_type(ctx, ACCESS_CACHE); 4945 t0 = tcg_temp_new(); 4946 gen_addr_reg_index(ctx, t0); 4947 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4948 } 4949 4950 /* dcbi (Supervisor only) */ 4951 static void gen_dcbi(DisasContext *ctx) 4952 { 4953 #if defined(CONFIG_USER_ONLY) 4954 GEN_PRIV(ctx); 4955 #else 4956 TCGv EA, val; 4957 4958 CHK_SV(ctx); 4959 EA = tcg_temp_new(); 4960 gen_set_access_type(ctx, ACCESS_CACHE); 4961 gen_addr_reg_index(ctx, EA); 4962 val = tcg_temp_new(); 4963 /* XXX: specification says this should be treated as a store by the MMU */ 4964 gen_qemu_ld8u(ctx, val, EA); 4965 gen_qemu_st8(ctx, val, EA); 4966 #endif /* defined(CONFIG_USER_ONLY) */ 4967 } 4968 4969 /* dcdst */ 4970 static void gen_dcbst(DisasContext *ctx) 4971 { 4972 /* XXX: specification say this is treated as a load by the MMU */ 4973 TCGv t0; 4974 gen_set_access_type(ctx, ACCESS_CACHE); 4975 t0 = tcg_temp_new(); 4976 gen_addr_reg_index(ctx, t0); 4977 gen_qemu_ld8u(ctx, t0, t0); 4978 } 4979 4980 /* dcbstep (dcbstep External PID version) */ 4981 static void gen_dcbstep(DisasContext *ctx) 4982 { 4983 /* XXX: specification say this is treated as a load by the MMU */ 4984 TCGv t0; 4985 gen_set_access_type(ctx, ACCESS_CACHE); 4986 t0 = tcg_temp_new(); 4987 gen_addr_reg_index(ctx, t0); 4988 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4989 } 4990 4991 /* dcbt */ 4992 static void gen_dcbt(DisasContext *ctx) 4993 { 4994 /* 4995 * interpreted as no-op 4996 * XXX: specification say this is treated as a load by the MMU but 4997 * does not generate any exception 4998 */ 4999 } 5000 5001 /* dcbtep */ 5002 static void gen_dcbtep(DisasContext *ctx) 5003 { 5004 /* 5005 * interpreted as no-op 5006 * XXX: specification say this is treated as a load by the MMU but 5007 * does not generate any exception 5008 */ 5009 } 5010 5011 /* dcbtst */ 5012 static void gen_dcbtst(DisasContext *ctx) 5013 { 5014 /* 5015 * interpreted as no-op 5016 * XXX: specification say this is treated as a load by the MMU but 5017 * does not generate any exception 5018 */ 5019 } 5020 5021 /* dcbtstep */ 5022 static void gen_dcbtstep(DisasContext *ctx) 5023 { 5024 /* 5025 * interpreted as no-op 5026 * XXX: specification say this is treated as a load by the MMU but 5027 * does not generate any exception 5028 */ 5029 } 5030 5031 /* dcbtls */ 5032 static void gen_dcbtls(DisasContext *ctx) 5033 { 5034 /* Always fails locking the cache */ 5035 TCGv t0 = tcg_temp_new(); 5036 gen_load_spr(t0, SPR_Exxx_L1CSR0); 5037 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5038 gen_store_spr(SPR_Exxx_L1CSR0, t0); 5039 } 5040 5041 /* dcblc */ 5042 static void gen_dcblc(DisasContext *ctx) 5043 { 5044 /* 5045 * interpreted as no-op 5046 */ 5047 } 5048 5049 /* dcbz */ 5050 static void gen_dcbz(DisasContext *ctx) 5051 { 5052 TCGv tcgv_addr; 5053 TCGv_i32 tcgv_op; 5054 5055 gen_set_access_type(ctx, ACCESS_CACHE); 5056 tcgv_addr = tcg_temp_new(); 5057 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5058 gen_addr_reg_index(ctx, tcgv_addr); 5059 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5060 } 5061 5062 /* dcbzep */ 5063 static void gen_dcbzep(DisasContext *ctx) 5064 { 5065 TCGv tcgv_addr; 5066 TCGv_i32 tcgv_op; 5067 5068 gen_set_access_type(ctx, ACCESS_CACHE); 5069 tcgv_addr = tcg_temp_new(); 5070 tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5071 gen_addr_reg_index(ctx, tcgv_addr); 5072 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 5073 } 5074 5075 /* dst / dstt */ 5076 static void gen_dst(DisasContext *ctx) 5077 { 5078 if (rA(ctx->opcode) == 0) { 5079 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5080 } else { 5081 /* interpreted as no-op */ 5082 } 5083 } 5084 5085 /* dstst /dststt */ 5086 static void gen_dstst(DisasContext *ctx) 5087 { 5088 if (rA(ctx->opcode) == 0) { 5089 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5090 } else { 5091 /* interpreted as no-op */ 5092 } 5093 5094 } 5095 5096 /* dss / dssall */ 5097 static void gen_dss(DisasContext *ctx) 5098 { 5099 /* interpreted as no-op */ 5100 } 5101 5102 /* icbi */ 5103 static void gen_icbi(DisasContext *ctx) 5104 { 5105 TCGv t0; 5106 gen_set_access_type(ctx, ACCESS_CACHE); 5107 t0 = tcg_temp_new(); 5108 gen_addr_reg_index(ctx, t0); 5109 gen_helper_icbi(cpu_env, t0); 5110 } 5111 5112 /* icbiep */ 5113 static void gen_icbiep(DisasContext *ctx) 5114 { 5115 TCGv t0; 5116 gen_set_access_type(ctx, ACCESS_CACHE); 5117 t0 = tcg_temp_new(); 5118 gen_addr_reg_index(ctx, t0); 5119 gen_helper_icbiep(cpu_env, t0); 5120 } 5121 5122 /* Optional: */ 5123 /* dcba */ 5124 static void gen_dcba(DisasContext *ctx) 5125 { 5126 /* 5127 * interpreted as no-op 5128 * XXX: specification say this is treated as a store by the MMU 5129 * but does not generate any exception 5130 */ 5131 } 5132 5133 /*** Segment register manipulation ***/ 5134 /* Supervisor only: */ 5135 5136 /* mfsr */ 5137 static void gen_mfsr(DisasContext *ctx) 5138 { 5139 #if defined(CONFIG_USER_ONLY) 5140 GEN_PRIV(ctx); 5141 #else 5142 TCGv t0; 5143 5144 CHK_SV(ctx); 5145 t0 = tcg_constant_tl(SR(ctx->opcode)); 5146 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5147 #endif /* defined(CONFIG_USER_ONLY) */ 5148 } 5149 5150 /* mfsrin */ 5151 static void gen_mfsrin(DisasContext *ctx) 5152 { 5153 #if defined(CONFIG_USER_ONLY) 5154 GEN_PRIV(ctx); 5155 #else 5156 TCGv t0; 5157 5158 CHK_SV(ctx); 5159 t0 = tcg_temp_new(); 5160 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5161 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5162 #endif /* defined(CONFIG_USER_ONLY) */ 5163 } 5164 5165 /* mtsr */ 5166 static void gen_mtsr(DisasContext *ctx) 5167 { 5168 #if defined(CONFIG_USER_ONLY) 5169 GEN_PRIV(ctx); 5170 #else 5171 TCGv t0; 5172 5173 CHK_SV(ctx); 5174 t0 = tcg_constant_tl(SR(ctx->opcode)); 5175 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5176 #endif /* defined(CONFIG_USER_ONLY) */ 5177 } 5178 5179 /* mtsrin */ 5180 static void gen_mtsrin(DisasContext *ctx) 5181 { 5182 #if defined(CONFIG_USER_ONLY) 5183 GEN_PRIV(ctx); 5184 #else 5185 TCGv t0; 5186 CHK_SV(ctx); 5187 5188 t0 = tcg_temp_new(); 5189 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5190 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5191 #endif /* defined(CONFIG_USER_ONLY) */ 5192 } 5193 5194 #if defined(TARGET_PPC64) 5195 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5196 5197 /* mfsr */ 5198 static void gen_mfsr_64b(DisasContext *ctx) 5199 { 5200 #if defined(CONFIG_USER_ONLY) 5201 GEN_PRIV(ctx); 5202 #else 5203 TCGv t0; 5204 5205 CHK_SV(ctx); 5206 t0 = tcg_constant_tl(SR(ctx->opcode)); 5207 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5208 #endif /* defined(CONFIG_USER_ONLY) */ 5209 } 5210 5211 /* mfsrin */ 5212 static void gen_mfsrin_64b(DisasContext *ctx) 5213 { 5214 #if defined(CONFIG_USER_ONLY) 5215 GEN_PRIV(ctx); 5216 #else 5217 TCGv t0; 5218 5219 CHK_SV(ctx); 5220 t0 = tcg_temp_new(); 5221 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5222 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5223 #endif /* defined(CONFIG_USER_ONLY) */ 5224 } 5225 5226 /* mtsr */ 5227 static void gen_mtsr_64b(DisasContext *ctx) 5228 { 5229 #if defined(CONFIG_USER_ONLY) 5230 GEN_PRIV(ctx); 5231 #else 5232 TCGv t0; 5233 5234 CHK_SV(ctx); 5235 t0 = tcg_constant_tl(SR(ctx->opcode)); 5236 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5237 #endif /* defined(CONFIG_USER_ONLY) */ 5238 } 5239 5240 /* mtsrin */ 5241 static void gen_mtsrin_64b(DisasContext *ctx) 5242 { 5243 #if defined(CONFIG_USER_ONLY) 5244 GEN_PRIV(ctx); 5245 #else 5246 TCGv t0; 5247 5248 CHK_SV(ctx); 5249 t0 = tcg_temp_new(); 5250 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5251 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5252 #endif /* defined(CONFIG_USER_ONLY) */ 5253 } 5254 5255 #endif /* defined(TARGET_PPC64) */ 5256 5257 /*** Lookaside buffer management ***/ 5258 /* Optional & supervisor only: */ 5259 5260 /* tlbia */ 5261 static void gen_tlbia(DisasContext *ctx) 5262 { 5263 #if defined(CONFIG_USER_ONLY) 5264 GEN_PRIV(ctx); 5265 #else 5266 CHK_HV(ctx); 5267 5268 gen_helper_tlbia(cpu_env); 5269 #endif /* defined(CONFIG_USER_ONLY) */ 5270 } 5271 5272 /* tlbsync */ 5273 static void gen_tlbsync(DisasContext *ctx) 5274 { 5275 #if defined(CONFIG_USER_ONLY) 5276 GEN_PRIV(ctx); 5277 #else 5278 5279 if (ctx->gtse) { 5280 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 5281 } else { 5282 CHK_HV(ctx); /* Else hypervisor privileged */ 5283 } 5284 5285 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5286 if (ctx->insns_flags & PPC_BOOKE) { 5287 gen_check_tlb_flush(ctx, true); 5288 } 5289 #endif /* defined(CONFIG_USER_ONLY) */ 5290 } 5291 5292 /*** External control ***/ 5293 /* Optional: */ 5294 5295 /* eciwx */ 5296 static void gen_eciwx(DisasContext *ctx) 5297 { 5298 TCGv t0; 5299 /* Should check EAR[E] ! */ 5300 gen_set_access_type(ctx, ACCESS_EXT); 5301 t0 = tcg_temp_new(); 5302 gen_addr_reg_index(ctx, t0); 5303 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5304 DEF_MEMOP(MO_UL | MO_ALIGN)); 5305 } 5306 5307 /* ecowx */ 5308 static void gen_ecowx(DisasContext *ctx) 5309 { 5310 TCGv t0; 5311 /* Should check EAR[E] ! */ 5312 gen_set_access_type(ctx, ACCESS_EXT); 5313 t0 = tcg_temp_new(); 5314 gen_addr_reg_index(ctx, t0); 5315 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5316 DEF_MEMOP(MO_UL | MO_ALIGN)); 5317 } 5318 5319 /* 602 - 603 - G2 TLB management */ 5320 5321 /* tlbld */ 5322 static void gen_tlbld_6xx(DisasContext *ctx) 5323 { 5324 #if defined(CONFIG_USER_ONLY) 5325 GEN_PRIV(ctx); 5326 #else 5327 CHK_SV(ctx); 5328 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5329 #endif /* defined(CONFIG_USER_ONLY) */ 5330 } 5331 5332 /* tlbli */ 5333 static void gen_tlbli_6xx(DisasContext *ctx) 5334 { 5335 #if defined(CONFIG_USER_ONLY) 5336 GEN_PRIV(ctx); 5337 #else 5338 CHK_SV(ctx); 5339 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5340 #endif /* defined(CONFIG_USER_ONLY) */ 5341 } 5342 5343 /* BookE specific instructions */ 5344 5345 /* XXX: not implemented on 440 ? */ 5346 static void gen_mfapidi(DisasContext *ctx) 5347 { 5348 /* XXX: TODO */ 5349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5350 } 5351 5352 /* XXX: not implemented on 440 ? */ 5353 static void gen_tlbiva(DisasContext *ctx) 5354 { 5355 #if defined(CONFIG_USER_ONLY) 5356 GEN_PRIV(ctx); 5357 #else 5358 TCGv t0; 5359 5360 CHK_SV(ctx); 5361 t0 = tcg_temp_new(); 5362 gen_addr_reg_index(ctx, t0); 5363 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364 #endif /* defined(CONFIG_USER_ONLY) */ 5365 } 5366 5367 /* All 405 MAC instructions are translated here */ 5368 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5369 int ra, int rb, int rt, int Rc) 5370 { 5371 TCGv t0, t1; 5372 5373 t0 = tcg_temp_new(); 5374 t1 = tcg_temp_new(); 5375 5376 switch (opc3 & 0x0D) { 5377 case 0x05: 5378 /* macchw - macchw. - macchwo - macchwo. */ 5379 /* macchws - macchws. - macchwso - macchwso. */ 5380 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5381 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5382 /* mulchw - mulchw. */ 5383 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5384 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5385 tcg_gen_ext16s_tl(t1, t1); 5386 break; 5387 case 0x04: 5388 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5389 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5390 /* mulchwu - mulchwu. */ 5391 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5392 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5393 tcg_gen_ext16u_tl(t1, t1); 5394 break; 5395 case 0x01: 5396 /* machhw - machhw. - machhwo - machhwo. */ 5397 /* machhws - machhws. - machhwso - machhwso. */ 5398 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5399 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5400 /* mulhhw - mulhhw. */ 5401 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5402 tcg_gen_ext16s_tl(t0, t0); 5403 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5404 tcg_gen_ext16s_tl(t1, t1); 5405 break; 5406 case 0x00: 5407 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5408 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5409 /* mulhhwu - mulhhwu. */ 5410 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5411 tcg_gen_ext16u_tl(t0, t0); 5412 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5413 tcg_gen_ext16u_tl(t1, t1); 5414 break; 5415 case 0x0D: 5416 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5417 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5418 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5419 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5420 /* mullhw - mullhw. */ 5421 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5422 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5423 break; 5424 case 0x0C: 5425 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5426 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5427 /* mullhwu - mullhwu. */ 5428 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5429 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5430 break; 5431 } 5432 if (opc2 & 0x04) { 5433 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5434 tcg_gen_mul_tl(t1, t0, t1); 5435 if (opc2 & 0x02) { 5436 /* nmultiply-and-accumulate (0x0E) */ 5437 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5438 } else { 5439 /* multiply-and-accumulate (0x0C) */ 5440 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5441 } 5442 5443 if (opc3 & 0x12) { 5444 /* Check overflow and/or saturate */ 5445 TCGLabel *l1 = gen_new_label(); 5446 5447 if (opc3 & 0x10) { 5448 /* Start with XER OV disabled, the most likely case */ 5449 tcg_gen_movi_tl(cpu_ov, 0); 5450 } 5451 if (opc3 & 0x01) { 5452 /* Signed */ 5453 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5454 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5455 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5456 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5457 if (opc3 & 0x02) { 5458 /* Saturate */ 5459 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5460 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5461 } 5462 } else { 5463 /* Unsigned */ 5464 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5465 if (opc3 & 0x02) { 5466 /* Saturate */ 5467 tcg_gen_movi_tl(t0, UINT32_MAX); 5468 } 5469 } 5470 if (opc3 & 0x10) { 5471 /* Check overflow */ 5472 tcg_gen_movi_tl(cpu_ov, 1); 5473 tcg_gen_movi_tl(cpu_so, 1); 5474 } 5475 gen_set_label(l1); 5476 tcg_gen_mov_tl(cpu_gpr[rt], t0); 5477 } 5478 } else { 5479 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5480 } 5481 if (unlikely(Rc) != 0) { 5482 /* Update Rc0 */ 5483 gen_set_Rc0(ctx, cpu_gpr[rt]); 5484 } 5485 } 5486 5487 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5488 static void glue(gen_, name)(DisasContext *ctx) \ 5489 { \ 5490 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5491 rD(ctx->opcode), Rc(ctx->opcode)); \ 5492 } 5493 5494 /* macchw - macchw. */ 5495 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5496 /* macchwo - macchwo. */ 5497 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5498 /* macchws - macchws. */ 5499 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5500 /* macchwso - macchwso. */ 5501 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5502 /* macchwsu - macchwsu. */ 5503 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5504 /* macchwsuo - macchwsuo. */ 5505 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5506 /* macchwu - macchwu. */ 5507 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5508 /* macchwuo - macchwuo. */ 5509 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5510 /* machhw - machhw. */ 5511 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5512 /* machhwo - machhwo. */ 5513 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5514 /* machhws - machhws. */ 5515 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5516 /* machhwso - machhwso. */ 5517 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5518 /* machhwsu - machhwsu. */ 5519 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5520 /* machhwsuo - machhwsuo. */ 5521 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5522 /* machhwu - machhwu. */ 5523 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5524 /* machhwuo - machhwuo. */ 5525 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5526 /* maclhw - maclhw. */ 5527 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5528 /* maclhwo - maclhwo. */ 5529 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5530 /* maclhws - maclhws. */ 5531 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5532 /* maclhwso - maclhwso. */ 5533 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5534 /* maclhwu - maclhwu. */ 5535 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5536 /* maclhwuo - maclhwuo. */ 5537 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5538 /* maclhwsu - maclhwsu. */ 5539 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5540 /* maclhwsuo - maclhwsuo. */ 5541 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5542 /* nmacchw - nmacchw. */ 5543 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5544 /* nmacchwo - nmacchwo. */ 5545 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5546 /* nmacchws - nmacchws. */ 5547 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5548 /* nmacchwso - nmacchwso. */ 5549 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5550 /* nmachhw - nmachhw. */ 5551 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5552 /* nmachhwo - nmachhwo. */ 5553 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5554 /* nmachhws - nmachhws. */ 5555 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5556 /* nmachhwso - nmachhwso. */ 5557 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5558 /* nmaclhw - nmaclhw. */ 5559 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5560 /* nmaclhwo - nmaclhwo. */ 5561 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5562 /* nmaclhws - nmaclhws. */ 5563 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5564 /* nmaclhwso - nmaclhwso. */ 5565 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5566 5567 /* mulchw - mulchw. */ 5568 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5569 /* mulchwu - mulchwu. */ 5570 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5571 /* mulhhw - mulhhw. */ 5572 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5573 /* mulhhwu - mulhhwu. */ 5574 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5575 /* mullhw - mullhw. */ 5576 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5577 /* mullhwu - mullhwu. */ 5578 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5579 5580 /* mfdcr */ 5581 static void gen_mfdcr(DisasContext *ctx) 5582 { 5583 #if defined(CONFIG_USER_ONLY) 5584 GEN_PRIV(ctx); 5585 #else 5586 TCGv dcrn; 5587 5588 CHK_SV(ctx); 5589 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5590 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5591 #endif /* defined(CONFIG_USER_ONLY) */ 5592 } 5593 5594 /* mtdcr */ 5595 static void gen_mtdcr(DisasContext *ctx) 5596 { 5597 #if defined(CONFIG_USER_ONLY) 5598 GEN_PRIV(ctx); 5599 #else 5600 TCGv dcrn; 5601 5602 CHK_SV(ctx); 5603 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5604 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5605 #endif /* defined(CONFIG_USER_ONLY) */ 5606 } 5607 5608 /* mfdcrx */ 5609 /* XXX: not implemented on 440 ? */ 5610 static void gen_mfdcrx(DisasContext *ctx) 5611 { 5612 #if defined(CONFIG_USER_ONLY) 5613 GEN_PRIV(ctx); 5614 #else 5615 CHK_SV(ctx); 5616 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5617 cpu_gpr[rA(ctx->opcode)]); 5618 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5619 #endif /* defined(CONFIG_USER_ONLY) */ 5620 } 5621 5622 /* mtdcrx */ 5623 /* XXX: not implemented on 440 ? */ 5624 static void gen_mtdcrx(DisasContext *ctx) 5625 { 5626 #if defined(CONFIG_USER_ONLY) 5627 GEN_PRIV(ctx); 5628 #else 5629 CHK_SV(ctx); 5630 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5631 cpu_gpr[rS(ctx->opcode)]); 5632 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5633 #endif /* defined(CONFIG_USER_ONLY) */ 5634 } 5635 5636 /* dccci */ 5637 static void gen_dccci(DisasContext *ctx) 5638 { 5639 CHK_SV(ctx); 5640 /* interpreted as no-op */ 5641 } 5642 5643 /* dcread */ 5644 static void gen_dcread(DisasContext *ctx) 5645 { 5646 #if defined(CONFIG_USER_ONLY) 5647 GEN_PRIV(ctx); 5648 #else 5649 TCGv EA, val; 5650 5651 CHK_SV(ctx); 5652 gen_set_access_type(ctx, ACCESS_CACHE); 5653 EA = tcg_temp_new(); 5654 gen_addr_reg_index(ctx, EA); 5655 val = tcg_temp_new(); 5656 gen_qemu_ld32u(ctx, val, EA); 5657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5658 #endif /* defined(CONFIG_USER_ONLY) */ 5659 } 5660 5661 /* icbt */ 5662 static void gen_icbt_40x(DisasContext *ctx) 5663 { 5664 /* 5665 * interpreted as no-op 5666 * XXX: specification say this is treated as a load by the MMU but 5667 * does not generate any exception 5668 */ 5669 } 5670 5671 /* iccci */ 5672 static void gen_iccci(DisasContext *ctx) 5673 { 5674 CHK_SV(ctx); 5675 /* interpreted as no-op */ 5676 } 5677 5678 /* icread */ 5679 static void gen_icread(DisasContext *ctx) 5680 { 5681 CHK_SV(ctx); 5682 /* interpreted as no-op */ 5683 } 5684 5685 /* rfci (supervisor only) */ 5686 static void gen_rfci_40x(DisasContext *ctx) 5687 { 5688 #if defined(CONFIG_USER_ONLY) 5689 GEN_PRIV(ctx); 5690 #else 5691 CHK_SV(ctx); 5692 /* Restore CPU state */ 5693 gen_helper_40x_rfci(cpu_env); 5694 ctx->base.is_jmp = DISAS_EXIT; 5695 #endif /* defined(CONFIG_USER_ONLY) */ 5696 } 5697 5698 static void gen_rfci(DisasContext *ctx) 5699 { 5700 #if defined(CONFIG_USER_ONLY) 5701 GEN_PRIV(ctx); 5702 #else 5703 CHK_SV(ctx); 5704 /* Restore CPU state */ 5705 gen_helper_rfci(cpu_env); 5706 ctx->base.is_jmp = DISAS_EXIT; 5707 #endif /* defined(CONFIG_USER_ONLY) */ 5708 } 5709 5710 /* BookE specific */ 5711 5712 /* XXX: not implemented on 440 ? */ 5713 static void gen_rfdi(DisasContext *ctx) 5714 { 5715 #if defined(CONFIG_USER_ONLY) 5716 GEN_PRIV(ctx); 5717 #else 5718 CHK_SV(ctx); 5719 /* Restore CPU state */ 5720 gen_helper_rfdi(cpu_env); 5721 ctx->base.is_jmp = DISAS_EXIT; 5722 #endif /* defined(CONFIG_USER_ONLY) */ 5723 } 5724 5725 /* XXX: not implemented on 440 ? */ 5726 static void gen_rfmci(DisasContext *ctx) 5727 { 5728 #if defined(CONFIG_USER_ONLY) 5729 GEN_PRIV(ctx); 5730 #else 5731 CHK_SV(ctx); 5732 /* Restore CPU state */ 5733 gen_helper_rfmci(cpu_env); 5734 ctx->base.is_jmp = DISAS_EXIT; 5735 #endif /* defined(CONFIG_USER_ONLY) */ 5736 } 5737 5738 /* TLB management - PowerPC 405 implementation */ 5739 5740 /* tlbre */ 5741 static void gen_tlbre_40x(DisasContext *ctx) 5742 { 5743 #if defined(CONFIG_USER_ONLY) 5744 GEN_PRIV(ctx); 5745 #else 5746 CHK_SV(ctx); 5747 switch (rB(ctx->opcode)) { 5748 case 0: 5749 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5750 cpu_gpr[rA(ctx->opcode)]); 5751 break; 5752 case 1: 5753 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5754 cpu_gpr[rA(ctx->opcode)]); 5755 break; 5756 default: 5757 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5758 break; 5759 } 5760 #endif /* defined(CONFIG_USER_ONLY) */ 5761 } 5762 5763 /* tlbsx - tlbsx. */ 5764 static void gen_tlbsx_40x(DisasContext *ctx) 5765 { 5766 #if defined(CONFIG_USER_ONLY) 5767 GEN_PRIV(ctx); 5768 #else 5769 TCGv t0; 5770 5771 CHK_SV(ctx); 5772 t0 = tcg_temp_new(); 5773 gen_addr_reg_index(ctx, t0); 5774 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5775 if (Rc(ctx->opcode)) { 5776 TCGLabel *l1 = gen_new_label(); 5777 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5778 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5779 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5780 gen_set_label(l1); 5781 } 5782 #endif /* defined(CONFIG_USER_ONLY) */ 5783 } 5784 5785 /* tlbwe */ 5786 static void gen_tlbwe_40x(DisasContext *ctx) 5787 { 5788 #if defined(CONFIG_USER_ONLY) 5789 GEN_PRIV(ctx); 5790 #else 5791 CHK_SV(ctx); 5792 5793 switch (rB(ctx->opcode)) { 5794 case 0: 5795 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5796 cpu_gpr[rS(ctx->opcode)]); 5797 break; 5798 case 1: 5799 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5800 cpu_gpr[rS(ctx->opcode)]); 5801 break; 5802 default: 5803 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5804 break; 5805 } 5806 #endif /* defined(CONFIG_USER_ONLY) */ 5807 } 5808 5809 /* TLB management - PowerPC 440 implementation */ 5810 5811 /* tlbre */ 5812 static void gen_tlbre_440(DisasContext *ctx) 5813 { 5814 #if defined(CONFIG_USER_ONLY) 5815 GEN_PRIV(ctx); 5816 #else 5817 CHK_SV(ctx); 5818 5819 switch (rB(ctx->opcode)) { 5820 case 0: 5821 case 1: 5822 case 2: 5823 { 5824 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5825 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5826 t0, cpu_gpr[rA(ctx->opcode)]); 5827 } 5828 break; 5829 default: 5830 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5831 break; 5832 } 5833 #endif /* defined(CONFIG_USER_ONLY) */ 5834 } 5835 5836 /* tlbsx - tlbsx. */ 5837 static void gen_tlbsx_440(DisasContext *ctx) 5838 { 5839 #if defined(CONFIG_USER_ONLY) 5840 GEN_PRIV(ctx); 5841 #else 5842 TCGv t0; 5843 5844 CHK_SV(ctx); 5845 t0 = tcg_temp_new(); 5846 gen_addr_reg_index(ctx, t0); 5847 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5848 if (Rc(ctx->opcode)) { 5849 TCGLabel *l1 = gen_new_label(); 5850 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5851 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5852 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5853 gen_set_label(l1); 5854 } 5855 #endif /* defined(CONFIG_USER_ONLY) */ 5856 } 5857 5858 /* tlbwe */ 5859 static void gen_tlbwe_440(DisasContext *ctx) 5860 { 5861 #if defined(CONFIG_USER_ONLY) 5862 GEN_PRIV(ctx); 5863 #else 5864 CHK_SV(ctx); 5865 switch (rB(ctx->opcode)) { 5866 case 0: 5867 case 1: 5868 case 2: 5869 { 5870 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5871 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5872 cpu_gpr[rS(ctx->opcode)]); 5873 } 5874 break; 5875 default: 5876 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5877 break; 5878 } 5879 #endif /* defined(CONFIG_USER_ONLY) */ 5880 } 5881 5882 /* TLB management - PowerPC BookE 2.06 implementation */ 5883 5884 /* tlbre */ 5885 static void gen_tlbre_booke206(DisasContext *ctx) 5886 { 5887 #if defined(CONFIG_USER_ONLY) 5888 GEN_PRIV(ctx); 5889 #else 5890 CHK_SV(ctx); 5891 gen_helper_booke206_tlbre(cpu_env); 5892 #endif /* defined(CONFIG_USER_ONLY) */ 5893 } 5894 5895 /* tlbsx - tlbsx. */ 5896 static void gen_tlbsx_booke206(DisasContext *ctx) 5897 { 5898 #if defined(CONFIG_USER_ONLY) 5899 GEN_PRIV(ctx); 5900 #else 5901 TCGv t0; 5902 5903 CHK_SV(ctx); 5904 if (rA(ctx->opcode)) { 5905 t0 = tcg_temp_new(); 5906 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5907 } else { 5908 t0 = cpu_gpr[rB(ctx->opcode)]; 5909 } 5910 gen_helper_booke206_tlbsx(cpu_env, t0); 5911 #endif /* defined(CONFIG_USER_ONLY) */ 5912 } 5913 5914 /* tlbwe */ 5915 static void gen_tlbwe_booke206(DisasContext *ctx) 5916 { 5917 #if defined(CONFIG_USER_ONLY) 5918 GEN_PRIV(ctx); 5919 #else 5920 CHK_SV(ctx); 5921 gen_helper_booke206_tlbwe(cpu_env); 5922 #endif /* defined(CONFIG_USER_ONLY) */ 5923 } 5924 5925 static void gen_tlbivax_booke206(DisasContext *ctx) 5926 { 5927 #if defined(CONFIG_USER_ONLY) 5928 GEN_PRIV(ctx); 5929 #else 5930 TCGv t0; 5931 5932 CHK_SV(ctx); 5933 t0 = tcg_temp_new(); 5934 gen_addr_reg_index(ctx, t0); 5935 gen_helper_booke206_tlbivax(cpu_env, t0); 5936 #endif /* defined(CONFIG_USER_ONLY) */ 5937 } 5938 5939 static void gen_tlbilx_booke206(DisasContext *ctx) 5940 { 5941 #if defined(CONFIG_USER_ONLY) 5942 GEN_PRIV(ctx); 5943 #else 5944 TCGv t0; 5945 5946 CHK_SV(ctx); 5947 t0 = tcg_temp_new(); 5948 gen_addr_reg_index(ctx, t0); 5949 5950 switch ((ctx->opcode >> 21) & 0x3) { 5951 case 0: 5952 gen_helper_booke206_tlbilx0(cpu_env, t0); 5953 break; 5954 case 1: 5955 gen_helper_booke206_tlbilx1(cpu_env, t0); 5956 break; 5957 case 3: 5958 gen_helper_booke206_tlbilx3(cpu_env, t0); 5959 break; 5960 default: 5961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5962 break; 5963 } 5964 #endif /* defined(CONFIG_USER_ONLY) */ 5965 } 5966 5967 /* wrtee */ 5968 static void gen_wrtee(DisasContext *ctx) 5969 { 5970 #if defined(CONFIG_USER_ONLY) 5971 GEN_PRIV(ctx); 5972 #else 5973 TCGv t0; 5974 5975 CHK_SV(ctx); 5976 t0 = tcg_temp_new(); 5977 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5978 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5979 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5980 gen_ppc_maybe_interrupt(ctx); 5981 /* 5982 * Stop translation to have a chance to raise an exception if we 5983 * just set msr_ee to 1 5984 */ 5985 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5986 #endif /* defined(CONFIG_USER_ONLY) */ 5987 } 5988 5989 /* wrteei */ 5990 static void gen_wrteei(DisasContext *ctx) 5991 { 5992 #if defined(CONFIG_USER_ONLY) 5993 GEN_PRIV(ctx); 5994 #else 5995 CHK_SV(ctx); 5996 if (ctx->opcode & 0x00008000) { 5997 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5998 gen_ppc_maybe_interrupt(ctx); 5999 /* Stop translation to have a chance to raise an exception */ 6000 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6001 } else { 6002 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6003 } 6004 #endif /* defined(CONFIG_USER_ONLY) */ 6005 } 6006 6007 /* PowerPC 440 specific instructions */ 6008 6009 /* dlmzb */ 6010 static void gen_dlmzb(DisasContext *ctx) 6011 { 6012 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6013 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6014 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6015 } 6016 6017 /* mbar replaces eieio on 440 */ 6018 static void gen_mbar(DisasContext *ctx) 6019 { 6020 /* interpreted as no-op */ 6021 } 6022 6023 /* msync replaces sync on 440 */ 6024 static void gen_msync_4xx(DisasContext *ctx) 6025 { 6026 /* Only e500 seems to treat reserved bits as invalid */ 6027 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6028 (ctx->opcode & 0x03FFF801)) { 6029 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6030 } 6031 /* otherwise interpreted as no-op */ 6032 } 6033 6034 /* icbt */ 6035 static void gen_icbt_440(DisasContext *ctx) 6036 { 6037 /* 6038 * interpreted as no-op 6039 * XXX: specification say this is treated as a load by the MMU but 6040 * does not generate any exception 6041 */ 6042 } 6043 6044 #if defined(TARGET_PPC64) 6045 static void gen_maddld(DisasContext *ctx) 6046 { 6047 TCGv_i64 t1 = tcg_temp_new_i64(); 6048 6049 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6050 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6051 } 6052 6053 /* maddhd maddhdu */ 6054 static void gen_maddhd_maddhdu(DisasContext *ctx) 6055 { 6056 TCGv_i64 lo = tcg_temp_new_i64(); 6057 TCGv_i64 hi = tcg_temp_new_i64(); 6058 TCGv_i64 t1 = tcg_temp_new_i64(); 6059 6060 if (Rc(ctx->opcode)) { 6061 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6062 cpu_gpr[rB(ctx->opcode)]); 6063 tcg_gen_movi_i64(t1, 0); 6064 } else { 6065 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6066 cpu_gpr[rB(ctx->opcode)]); 6067 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6068 } 6069 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6070 cpu_gpr[rC(ctx->opcode)], t1); 6071 } 6072 #endif /* defined(TARGET_PPC64) */ 6073 6074 static void gen_tbegin(DisasContext *ctx) 6075 { 6076 if (unlikely(!ctx->tm_enabled)) { 6077 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6078 return; 6079 } 6080 gen_helper_tbegin(cpu_env); 6081 } 6082 6083 #define GEN_TM_NOOP(name) \ 6084 static inline void gen_##name(DisasContext *ctx) \ 6085 { \ 6086 if (unlikely(!ctx->tm_enabled)) { \ 6087 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6088 return; \ 6089 } \ 6090 /* \ 6091 * Because tbegin always fails in QEMU, these user \ 6092 * space instructions all have a simple implementation: \ 6093 * \ 6094 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6095 * = 0b0 || 0b00 || 0b0 \ 6096 */ \ 6097 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6098 } 6099 6100 GEN_TM_NOOP(tend); 6101 GEN_TM_NOOP(tabort); 6102 GEN_TM_NOOP(tabortwc); 6103 GEN_TM_NOOP(tabortwci); 6104 GEN_TM_NOOP(tabortdc); 6105 GEN_TM_NOOP(tabortdci); 6106 GEN_TM_NOOP(tsr); 6107 6108 static inline void gen_cp_abort(DisasContext *ctx) 6109 { 6110 /* Do Nothing */ 6111 } 6112 6113 #define GEN_CP_PASTE_NOOP(name) \ 6114 static inline void gen_##name(DisasContext *ctx) \ 6115 { \ 6116 /* \ 6117 * Generate invalid exception until we have an \ 6118 * implementation of the copy paste facility \ 6119 */ \ 6120 gen_invalid(ctx); \ 6121 } 6122 6123 GEN_CP_PASTE_NOOP(copy) 6124 GEN_CP_PASTE_NOOP(paste) 6125 6126 static void gen_tcheck(DisasContext *ctx) 6127 { 6128 if (unlikely(!ctx->tm_enabled)) { 6129 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6130 return; 6131 } 6132 /* 6133 * Because tbegin always fails, the tcheck implementation is 6134 * simple: 6135 * 6136 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6137 * = 0b1 || 0b00 || 0b0 6138 */ 6139 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6140 } 6141 6142 #if defined(CONFIG_USER_ONLY) 6143 #define GEN_TM_PRIV_NOOP(name) \ 6144 static inline void gen_##name(DisasContext *ctx) \ 6145 { \ 6146 gen_priv_opc(ctx); \ 6147 } 6148 6149 #else 6150 6151 #define GEN_TM_PRIV_NOOP(name) \ 6152 static inline void gen_##name(DisasContext *ctx) \ 6153 { \ 6154 CHK_SV(ctx); \ 6155 if (unlikely(!ctx->tm_enabled)) { \ 6156 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6157 return; \ 6158 } \ 6159 /* \ 6160 * Because tbegin always fails, the implementation is \ 6161 * simple: \ 6162 * \ 6163 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6164 * = 0b0 || 0b00 | 0b0 \ 6165 */ \ 6166 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6167 } 6168 6169 #endif 6170 6171 GEN_TM_PRIV_NOOP(treclaim); 6172 GEN_TM_PRIV_NOOP(trechkpt); 6173 6174 static inline void get_fpr(TCGv_i64 dst, int regno) 6175 { 6176 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6177 } 6178 6179 static inline void set_fpr(int regno, TCGv_i64 src) 6180 { 6181 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6182 /* 6183 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 6184 * corresponding to the target FPR was undefined. However, 6185 * most (if not all) real hardware were setting the result to 0. 6186 * Starting at ISA v3.1, the result for doubleword 1 is now defined 6187 * to be 0. 6188 */ 6189 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 6190 } 6191 6192 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6193 { 6194 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6195 } 6196 6197 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6198 { 6199 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6200 } 6201 6202 /* 6203 * Helpers for decodetree used by !function for decoding arguments. 6204 */ 6205 static int times_2(DisasContext *ctx, int x) 6206 { 6207 return x * 2; 6208 } 6209 6210 static int times_4(DisasContext *ctx, int x) 6211 { 6212 return x * 4; 6213 } 6214 6215 static int times_16(DisasContext *ctx, int x) 6216 { 6217 return x * 16; 6218 } 6219 6220 static int64_t dw_compose_ea(DisasContext *ctx, int x) 6221 { 6222 return deposit64(0xfffffffffffffe00, 3, 6, x); 6223 } 6224 6225 /* 6226 * Helpers for trans_* functions to check for specific insns flags. 6227 * Use token pasting to ensure that we use the proper flag with the 6228 * proper variable. 6229 */ 6230 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6231 do { \ 6232 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6233 return false; \ 6234 } \ 6235 } while (0) 6236 6237 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6238 do { \ 6239 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6240 return false; \ 6241 } \ 6242 } while (0) 6243 6244 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6245 #if TARGET_LONG_BITS == 32 6246 # define REQUIRE_64BIT(CTX) return false 6247 #else 6248 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6249 #endif 6250 6251 #define REQUIRE_VECTOR(CTX) \ 6252 do { \ 6253 if (unlikely(!(CTX)->altivec_enabled)) { \ 6254 gen_exception((CTX), POWERPC_EXCP_VPU); \ 6255 return true; \ 6256 } \ 6257 } while (0) 6258 6259 #define REQUIRE_VSX(CTX) \ 6260 do { \ 6261 if (unlikely(!(CTX)->vsx_enabled)) { \ 6262 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 6263 return true; \ 6264 } \ 6265 } while (0) 6266 6267 #define REQUIRE_FPU(ctx) \ 6268 do { \ 6269 if (unlikely(!(ctx)->fpu_enabled)) { \ 6270 gen_exception((ctx), POWERPC_EXCP_FPU); \ 6271 return true; \ 6272 } \ 6273 } while (0) 6274 6275 #if !defined(CONFIG_USER_ONLY) 6276 #define REQUIRE_SV(CTX) \ 6277 do { \ 6278 if (unlikely((CTX)->pr)) { \ 6279 gen_priv_opc(CTX); \ 6280 return true; \ 6281 } \ 6282 } while (0) 6283 6284 #define REQUIRE_HV(CTX) \ 6285 do { \ 6286 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6287 gen_priv_opc(CTX); \ 6288 return true; \ 6289 } \ 6290 } while (0) 6291 #else 6292 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6293 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6294 #endif 6295 6296 /* 6297 * Helpers for implementing sets of trans_* functions. 6298 * Defer the implementation of NAME to FUNC, with optional extra arguments. 6299 */ 6300 #define TRANS(NAME, FUNC, ...) \ 6301 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6302 { return FUNC(ctx, a, __VA_ARGS__); } 6303 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 6304 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6305 { \ 6306 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 6307 return FUNC(ctx, a, __VA_ARGS__); \ 6308 } 6309 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6310 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6311 { \ 6312 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6313 return FUNC(ctx, a, __VA_ARGS__); \ 6314 } 6315 6316 #define TRANS64(NAME, FUNC, ...) \ 6317 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6318 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 6319 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 6320 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6321 { \ 6322 REQUIRE_64BIT(ctx); \ 6323 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 6324 return FUNC(ctx, a, __VA_ARGS__); \ 6325 } 6326 6327 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6328 6329 6330 #include "decode-insn32.c.inc" 6331 #include "decode-insn64.c.inc" 6332 #include "power8-pmu-regs.c.inc" 6333 6334 /* 6335 * Incorporate CIA into the constant when R=1. 6336 * Validate that when R=1, RA=0. 6337 */ 6338 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6339 { 6340 d->rt = a->rt; 6341 d->ra = a->ra; 6342 d->si = a->si; 6343 if (a->r) { 6344 if (unlikely(a->ra != 0)) { 6345 gen_invalid(ctx); 6346 return false; 6347 } 6348 d->si += ctx->cia; 6349 } 6350 return true; 6351 } 6352 6353 #include "translate/fixedpoint-impl.c.inc" 6354 6355 #include "translate/fp-impl.c.inc" 6356 6357 #include "translate/vmx-impl.c.inc" 6358 6359 #include "translate/vsx-impl.c.inc" 6360 6361 #include "translate/dfp-impl.c.inc" 6362 6363 #include "translate/spe-impl.c.inc" 6364 6365 #include "translate/branch-impl.c.inc" 6366 6367 #include "translate/processor-ctrl-impl.c.inc" 6368 6369 #include "translate/storage-ctrl-impl.c.inc" 6370 6371 /* Handles lfdp */ 6372 static void gen_dform39(DisasContext *ctx) 6373 { 6374 if ((ctx->opcode & 0x3) == 0) { 6375 if (ctx->insns_flags2 & PPC2_ISA205) { 6376 return gen_lfdp(ctx); 6377 } 6378 } 6379 return gen_invalid(ctx); 6380 } 6381 6382 /* Handles stfdp */ 6383 static void gen_dform3D(DisasContext *ctx) 6384 { 6385 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 6386 /* stfdp */ 6387 if (ctx->insns_flags2 & PPC2_ISA205) { 6388 return gen_stfdp(ctx); 6389 } 6390 } 6391 return gen_invalid(ctx); 6392 } 6393 6394 #if defined(TARGET_PPC64) 6395 /* brd */ 6396 static void gen_brd(DisasContext *ctx) 6397 { 6398 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6399 } 6400 6401 /* brw */ 6402 static void gen_brw(DisasContext *ctx) 6403 { 6404 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6405 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6406 6407 } 6408 6409 /* brh */ 6410 static void gen_brh(DisasContext *ctx) 6411 { 6412 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 6413 TCGv_i64 t1 = tcg_temp_new_i64(); 6414 TCGv_i64 t2 = tcg_temp_new_i64(); 6415 6416 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6417 tcg_gen_and_i64(t2, t1, mask); 6418 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 6419 tcg_gen_shli_i64(t1, t1, 8); 6420 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 6421 } 6422 #endif 6423 6424 static opcode_t opcodes[] = { 6425 #if defined(TARGET_PPC64) 6426 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 6427 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 6428 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 6429 #endif 6430 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6431 #if defined(TARGET_PPC64) 6432 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6433 #endif 6434 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6435 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6436 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6437 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6438 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6439 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6440 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6441 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6442 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6443 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6444 #if defined(TARGET_PPC64) 6445 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6446 #endif 6447 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6448 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6449 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6452 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6453 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6454 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6455 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6456 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6457 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6458 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6459 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6460 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6461 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6462 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6463 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6464 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6465 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6466 #if defined(TARGET_PPC64) 6467 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6468 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6469 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6470 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6471 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6472 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6473 #endif 6474 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6475 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6476 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6477 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6478 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6479 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6480 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6481 #if defined(TARGET_PPC64) 6482 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6483 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6484 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6485 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6486 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6487 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6488 PPC_NONE, PPC2_ISA300), 6489 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6490 PPC_NONE, PPC2_ISA300), 6491 #endif 6492 /* handles lfdp, lxsd, lxssp */ 6493 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6494 /* handles stfdp, stxsd, stxssp */ 6495 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6496 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6497 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6498 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6499 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6500 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6501 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6502 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6503 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6504 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6505 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6506 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6507 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6508 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6509 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6510 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6511 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6512 #if defined(TARGET_PPC64) 6513 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6514 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6515 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6516 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6517 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6518 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6519 #endif 6520 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6521 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 6522 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 6523 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6524 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6525 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6526 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6527 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6528 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6529 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6530 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6531 #if defined(TARGET_PPC64) 6532 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6533 #if !defined(CONFIG_USER_ONLY) 6534 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6535 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6536 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 6537 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 6538 #endif 6539 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6540 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6541 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6542 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6543 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6544 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6545 #endif 6546 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 6547 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 6548 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6549 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6550 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6551 #if defined(TARGET_PPC64) 6552 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6553 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6554 #endif 6555 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6556 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6557 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6558 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6559 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6560 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6561 #if defined(TARGET_PPC64) 6562 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6563 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6564 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6565 #endif 6566 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6567 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6568 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6569 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6570 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6571 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6572 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6573 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6574 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6575 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6576 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6577 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6578 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6579 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6580 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6581 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6582 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6583 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6584 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6585 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6586 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6587 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6588 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6589 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6590 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6591 #if defined(TARGET_PPC64) 6592 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6593 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6594 PPC_SEGMENT_64B), 6595 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6596 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6597 PPC_SEGMENT_64B), 6598 #endif 6599 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6600 /* 6601 * XXX Those instructions will need to be handled differently for 6602 * different ISA versions 6603 */ 6604 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6605 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6606 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6607 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6608 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6609 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6610 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6611 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6612 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6613 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6614 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6615 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6616 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6617 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6618 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6619 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6620 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6621 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6622 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6623 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6624 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6625 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6626 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6627 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6628 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6629 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6630 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6631 PPC_NONE, PPC2_BOOKE206), 6632 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6633 PPC_NONE, PPC2_BOOKE206), 6634 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6635 PPC_NONE, PPC2_BOOKE206), 6636 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6637 PPC_NONE, PPC2_BOOKE206), 6638 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6639 PPC_NONE, PPC2_BOOKE206), 6640 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6641 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6642 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6643 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6644 PPC_BOOKE, PPC2_BOOKE206), 6645 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6646 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6647 PPC_BOOKE, PPC2_BOOKE206), 6648 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 6649 PPC_440_SPEC), 6650 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6651 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6652 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6653 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6654 #if defined(TARGET_PPC64) 6655 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6656 PPC2_ISA300), 6657 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6658 #endif 6659 6660 #undef GEN_INT_ARITH_ADD 6661 #undef GEN_INT_ARITH_ADD_CONST 6662 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6663 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6664 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6665 add_ca, compute_ca, compute_ov) \ 6666 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6667 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6668 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6669 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6670 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6671 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6672 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6673 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6674 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6675 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6676 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6677 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6678 6679 #undef GEN_INT_ARITH_DIVW 6680 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6681 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6682 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6683 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6684 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6685 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6686 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6687 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6688 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6689 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6690 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6691 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6692 6693 #if defined(TARGET_PPC64) 6694 #undef GEN_INT_ARITH_DIVD 6695 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6696 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6697 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6698 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6699 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6700 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6701 6702 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6703 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6704 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6705 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6706 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6707 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6708 6709 #undef GEN_INT_ARITH_MUL_HELPER 6710 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6711 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6712 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6713 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6714 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6715 #endif 6716 6717 #undef GEN_INT_ARITH_SUBF 6718 #undef GEN_INT_ARITH_SUBF_CONST 6719 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6720 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6721 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6722 add_ca, compute_ca, compute_ov) \ 6723 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6724 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6725 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6726 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6727 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6728 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6729 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6730 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6731 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6732 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6733 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6734 6735 #undef GEN_LOGICAL1 6736 #undef GEN_LOGICAL2 6737 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6738 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6739 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6740 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6741 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6742 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6743 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6744 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6745 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6746 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6747 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6748 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6749 #if defined(TARGET_PPC64) 6750 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6751 #endif 6752 6753 #if defined(TARGET_PPC64) 6754 #undef GEN_PPC64_R2 6755 #undef GEN_PPC64_R4 6756 #define GEN_PPC64_R2(name, opc1, opc2) \ 6757 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6758 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6759 PPC_64B) 6760 #define GEN_PPC64_R4(name, opc1, opc2) \ 6761 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6762 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6763 PPC_64B), \ 6764 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6765 PPC_64B), \ 6766 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6767 PPC_64B) 6768 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6769 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6770 GEN_PPC64_R4(rldic, 0x1E, 0x04), 6771 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6772 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6773 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6774 #endif 6775 6776 #undef GEN_LDX_E 6777 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6778 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6779 6780 #if defined(TARGET_PPC64) 6781 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6782 6783 /* HV/P7 and later only */ 6784 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6785 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6786 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6787 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6788 #endif 6789 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6790 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6791 6792 /* External PID based load */ 6793 #undef GEN_LDEPX 6794 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6795 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6796 0x00000001, PPC_NONE, PPC2_BOOKE206), 6797 6798 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6799 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6800 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6801 #if defined(TARGET_PPC64) 6802 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6803 #endif 6804 6805 #undef GEN_STX_E 6806 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6807 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6808 6809 #if defined(TARGET_PPC64) 6810 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6811 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6812 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6813 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6814 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6815 #endif 6816 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6817 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6818 6819 #undef GEN_STEPX 6820 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6821 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6822 0x00000001, PPC_NONE, PPC2_BOOKE206), 6823 6824 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6825 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6826 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6827 #if defined(TARGET_PPC64) 6828 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6829 #endif 6830 6831 #undef GEN_CRLOGIC 6832 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6833 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6834 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6835 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6836 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6837 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6838 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6839 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6840 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6841 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6842 6843 #undef GEN_MAC_HANDLER 6844 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6845 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6846 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6847 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6848 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6849 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6850 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6851 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6852 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6853 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6854 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6855 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6856 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6857 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6858 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6859 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6860 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6861 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6862 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6863 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6864 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6865 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6866 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6867 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6868 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6869 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6870 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6871 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6872 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6873 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6874 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6875 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6876 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6877 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6878 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6879 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6880 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6881 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6882 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6883 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6884 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6885 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6886 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6887 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6888 6889 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6890 PPC_NONE, PPC2_TM), 6891 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6892 PPC_NONE, PPC2_TM), 6893 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6894 PPC_NONE, PPC2_TM), 6895 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6896 PPC_NONE, PPC2_TM), 6897 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6898 PPC_NONE, PPC2_TM), 6899 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6900 PPC_NONE, PPC2_TM), 6901 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6902 PPC_NONE, PPC2_TM), 6903 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6904 PPC_NONE, PPC2_TM), 6905 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6906 PPC_NONE, PPC2_TM), 6907 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6908 PPC_NONE, PPC2_TM), 6909 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6910 PPC_NONE, PPC2_TM), 6911 6912 #include "translate/fp-ops.c.inc" 6913 6914 #include "translate/vmx-ops.c.inc" 6915 6916 #include "translate/vsx-ops.c.inc" 6917 6918 #include "translate/spe-ops.c.inc" 6919 }; 6920 6921 /*****************************************************************************/ 6922 /* Opcode types */ 6923 enum { 6924 PPC_DIRECT = 0, /* Opcode routine */ 6925 PPC_INDIRECT = 1, /* Indirect opcode table */ 6926 }; 6927 6928 #define PPC_OPCODE_MASK 0x3 6929 6930 static inline int is_indirect_opcode(void *handler) 6931 { 6932 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6933 } 6934 6935 static inline opc_handler_t **ind_table(void *handler) 6936 { 6937 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6938 } 6939 6940 /* Instruction table creation */ 6941 /* Opcodes tables creation */ 6942 static void fill_new_table(opc_handler_t **table, int len) 6943 { 6944 int i; 6945 6946 for (i = 0; i < len; i++) { 6947 table[i] = &invalid_handler; 6948 } 6949 } 6950 6951 static int create_new_table(opc_handler_t **table, unsigned char idx) 6952 { 6953 opc_handler_t **tmp; 6954 6955 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6956 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6957 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6958 6959 return 0; 6960 } 6961 6962 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6963 opc_handler_t *handler) 6964 { 6965 if (table[idx] != &invalid_handler) { 6966 return -1; 6967 } 6968 table[idx] = handler; 6969 6970 return 0; 6971 } 6972 6973 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6974 unsigned char idx, opc_handler_t *handler) 6975 { 6976 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6977 printf("*** ERROR: opcode %02x already assigned in main " 6978 "opcode table\n", idx); 6979 return -1; 6980 } 6981 6982 return 0; 6983 } 6984 6985 static int register_ind_in_table(opc_handler_t **table, 6986 unsigned char idx1, unsigned char idx2, 6987 opc_handler_t *handler) 6988 { 6989 if (table[idx1] == &invalid_handler) { 6990 if (create_new_table(table, idx1) < 0) { 6991 printf("*** ERROR: unable to create indirect table " 6992 "idx=%02x\n", idx1); 6993 return -1; 6994 } 6995 } else { 6996 if (!is_indirect_opcode(table[idx1])) { 6997 printf("*** ERROR: idx %02x already assigned to a direct " 6998 "opcode\n", idx1); 6999 return -1; 7000 } 7001 } 7002 if (handler != NULL && 7003 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7004 printf("*** ERROR: opcode %02x already assigned in " 7005 "opcode table %02x\n", idx2, idx1); 7006 return -1; 7007 } 7008 7009 return 0; 7010 } 7011 7012 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7013 unsigned char idx1, unsigned char idx2, 7014 opc_handler_t *handler) 7015 { 7016 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7017 } 7018 7019 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7020 unsigned char idx1, unsigned char idx2, 7021 unsigned char idx3, opc_handler_t *handler) 7022 { 7023 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7024 printf("*** ERROR: unable to join indirect table idx " 7025 "[%02x-%02x]\n", idx1, idx2); 7026 return -1; 7027 } 7028 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7029 handler) < 0) { 7030 printf("*** ERROR: unable to insert opcode " 7031 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7032 return -1; 7033 } 7034 7035 return 0; 7036 } 7037 7038 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7039 unsigned char idx1, unsigned char idx2, 7040 unsigned char idx3, unsigned char idx4, 7041 opc_handler_t *handler) 7042 { 7043 opc_handler_t **table; 7044 7045 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7046 printf("*** ERROR: unable to join indirect table idx " 7047 "[%02x-%02x]\n", idx1, idx2); 7048 return -1; 7049 } 7050 table = ind_table(ppc_opcodes[idx1]); 7051 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7052 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7053 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7054 return -1; 7055 } 7056 table = ind_table(table[idx2]); 7057 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7058 printf("*** ERROR: unable to insert opcode " 7059 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7060 return -1; 7061 } 7062 return 0; 7063 } 7064 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7065 { 7066 if (insn->opc2 != 0xFF) { 7067 if (insn->opc3 != 0xFF) { 7068 if (insn->opc4 != 0xFF) { 7069 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7070 insn->opc3, insn->opc4, 7071 &insn->handler) < 0) { 7072 return -1; 7073 } 7074 } else { 7075 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7076 insn->opc3, &insn->handler) < 0) { 7077 return -1; 7078 } 7079 } 7080 } else { 7081 if (register_ind_insn(ppc_opcodes, insn->opc1, 7082 insn->opc2, &insn->handler) < 0) { 7083 return -1; 7084 } 7085 } 7086 } else { 7087 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 7088 return -1; 7089 } 7090 } 7091 7092 return 0; 7093 } 7094 7095 static int test_opcode_table(opc_handler_t **table, int len) 7096 { 7097 int i, count, tmp; 7098 7099 for (i = 0, count = 0; i < len; i++) { 7100 /* Consistency fixup */ 7101 if (table[i] == NULL) { 7102 table[i] = &invalid_handler; 7103 } 7104 if (table[i] != &invalid_handler) { 7105 if (is_indirect_opcode(table[i])) { 7106 tmp = test_opcode_table(ind_table(table[i]), 7107 PPC_CPU_INDIRECT_OPCODES_LEN); 7108 if (tmp == 0) { 7109 free(table[i]); 7110 table[i] = &invalid_handler; 7111 } else { 7112 count++; 7113 } 7114 } else { 7115 count++; 7116 } 7117 } 7118 } 7119 7120 return count; 7121 } 7122 7123 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 7124 { 7125 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 7126 printf("*** WARNING: no opcode defined !\n"); 7127 } 7128 } 7129 7130 /*****************************************************************************/ 7131 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 7132 { 7133 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7134 opcode_t *opc; 7135 7136 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 7137 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 7138 if (((opc->handler.type & pcc->insns_flags) != 0) || 7139 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 7140 if (register_insn(cpu->opcodes, opc) < 0) { 7141 error_setg(errp, "ERROR initializing PowerPC instruction " 7142 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 7143 opc->opc3); 7144 return; 7145 } 7146 } 7147 } 7148 fix_opcode_tables(cpu->opcodes); 7149 fflush(stdout); 7150 fflush(stderr); 7151 } 7152 7153 void destroy_ppc_opcodes(PowerPCCPU *cpu) 7154 { 7155 opc_handler_t **table, **table_2; 7156 int i, j, k; 7157 7158 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 7159 if (cpu->opcodes[i] == &invalid_handler) { 7160 continue; 7161 } 7162 if (is_indirect_opcode(cpu->opcodes[i])) { 7163 table = ind_table(cpu->opcodes[i]); 7164 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 7165 if (table[j] == &invalid_handler) { 7166 continue; 7167 } 7168 if (is_indirect_opcode(table[j])) { 7169 table_2 = ind_table(table[j]); 7170 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 7171 if (table_2[k] != &invalid_handler && 7172 is_indirect_opcode(table_2[k])) { 7173 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 7174 ~PPC_INDIRECT)); 7175 } 7176 } 7177 g_free((opc_handler_t *)((uintptr_t)table[j] & 7178 ~PPC_INDIRECT)); 7179 } 7180 } 7181 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 7182 ~PPC_INDIRECT)); 7183 } 7184 } 7185 } 7186 7187 int ppc_fixup_cpu(PowerPCCPU *cpu) 7188 { 7189 CPUPPCState *env = &cpu->env; 7190 7191 /* 7192 * TCG doesn't (yet) emulate some groups of instructions that are 7193 * implemented on some otherwise supported CPUs (e.g. VSX and 7194 * decimal floating point instructions on POWER7). We remove 7195 * unsupported instruction groups from the cpu state's instruction 7196 * masks and hope the guest can cope. For at least the pseries 7197 * machine, the unavailability of these instructions can be 7198 * advertised to the guest via the device tree. 7199 */ 7200 if ((env->insns_flags & ~PPC_TCG_INSNS) 7201 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 7202 warn_report("Disabling some instructions which are not " 7203 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 7204 env->insns_flags & ~PPC_TCG_INSNS, 7205 env->insns_flags2 & ~PPC_TCG_INSNS2); 7206 } 7207 env->insns_flags &= PPC_TCG_INSNS; 7208 env->insns_flags2 &= PPC_TCG_INSNS2; 7209 return 0; 7210 } 7211 7212 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7213 { 7214 opc_handler_t **table, *handler; 7215 uint32_t inval; 7216 7217 ctx->opcode = insn; 7218 7219 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7220 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7221 ctx->le_mode ? "little" : "big"); 7222 7223 table = cpu->opcodes; 7224 handler = table[opc1(insn)]; 7225 if (is_indirect_opcode(handler)) { 7226 table = ind_table(handler); 7227 handler = table[opc2(insn)]; 7228 if (is_indirect_opcode(handler)) { 7229 table = ind_table(handler); 7230 handler = table[opc3(insn)]; 7231 if (is_indirect_opcode(handler)) { 7232 table = ind_table(handler); 7233 handler = table[opc4(insn)]; 7234 } 7235 } 7236 } 7237 7238 /* Is opcode *REALLY* valid ? */ 7239 if (unlikely(handler->handler == &gen_invalid)) { 7240 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7241 "%02x - %02x - %02x - %02x (%08x) " 7242 TARGET_FMT_lx "\n", 7243 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7244 insn, ctx->cia); 7245 return false; 7246 } 7247 7248 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7249 && Rc(insn))) { 7250 inval = handler->inval2; 7251 } else { 7252 inval = handler->inval1; 7253 } 7254 7255 if (unlikely((insn & inval) != 0)) { 7256 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7257 "%02x - %02x - %02x - %02x (%08x) " 7258 TARGET_FMT_lx "\n", insn & inval, 7259 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7260 insn, ctx->cia); 7261 return false; 7262 } 7263 7264 handler->handler(ctx); 7265 return true; 7266 } 7267 7268 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7269 { 7270 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7271 CPUPPCState *env = cs->env_ptr; 7272 uint32_t hflags = ctx->base.tb->flags; 7273 7274 ctx->spr_cb = env->spr_cb; 7275 ctx->pr = (hflags >> HFLAGS_PR) & 1; 7276 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 7277 ctx->dr = (hflags >> HFLAGS_DR) & 1; 7278 ctx->hv = (hflags >> HFLAGS_HV) & 1; 7279 ctx->insns_flags = env->insns_flags; 7280 ctx->insns_flags2 = env->insns_flags2; 7281 ctx->access_type = -1; 7282 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7283 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7284 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7285 ctx->flags = env->flags; 7286 #if defined(TARGET_PPC64) 7287 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7288 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7289 #endif 7290 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7291 || env->mmu_model & POWERPC_MMU_64; 7292 7293 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7294 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7295 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7296 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 7297 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7298 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 7299 ctx->hr = (hflags >> HFLAGS_HR) & 1; 7300 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7301 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 7302 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 7303 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 7304 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 7305 7306 ctx->singlestep_enabled = 0; 7307 if ((hflags >> HFLAGS_SE) & 1) { 7308 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7309 ctx->base.max_insns = 1; 7310 } 7311 if ((hflags >> HFLAGS_BE) & 1) { 7312 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7313 } 7314 } 7315 7316 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7317 { 7318 } 7319 7320 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7321 { 7322 tcg_gen_insn_start(dcbase->pc_next); 7323 } 7324 7325 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 7326 { 7327 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 7328 return opc1(insn) == 1; 7329 } 7330 7331 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7332 { 7333 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7334 PowerPCCPU *cpu = POWERPC_CPU(cs); 7335 CPUPPCState *env = cs->env_ptr; 7336 target_ulong pc; 7337 uint32_t insn; 7338 bool ok; 7339 7340 LOG_DISAS("----------------\n"); 7341 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7342 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7343 7344 ctx->cia = pc = ctx->base.pc_next; 7345 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 7346 ctx->base.pc_next = pc += 4; 7347 7348 if (!is_prefix_insn(ctx, insn)) { 7349 ok = (decode_insn32(ctx, insn) || 7350 decode_legacy(cpu, ctx, insn)); 7351 } else if ((pc & 63) == 0) { 7352 /* 7353 * Power v3.1, section 1.9 Exceptions: 7354 * attempt to execute a prefixed instruction that crosses a 7355 * 64-byte address boundary (system alignment error). 7356 */ 7357 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 7358 ok = true; 7359 } else { 7360 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 7361 need_byteswap(ctx)); 7362 ctx->base.pc_next = pc += 4; 7363 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 7364 } 7365 if (!ok) { 7366 gen_invalid(ctx); 7367 } 7368 7369 /* End the TB when crossing a page boundary. */ 7370 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 7371 ctx->base.is_jmp = DISAS_TOO_MANY; 7372 } 7373 } 7374 7375 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7376 { 7377 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7378 DisasJumpType is_jmp = ctx->base.is_jmp; 7379 target_ulong nip = ctx->base.pc_next; 7380 7381 if (is_jmp == DISAS_NORETURN) { 7382 /* We have already exited the TB. */ 7383 return; 7384 } 7385 7386 /* Honor single stepping. */ 7387 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 7388 && (nip <= 0x100 || nip > 0xf00)) { 7389 switch (is_jmp) { 7390 case DISAS_TOO_MANY: 7391 case DISAS_EXIT_UPDATE: 7392 case DISAS_CHAIN_UPDATE: 7393 gen_update_nip(ctx, nip); 7394 break; 7395 case DISAS_EXIT: 7396 case DISAS_CHAIN: 7397 break; 7398 default: 7399 g_assert_not_reached(); 7400 } 7401 7402 gen_debug_exception(ctx); 7403 return; 7404 } 7405 7406 switch (is_jmp) { 7407 case DISAS_TOO_MANY: 7408 if (use_goto_tb(ctx, nip)) { 7409 pmu_count_insns(ctx); 7410 tcg_gen_goto_tb(0); 7411 gen_update_nip(ctx, nip); 7412 tcg_gen_exit_tb(ctx->base.tb, 0); 7413 break; 7414 } 7415 /* fall through */ 7416 case DISAS_CHAIN_UPDATE: 7417 gen_update_nip(ctx, nip); 7418 /* fall through */ 7419 case DISAS_CHAIN: 7420 /* 7421 * tcg_gen_lookup_and_goto_ptr will exit the TB if 7422 * CF_NO_GOTO_PTR is set. Count insns now. 7423 */ 7424 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 7425 pmu_count_insns(ctx); 7426 } 7427 7428 tcg_gen_lookup_and_goto_ptr(); 7429 break; 7430 7431 case DISAS_EXIT_UPDATE: 7432 gen_update_nip(ctx, nip); 7433 /* fall through */ 7434 case DISAS_EXIT: 7435 pmu_count_insns(ctx); 7436 tcg_gen_exit_tb(NULL, 0); 7437 break; 7438 7439 default: 7440 g_assert_not_reached(); 7441 } 7442 } 7443 7444 static void ppc_tr_disas_log(const DisasContextBase *dcbase, 7445 CPUState *cs, FILE *logfile) 7446 { 7447 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 7448 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7449 } 7450 7451 static const TranslatorOps ppc_tr_ops = { 7452 .init_disas_context = ppc_tr_init_disas_context, 7453 .tb_start = ppc_tr_tb_start, 7454 .insn_start = ppc_tr_insn_start, 7455 .translate_insn = ppc_tr_translate_insn, 7456 .tb_stop = ppc_tr_tb_stop, 7457 .disas_log = ppc_tr_disas_log, 7458 }; 7459 7460 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7461 target_ulong pc, void *host_pc) 7462 { 7463 DisasContext ctx; 7464 7465 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7466 } 7467