arm64: tegra: Add XUDC node for Tegra186

Tegra186 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Signed-off-by: Nagarju

arm64: tegra: Add XUDC node for Tegra186

Tegra186 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Make XUSB node consistent with the rest

The ordering of properties in the XUSB node is inconsistent with the
ordering of the properties in other nodes. Resort them to make the node
mor

arm64: tegra: Make XUSB node consistent with the rest

The ordering of properties in the XUSB node is inconsistent with the
ordering of the properties in other nodes. Resort them to make the node
more consistent. Also get rid of some unnecessary whitespace.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add external memory controller on Tegra186

Add the external memory controller as a child device of the memory
controller on Tegra186. The memory controller really represents the
memory

arm64: tegra: Add external memory controller on Tegra186

Add the external memory controller as a child device of the memory
controller on Tegra186. The memory controller really represents the
memory subsystem that encompasses both the memory and external memory
controllers. The external memory controller uses the BPMP to obtain the
list of supported EMC frequencies and set the EMC frequency.

Also set up the dma-ranges property to describe that all memory clients
can address up to 40 bits using the memory controller client interface
(MCCIF), unless otherwise limited by the DMA engines of the hardware.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt for memory controller on Tegra186

The memory controller can be interrupted by certain conditions. Add the
interrupt to the device tree node to allow drivers to trap these

arm64: tegra: Add interrupt for memory controller on Tegra186

The memory controller can be interrupted by certain conditions. Add the
interrupt to the device tree node to allow drivers to trap these
conditions.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix compatible for SOR1

It turns out that both SORs on Tegra186 are the same, so there's no need
to distinguish between them in the compatible string.

Signed-off-by: Thierry Reding <t

arm64: tegra: Fix compatible for SOR1

It turns out that both SORs on Tegra186 are the same, so there's no need
to distinguish between them in the compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable SMMU for VIC on Tegra186

Enable address translation for VIC via the SMMU on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Enable SMMU for XUSB host on Tegra186

Enabling the SMMU for XUSB host allows buffers to be mapped through the
ARM SMMU, which helps protecting the system from rogue memory accesses
by

arm64: tegra: Enable SMMU for XUSB host on Tegra186

Enabling the SMMU for XUSB host allows buffers to be mapped through the
ARM SMMU, which helps protecting the system from rogue memory accesses
by the XUSB host.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon

arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Sort device tree nodes alphabetically

Device tree nodes without unit-address are to be sorted alphabetically.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
alwa

arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
always on.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add pin control states for I2C on Tegra186

Two of the Tegra I2C controllers share pads with the DPAUX controllers.
In order for the I2C controllers to use these pads, they have to be s

arm64: tegra: Add pin control states for I2C on Tegra186

Two of the Tegra I2C controllers share pads with the DPAUX controllers.
In order for the I2C controllers to use these pads, they have to be set
into I2C mode. Use the I2C and off pin control states defined in the DT
nodes for DPAUX as "default" and "idle" states, respectively. This
ensures that the I2C controller driver can properly configure the pins
when it needs to perform I2C transactions.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU cache topology for Tegra186

Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.

Signed-off-by: Jos

arm64: tegra: Add CPU cache topology for Tegra186

Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable SMMU translation for PCI on Tegra186

Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling
bypass by default") intentionally breaks all devices using the SMMU

arm64: tegra: Enable SMMU translation for PCI on Tegra186

Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling
bypass by default") intentionally breaks all devices using the SMMU in
bypass mode. This breaks, among other things, PCI support on Tegra186.
Fix this by populating the iommus property and friends for the PCIe
controller.

Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default")
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix insecure SMMU users for Tegra186

Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling
bypass by default") intentionally breaks all devices using the SMMU in
bypa

arm64: tegra: Fix insecure SMMU users for Tegra186

Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling
bypass by default") intentionally breaks all devices using the SMMU in
bypass mode. This is breaking various devices on Tegra186 which include
the ethernet, BPMP and HDA device. Fix this by populating the iommus
property for these devices with their stream ID.

Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default")
Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUSB and pad controller on Tegra186

Adds the XUSB pad and XUSB controllers on Tegra186.

Reviewed-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Enable command queue for Tegra186 SDMMC4

The workaround for a hardware bug preventing this from working has been
merged now, so command queue support can be enabled again for Tegra186.

arm64: tegra: Enable command queue for Tegra186 SDMMC4

The workaround for a hardware bug preventing this from working has been
merged now, so command queue support can be enabled again for Tegra186.

Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix default tap and trim values

Default tap and trim values are incorrect for Tegra186 SDMMC4. This
patch fixes them.

Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowja

arm64: tegra: Fix default tap and trim values

Default tap and trim values are incorrect for Tegra186 SDMMC4. This
patch fixes them.

Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Disable CQE Support for SDMMC4 on Tegra186

Enabling CQE support on Tegra186 Jetson TX2 has introduced a regression
that is causing accesses to the file-system on the eMMC to fail. Erro

arm64: tegra: Disable CQE Support for SDMMC4 on Tegra186

Enabling CQE support on Tegra186 Jetson TX2 has introduced a regression
that is causing accesses to the file-system on the eMMC to fail. Errors
such as the following have been observed ...

mmc2: running CQE recovery
mmc2: mmc_select_hs400 failed, error -110
print_req_error: I/O error, dev mmcblk2, sector 8 flags 80700
mmc2: cqhci: CQE failed to exit halt state

For now disable CQE support for Tegra186 until this issue is resolved.

Fixes: dfd3cb6feb73 arm64: tegra: Add CQE Support for SDMMC4
Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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arm64: tegra: Update compatible for Tegra186 I2C

Update I2C Device node compatible string to be appropriate.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Redin

arm64: tegra: Update compatible for Tegra186 I2C

Update I2C Device node compatible string to be appropriate.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <tredi

arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used

arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.

Fixed drive strengths are based on Pre SI Analysis of the pads.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fal

arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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arm64: tegra: Set reg property for display-hub on Tegra186

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
contro

arm64: tegra: Set reg property for display-hub on Tegra186

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: tegra186: Enable IOMMU for SDHCI

Enable IOMMU for all SDHCI controllers in Tegra186.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add CEC controller on Tegra186

The CEC controller found on Tegra186 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <treding@nvidia.com>