1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 nvidia,dqs-trim = <63>; 317 mmc-hs400-1_8v; 318 status = "disabled"; 319 }; 320 321 hda@3510000 { 322 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 323 reg = <0x0 0x03510000 0x0 0x10000>; 324 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&bpmp TEGRA186_CLK_HDA>, 326 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 327 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 328 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 329 resets = <&bpmp TEGRA186_RESET_HDA>, 330 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 331 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 332 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 333 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 334 status = "disabled"; 335 }; 336 337 fuse@3820000 { 338 compatible = "nvidia,tegra186-efuse"; 339 reg = <0x0 0x03820000 0x0 0x10000>; 340 clocks = <&bpmp TEGRA186_CLK_FUSE>; 341 clock-names = "fuse"; 342 }; 343 344 gic: interrupt-controller@3881000 { 345 compatible = "arm,gic-400"; 346 #interrupt-cells = <3>; 347 interrupt-controller; 348 reg = <0x0 0x03881000 0x0 0x1000>, 349 <0x0 0x03882000 0x0 0x2000>; 350 interrupts = <GIC_PPI 9 351 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 352 interrupt-parent = <&gic>; 353 }; 354 355 cec@3960000 { 356 compatible = "nvidia,tegra186-cec"; 357 reg = <0x0 0x03960000 0x0 0x10000>; 358 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&bpmp TEGRA186_CLK_CEC>; 360 clock-names = "cec"; 361 status = "disabled"; 362 }; 363 364 hsp_top0: hsp@3c00000 { 365 compatible = "nvidia,tegra186-hsp"; 366 reg = <0x0 0x03c00000 0x0 0xa0000>; 367 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 368 interrupt-names = "doorbell"; 369 #mbox-cells = <2>; 370 status = "disabled"; 371 }; 372 373 gen2_i2c: i2c@c240000 { 374 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 375 reg = <0x0 0x0c240000 0x0 0x10000>; 376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&bpmp TEGRA186_CLK_I2C2>; 380 clock-names = "div-clk"; 381 resets = <&bpmp TEGRA186_RESET_I2C2>; 382 reset-names = "i2c"; 383 status = "disabled"; 384 }; 385 386 gen8_i2c: i2c@c250000 { 387 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 388 reg = <0x0 0x0c250000 0x0 0x10000>; 389 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&bpmp TEGRA186_CLK_I2C8>; 393 clock-names = "div-clk"; 394 resets = <&bpmp TEGRA186_RESET_I2C8>; 395 reset-names = "i2c"; 396 status = "disabled"; 397 }; 398 399 uartc: serial@c280000 { 400 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 401 reg = <0x0 0x0c280000 0x0 0x40>; 402 reg-shift = <2>; 403 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&bpmp TEGRA186_CLK_UARTC>; 405 clock-names = "serial"; 406 resets = <&bpmp TEGRA186_RESET_UARTC>; 407 reset-names = "serial"; 408 status = "disabled"; 409 }; 410 411 uartg: serial@c290000 { 412 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 413 reg = <0x0 0x0c290000 0x0 0x40>; 414 reg-shift = <2>; 415 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&bpmp TEGRA186_CLK_UARTG>; 417 clock-names = "serial"; 418 resets = <&bpmp TEGRA186_RESET_UARTG>; 419 reset-names = "serial"; 420 status = "disabled"; 421 }; 422 423 rtc: rtc@c2a0000 { 424 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 425 reg = <0 0x0c2a0000 0 0x10000>; 426 interrupt-parent = <&pmc>; 427 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 429 clock-names = "rtc"; 430 status = "disabled"; 431 }; 432 433 gpio_aon: gpio@c2f0000 { 434 compatible = "nvidia,tegra186-gpio-aon"; 435 reg-names = "security", "gpio"; 436 reg = <0x0 0xc2f0000 0x0 0x1000>, 437 <0x0 0xc2f1000 0x0 0x1000>; 438 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 }; 444 445 pmc: pmc@c360000 { 446 compatible = "nvidia,tegra186-pmc"; 447 reg = <0 0x0c360000 0 0x10000>, 448 <0 0x0c370000 0 0x10000>, 449 <0 0x0c380000 0 0x10000>, 450 <0 0x0c390000 0 0x10000>; 451 reg-names = "pmc", "wake", "aotag", "scratch"; 452 453 #interrupt-cells = <2>; 454 interrupt-controller; 455 456 sdmmc1_3v3: sdmmc1-3v3 { 457 pins = "sdmmc1-hv"; 458 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 459 }; 460 461 sdmmc1_1v8: sdmmc1-1v8 { 462 pins = "sdmmc1-hv"; 463 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 464 }; 465 466 sdmmc2_3v3: sdmmc2-3v3 { 467 pins = "sdmmc2-hv"; 468 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 469 }; 470 471 sdmmc2_1v8: sdmmc2-1v8 { 472 pins = "sdmmc2-hv"; 473 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 474 }; 475 476 sdmmc3_3v3: sdmmc3-3v3 { 477 pins = "sdmmc3-hv"; 478 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 479 }; 480 481 sdmmc3_1v8: sdmmc3-1v8 { 482 pins = "sdmmc3-hv"; 483 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 484 }; 485 }; 486 487 ccplex@e000000 { 488 compatible = "nvidia,tegra186-ccplex-cluster"; 489 reg = <0x0 0x0e000000 0x0 0x3fffff>; 490 491 nvidia,bpmp = <&bpmp>; 492 }; 493 494 pcie@10003000 { 495 compatible = "nvidia,tegra186-pcie"; 496 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 497 device_type = "pci"; 498 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 499 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 500 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 501 reg-names = "pads", "afi", "cs"; 502 503 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 504 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 505 interrupt-names = "intr", "msi"; 506 507 #interrupt-cells = <1>; 508 interrupt-map-mask = <0 0 0 0>; 509 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 510 511 bus-range = <0x00 0xff>; 512 #address-cells = <3>; 513 #size-cells = <2>; 514 515 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 516 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 517 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 518 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 519 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 520 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 521 522 clocks = <&bpmp TEGRA186_CLK_AFI>, 523 <&bpmp TEGRA186_CLK_PCIE>, 524 <&bpmp TEGRA186_CLK_PLLE>; 525 clock-names = "afi", "pex", "pll_e"; 526 527 resets = <&bpmp TEGRA186_RESET_AFI>, 528 <&bpmp TEGRA186_RESET_PCIE>, 529 <&bpmp TEGRA186_RESET_PCIEXCLK>; 530 reset-names = "afi", "pex", "pcie_x"; 531 532 status = "disabled"; 533 534 pci@1,0 { 535 device_type = "pci"; 536 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 537 reg = <0x000800 0 0 0 0>; 538 status = "disabled"; 539 540 #address-cells = <3>; 541 #size-cells = <2>; 542 ranges; 543 544 nvidia,num-lanes = <2>; 545 }; 546 547 pci@2,0 { 548 device_type = "pci"; 549 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 550 reg = <0x001000 0 0 0 0>; 551 status = "disabled"; 552 553 #address-cells = <3>; 554 #size-cells = <2>; 555 ranges; 556 557 nvidia,num-lanes = <1>; 558 }; 559 560 pci@3,0 { 561 device_type = "pci"; 562 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 563 reg = <0x001800 0 0 0 0>; 564 status = "disabled"; 565 566 #address-cells = <3>; 567 #size-cells = <2>; 568 ranges; 569 570 nvidia,num-lanes = <1>; 571 }; 572 }; 573 574 smmu: iommu@12000000 { 575 compatible = "arm,mmu-500"; 576 reg = <0 0x12000000 0 0x800000>; 577 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 642 stream-match-mask = <0x7f80>; 643 #global-interrupts = <1>; 644 #iommu-cells = <1>; 645 }; 646 647 host1x@13e00000 { 648 compatible = "nvidia,tegra186-host1x", "simple-bus"; 649 reg = <0x0 0x13e00000 0x0 0x10000>, 650 <0x0 0x13e10000 0x0 0x10000>; 651 reg-names = "hypervisor", "vm"; 652 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 655 clock-names = "host1x"; 656 resets = <&bpmp TEGRA186_RESET_HOST1X>; 657 reset-names = "host1x"; 658 659 #address-cells = <1>; 660 #size-cells = <1>; 661 662 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 663 iommus = <&smmu TEGRA186_SID_HOST1X>; 664 665 dpaux1: dpaux@15040000 { 666 compatible = "nvidia,tegra186-dpaux"; 667 reg = <0x15040000 0x10000>; 668 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 670 <&bpmp TEGRA186_CLK_PLLDP>; 671 clock-names = "dpaux", "parent"; 672 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 673 reset-names = "dpaux"; 674 status = "disabled"; 675 676 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 677 678 state_dpaux1_aux: pinmux-aux { 679 groups = "dpaux-io"; 680 function = "aux"; 681 }; 682 683 state_dpaux1_i2c: pinmux-i2c { 684 groups = "dpaux-io"; 685 function = "i2c"; 686 }; 687 688 state_dpaux1_off: pinmux-off { 689 groups = "dpaux-io"; 690 function = "off"; 691 }; 692 693 i2c-bus { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 }; 697 }; 698 699 display-hub@15200000 { 700 compatible = "nvidia,tegra186-display", "simple-bus"; 701 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 702 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 703 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 704 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 705 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 706 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 707 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 708 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 709 "wgrp3", "wgrp4", "wgrp5"; 710 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 711 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 712 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 713 clock-names = "disp", "dsc", "hub"; 714 status = "disabled"; 715 716 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 717 718 #address-cells = <1>; 719 #size-cells = <1>; 720 721 ranges = <0x15200000 0x15200000 0x40000>; 722 723 display@15200000 { 724 compatible = "nvidia,tegra186-dc"; 725 reg = <0x15200000 0x10000>; 726 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 728 clock-names = "dc"; 729 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 730 reset-names = "dc"; 731 732 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 733 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 734 735 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 736 nvidia,head = <0>; 737 }; 738 739 display@15210000 { 740 compatible = "nvidia,tegra186-dc"; 741 reg = <0x15210000 0x10000>; 742 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 744 clock-names = "dc"; 745 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 746 reset-names = "dc"; 747 748 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 749 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 750 751 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 752 nvidia,head = <1>; 753 }; 754 755 display@15220000 { 756 compatible = "nvidia,tegra186-dc"; 757 reg = <0x15220000 0x10000>; 758 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 760 clock-names = "dc"; 761 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 762 reset-names = "dc"; 763 764 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 765 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 766 767 nvidia,outputs = <&sor0 &sor1>; 768 nvidia,head = <2>; 769 }; 770 }; 771 772 dsia: dsi@15300000 { 773 compatible = "nvidia,tegra186-dsi"; 774 reg = <0x15300000 0x10000>; 775 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&bpmp TEGRA186_CLK_DSI>, 777 <&bpmp TEGRA186_CLK_DSIA_LP>, 778 <&bpmp TEGRA186_CLK_PLLD>; 779 clock-names = "dsi", "lp", "parent"; 780 resets = <&bpmp TEGRA186_RESET_DSI>; 781 reset-names = "dsi"; 782 status = "disabled"; 783 784 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 785 }; 786 787 vic@15340000 { 788 compatible = "nvidia,tegra186-vic"; 789 reg = <0x15340000 0x40000>; 790 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA186_CLK_VIC>; 792 clock-names = "vic"; 793 resets = <&bpmp TEGRA186_RESET_VIC>; 794 reset-names = "vic"; 795 796 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 797 }; 798 799 dsib: dsi@15400000 { 800 compatible = "nvidia,tegra186-dsi"; 801 reg = <0x15400000 0x10000>; 802 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&bpmp TEGRA186_CLK_DSIB>, 804 <&bpmp TEGRA186_CLK_DSIB_LP>, 805 <&bpmp TEGRA186_CLK_PLLD>; 806 clock-names = "dsi", "lp", "parent"; 807 resets = <&bpmp TEGRA186_RESET_DSIB>; 808 reset-names = "dsi"; 809 status = "disabled"; 810 811 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 812 }; 813 814 sor0: sor@15540000 { 815 compatible = "nvidia,tegra186-sor"; 816 reg = <0x15540000 0x10000>; 817 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&bpmp TEGRA186_CLK_SOR0>, 819 <&bpmp TEGRA186_CLK_SOR0_OUT>, 820 <&bpmp TEGRA186_CLK_PLLD2>, 821 <&bpmp TEGRA186_CLK_PLLDP>, 822 <&bpmp TEGRA186_CLK_SOR_SAFE>, 823 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 824 clock-names = "sor", "out", "parent", "dp", "safe", 825 "pad"; 826 resets = <&bpmp TEGRA186_RESET_SOR0>; 827 reset-names = "sor"; 828 pinctrl-0 = <&state_dpaux_aux>; 829 pinctrl-1 = <&state_dpaux_i2c>; 830 pinctrl-2 = <&state_dpaux_off>; 831 pinctrl-names = "aux", "i2c", "off"; 832 status = "disabled"; 833 834 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 835 nvidia,interface = <0>; 836 }; 837 838 sor1: sor@15580000 { 839 compatible = "nvidia,tegra186-sor1"; 840 reg = <0x15580000 0x10000>; 841 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&bpmp TEGRA186_CLK_SOR1>, 843 <&bpmp TEGRA186_CLK_SOR1_OUT>, 844 <&bpmp TEGRA186_CLK_PLLD3>, 845 <&bpmp TEGRA186_CLK_PLLDP>, 846 <&bpmp TEGRA186_CLK_SOR_SAFE>, 847 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 848 clock-names = "sor", "out", "parent", "dp", "safe", 849 "pad"; 850 resets = <&bpmp TEGRA186_RESET_SOR1>; 851 reset-names = "sor"; 852 pinctrl-0 = <&state_dpaux1_aux>; 853 pinctrl-1 = <&state_dpaux1_i2c>; 854 pinctrl-2 = <&state_dpaux1_off>; 855 pinctrl-names = "aux", "i2c", "off"; 856 status = "disabled"; 857 858 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 859 nvidia,interface = <1>; 860 }; 861 862 dpaux: dpaux@155c0000 { 863 compatible = "nvidia,tegra186-dpaux"; 864 reg = <0x155c0000 0x10000>; 865 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 867 <&bpmp TEGRA186_CLK_PLLDP>; 868 clock-names = "dpaux", "parent"; 869 resets = <&bpmp TEGRA186_RESET_DPAUX>; 870 reset-names = "dpaux"; 871 status = "disabled"; 872 873 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 874 875 state_dpaux_aux: pinmux-aux { 876 groups = "dpaux-io"; 877 function = "aux"; 878 }; 879 880 state_dpaux_i2c: pinmux-i2c { 881 groups = "dpaux-io"; 882 function = "i2c"; 883 }; 884 885 state_dpaux_off: pinmux-off { 886 groups = "dpaux-io"; 887 function = "off"; 888 }; 889 890 i2c-bus { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 }; 894 }; 895 896 padctl@15880000 { 897 compatible = "nvidia,tegra186-dsi-padctl"; 898 reg = <0x15880000 0x10000>; 899 resets = <&bpmp TEGRA186_RESET_DSI>; 900 reset-names = "dsi"; 901 status = "disabled"; 902 }; 903 904 dsic: dsi@15900000 { 905 compatible = "nvidia,tegra186-dsi"; 906 reg = <0x15900000 0x10000>; 907 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&bpmp TEGRA186_CLK_DSIC>, 909 <&bpmp TEGRA186_CLK_DSIC_LP>, 910 <&bpmp TEGRA186_CLK_PLLD>; 911 clock-names = "dsi", "lp", "parent"; 912 resets = <&bpmp TEGRA186_RESET_DSIC>; 913 reset-names = "dsi"; 914 status = "disabled"; 915 916 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 917 }; 918 919 dsid: dsi@15940000 { 920 compatible = "nvidia,tegra186-dsi"; 921 reg = <0x15940000 0x10000>; 922 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&bpmp TEGRA186_CLK_DSID>, 924 <&bpmp TEGRA186_CLK_DSID_LP>, 925 <&bpmp TEGRA186_CLK_PLLD>; 926 clock-names = "dsi", "lp", "parent"; 927 resets = <&bpmp TEGRA186_RESET_DSID>; 928 reset-names = "dsi"; 929 status = "disabled"; 930 931 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 932 }; 933 }; 934 935 gpu@17000000 { 936 compatible = "nvidia,gp10b"; 937 reg = <0x0 0x17000000 0x0 0x1000000>, 938 <0x0 0x18000000 0x0 0x1000000>; 939 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 940 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "stall", "nonstall"; 942 943 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 944 <&bpmp TEGRA186_CLK_GPU>; 945 clock-names = "gpu", "pwr"; 946 resets = <&bpmp TEGRA186_RESET_GPU>; 947 reset-names = "gpu"; 948 status = "disabled"; 949 950 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 951 }; 952 953 sysram@30000000 { 954 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 955 reg = <0x0 0x30000000 0x0 0x50000>; 956 #address-cells = <2>; 957 #size-cells = <2>; 958 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 959 960 cpu_bpmp_tx: shmem@4e000 { 961 compatible = "nvidia,tegra186-bpmp-shmem"; 962 reg = <0x0 0x4e000 0x0 0x1000>; 963 label = "cpu-bpmp-tx"; 964 pool; 965 }; 966 967 cpu_bpmp_rx: shmem@4f000 { 968 compatible = "nvidia,tegra186-bpmp-shmem"; 969 reg = <0x0 0x4f000 0x0 0x1000>; 970 label = "cpu-bpmp-rx"; 971 pool; 972 }; 973 }; 974 975 cpus { 976 #address-cells = <1>; 977 #size-cells = <0>; 978 979 cpu@0 { 980 compatible = "nvidia,tegra186-denver", "arm,armv8"; 981 device_type = "cpu"; 982 reg = <0x000>; 983 }; 984 985 cpu@1 { 986 compatible = "nvidia,tegra186-denver", "arm,armv8"; 987 device_type = "cpu"; 988 reg = <0x001>; 989 }; 990 991 cpu@2 { 992 compatible = "arm,cortex-a57", "arm,armv8"; 993 device_type = "cpu"; 994 reg = <0x100>; 995 }; 996 997 cpu@3 { 998 compatible = "arm,cortex-a57", "arm,armv8"; 999 device_type = "cpu"; 1000 reg = <0x101>; 1001 }; 1002 1003 cpu@4 { 1004 compatible = "arm,cortex-a57", "arm,armv8"; 1005 device_type = "cpu"; 1006 reg = <0x102>; 1007 }; 1008 1009 cpu@5 { 1010 compatible = "arm,cortex-a57", "arm,armv8"; 1011 device_type = "cpu"; 1012 reg = <0x103>; 1013 }; 1014 }; 1015 1016 bpmp: bpmp { 1017 compatible = "nvidia,tegra186-bpmp"; 1018 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1019 TEGRA_HSP_DB_MASTER_BPMP>; 1020 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1021 #clock-cells = <1>; 1022 #reset-cells = <1>; 1023 #power-domain-cells = <1>; 1024 1025 bpmp_i2c: i2c { 1026 compatible = "nvidia,tegra186-bpmp-i2c"; 1027 nvidia,bpmp-bus-id = <5>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 bpmp_thermal: thermal { 1034 compatible = "nvidia,tegra186-bpmp-thermal"; 1035 #thermal-sensor-cells = <1>; 1036 }; 1037 }; 1038 1039 thermal-zones { 1040 a57 { 1041 polling-delay = <0>; 1042 polling-delay-passive = <1000>; 1043 1044 thermal-sensors = 1045 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1046 1047 trips { 1048 critical { 1049 temperature = <101000>; 1050 hysteresis = <0>; 1051 type = "critical"; 1052 }; 1053 }; 1054 1055 cooling-maps { 1056 }; 1057 }; 1058 1059 denver { 1060 polling-delay = <0>; 1061 polling-delay-passive = <1000>; 1062 1063 thermal-sensors = 1064 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1065 1066 trips { 1067 critical { 1068 temperature = <101000>; 1069 hysteresis = <0>; 1070 type = "critical"; 1071 }; 1072 }; 1073 1074 cooling-maps { 1075 }; 1076 }; 1077 1078 gpu { 1079 polling-delay = <0>; 1080 polling-delay-passive = <1000>; 1081 1082 thermal-sensors = 1083 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1084 1085 trips { 1086 critical { 1087 temperature = <101000>; 1088 hysteresis = <0>; 1089 type = "critical"; 1090 }; 1091 }; 1092 1093 cooling-maps { 1094 }; 1095 }; 1096 1097 pll { 1098 polling-delay = <0>; 1099 polling-delay-passive = <1000>; 1100 1101 thermal-sensors = 1102 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1103 1104 trips { 1105 critical { 1106 temperature = <101000>; 1107 hysteresis = <0>; 1108 type = "critical"; 1109 }; 1110 }; 1111 1112 cooling-maps { 1113 }; 1114 }; 1115 1116 always_on { 1117 polling-delay = <0>; 1118 polling-delay-passive = <1000>; 1119 1120 thermal-sensors = 1121 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1122 1123 trips { 1124 critical { 1125 temperature = <101000>; 1126 hysteresis = <0>; 1127 type = "critical"; 1128 }; 1129 }; 1130 1131 cooling-maps { 1132 }; 1133 }; 1134 }; 1135 1136 timer { 1137 compatible = "arm,armv8-timer"; 1138 interrupts = <GIC_PPI 13 1139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1140 <GIC_PPI 14 1141 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1142 <GIC_PPI 11 1143 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1144 <GIC_PPI 10 1145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1146 interrupt-parent = <&gic>; 1147 }; 1148}; 1149