1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 memory-controller@2c00000 { 74 compatible = "nvidia,tegra186-mc"; 75 reg = <0x0 0x02c00000 0x0 0xb0000>; 76 status = "disabled"; 77 }; 78 79 uarta: serial@3100000 { 80 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 81 reg = <0x0 0x03100000 0x0 0x40>; 82 reg-shift = <2>; 83 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 84 clocks = <&bpmp TEGRA186_CLK_UARTA>; 85 clock-names = "serial"; 86 resets = <&bpmp TEGRA186_RESET_UARTA>; 87 reset-names = "serial"; 88 status = "disabled"; 89 }; 90 91 uartb: serial@3110000 { 92 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 93 reg = <0x0 0x03110000 0x0 0x40>; 94 reg-shift = <2>; 95 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&bpmp TEGRA186_CLK_UARTB>; 97 clock-names = "serial"; 98 resets = <&bpmp TEGRA186_RESET_UARTB>; 99 reset-names = "serial"; 100 status = "disabled"; 101 }; 102 103 uartd: serial@3130000 { 104 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 105 reg = <0x0 0x03130000 0x0 0x40>; 106 reg-shift = <2>; 107 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&bpmp TEGRA186_CLK_UARTD>; 109 clock-names = "serial"; 110 resets = <&bpmp TEGRA186_RESET_UARTD>; 111 reset-names = "serial"; 112 status = "disabled"; 113 }; 114 115 uarte: serial@3140000 { 116 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 117 reg = <0x0 0x03140000 0x0 0x40>; 118 reg-shift = <2>; 119 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&bpmp TEGRA186_CLK_UARTE>; 121 clock-names = "serial"; 122 resets = <&bpmp TEGRA186_RESET_UARTE>; 123 reset-names = "serial"; 124 status = "disabled"; 125 }; 126 127 uartf: serial@3150000 { 128 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 129 reg = <0x0 0x03150000 0x0 0x40>; 130 reg-shift = <2>; 131 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&bpmp TEGRA186_CLK_UARTF>; 133 clock-names = "serial"; 134 resets = <&bpmp TEGRA186_RESET_UARTF>; 135 reset-names = "serial"; 136 status = "disabled"; 137 }; 138 139 gen1_i2c: i2c@3160000 { 140 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 141 reg = <0x0 0x03160000 0x0 0x10000>; 142 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 clocks = <&bpmp TEGRA186_CLK_I2C1>; 146 clock-names = "div-clk"; 147 resets = <&bpmp TEGRA186_RESET_I2C1>; 148 reset-names = "i2c"; 149 status = "disabled"; 150 }; 151 152 cam_i2c: i2c@3180000 { 153 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 154 reg = <0x0 0x03180000 0x0 0x10000>; 155 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clocks = <&bpmp TEGRA186_CLK_I2C3>; 159 clock-names = "div-clk"; 160 resets = <&bpmp TEGRA186_RESET_I2C3>; 161 reset-names = "i2c"; 162 status = "disabled"; 163 }; 164 165 /* shares pads with dpaux1 */ 166 dp_aux_ch1_i2c: i2c@3190000 { 167 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 168 reg = <0x0 0x03190000 0x0 0x10000>; 169 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 clocks = <&bpmp TEGRA186_CLK_I2C4>; 173 clock-names = "div-clk"; 174 resets = <&bpmp TEGRA186_RESET_I2C4>; 175 reset-names = "i2c"; 176 pinctrl-names = "default", "idle"; 177 pinctrl-0 = <&state_dpaux1_i2c>; 178 pinctrl-1 = <&state_dpaux1_off>; 179 status = "disabled"; 180 }; 181 182 /* controlled by BPMP, should not be enabled */ 183 pwr_i2c: i2c@31a0000 { 184 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 185 reg = <0x0 0x031a0000 0x0 0x10000>; 186 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 clocks = <&bpmp TEGRA186_CLK_I2C5>; 190 clock-names = "div-clk"; 191 resets = <&bpmp TEGRA186_RESET_I2C5>; 192 reset-names = "i2c"; 193 status = "disabled"; 194 }; 195 196 /* shares pads with dpaux0 */ 197 dp_aux_ch0_i2c: i2c@31b0000 { 198 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 199 reg = <0x0 0x031b0000 0x0 0x10000>; 200 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 clocks = <&bpmp TEGRA186_CLK_I2C6>; 204 clock-names = "div-clk"; 205 resets = <&bpmp TEGRA186_RESET_I2C6>; 206 reset-names = "i2c"; 207 pinctrl-names = "default", "idle"; 208 pinctrl-0 = <&state_dpaux_i2c>; 209 pinctrl-1 = <&state_dpaux_off>; 210 status = "disabled"; 211 }; 212 213 gen7_i2c: i2c@31c0000 { 214 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 215 reg = <0x0 0x031c0000 0x0 0x10000>; 216 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 clocks = <&bpmp TEGRA186_CLK_I2C7>; 220 clock-names = "div-clk"; 221 resets = <&bpmp TEGRA186_RESET_I2C7>; 222 reset-names = "i2c"; 223 status = "disabled"; 224 }; 225 226 gen9_i2c: i2c@31e0000 { 227 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 228 reg = <0x0 0x031e0000 0x0 0x10000>; 229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 clocks = <&bpmp TEGRA186_CLK_I2C9>; 233 clock-names = "div-clk"; 234 resets = <&bpmp TEGRA186_RESET_I2C9>; 235 reset-names = "i2c"; 236 status = "disabled"; 237 }; 238 239 sdmmc1: sdhci@3400000 { 240 compatible = "nvidia,tegra186-sdhci"; 241 reg = <0x0 0x03400000 0x0 0x10000>; 242 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 244 clock-names = "sdhci"; 245 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 246 reset-names = "sdhci"; 247 iommus = <&smmu TEGRA186_SID_SDMMC1>; 248 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 249 pinctrl-0 = <&sdmmc1_3v3>; 250 pinctrl-1 = <&sdmmc1_1v8>; 251 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 252 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 253 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 254 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 255 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 256 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 257 nvidia,default-tap = <0x5>; 258 nvidia,default-trim = <0xb>; 259 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 260 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 261 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 262 status = "disabled"; 263 }; 264 265 sdmmc2: sdhci@3420000 { 266 compatible = "nvidia,tegra186-sdhci"; 267 reg = <0x0 0x03420000 0x0 0x10000>; 268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 270 clock-names = "sdhci"; 271 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 272 reset-names = "sdhci"; 273 iommus = <&smmu TEGRA186_SID_SDMMC2>; 274 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 275 pinctrl-0 = <&sdmmc2_3v3>; 276 pinctrl-1 = <&sdmmc2_1v8>; 277 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 278 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 279 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 280 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 281 nvidia,default-tap = <0x5>; 282 nvidia,default-trim = <0xb>; 283 status = "disabled"; 284 }; 285 286 sdmmc3: sdhci@3440000 { 287 compatible = "nvidia,tegra186-sdhci"; 288 reg = <0x0 0x03440000 0x0 0x10000>; 289 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 291 clock-names = "sdhci"; 292 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 293 reset-names = "sdhci"; 294 iommus = <&smmu TEGRA186_SID_SDMMC3>; 295 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 296 pinctrl-0 = <&sdmmc3_3v3>; 297 pinctrl-1 = <&sdmmc3_1v8>; 298 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 299 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 300 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 301 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 302 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 303 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 304 nvidia,default-tap = <0x5>; 305 nvidia,default-trim = <0xb>; 306 status = "disabled"; 307 }; 308 309 sdmmc4: sdhci@3460000 { 310 compatible = "nvidia,tegra186-sdhci"; 311 reg = <0x0 0x03460000 0x0 0x10000>; 312 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 314 clock-names = "sdhci"; 315 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 316 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 317 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 318 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 319 reset-names = "sdhci"; 320 iommus = <&smmu TEGRA186_SID_SDMMC4>; 321 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 322 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 323 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 324 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 325 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 326 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 327 nvidia,default-tap = <0x9>; 328 nvidia,default-trim = <0x5>; 329 nvidia,dqs-trim = <63>; 330 mmc-hs400-1_8v; 331 supports-cqe; 332 status = "disabled"; 333 }; 334 335 hda@3510000 { 336 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 337 reg = <0x0 0x03510000 0x0 0x10000>; 338 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&bpmp TEGRA186_CLK_HDA>, 340 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 341 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 342 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 343 resets = <&bpmp TEGRA186_RESET_HDA>, 344 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 345 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 346 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 347 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 348 iommus = <&smmu TEGRA186_SID_HDA>; 349 status = "disabled"; 350 }; 351 352 padctl: padctl@3520000 { 353 compatible = "nvidia,tegra186-xusb-padctl"; 354 reg = <0x0 0x03520000 0x0 0x1000>, 355 <0x0 0x03540000 0x0 0x1000>; 356 reg-names = "padctl", "ao"; 357 358 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 359 reset-names = "padctl"; 360 361 status = "disabled"; 362 363 pads { 364 usb2 { 365 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 366 clock-names = "trk"; 367 status = "disabled"; 368 369 lanes { 370 usb2-0 { 371 status = "disabled"; 372 #phy-cells = <0>; 373 }; 374 375 usb2-1 { 376 status = "disabled"; 377 #phy-cells = <0>; 378 }; 379 380 usb2-2 { 381 status = "disabled"; 382 #phy-cells = <0>; 383 }; 384 }; 385 }; 386 387 hsic { 388 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 389 clock-names = "trk"; 390 status = "disabled"; 391 392 lanes { 393 hsic-0 { 394 status = "disabled"; 395 #phy-cells = <0>; 396 }; 397 }; 398 }; 399 400 usb3 { 401 status = "disabled"; 402 403 lanes { 404 usb3-0 { 405 status = "disabled"; 406 #phy-cells = <0>; 407 }; 408 409 usb3-1 { 410 status = "disabled"; 411 #phy-cells = <0>; 412 }; 413 414 usb3-2 { 415 status = "disabled"; 416 #phy-cells = <0>; 417 }; 418 }; 419 }; 420 }; 421 422 ports { 423 usb2-0 { 424 status = "disabled"; 425 }; 426 427 usb2-1 { 428 status = "disabled"; 429 }; 430 431 usb2-2 { 432 status = "disabled"; 433 }; 434 435 hsic-0 { 436 status = "disabled"; 437 }; 438 439 usb3-0 { 440 status = "disabled"; 441 }; 442 443 usb3-1 { 444 status = "disabled"; 445 }; 446 447 usb3-2 { 448 status = "disabled"; 449 }; 450 }; 451 }; 452 453 usb@3530000 { 454 compatible = "nvidia,tegra186-xusb"; 455 reg = <0x0 0x03530000 0x0 0x8000>, 456 <0x0 0x03538000 0x0 0x1000>; 457 reg-names = "hcd", "fpci"; 458 459 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 462 463 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 464 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 465 <&bpmp TEGRA186_CLK_XUSB_SS>, 466 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 467 <&bpmp TEGRA186_CLK_CLK_M>, 468 <&bpmp TEGRA186_CLK_XUSB_FS>, 469 <&bpmp TEGRA186_CLK_PLLU>, 470 <&bpmp TEGRA186_CLK_CLK_M>, 471 <&bpmp TEGRA186_CLK_PLLE>; 472 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 473 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 474 "pll_u_480m", "clk_m", "pll_e"; 475 476 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 477 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 478 power-domain-names = "xusb_host", "xusb_ss"; 479 nvidia,xusb-padctl = <&padctl>; 480 481 status = "disabled"; 482 483 #address-cells = <1>; 484 #size-cells = <0>; 485 }; 486 487 fuse@3820000 { 488 compatible = "nvidia,tegra186-efuse"; 489 reg = <0x0 0x03820000 0x0 0x10000>; 490 clocks = <&bpmp TEGRA186_CLK_FUSE>; 491 clock-names = "fuse"; 492 }; 493 494 gic: interrupt-controller@3881000 { 495 compatible = "arm,gic-400"; 496 #interrupt-cells = <3>; 497 interrupt-controller; 498 reg = <0x0 0x03881000 0x0 0x1000>, 499 <0x0 0x03882000 0x0 0x2000>; 500 interrupts = <GIC_PPI 9 501 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 502 interrupt-parent = <&gic>; 503 }; 504 505 cec@3960000 { 506 compatible = "nvidia,tegra186-cec"; 507 reg = <0x0 0x03960000 0x0 0x10000>; 508 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&bpmp TEGRA186_CLK_CEC>; 510 clock-names = "cec"; 511 status = "disabled"; 512 }; 513 514 hsp_top0: hsp@3c00000 { 515 compatible = "nvidia,tegra186-hsp"; 516 reg = <0x0 0x03c00000 0x0 0xa0000>; 517 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "doorbell"; 519 #mbox-cells = <2>; 520 status = "disabled"; 521 }; 522 523 gen2_i2c: i2c@c240000 { 524 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 525 reg = <0x0 0x0c240000 0x0 0x10000>; 526 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 clocks = <&bpmp TEGRA186_CLK_I2C2>; 530 clock-names = "div-clk"; 531 resets = <&bpmp TEGRA186_RESET_I2C2>; 532 reset-names = "i2c"; 533 status = "disabled"; 534 }; 535 536 gen8_i2c: i2c@c250000 { 537 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 538 reg = <0x0 0x0c250000 0x0 0x10000>; 539 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 clocks = <&bpmp TEGRA186_CLK_I2C8>; 543 clock-names = "div-clk"; 544 resets = <&bpmp TEGRA186_RESET_I2C8>; 545 reset-names = "i2c"; 546 status = "disabled"; 547 }; 548 549 uartc: serial@c280000 { 550 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 551 reg = <0x0 0x0c280000 0x0 0x40>; 552 reg-shift = <2>; 553 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&bpmp TEGRA186_CLK_UARTC>; 555 clock-names = "serial"; 556 resets = <&bpmp TEGRA186_RESET_UARTC>; 557 reset-names = "serial"; 558 status = "disabled"; 559 }; 560 561 uartg: serial@c290000 { 562 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 563 reg = <0x0 0x0c290000 0x0 0x40>; 564 reg-shift = <2>; 565 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&bpmp TEGRA186_CLK_UARTG>; 567 clock-names = "serial"; 568 resets = <&bpmp TEGRA186_RESET_UARTG>; 569 reset-names = "serial"; 570 status = "disabled"; 571 }; 572 573 rtc: rtc@c2a0000 { 574 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 575 reg = <0 0x0c2a0000 0 0x10000>; 576 interrupt-parent = <&pmc>; 577 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 579 clock-names = "rtc"; 580 status = "disabled"; 581 }; 582 583 gpio_aon: gpio@c2f0000 { 584 compatible = "nvidia,tegra186-gpio-aon"; 585 reg-names = "security", "gpio"; 586 reg = <0x0 0xc2f0000 0x0 0x1000>, 587 <0x0 0xc2f1000 0x0 0x1000>; 588 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 }; 594 595 pmc: pmc@c360000 { 596 compatible = "nvidia,tegra186-pmc"; 597 reg = <0 0x0c360000 0 0x10000>, 598 <0 0x0c370000 0 0x10000>, 599 <0 0x0c380000 0 0x10000>, 600 <0 0x0c390000 0 0x10000>; 601 reg-names = "pmc", "wake", "aotag", "scratch"; 602 603 #interrupt-cells = <2>; 604 interrupt-controller; 605 606 sdmmc1_3v3: sdmmc1-3v3 { 607 pins = "sdmmc1-hv"; 608 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 609 }; 610 611 sdmmc1_1v8: sdmmc1-1v8 { 612 pins = "sdmmc1-hv"; 613 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 614 }; 615 616 sdmmc2_3v3: sdmmc2-3v3 { 617 pins = "sdmmc2-hv"; 618 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 619 }; 620 621 sdmmc2_1v8: sdmmc2-1v8 { 622 pins = "sdmmc2-hv"; 623 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 624 }; 625 626 sdmmc3_3v3: sdmmc3-3v3 { 627 pins = "sdmmc3-hv"; 628 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 629 }; 630 631 sdmmc3_1v8: sdmmc3-1v8 { 632 pins = "sdmmc3-hv"; 633 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 634 }; 635 }; 636 637 ccplex@e000000 { 638 compatible = "nvidia,tegra186-ccplex-cluster"; 639 reg = <0x0 0x0e000000 0x0 0x3fffff>; 640 641 nvidia,bpmp = <&bpmp>; 642 }; 643 644 pcie@10003000 { 645 compatible = "nvidia,tegra186-pcie"; 646 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 647 device_type = "pci"; 648 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 649 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 650 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 651 reg-names = "pads", "afi", "cs"; 652 653 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 654 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 655 interrupt-names = "intr", "msi"; 656 657 #interrupt-cells = <1>; 658 interrupt-map-mask = <0 0 0 0>; 659 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 660 661 bus-range = <0x00 0xff>; 662 #address-cells = <3>; 663 #size-cells = <2>; 664 665 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 666 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 667 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 668 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 669 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 670 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 671 672 clocks = <&bpmp TEGRA186_CLK_AFI>, 673 <&bpmp TEGRA186_CLK_PCIE>, 674 <&bpmp TEGRA186_CLK_PLLE>; 675 clock-names = "afi", "pex", "pll_e"; 676 677 resets = <&bpmp TEGRA186_RESET_AFI>, 678 <&bpmp TEGRA186_RESET_PCIE>, 679 <&bpmp TEGRA186_RESET_PCIEXCLK>; 680 reset-names = "afi", "pex", "pcie_x"; 681 682 iommus = <&smmu TEGRA186_SID_AFI>; 683 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 684 iommu-map-mask = <0x0>; 685 686 status = "disabled"; 687 688 pci@1,0 { 689 device_type = "pci"; 690 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 691 reg = <0x000800 0 0 0 0>; 692 status = "disabled"; 693 694 #address-cells = <3>; 695 #size-cells = <2>; 696 ranges; 697 698 nvidia,num-lanes = <2>; 699 }; 700 701 pci@2,0 { 702 device_type = "pci"; 703 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 704 reg = <0x001000 0 0 0 0>; 705 status = "disabled"; 706 707 #address-cells = <3>; 708 #size-cells = <2>; 709 ranges; 710 711 nvidia,num-lanes = <1>; 712 }; 713 714 pci@3,0 { 715 device_type = "pci"; 716 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 717 reg = <0x001800 0 0 0 0>; 718 status = "disabled"; 719 720 #address-cells = <3>; 721 #size-cells = <2>; 722 ranges; 723 724 nvidia,num-lanes = <1>; 725 }; 726 }; 727 728 smmu: iommu@12000000 { 729 compatible = "arm,mmu-500"; 730 reg = <0 0x12000000 0 0x800000>; 731 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 796 stream-match-mask = <0x7f80>; 797 #global-interrupts = <1>; 798 #iommu-cells = <1>; 799 }; 800 801 host1x@13e00000 { 802 compatible = "nvidia,tegra186-host1x", "simple-bus"; 803 reg = <0x0 0x13e00000 0x0 0x10000>, 804 <0x0 0x13e10000 0x0 0x10000>; 805 reg-names = "hypervisor", "vm"; 806 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 809 clock-names = "host1x"; 810 resets = <&bpmp TEGRA186_RESET_HOST1X>; 811 reset-names = "host1x"; 812 813 #address-cells = <1>; 814 #size-cells = <1>; 815 816 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 817 iommus = <&smmu TEGRA186_SID_HOST1X>; 818 819 dpaux1: dpaux@15040000 { 820 compatible = "nvidia,tegra186-dpaux"; 821 reg = <0x15040000 0x10000>; 822 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 824 <&bpmp TEGRA186_CLK_PLLDP>; 825 clock-names = "dpaux", "parent"; 826 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 827 reset-names = "dpaux"; 828 status = "disabled"; 829 830 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 831 832 state_dpaux1_aux: pinmux-aux { 833 groups = "dpaux-io"; 834 function = "aux"; 835 }; 836 837 state_dpaux1_i2c: pinmux-i2c { 838 groups = "dpaux-io"; 839 function = "i2c"; 840 }; 841 842 state_dpaux1_off: pinmux-off { 843 groups = "dpaux-io"; 844 function = "off"; 845 }; 846 847 i2c-bus { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 }; 851 }; 852 853 display-hub@15200000 { 854 compatible = "nvidia,tegra186-display", "simple-bus"; 855 reg = <0x15200000 0x00040000>; 856 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 857 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 858 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 859 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 860 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 861 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 862 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 863 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 864 "wgrp3", "wgrp4", "wgrp5"; 865 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 866 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 867 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 868 clock-names = "disp", "dsc", "hub"; 869 status = "disabled"; 870 871 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 872 873 #address-cells = <1>; 874 #size-cells = <1>; 875 876 ranges = <0x15200000 0x15200000 0x40000>; 877 878 display@15200000 { 879 compatible = "nvidia,tegra186-dc"; 880 reg = <0x15200000 0x10000>; 881 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 883 clock-names = "dc"; 884 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 885 reset-names = "dc"; 886 887 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 888 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 889 890 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 891 nvidia,head = <0>; 892 }; 893 894 display@15210000 { 895 compatible = "nvidia,tegra186-dc"; 896 reg = <0x15210000 0x10000>; 897 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 899 clock-names = "dc"; 900 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 901 reset-names = "dc"; 902 903 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 904 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 905 906 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 907 nvidia,head = <1>; 908 }; 909 910 display@15220000 { 911 compatible = "nvidia,tegra186-dc"; 912 reg = <0x15220000 0x10000>; 913 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 915 clock-names = "dc"; 916 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 917 reset-names = "dc"; 918 919 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 920 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 921 922 nvidia,outputs = <&sor0 &sor1>; 923 nvidia,head = <2>; 924 }; 925 }; 926 927 dsia: dsi@15300000 { 928 compatible = "nvidia,tegra186-dsi"; 929 reg = <0x15300000 0x10000>; 930 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&bpmp TEGRA186_CLK_DSI>, 932 <&bpmp TEGRA186_CLK_DSIA_LP>, 933 <&bpmp TEGRA186_CLK_PLLD>; 934 clock-names = "dsi", "lp", "parent"; 935 resets = <&bpmp TEGRA186_RESET_DSI>; 936 reset-names = "dsi"; 937 status = "disabled"; 938 939 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 940 }; 941 942 vic@15340000 { 943 compatible = "nvidia,tegra186-vic"; 944 reg = <0x15340000 0x40000>; 945 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&bpmp TEGRA186_CLK_VIC>; 947 clock-names = "vic"; 948 resets = <&bpmp TEGRA186_RESET_VIC>; 949 reset-names = "vic"; 950 951 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 952 }; 953 954 dsib: dsi@15400000 { 955 compatible = "nvidia,tegra186-dsi"; 956 reg = <0x15400000 0x10000>; 957 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&bpmp TEGRA186_CLK_DSIB>, 959 <&bpmp TEGRA186_CLK_DSIB_LP>, 960 <&bpmp TEGRA186_CLK_PLLD>; 961 clock-names = "dsi", "lp", "parent"; 962 resets = <&bpmp TEGRA186_RESET_DSIB>; 963 reset-names = "dsi"; 964 status = "disabled"; 965 966 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 967 }; 968 969 sor0: sor@15540000 { 970 compatible = "nvidia,tegra186-sor"; 971 reg = <0x15540000 0x10000>; 972 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&bpmp TEGRA186_CLK_SOR0>, 974 <&bpmp TEGRA186_CLK_SOR0_OUT>, 975 <&bpmp TEGRA186_CLK_PLLD2>, 976 <&bpmp TEGRA186_CLK_PLLDP>, 977 <&bpmp TEGRA186_CLK_SOR_SAFE>, 978 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 979 clock-names = "sor", "out", "parent", "dp", "safe", 980 "pad"; 981 resets = <&bpmp TEGRA186_RESET_SOR0>; 982 reset-names = "sor"; 983 pinctrl-0 = <&state_dpaux_aux>; 984 pinctrl-1 = <&state_dpaux_i2c>; 985 pinctrl-2 = <&state_dpaux_off>; 986 pinctrl-names = "aux", "i2c", "off"; 987 status = "disabled"; 988 989 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 990 nvidia,interface = <0>; 991 }; 992 993 sor1: sor@15580000 { 994 compatible = "nvidia,tegra186-sor1"; 995 reg = <0x15580000 0x10000>; 996 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&bpmp TEGRA186_CLK_SOR1>, 998 <&bpmp TEGRA186_CLK_SOR1_OUT>, 999 <&bpmp TEGRA186_CLK_PLLD3>, 1000 <&bpmp TEGRA186_CLK_PLLDP>, 1001 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1002 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1003 clock-names = "sor", "out", "parent", "dp", "safe", 1004 "pad"; 1005 resets = <&bpmp TEGRA186_RESET_SOR1>; 1006 reset-names = "sor"; 1007 pinctrl-0 = <&state_dpaux1_aux>; 1008 pinctrl-1 = <&state_dpaux1_i2c>; 1009 pinctrl-2 = <&state_dpaux1_off>; 1010 pinctrl-names = "aux", "i2c", "off"; 1011 status = "disabled"; 1012 1013 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1014 nvidia,interface = <1>; 1015 }; 1016 1017 dpaux: dpaux@155c0000 { 1018 compatible = "nvidia,tegra186-dpaux"; 1019 reg = <0x155c0000 0x10000>; 1020 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1022 <&bpmp TEGRA186_CLK_PLLDP>; 1023 clock-names = "dpaux", "parent"; 1024 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1025 reset-names = "dpaux"; 1026 status = "disabled"; 1027 1028 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1029 1030 state_dpaux_aux: pinmux-aux { 1031 groups = "dpaux-io"; 1032 function = "aux"; 1033 }; 1034 1035 state_dpaux_i2c: pinmux-i2c { 1036 groups = "dpaux-io"; 1037 function = "i2c"; 1038 }; 1039 1040 state_dpaux_off: pinmux-off { 1041 groups = "dpaux-io"; 1042 function = "off"; 1043 }; 1044 1045 i2c-bus { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 }; 1049 }; 1050 1051 padctl@15880000 { 1052 compatible = "nvidia,tegra186-dsi-padctl"; 1053 reg = <0x15880000 0x10000>; 1054 resets = <&bpmp TEGRA186_RESET_DSI>; 1055 reset-names = "dsi"; 1056 status = "disabled"; 1057 }; 1058 1059 dsic: dsi@15900000 { 1060 compatible = "nvidia,tegra186-dsi"; 1061 reg = <0x15900000 0x10000>; 1062 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1064 <&bpmp TEGRA186_CLK_DSIC_LP>, 1065 <&bpmp TEGRA186_CLK_PLLD>; 1066 clock-names = "dsi", "lp", "parent"; 1067 resets = <&bpmp TEGRA186_RESET_DSIC>; 1068 reset-names = "dsi"; 1069 status = "disabled"; 1070 1071 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1072 }; 1073 1074 dsid: dsi@15940000 { 1075 compatible = "nvidia,tegra186-dsi"; 1076 reg = <0x15940000 0x10000>; 1077 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&bpmp TEGRA186_CLK_DSID>, 1079 <&bpmp TEGRA186_CLK_DSID_LP>, 1080 <&bpmp TEGRA186_CLK_PLLD>; 1081 clock-names = "dsi", "lp", "parent"; 1082 resets = <&bpmp TEGRA186_RESET_DSID>; 1083 reset-names = "dsi"; 1084 status = "disabled"; 1085 1086 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1087 }; 1088 }; 1089 1090 gpu@17000000 { 1091 compatible = "nvidia,gp10b"; 1092 reg = <0x0 0x17000000 0x0 0x1000000>, 1093 <0x0 0x18000000 0x0 0x1000000>; 1094 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1095 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1096 interrupt-names = "stall", "nonstall"; 1097 1098 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1099 <&bpmp TEGRA186_CLK_GPU>; 1100 clock-names = "gpu", "pwr"; 1101 resets = <&bpmp TEGRA186_RESET_GPU>; 1102 reset-names = "gpu"; 1103 status = "disabled"; 1104 1105 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1106 }; 1107 1108 sysram@30000000 { 1109 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1110 reg = <0x0 0x30000000 0x0 0x50000>; 1111 #address-cells = <2>; 1112 #size-cells = <2>; 1113 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1114 1115 cpu_bpmp_tx: shmem@4e000 { 1116 compatible = "nvidia,tegra186-bpmp-shmem"; 1117 reg = <0x0 0x4e000 0x0 0x1000>; 1118 label = "cpu-bpmp-tx"; 1119 pool; 1120 }; 1121 1122 cpu_bpmp_rx: shmem@4f000 { 1123 compatible = "nvidia,tegra186-bpmp-shmem"; 1124 reg = <0x0 0x4f000 0x0 0x1000>; 1125 label = "cpu-bpmp-rx"; 1126 pool; 1127 }; 1128 }; 1129 1130 cpus { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 cpu@0 { 1135 compatible = "nvidia,tegra186-denver"; 1136 device_type = "cpu"; 1137 i-cache-size = <0x20000>; 1138 i-cache-line-size = <64>; 1139 i-cache-sets = <512>; 1140 d-cache-size = <0x10000>; 1141 d-cache-line-size = <64>; 1142 d-cache-sets = <256>; 1143 next-level-cache = <&L2_DENVER>; 1144 reg = <0x000>; 1145 }; 1146 1147 cpu@1 { 1148 compatible = "nvidia,tegra186-denver"; 1149 device_type = "cpu"; 1150 i-cache-size = <0x20000>; 1151 i-cache-line-size = <64>; 1152 i-cache-sets = <512>; 1153 d-cache-size = <0x10000>; 1154 d-cache-line-size = <64>; 1155 d-cache-sets = <256>; 1156 next-level-cache = <&L2_DENVER>; 1157 reg = <0x001>; 1158 }; 1159 1160 cpu@2 { 1161 compatible = "arm,cortex-a57"; 1162 device_type = "cpu"; 1163 i-cache-size = <0xC000>; 1164 i-cache-line-size = <64>; 1165 i-cache-sets = <256>; 1166 d-cache-size = <0x8000>; 1167 d-cache-line-size = <64>; 1168 d-cache-sets = <256>; 1169 next-level-cache = <&L2_A57>; 1170 reg = <0x100>; 1171 }; 1172 1173 cpu@3 { 1174 compatible = "arm,cortex-a57"; 1175 device_type = "cpu"; 1176 i-cache-size = <0xC000>; 1177 i-cache-line-size = <64>; 1178 i-cache-sets = <256>; 1179 d-cache-size = <0x8000>; 1180 d-cache-line-size = <64>; 1181 d-cache-sets = <256>; 1182 next-level-cache = <&L2_A57>; 1183 reg = <0x101>; 1184 }; 1185 1186 cpu@4 { 1187 compatible = "arm,cortex-a57"; 1188 device_type = "cpu"; 1189 i-cache-size = <0xC000>; 1190 i-cache-line-size = <64>; 1191 i-cache-sets = <256>; 1192 d-cache-size = <0x8000>; 1193 d-cache-line-size = <64>; 1194 d-cache-sets = <256>; 1195 next-level-cache = <&L2_A57>; 1196 reg = <0x102>; 1197 }; 1198 1199 cpu@5 { 1200 compatible = "arm,cortex-a57"; 1201 device_type = "cpu"; 1202 i-cache-size = <0xC000>; 1203 i-cache-line-size = <64>; 1204 i-cache-sets = <256>; 1205 d-cache-size = <0x8000>; 1206 d-cache-line-size = <64>; 1207 d-cache-sets = <256>; 1208 next-level-cache = <&L2_A57>; 1209 reg = <0x103>; 1210 }; 1211 1212 L2_DENVER: l2-cache0 { 1213 compatible = "cache"; 1214 cache-unified; 1215 cache-level = <2>; 1216 cache-size = <0x200000>; 1217 cache-line-size = <64>; 1218 cache-sets = <2048>; 1219 }; 1220 1221 L2_A57: l2-cache1 { 1222 compatible = "cache"; 1223 cache-unified; 1224 cache-level = <2>; 1225 cache-size = <0x200000>; 1226 cache-line-size = <64>; 1227 cache-sets = <2048>; 1228 }; 1229 }; 1230 1231 bpmp: bpmp { 1232 compatible = "nvidia,tegra186-bpmp"; 1233 iommus = <&smmu TEGRA186_SID_BPMP>; 1234 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1235 TEGRA_HSP_DB_MASTER_BPMP>; 1236 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1237 #clock-cells = <1>; 1238 #reset-cells = <1>; 1239 #power-domain-cells = <1>; 1240 1241 bpmp_i2c: i2c { 1242 compatible = "nvidia,tegra186-bpmp-i2c"; 1243 nvidia,bpmp-bus-id = <5>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 bpmp_thermal: thermal { 1250 compatible = "nvidia,tegra186-bpmp-thermal"; 1251 #thermal-sensor-cells = <1>; 1252 }; 1253 }; 1254 1255 thermal-zones { 1256 a57 { 1257 polling-delay = <0>; 1258 polling-delay-passive = <1000>; 1259 1260 thermal-sensors = 1261 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1262 1263 trips { 1264 critical { 1265 temperature = <101000>; 1266 hysteresis = <0>; 1267 type = "critical"; 1268 }; 1269 }; 1270 1271 cooling-maps { 1272 }; 1273 }; 1274 1275 denver { 1276 polling-delay = <0>; 1277 polling-delay-passive = <1000>; 1278 1279 thermal-sensors = 1280 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1281 1282 trips { 1283 critical { 1284 temperature = <101000>; 1285 hysteresis = <0>; 1286 type = "critical"; 1287 }; 1288 }; 1289 1290 cooling-maps { 1291 }; 1292 }; 1293 1294 gpu { 1295 polling-delay = <0>; 1296 polling-delay-passive = <1000>; 1297 1298 thermal-sensors = 1299 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1300 1301 trips { 1302 critical { 1303 temperature = <101000>; 1304 hysteresis = <0>; 1305 type = "critical"; 1306 }; 1307 }; 1308 1309 cooling-maps { 1310 }; 1311 }; 1312 1313 pll { 1314 polling-delay = <0>; 1315 polling-delay-passive = <1000>; 1316 1317 thermal-sensors = 1318 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1319 1320 trips { 1321 critical { 1322 temperature = <101000>; 1323 hysteresis = <0>; 1324 type = "critical"; 1325 }; 1326 }; 1327 1328 cooling-maps { 1329 }; 1330 }; 1331 1332 always_on { 1333 polling-delay = <0>; 1334 polling-delay-passive = <1000>; 1335 1336 thermal-sensors = 1337 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1338 1339 trips { 1340 critical { 1341 temperature = <101000>; 1342 hysteresis = <0>; 1343 type = "critical"; 1344 }; 1345 }; 1346 1347 cooling-maps { 1348 }; 1349 }; 1350 }; 1351 1352 timer { 1353 compatible = "arm,armv8-timer"; 1354 interrupts = <GIC_PPI 13 1355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1356 <GIC_PPI 14 1357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1358 <GIC_PPI 11 1359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1360 <GIC_PPI 10 1361 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1362 interrupt-parent = <&gic>; 1363 always-on; 1364 }; 1365}; 1366