1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 aconnect { 74 compatible = "nvidia,tegra186-aconnect", 75 "nvidia,tegra210-aconnect"; 76 clocks = <&bpmp TEGRA186_CLK_APE>, 77 <&bpmp TEGRA186_CLK_APB2APE>; 78 clock-names = "ape", "apb2ape"; 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 83 status = "disabled"; 84 85 dma-controller@2930000 { 86 compatible = "nvidia,tegra186-adma"; 87 reg = <0x02930000 0x20000>; 88 interrupt-parent = <&agic>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 121 #dma-cells = <1>; 122 clocks = <&bpmp TEGRA186_CLK_AHUB>; 123 clock-names = "d_audio"; 124 status = "disabled"; 125 }; 126 127 agic: interrupt-controller@2a40000 { 128 compatible = "nvidia,tegra186-agic", 129 "nvidia,tegra210-agic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x02a41000 0x1000>, 133 <0x02a42000 0x2000>; 134 interrupts = <GIC_SPI 145 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA186_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 memory-controller@2c00000 { 143 compatible = "nvidia,tegra186-mc"; 144 reg = <0x0 0x02c00000 0x0 0xb0000>; 145 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146 status = "disabled"; 147 }; 148 149 uarta: serial@3100000 { 150 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 151 reg = <0x0 0x03100000 0x0 0x40>; 152 reg-shift = <2>; 153 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&bpmp TEGRA186_CLK_UARTA>; 155 clock-names = "serial"; 156 resets = <&bpmp TEGRA186_RESET_UARTA>; 157 reset-names = "serial"; 158 status = "disabled"; 159 }; 160 161 uartb: serial@3110000 { 162 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 163 reg = <0x0 0x03110000 0x0 0x40>; 164 reg-shift = <2>; 165 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&bpmp TEGRA186_CLK_UARTB>; 167 clock-names = "serial"; 168 resets = <&bpmp TEGRA186_RESET_UARTB>; 169 reset-names = "serial"; 170 status = "disabled"; 171 }; 172 173 uartd: serial@3130000 { 174 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 175 reg = <0x0 0x03130000 0x0 0x40>; 176 reg-shift = <2>; 177 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&bpmp TEGRA186_CLK_UARTD>; 179 clock-names = "serial"; 180 resets = <&bpmp TEGRA186_RESET_UARTD>; 181 reset-names = "serial"; 182 status = "disabled"; 183 }; 184 185 uarte: serial@3140000 { 186 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 187 reg = <0x0 0x03140000 0x0 0x40>; 188 reg-shift = <2>; 189 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&bpmp TEGRA186_CLK_UARTE>; 191 clock-names = "serial"; 192 resets = <&bpmp TEGRA186_RESET_UARTE>; 193 reset-names = "serial"; 194 status = "disabled"; 195 }; 196 197 uartf: serial@3150000 { 198 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 199 reg = <0x0 0x03150000 0x0 0x40>; 200 reg-shift = <2>; 201 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&bpmp TEGRA186_CLK_UARTF>; 203 clock-names = "serial"; 204 resets = <&bpmp TEGRA186_RESET_UARTF>; 205 reset-names = "serial"; 206 status = "disabled"; 207 }; 208 209 gen1_i2c: i2c@3160000 { 210 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 211 reg = <0x0 0x03160000 0x0 0x10000>; 212 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 clocks = <&bpmp TEGRA186_CLK_I2C1>; 216 clock-names = "div-clk"; 217 resets = <&bpmp TEGRA186_RESET_I2C1>; 218 reset-names = "i2c"; 219 status = "disabled"; 220 }; 221 222 cam_i2c: i2c@3180000 { 223 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 224 reg = <0x0 0x03180000 0x0 0x10000>; 225 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 clocks = <&bpmp TEGRA186_CLK_I2C3>; 229 clock-names = "div-clk"; 230 resets = <&bpmp TEGRA186_RESET_I2C3>; 231 reset-names = "i2c"; 232 status = "disabled"; 233 }; 234 235 /* shares pads with dpaux1 */ 236 dp_aux_ch1_i2c: i2c@3190000 { 237 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 238 reg = <0x0 0x03190000 0x0 0x10000>; 239 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 clocks = <&bpmp TEGRA186_CLK_I2C4>; 243 clock-names = "div-clk"; 244 resets = <&bpmp TEGRA186_RESET_I2C4>; 245 reset-names = "i2c"; 246 pinctrl-names = "default", "idle"; 247 pinctrl-0 = <&state_dpaux1_i2c>; 248 pinctrl-1 = <&state_dpaux1_off>; 249 status = "disabled"; 250 }; 251 252 /* controlled by BPMP, should not be enabled */ 253 pwr_i2c: i2c@31a0000 { 254 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 255 reg = <0x0 0x031a0000 0x0 0x10000>; 256 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&bpmp TEGRA186_CLK_I2C5>; 260 clock-names = "div-clk"; 261 resets = <&bpmp TEGRA186_RESET_I2C5>; 262 reset-names = "i2c"; 263 status = "disabled"; 264 }; 265 266 /* shares pads with dpaux0 */ 267 dp_aux_ch0_i2c: i2c@31b0000 { 268 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 269 reg = <0x0 0x031b0000 0x0 0x10000>; 270 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 clocks = <&bpmp TEGRA186_CLK_I2C6>; 274 clock-names = "div-clk"; 275 resets = <&bpmp TEGRA186_RESET_I2C6>; 276 reset-names = "i2c"; 277 pinctrl-names = "default", "idle"; 278 pinctrl-0 = <&state_dpaux_i2c>; 279 pinctrl-1 = <&state_dpaux_off>; 280 status = "disabled"; 281 }; 282 283 gen7_i2c: i2c@31c0000 { 284 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 285 reg = <0x0 0x031c0000 0x0 0x10000>; 286 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&bpmp TEGRA186_CLK_I2C7>; 290 clock-names = "div-clk"; 291 resets = <&bpmp TEGRA186_RESET_I2C7>; 292 reset-names = "i2c"; 293 status = "disabled"; 294 }; 295 296 gen9_i2c: i2c@31e0000 { 297 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 298 reg = <0x0 0x031e0000 0x0 0x10000>; 299 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clocks = <&bpmp TEGRA186_CLK_I2C9>; 303 clock-names = "div-clk"; 304 resets = <&bpmp TEGRA186_RESET_I2C9>; 305 reset-names = "i2c"; 306 status = "disabled"; 307 }; 308 309 sdmmc1: sdhci@3400000 { 310 compatible = "nvidia,tegra186-sdhci"; 311 reg = <0x0 0x03400000 0x0 0x10000>; 312 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 314 clock-names = "sdhci"; 315 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 316 reset-names = "sdhci"; 317 iommus = <&smmu TEGRA186_SID_SDMMC1>; 318 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 319 pinctrl-0 = <&sdmmc1_3v3>; 320 pinctrl-1 = <&sdmmc1_1v8>; 321 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 322 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 323 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 324 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 325 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 326 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 327 nvidia,default-tap = <0x5>; 328 nvidia,default-trim = <0xb>; 329 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 330 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 332 status = "disabled"; 333 }; 334 335 sdmmc2: sdhci@3420000 { 336 compatible = "nvidia,tegra186-sdhci"; 337 reg = <0x0 0x03420000 0x0 0x10000>; 338 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 340 clock-names = "sdhci"; 341 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 342 reset-names = "sdhci"; 343 iommus = <&smmu TEGRA186_SID_SDMMC2>; 344 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 345 pinctrl-0 = <&sdmmc2_3v3>; 346 pinctrl-1 = <&sdmmc2_1v8>; 347 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 348 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 349 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 350 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 351 nvidia,default-tap = <0x5>; 352 nvidia,default-trim = <0xb>; 353 status = "disabled"; 354 }; 355 356 sdmmc3: sdhci@3440000 { 357 compatible = "nvidia,tegra186-sdhci"; 358 reg = <0x0 0x03440000 0x0 0x10000>; 359 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 361 clock-names = "sdhci"; 362 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 363 reset-names = "sdhci"; 364 iommus = <&smmu TEGRA186_SID_SDMMC3>; 365 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 366 pinctrl-0 = <&sdmmc3_3v3>; 367 pinctrl-1 = <&sdmmc3_1v8>; 368 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 369 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 370 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 371 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 372 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 373 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 374 nvidia,default-tap = <0x5>; 375 nvidia,default-trim = <0xb>; 376 status = "disabled"; 377 }; 378 379 sdmmc4: sdhci@3460000 { 380 compatible = "nvidia,tegra186-sdhci"; 381 reg = <0x0 0x03460000 0x0 0x10000>; 382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 384 clock-names = "sdhci"; 385 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 386 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 387 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 388 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 389 reset-names = "sdhci"; 390 iommus = <&smmu TEGRA186_SID_SDMMC4>; 391 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 392 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 393 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 394 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 395 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 396 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 397 nvidia,default-tap = <0x9>; 398 nvidia,default-trim = <0x5>; 399 nvidia,dqs-trim = <63>; 400 mmc-hs400-1_8v; 401 supports-cqe; 402 status = "disabled"; 403 }; 404 405 hda@3510000 { 406 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 407 reg = <0x0 0x03510000 0x0 0x10000>; 408 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&bpmp TEGRA186_CLK_HDA>, 410 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 411 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 412 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 413 resets = <&bpmp TEGRA186_RESET_HDA>, 414 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 415 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 416 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 417 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 418 iommus = <&smmu TEGRA186_SID_HDA>; 419 status = "disabled"; 420 }; 421 422 padctl: padctl@3520000 { 423 compatible = "nvidia,tegra186-xusb-padctl"; 424 reg = <0x0 0x03520000 0x0 0x1000>, 425 <0x0 0x03540000 0x0 0x1000>; 426 reg-names = "padctl", "ao"; 427 428 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 429 reset-names = "padctl"; 430 431 status = "disabled"; 432 433 pads { 434 usb2 { 435 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 436 clock-names = "trk"; 437 status = "disabled"; 438 439 lanes { 440 usb2-0 { 441 status = "disabled"; 442 #phy-cells = <0>; 443 }; 444 445 usb2-1 { 446 status = "disabled"; 447 #phy-cells = <0>; 448 }; 449 450 usb2-2 { 451 status = "disabled"; 452 #phy-cells = <0>; 453 }; 454 }; 455 }; 456 457 hsic { 458 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 459 clock-names = "trk"; 460 status = "disabled"; 461 462 lanes { 463 hsic-0 { 464 status = "disabled"; 465 #phy-cells = <0>; 466 }; 467 }; 468 }; 469 470 usb3 { 471 status = "disabled"; 472 473 lanes { 474 usb3-0 { 475 status = "disabled"; 476 #phy-cells = <0>; 477 }; 478 479 usb3-1 { 480 status = "disabled"; 481 #phy-cells = <0>; 482 }; 483 484 usb3-2 { 485 status = "disabled"; 486 #phy-cells = <0>; 487 }; 488 }; 489 }; 490 }; 491 492 ports { 493 usb2-0 { 494 status = "disabled"; 495 }; 496 497 usb2-1 { 498 status = "disabled"; 499 }; 500 501 usb2-2 { 502 status = "disabled"; 503 }; 504 505 hsic-0 { 506 status = "disabled"; 507 }; 508 509 usb3-0 { 510 status = "disabled"; 511 }; 512 513 usb3-1 { 514 status = "disabled"; 515 }; 516 517 usb3-2 { 518 status = "disabled"; 519 }; 520 }; 521 }; 522 523 usb@3530000 { 524 compatible = "nvidia,tegra186-xusb"; 525 reg = <0x0 0x03530000 0x0 0x8000>, 526 <0x0 0x03538000 0x0 0x1000>; 527 reg-names = "hcd", "fpci"; 528 529 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 530 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 533 534 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 535 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 536 <&bpmp TEGRA186_CLK_XUSB_SS>, 537 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 538 <&bpmp TEGRA186_CLK_CLK_M>, 539 <&bpmp TEGRA186_CLK_XUSB_FS>, 540 <&bpmp TEGRA186_CLK_PLLU>, 541 <&bpmp TEGRA186_CLK_CLK_M>, 542 <&bpmp TEGRA186_CLK_PLLE>; 543 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 544 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 545 "pll_u_480m", "clk_m", "pll_e"; 546 547 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 548 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 549 power-domain-names = "xusb_host", "xusb_ss"; 550 nvidia,xusb-padctl = <&padctl>; 551 552 status = "disabled"; 553 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 558 fuse@3820000 { 559 compatible = "nvidia,tegra186-efuse"; 560 reg = <0x0 0x03820000 0x0 0x10000>; 561 clocks = <&bpmp TEGRA186_CLK_FUSE>; 562 clock-names = "fuse"; 563 }; 564 565 gic: interrupt-controller@3881000 { 566 compatible = "arm,gic-400"; 567 #interrupt-cells = <3>; 568 interrupt-controller; 569 reg = <0x0 0x03881000 0x0 0x1000>, 570 <0x0 0x03882000 0x0 0x2000>; 571 interrupts = <GIC_PPI 9 572 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 573 interrupt-parent = <&gic>; 574 }; 575 576 cec@3960000 { 577 compatible = "nvidia,tegra186-cec"; 578 reg = <0x0 0x03960000 0x0 0x10000>; 579 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&bpmp TEGRA186_CLK_CEC>; 581 clock-names = "cec"; 582 status = "disabled"; 583 }; 584 585 hsp_top0: hsp@3c00000 { 586 compatible = "nvidia,tegra186-hsp"; 587 reg = <0x0 0x03c00000 0x0 0xa0000>; 588 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "doorbell"; 590 #mbox-cells = <2>; 591 status = "disabled"; 592 }; 593 594 gen2_i2c: i2c@c240000 { 595 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 596 reg = <0x0 0x0c240000 0x0 0x10000>; 597 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 clocks = <&bpmp TEGRA186_CLK_I2C2>; 601 clock-names = "div-clk"; 602 resets = <&bpmp TEGRA186_RESET_I2C2>; 603 reset-names = "i2c"; 604 status = "disabled"; 605 }; 606 607 gen8_i2c: i2c@c250000 { 608 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 609 reg = <0x0 0x0c250000 0x0 0x10000>; 610 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&bpmp TEGRA186_CLK_I2C8>; 614 clock-names = "div-clk"; 615 resets = <&bpmp TEGRA186_RESET_I2C8>; 616 reset-names = "i2c"; 617 status = "disabled"; 618 }; 619 620 uartc: serial@c280000 { 621 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 622 reg = <0x0 0x0c280000 0x0 0x40>; 623 reg-shift = <2>; 624 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&bpmp TEGRA186_CLK_UARTC>; 626 clock-names = "serial"; 627 resets = <&bpmp TEGRA186_RESET_UARTC>; 628 reset-names = "serial"; 629 status = "disabled"; 630 }; 631 632 uartg: serial@c290000 { 633 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 634 reg = <0x0 0x0c290000 0x0 0x40>; 635 reg-shift = <2>; 636 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&bpmp TEGRA186_CLK_UARTG>; 638 clock-names = "serial"; 639 resets = <&bpmp TEGRA186_RESET_UARTG>; 640 reset-names = "serial"; 641 status = "disabled"; 642 }; 643 644 rtc: rtc@c2a0000 { 645 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 646 reg = <0 0x0c2a0000 0 0x10000>; 647 interrupt-parent = <&pmc>; 648 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 650 clock-names = "rtc"; 651 status = "disabled"; 652 }; 653 654 gpio_aon: gpio@c2f0000 { 655 compatible = "nvidia,tegra186-gpio-aon"; 656 reg-names = "security", "gpio"; 657 reg = <0x0 0xc2f0000 0x0 0x1000>, 658 <0x0 0xc2f1000 0x0 0x1000>; 659 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 660 gpio-controller; 661 #gpio-cells = <2>; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 }; 665 666 pmc: pmc@c360000 { 667 compatible = "nvidia,tegra186-pmc"; 668 reg = <0 0x0c360000 0 0x10000>, 669 <0 0x0c370000 0 0x10000>, 670 <0 0x0c380000 0 0x10000>, 671 <0 0x0c390000 0 0x10000>; 672 reg-names = "pmc", "wake", "aotag", "scratch"; 673 674 #interrupt-cells = <2>; 675 interrupt-controller; 676 677 sdmmc1_3v3: sdmmc1-3v3 { 678 pins = "sdmmc1-hv"; 679 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 680 }; 681 682 sdmmc1_1v8: sdmmc1-1v8 { 683 pins = "sdmmc1-hv"; 684 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 685 }; 686 687 sdmmc2_3v3: sdmmc2-3v3 { 688 pins = "sdmmc2-hv"; 689 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 690 }; 691 692 sdmmc2_1v8: sdmmc2-1v8 { 693 pins = "sdmmc2-hv"; 694 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 695 }; 696 697 sdmmc3_3v3: sdmmc3-3v3 { 698 pins = "sdmmc3-hv"; 699 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 700 }; 701 702 sdmmc3_1v8: sdmmc3-1v8 { 703 pins = "sdmmc3-hv"; 704 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 705 }; 706 }; 707 708 ccplex@e000000 { 709 compatible = "nvidia,tegra186-ccplex-cluster"; 710 reg = <0x0 0x0e000000 0x0 0x3fffff>; 711 712 nvidia,bpmp = <&bpmp>; 713 }; 714 715 pcie@10003000 { 716 compatible = "nvidia,tegra186-pcie"; 717 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 718 device_type = "pci"; 719 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 720 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 721 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 722 reg-names = "pads", "afi", "cs"; 723 724 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 725 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 726 interrupt-names = "intr", "msi"; 727 728 #interrupt-cells = <1>; 729 interrupt-map-mask = <0 0 0 0>; 730 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 731 732 bus-range = <0x00 0xff>; 733 #address-cells = <3>; 734 #size-cells = <2>; 735 736 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 737 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 738 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 739 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 740 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 741 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 742 743 clocks = <&bpmp TEGRA186_CLK_AFI>, 744 <&bpmp TEGRA186_CLK_PCIE>, 745 <&bpmp TEGRA186_CLK_PLLE>; 746 clock-names = "afi", "pex", "pll_e"; 747 748 resets = <&bpmp TEGRA186_RESET_AFI>, 749 <&bpmp TEGRA186_RESET_PCIE>, 750 <&bpmp TEGRA186_RESET_PCIEXCLK>; 751 reset-names = "afi", "pex", "pcie_x"; 752 753 iommus = <&smmu TEGRA186_SID_AFI>; 754 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 755 iommu-map-mask = <0x0>; 756 757 status = "disabled"; 758 759 pci@1,0 { 760 device_type = "pci"; 761 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 762 reg = <0x000800 0 0 0 0>; 763 status = "disabled"; 764 765 #address-cells = <3>; 766 #size-cells = <2>; 767 ranges; 768 769 nvidia,num-lanes = <2>; 770 }; 771 772 pci@2,0 { 773 device_type = "pci"; 774 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 775 reg = <0x001000 0 0 0 0>; 776 status = "disabled"; 777 778 #address-cells = <3>; 779 #size-cells = <2>; 780 ranges; 781 782 nvidia,num-lanes = <1>; 783 }; 784 785 pci@3,0 { 786 device_type = "pci"; 787 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 788 reg = <0x001800 0 0 0 0>; 789 status = "disabled"; 790 791 #address-cells = <3>; 792 #size-cells = <2>; 793 ranges; 794 795 nvidia,num-lanes = <1>; 796 }; 797 }; 798 799 smmu: iommu@12000000 { 800 compatible = "arm,mmu-500"; 801 reg = <0 0x12000000 0 0x800000>; 802 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 867 stream-match-mask = <0x7f80>; 868 #global-interrupts = <1>; 869 #iommu-cells = <1>; 870 }; 871 872 host1x@13e00000 { 873 compatible = "nvidia,tegra186-host1x", "simple-bus"; 874 reg = <0x0 0x13e00000 0x0 0x10000>, 875 <0x0 0x13e10000 0x0 0x10000>; 876 reg-names = "hypervisor", "vm"; 877 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 880 clock-names = "host1x"; 881 resets = <&bpmp TEGRA186_RESET_HOST1X>; 882 reset-names = "host1x"; 883 884 #address-cells = <1>; 885 #size-cells = <1>; 886 887 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 888 iommus = <&smmu TEGRA186_SID_HOST1X>; 889 890 dpaux1: dpaux@15040000 { 891 compatible = "nvidia,tegra186-dpaux"; 892 reg = <0x15040000 0x10000>; 893 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 895 <&bpmp TEGRA186_CLK_PLLDP>; 896 clock-names = "dpaux", "parent"; 897 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 898 reset-names = "dpaux"; 899 status = "disabled"; 900 901 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 902 903 state_dpaux1_aux: pinmux-aux { 904 groups = "dpaux-io"; 905 function = "aux"; 906 }; 907 908 state_dpaux1_i2c: pinmux-i2c { 909 groups = "dpaux-io"; 910 function = "i2c"; 911 }; 912 913 state_dpaux1_off: pinmux-off { 914 groups = "dpaux-io"; 915 function = "off"; 916 }; 917 918 i2c-bus { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 }; 922 }; 923 924 display-hub@15200000 { 925 compatible = "nvidia,tegra186-display", "simple-bus"; 926 reg = <0x15200000 0x00040000>; 927 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 928 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 929 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 930 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 931 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 932 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 933 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 934 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 935 "wgrp3", "wgrp4", "wgrp5"; 936 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 937 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 938 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 939 clock-names = "disp", "dsc", "hub"; 940 status = "disabled"; 941 942 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 943 944 #address-cells = <1>; 945 #size-cells = <1>; 946 947 ranges = <0x15200000 0x15200000 0x40000>; 948 949 display@15200000 { 950 compatible = "nvidia,tegra186-dc"; 951 reg = <0x15200000 0x10000>; 952 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 954 clock-names = "dc"; 955 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 956 reset-names = "dc"; 957 958 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 959 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 960 961 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 962 nvidia,head = <0>; 963 }; 964 965 display@15210000 { 966 compatible = "nvidia,tegra186-dc"; 967 reg = <0x15210000 0x10000>; 968 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 970 clock-names = "dc"; 971 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 972 reset-names = "dc"; 973 974 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 975 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 976 977 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 978 nvidia,head = <1>; 979 }; 980 981 display@15220000 { 982 compatible = "nvidia,tegra186-dc"; 983 reg = <0x15220000 0x10000>; 984 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 986 clock-names = "dc"; 987 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 988 reset-names = "dc"; 989 990 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 991 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 992 993 nvidia,outputs = <&sor0 &sor1>; 994 nvidia,head = <2>; 995 }; 996 }; 997 998 dsia: dsi@15300000 { 999 compatible = "nvidia,tegra186-dsi"; 1000 reg = <0x15300000 0x10000>; 1001 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&bpmp TEGRA186_CLK_DSI>, 1003 <&bpmp TEGRA186_CLK_DSIA_LP>, 1004 <&bpmp TEGRA186_CLK_PLLD>; 1005 clock-names = "dsi", "lp", "parent"; 1006 resets = <&bpmp TEGRA186_RESET_DSI>; 1007 reset-names = "dsi"; 1008 status = "disabled"; 1009 1010 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1011 }; 1012 1013 vic@15340000 { 1014 compatible = "nvidia,tegra186-vic"; 1015 reg = <0x15340000 0x40000>; 1016 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&bpmp TEGRA186_CLK_VIC>; 1018 clock-names = "vic"; 1019 resets = <&bpmp TEGRA186_RESET_VIC>; 1020 reset-names = "vic"; 1021 1022 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1023 iommus = <&smmu TEGRA186_SID_VIC>; 1024 }; 1025 1026 dsib: dsi@15400000 { 1027 compatible = "nvidia,tegra186-dsi"; 1028 reg = <0x15400000 0x10000>; 1029 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1031 <&bpmp TEGRA186_CLK_DSIB_LP>, 1032 <&bpmp TEGRA186_CLK_PLLD>; 1033 clock-names = "dsi", "lp", "parent"; 1034 resets = <&bpmp TEGRA186_RESET_DSIB>; 1035 reset-names = "dsi"; 1036 status = "disabled"; 1037 1038 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1039 }; 1040 1041 sor0: sor@15540000 { 1042 compatible = "nvidia,tegra186-sor"; 1043 reg = <0x15540000 0x10000>; 1044 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1046 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1047 <&bpmp TEGRA186_CLK_PLLD2>, 1048 <&bpmp TEGRA186_CLK_PLLDP>, 1049 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1050 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1051 clock-names = "sor", "out", "parent", "dp", "safe", 1052 "pad"; 1053 resets = <&bpmp TEGRA186_RESET_SOR0>; 1054 reset-names = "sor"; 1055 pinctrl-0 = <&state_dpaux_aux>; 1056 pinctrl-1 = <&state_dpaux_i2c>; 1057 pinctrl-2 = <&state_dpaux_off>; 1058 pinctrl-names = "aux", "i2c", "off"; 1059 status = "disabled"; 1060 1061 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1062 nvidia,interface = <0>; 1063 }; 1064 1065 sor1: sor@15580000 { 1066 compatible = "nvidia,tegra186-sor"; 1067 reg = <0x15580000 0x10000>; 1068 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1070 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1071 <&bpmp TEGRA186_CLK_PLLD3>, 1072 <&bpmp TEGRA186_CLK_PLLDP>, 1073 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1074 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1075 clock-names = "sor", "out", "parent", "dp", "safe", 1076 "pad"; 1077 resets = <&bpmp TEGRA186_RESET_SOR1>; 1078 reset-names = "sor"; 1079 pinctrl-0 = <&state_dpaux1_aux>; 1080 pinctrl-1 = <&state_dpaux1_i2c>; 1081 pinctrl-2 = <&state_dpaux1_off>; 1082 pinctrl-names = "aux", "i2c", "off"; 1083 status = "disabled"; 1084 1085 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1086 nvidia,interface = <1>; 1087 }; 1088 1089 dpaux: dpaux@155c0000 { 1090 compatible = "nvidia,tegra186-dpaux"; 1091 reg = <0x155c0000 0x10000>; 1092 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1094 <&bpmp TEGRA186_CLK_PLLDP>; 1095 clock-names = "dpaux", "parent"; 1096 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1097 reset-names = "dpaux"; 1098 status = "disabled"; 1099 1100 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1101 1102 state_dpaux_aux: pinmux-aux { 1103 groups = "dpaux-io"; 1104 function = "aux"; 1105 }; 1106 1107 state_dpaux_i2c: pinmux-i2c { 1108 groups = "dpaux-io"; 1109 function = "i2c"; 1110 }; 1111 1112 state_dpaux_off: pinmux-off { 1113 groups = "dpaux-io"; 1114 function = "off"; 1115 }; 1116 1117 i2c-bus { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 }; 1121 }; 1122 1123 padctl@15880000 { 1124 compatible = "nvidia,tegra186-dsi-padctl"; 1125 reg = <0x15880000 0x10000>; 1126 resets = <&bpmp TEGRA186_RESET_DSI>; 1127 reset-names = "dsi"; 1128 status = "disabled"; 1129 }; 1130 1131 dsic: dsi@15900000 { 1132 compatible = "nvidia,tegra186-dsi"; 1133 reg = <0x15900000 0x10000>; 1134 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1136 <&bpmp TEGRA186_CLK_DSIC_LP>, 1137 <&bpmp TEGRA186_CLK_PLLD>; 1138 clock-names = "dsi", "lp", "parent"; 1139 resets = <&bpmp TEGRA186_RESET_DSIC>; 1140 reset-names = "dsi"; 1141 status = "disabled"; 1142 1143 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1144 }; 1145 1146 dsid: dsi@15940000 { 1147 compatible = "nvidia,tegra186-dsi"; 1148 reg = <0x15940000 0x10000>; 1149 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&bpmp TEGRA186_CLK_DSID>, 1151 <&bpmp TEGRA186_CLK_DSID_LP>, 1152 <&bpmp TEGRA186_CLK_PLLD>; 1153 clock-names = "dsi", "lp", "parent"; 1154 resets = <&bpmp TEGRA186_RESET_DSID>; 1155 reset-names = "dsi"; 1156 status = "disabled"; 1157 1158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1159 }; 1160 }; 1161 1162 gpu@17000000 { 1163 compatible = "nvidia,gp10b"; 1164 reg = <0x0 0x17000000 0x0 0x1000000>, 1165 <0x0 0x18000000 0x0 0x1000000>; 1166 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1167 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1168 interrupt-names = "stall", "nonstall"; 1169 1170 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1171 <&bpmp TEGRA186_CLK_GPU>; 1172 clock-names = "gpu", "pwr"; 1173 resets = <&bpmp TEGRA186_RESET_GPU>; 1174 reset-names = "gpu"; 1175 status = "disabled"; 1176 1177 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1178 }; 1179 1180 sysram@30000000 { 1181 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1182 reg = <0x0 0x30000000 0x0 0x50000>; 1183 #address-cells = <2>; 1184 #size-cells = <2>; 1185 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1186 1187 cpu_bpmp_tx: shmem@4e000 { 1188 compatible = "nvidia,tegra186-bpmp-shmem"; 1189 reg = <0x0 0x4e000 0x0 0x1000>; 1190 label = "cpu-bpmp-tx"; 1191 pool; 1192 }; 1193 1194 cpu_bpmp_rx: shmem@4f000 { 1195 compatible = "nvidia,tegra186-bpmp-shmem"; 1196 reg = <0x0 0x4f000 0x0 0x1000>; 1197 label = "cpu-bpmp-rx"; 1198 pool; 1199 }; 1200 }; 1201 1202 bpmp: bpmp { 1203 compatible = "nvidia,tegra186-bpmp"; 1204 iommus = <&smmu TEGRA186_SID_BPMP>; 1205 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1206 TEGRA_HSP_DB_MASTER_BPMP>; 1207 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1208 #clock-cells = <1>; 1209 #reset-cells = <1>; 1210 #power-domain-cells = <1>; 1211 1212 bpmp_i2c: i2c { 1213 compatible = "nvidia,tegra186-bpmp-i2c"; 1214 nvidia,bpmp-bus-id = <5>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 bpmp_thermal: thermal { 1221 compatible = "nvidia,tegra186-bpmp-thermal"; 1222 #thermal-sensor-cells = <1>; 1223 }; 1224 }; 1225 1226 cpus { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 cpu@0 { 1231 compatible = "nvidia,tegra186-denver"; 1232 device_type = "cpu"; 1233 i-cache-size = <0x20000>; 1234 i-cache-line-size = <64>; 1235 i-cache-sets = <512>; 1236 d-cache-size = <0x10000>; 1237 d-cache-line-size = <64>; 1238 d-cache-sets = <256>; 1239 next-level-cache = <&L2_DENVER>; 1240 reg = <0x000>; 1241 }; 1242 1243 cpu@1 { 1244 compatible = "nvidia,tegra186-denver"; 1245 device_type = "cpu"; 1246 i-cache-size = <0x20000>; 1247 i-cache-line-size = <64>; 1248 i-cache-sets = <512>; 1249 d-cache-size = <0x10000>; 1250 d-cache-line-size = <64>; 1251 d-cache-sets = <256>; 1252 next-level-cache = <&L2_DENVER>; 1253 reg = <0x001>; 1254 }; 1255 1256 cpu@2 { 1257 compatible = "arm,cortex-a57"; 1258 device_type = "cpu"; 1259 i-cache-size = <0xC000>; 1260 i-cache-line-size = <64>; 1261 i-cache-sets = <256>; 1262 d-cache-size = <0x8000>; 1263 d-cache-line-size = <64>; 1264 d-cache-sets = <256>; 1265 next-level-cache = <&L2_A57>; 1266 reg = <0x100>; 1267 }; 1268 1269 cpu@3 { 1270 compatible = "arm,cortex-a57"; 1271 device_type = "cpu"; 1272 i-cache-size = <0xC000>; 1273 i-cache-line-size = <64>; 1274 i-cache-sets = <256>; 1275 d-cache-size = <0x8000>; 1276 d-cache-line-size = <64>; 1277 d-cache-sets = <256>; 1278 next-level-cache = <&L2_A57>; 1279 reg = <0x101>; 1280 }; 1281 1282 cpu@4 { 1283 compatible = "arm,cortex-a57"; 1284 device_type = "cpu"; 1285 i-cache-size = <0xC000>; 1286 i-cache-line-size = <64>; 1287 i-cache-sets = <256>; 1288 d-cache-size = <0x8000>; 1289 d-cache-line-size = <64>; 1290 d-cache-sets = <256>; 1291 next-level-cache = <&L2_A57>; 1292 reg = <0x102>; 1293 }; 1294 1295 cpu@5 { 1296 compatible = "arm,cortex-a57"; 1297 device_type = "cpu"; 1298 i-cache-size = <0xC000>; 1299 i-cache-line-size = <64>; 1300 i-cache-sets = <256>; 1301 d-cache-size = <0x8000>; 1302 d-cache-line-size = <64>; 1303 d-cache-sets = <256>; 1304 next-level-cache = <&L2_A57>; 1305 reg = <0x103>; 1306 }; 1307 1308 L2_DENVER: l2-cache0 { 1309 compatible = "cache"; 1310 cache-unified; 1311 cache-level = <2>; 1312 cache-size = <0x200000>; 1313 cache-line-size = <64>; 1314 cache-sets = <2048>; 1315 }; 1316 1317 L2_A57: l2-cache1 { 1318 compatible = "cache"; 1319 cache-unified; 1320 cache-level = <2>; 1321 cache-size = <0x200000>; 1322 cache-line-size = <64>; 1323 cache-sets = <2048>; 1324 }; 1325 }; 1326 1327 thermal-zones { 1328 a57 { 1329 polling-delay = <0>; 1330 polling-delay-passive = <1000>; 1331 1332 thermal-sensors = 1333 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1334 1335 trips { 1336 critical { 1337 temperature = <101000>; 1338 hysteresis = <0>; 1339 type = "critical"; 1340 }; 1341 }; 1342 1343 cooling-maps { 1344 }; 1345 }; 1346 1347 denver { 1348 polling-delay = <0>; 1349 polling-delay-passive = <1000>; 1350 1351 thermal-sensors = 1352 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1353 1354 trips { 1355 critical { 1356 temperature = <101000>; 1357 hysteresis = <0>; 1358 type = "critical"; 1359 }; 1360 }; 1361 1362 cooling-maps { 1363 }; 1364 }; 1365 1366 gpu { 1367 polling-delay = <0>; 1368 polling-delay-passive = <1000>; 1369 1370 thermal-sensors = 1371 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1372 1373 trips { 1374 critical { 1375 temperature = <101000>; 1376 hysteresis = <0>; 1377 type = "critical"; 1378 }; 1379 }; 1380 1381 cooling-maps { 1382 }; 1383 }; 1384 1385 pll { 1386 polling-delay = <0>; 1387 polling-delay-passive = <1000>; 1388 1389 thermal-sensors = 1390 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1391 1392 trips { 1393 critical { 1394 temperature = <101000>; 1395 hysteresis = <0>; 1396 type = "critical"; 1397 }; 1398 }; 1399 1400 cooling-maps { 1401 }; 1402 }; 1403 1404 always_on { 1405 polling-delay = <0>; 1406 polling-delay-passive = <1000>; 1407 1408 thermal-sensors = 1409 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1410 1411 trips { 1412 critical { 1413 temperature = <101000>; 1414 hysteresis = <0>; 1415 type = "critical"; 1416 }; 1417 }; 1418 1419 cooling-maps { 1420 }; 1421 }; 1422 }; 1423 1424 timer { 1425 compatible = "arm,armv8-timer"; 1426 interrupts = <GIC_PPI 13 1427 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1428 <GIC_PPI 14 1429 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1430 <GIC_PPI 11 1431 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1432 <GIC_PPI 10 1433 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1434 interrupt-parent = <&gic>; 1435 always-on; 1436 }; 1437}; 1438