1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 iommus = <&smmu TEGRA186_SID_SDMMC1>; 241 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 242 pinctrl-0 = <&sdmmc1_3v3>; 243 pinctrl-1 = <&sdmmc1_1v8>; 244 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 245 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 246 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 248 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 249 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 250 nvidia,default-tap = <0x5>; 251 nvidia,default-trim = <0xb>; 252 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 253 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 255 status = "disabled"; 256 }; 257 258 sdmmc2: sdhci@3420000 { 259 compatible = "nvidia,tegra186-sdhci"; 260 reg = <0x0 0x03420000 0x0 0x10000>; 261 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 263 clock-names = "sdhci"; 264 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 265 reset-names = "sdhci"; 266 iommus = <&smmu TEGRA186_SID_SDMMC2>; 267 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 268 pinctrl-0 = <&sdmmc2_3v3>; 269 pinctrl-1 = <&sdmmc2_1v8>; 270 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 272 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 273 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 274 nvidia,default-tap = <0x5>; 275 nvidia,default-trim = <0xb>; 276 status = "disabled"; 277 }; 278 279 sdmmc3: sdhci@3440000 { 280 compatible = "nvidia,tegra186-sdhci"; 281 reg = <0x0 0x03440000 0x0 0x10000>; 282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 284 clock-names = "sdhci"; 285 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 286 reset-names = "sdhci"; 287 iommus = <&smmu TEGRA186_SID_SDMMC3>; 288 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 289 pinctrl-0 = <&sdmmc3_3v3>; 290 pinctrl-1 = <&sdmmc3_1v8>; 291 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 292 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 293 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 294 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 295 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 296 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 297 nvidia,default-tap = <0x5>; 298 nvidia,default-trim = <0xb>; 299 status = "disabled"; 300 }; 301 302 sdmmc4: sdhci@3460000 { 303 compatible = "nvidia,tegra186-sdhci"; 304 reg = <0x0 0x03460000 0x0 0x10000>; 305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 307 clock-names = "sdhci"; 308 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 309 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 310 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 311 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 312 reset-names = "sdhci"; 313 iommus = <&smmu TEGRA186_SID_SDMMC4>; 314 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 315 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 316 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 317 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 318 nvidia,default-tap = <0x5>; 319 nvidia,default-trim = <0x9>; 320 nvidia,dqs-trim = <63>; 321 mmc-hs400-1_8v; 322 status = "disabled"; 323 }; 324 325 hda@3510000 { 326 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 327 reg = <0x0 0x03510000 0x0 0x10000>; 328 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&bpmp TEGRA186_CLK_HDA>, 330 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 331 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 332 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 333 resets = <&bpmp TEGRA186_RESET_HDA>, 334 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 335 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 336 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 337 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 338 status = "disabled"; 339 }; 340 341 fuse@3820000 { 342 compatible = "nvidia,tegra186-efuse"; 343 reg = <0x0 0x03820000 0x0 0x10000>; 344 clocks = <&bpmp TEGRA186_CLK_FUSE>; 345 clock-names = "fuse"; 346 }; 347 348 gic: interrupt-controller@3881000 { 349 compatible = "arm,gic-400"; 350 #interrupt-cells = <3>; 351 interrupt-controller; 352 reg = <0x0 0x03881000 0x0 0x1000>, 353 <0x0 0x03882000 0x0 0x2000>; 354 interrupts = <GIC_PPI 9 355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 356 interrupt-parent = <&gic>; 357 }; 358 359 cec@3960000 { 360 compatible = "nvidia,tegra186-cec"; 361 reg = <0x0 0x03960000 0x0 0x10000>; 362 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&bpmp TEGRA186_CLK_CEC>; 364 clock-names = "cec"; 365 status = "disabled"; 366 }; 367 368 hsp_top0: hsp@3c00000 { 369 compatible = "nvidia,tegra186-hsp"; 370 reg = <0x0 0x03c00000 0x0 0xa0000>; 371 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-names = "doorbell"; 373 #mbox-cells = <2>; 374 status = "disabled"; 375 }; 376 377 gen2_i2c: i2c@c240000 { 378 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 379 reg = <0x0 0x0c240000 0x0 0x10000>; 380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&bpmp TEGRA186_CLK_I2C2>; 384 clock-names = "div-clk"; 385 resets = <&bpmp TEGRA186_RESET_I2C2>; 386 reset-names = "i2c"; 387 status = "disabled"; 388 }; 389 390 gen8_i2c: i2c@c250000 { 391 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 392 reg = <0x0 0x0c250000 0x0 0x10000>; 393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&bpmp TEGRA186_CLK_I2C8>; 397 clock-names = "div-clk"; 398 resets = <&bpmp TEGRA186_RESET_I2C8>; 399 reset-names = "i2c"; 400 status = "disabled"; 401 }; 402 403 uartc: serial@c280000 { 404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405 reg = <0x0 0x0c280000 0x0 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA186_CLK_UARTC>; 409 clock-names = "serial"; 410 resets = <&bpmp TEGRA186_RESET_UARTC>; 411 reset-names = "serial"; 412 status = "disabled"; 413 }; 414 415 uartg: serial@c290000 { 416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417 reg = <0x0 0x0c290000 0x0 0x40>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&bpmp TEGRA186_CLK_UARTG>; 421 clock-names = "serial"; 422 resets = <&bpmp TEGRA186_RESET_UARTG>; 423 reset-names = "serial"; 424 status = "disabled"; 425 }; 426 427 rtc: rtc@c2a0000 { 428 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 429 reg = <0 0x0c2a0000 0 0x10000>; 430 interrupt-parent = <&pmc>; 431 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 433 clock-names = "rtc"; 434 status = "disabled"; 435 }; 436 437 gpio_aon: gpio@c2f0000 { 438 compatible = "nvidia,tegra186-gpio-aon"; 439 reg-names = "security", "gpio"; 440 reg = <0x0 0xc2f0000 0x0 0x1000>, 441 <0x0 0xc2f1000 0x0 0x1000>; 442 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 }; 448 449 pmc: pmc@c360000 { 450 compatible = "nvidia,tegra186-pmc"; 451 reg = <0 0x0c360000 0 0x10000>, 452 <0 0x0c370000 0 0x10000>, 453 <0 0x0c380000 0 0x10000>, 454 <0 0x0c390000 0 0x10000>; 455 reg-names = "pmc", "wake", "aotag", "scratch"; 456 457 #interrupt-cells = <2>; 458 interrupt-controller; 459 460 sdmmc1_3v3: sdmmc1-3v3 { 461 pins = "sdmmc1-hv"; 462 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 463 }; 464 465 sdmmc1_1v8: sdmmc1-1v8 { 466 pins = "sdmmc1-hv"; 467 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 468 }; 469 470 sdmmc2_3v3: sdmmc2-3v3 { 471 pins = "sdmmc2-hv"; 472 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 473 }; 474 475 sdmmc2_1v8: sdmmc2-1v8 { 476 pins = "sdmmc2-hv"; 477 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 478 }; 479 480 sdmmc3_3v3: sdmmc3-3v3 { 481 pins = "sdmmc3-hv"; 482 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 483 }; 484 485 sdmmc3_1v8: sdmmc3-1v8 { 486 pins = "sdmmc3-hv"; 487 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 488 }; 489 }; 490 491 ccplex@e000000 { 492 compatible = "nvidia,tegra186-ccplex-cluster"; 493 reg = <0x0 0x0e000000 0x0 0x3fffff>; 494 495 nvidia,bpmp = <&bpmp>; 496 }; 497 498 pcie@10003000 { 499 compatible = "nvidia,tegra186-pcie"; 500 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 501 device_type = "pci"; 502 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 503 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 504 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 505 reg-names = "pads", "afi", "cs"; 506 507 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 508 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 509 interrupt-names = "intr", "msi"; 510 511 #interrupt-cells = <1>; 512 interrupt-map-mask = <0 0 0 0>; 513 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 514 515 bus-range = <0x00 0xff>; 516 #address-cells = <3>; 517 #size-cells = <2>; 518 519 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 520 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 521 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 522 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 523 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 524 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 525 526 clocks = <&bpmp TEGRA186_CLK_AFI>, 527 <&bpmp TEGRA186_CLK_PCIE>, 528 <&bpmp TEGRA186_CLK_PLLE>; 529 clock-names = "afi", "pex", "pll_e"; 530 531 resets = <&bpmp TEGRA186_RESET_AFI>, 532 <&bpmp TEGRA186_RESET_PCIE>, 533 <&bpmp TEGRA186_RESET_PCIEXCLK>; 534 reset-names = "afi", "pex", "pcie_x"; 535 536 status = "disabled"; 537 538 pci@1,0 { 539 device_type = "pci"; 540 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 541 reg = <0x000800 0 0 0 0>; 542 status = "disabled"; 543 544 #address-cells = <3>; 545 #size-cells = <2>; 546 ranges; 547 548 nvidia,num-lanes = <2>; 549 }; 550 551 pci@2,0 { 552 device_type = "pci"; 553 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 554 reg = <0x001000 0 0 0 0>; 555 status = "disabled"; 556 557 #address-cells = <3>; 558 #size-cells = <2>; 559 ranges; 560 561 nvidia,num-lanes = <1>; 562 }; 563 564 pci@3,0 { 565 device_type = "pci"; 566 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 567 reg = <0x001800 0 0 0 0>; 568 status = "disabled"; 569 570 #address-cells = <3>; 571 #size-cells = <2>; 572 ranges; 573 574 nvidia,num-lanes = <1>; 575 }; 576 }; 577 578 smmu: iommu@12000000 { 579 compatible = "arm,mmu-500"; 580 reg = <0 0x12000000 0 0x800000>; 581 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 646 stream-match-mask = <0x7f80>; 647 #global-interrupts = <1>; 648 #iommu-cells = <1>; 649 }; 650 651 host1x@13e00000 { 652 compatible = "nvidia,tegra186-host1x", "simple-bus"; 653 reg = <0x0 0x13e00000 0x0 0x10000>, 654 <0x0 0x13e10000 0x0 0x10000>; 655 reg-names = "hypervisor", "vm"; 656 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 659 clock-names = "host1x"; 660 resets = <&bpmp TEGRA186_RESET_HOST1X>; 661 reset-names = "host1x"; 662 663 #address-cells = <1>; 664 #size-cells = <1>; 665 666 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 667 iommus = <&smmu TEGRA186_SID_HOST1X>; 668 669 dpaux1: dpaux@15040000 { 670 compatible = "nvidia,tegra186-dpaux"; 671 reg = <0x15040000 0x10000>; 672 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 674 <&bpmp TEGRA186_CLK_PLLDP>; 675 clock-names = "dpaux", "parent"; 676 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 677 reset-names = "dpaux"; 678 status = "disabled"; 679 680 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 681 682 state_dpaux1_aux: pinmux-aux { 683 groups = "dpaux-io"; 684 function = "aux"; 685 }; 686 687 state_dpaux1_i2c: pinmux-i2c { 688 groups = "dpaux-io"; 689 function = "i2c"; 690 }; 691 692 state_dpaux1_off: pinmux-off { 693 groups = "dpaux-io"; 694 function = "off"; 695 }; 696 697 i2c-bus { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 }; 702 703 display-hub@15200000 { 704 compatible = "nvidia,tegra186-display", "simple-bus"; 705 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 706 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 707 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 708 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 709 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 710 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 711 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 712 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 713 "wgrp3", "wgrp4", "wgrp5"; 714 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 715 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 716 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 717 clock-names = "disp", "dsc", "hub"; 718 status = "disabled"; 719 720 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 721 722 #address-cells = <1>; 723 #size-cells = <1>; 724 725 ranges = <0x15200000 0x15200000 0x40000>; 726 727 display@15200000 { 728 compatible = "nvidia,tegra186-dc"; 729 reg = <0x15200000 0x10000>; 730 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 732 clock-names = "dc"; 733 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 734 reset-names = "dc"; 735 736 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 737 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 738 739 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 740 nvidia,head = <0>; 741 }; 742 743 display@15210000 { 744 compatible = "nvidia,tegra186-dc"; 745 reg = <0x15210000 0x10000>; 746 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 748 clock-names = "dc"; 749 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 750 reset-names = "dc"; 751 752 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 753 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 754 755 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 756 nvidia,head = <1>; 757 }; 758 759 display@15220000 { 760 compatible = "nvidia,tegra186-dc"; 761 reg = <0x15220000 0x10000>; 762 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 764 clock-names = "dc"; 765 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 766 reset-names = "dc"; 767 768 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 769 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 770 771 nvidia,outputs = <&sor0 &sor1>; 772 nvidia,head = <2>; 773 }; 774 }; 775 776 dsia: dsi@15300000 { 777 compatible = "nvidia,tegra186-dsi"; 778 reg = <0x15300000 0x10000>; 779 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&bpmp TEGRA186_CLK_DSI>, 781 <&bpmp TEGRA186_CLK_DSIA_LP>, 782 <&bpmp TEGRA186_CLK_PLLD>; 783 clock-names = "dsi", "lp", "parent"; 784 resets = <&bpmp TEGRA186_RESET_DSI>; 785 reset-names = "dsi"; 786 status = "disabled"; 787 788 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 789 }; 790 791 vic@15340000 { 792 compatible = "nvidia,tegra186-vic"; 793 reg = <0x15340000 0x40000>; 794 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&bpmp TEGRA186_CLK_VIC>; 796 clock-names = "vic"; 797 resets = <&bpmp TEGRA186_RESET_VIC>; 798 reset-names = "vic"; 799 800 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 801 }; 802 803 dsib: dsi@15400000 { 804 compatible = "nvidia,tegra186-dsi"; 805 reg = <0x15400000 0x10000>; 806 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&bpmp TEGRA186_CLK_DSIB>, 808 <&bpmp TEGRA186_CLK_DSIB_LP>, 809 <&bpmp TEGRA186_CLK_PLLD>; 810 clock-names = "dsi", "lp", "parent"; 811 resets = <&bpmp TEGRA186_RESET_DSIB>; 812 reset-names = "dsi"; 813 status = "disabled"; 814 815 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 816 }; 817 818 sor0: sor@15540000 { 819 compatible = "nvidia,tegra186-sor"; 820 reg = <0x15540000 0x10000>; 821 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&bpmp TEGRA186_CLK_SOR0>, 823 <&bpmp TEGRA186_CLK_SOR0_OUT>, 824 <&bpmp TEGRA186_CLK_PLLD2>, 825 <&bpmp TEGRA186_CLK_PLLDP>, 826 <&bpmp TEGRA186_CLK_SOR_SAFE>, 827 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 828 clock-names = "sor", "out", "parent", "dp", "safe", 829 "pad"; 830 resets = <&bpmp TEGRA186_RESET_SOR0>; 831 reset-names = "sor"; 832 pinctrl-0 = <&state_dpaux_aux>; 833 pinctrl-1 = <&state_dpaux_i2c>; 834 pinctrl-2 = <&state_dpaux_off>; 835 pinctrl-names = "aux", "i2c", "off"; 836 status = "disabled"; 837 838 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 839 nvidia,interface = <0>; 840 }; 841 842 sor1: sor@15580000 { 843 compatible = "nvidia,tegra186-sor1"; 844 reg = <0x15580000 0x10000>; 845 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&bpmp TEGRA186_CLK_SOR1>, 847 <&bpmp TEGRA186_CLK_SOR1_OUT>, 848 <&bpmp TEGRA186_CLK_PLLD3>, 849 <&bpmp TEGRA186_CLK_PLLDP>, 850 <&bpmp TEGRA186_CLK_SOR_SAFE>, 851 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 852 clock-names = "sor", "out", "parent", "dp", "safe", 853 "pad"; 854 resets = <&bpmp TEGRA186_RESET_SOR1>; 855 reset-names = "sor"; 856 pinctrl-0 = <&state_dpaux1_aux>; 857 pinctrl-1 = <&state_dpaux1_i2c>; 858 pinctrl-2 = <&state_dpaux1_off>; 859 pinctrl-names = "aux", "i2c", "off"; 860 status = "disabled"; 861 862 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 863 nvidia,interface = <1>; 864 }; 865 866 dpaux: dpaux@155c0000 { 867 compatible = "nvidia,tegra186-dpaux"; 868 reg = <0x155c0000 0x10000>; 869 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 871 <&bpmp TEGRA186_CLK_PLLDP>; 872 clock-names = "dpaux", "parent"; 873 resets = <&bpmp TEGRA186_RESET_DPAUX>; 874 reset-names = "dpaux"; 875 status = "disabled"; 876 877 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 878 879 state_dpaux_aux: pinmux-aux { 880 groups = "dpaux-io"; 881 function = "aux"; 882 }; 883 884 state_dpaux_i2c: pinmux-i2c { 885 groups = "dpaux-io"; 886 function = "i2c"; 887 }; 888 889 state_dpaux_off: pinmux-off { 890 groups = "dpaux-io"; 891 function = "off"; 892 }; 893 894 i2c-bus { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 }; 898 }; 899 900 padctl@15880000 { 901 compatible = "nvidia,tegra186-dsi-padctl"; 902 reg = <0x15880000 0x10000>; 903 resets = <&bpmp TEGRA186_RESET_DSI>; 904 reset-names = "dsi"; 905 status = "disabled"; 906 }; 907 908 dsic: dsi@15900000 { 909 compatible = "nvidia,tegra186-dsi"; 910 reg = <0x15900000 0x10000>; 911 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&bpmp TEGRA186_CLK_DSIC>, 913 <&bpmp TEGRA186_CLK_DSIC_LP>, 914 <&bpmp TEGRA186_CLK_PLLD>; 915 clock-names = "dsi", "lp", "parent"; 916 resets = <&bpmp TEGRA186_RESET_DSIC>; 917 reset-names = "dsi"; 918 status = "disabled"; 919 920 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 921 }; 922 923 dsid: dsi@15940000 { 924 compatible = "nvidia,tegra186-dsi"; 925 reg = <0x15940000 0x10000>; 926 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&bpmp TEGRA186_CLK_DSID>, 928 <&bpmp TEGRA186_CLK_DSID_LP>, 929 <&bpmp TEGRA186_CLK_PLLD>; 930 clock-names = "dsi", "lp", "parent"; 931 resets = <&bpmp TEGRA186_RESET_DSID>; 932 reset-names = "dsi"; 933 status = "disabled"; 934 935 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 936 }; 937 }; 938 939 gpu@17000000 { 940 compatible = "nvidia,gp10b"; 941 reg = <0x0 0x17000000 0x0 0x1000000>, 942 <0x0 0x18000000 0x0 0x1000000>; 943 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 944 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "stall", "nonstall"; 946 947 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 948 <&bpmp TEGRA186_CLK_GPU>; 949 clock-names = "gpu", "pwr"; 950 resets = <&bpmp TEGRA186_RESET_GPU>; 951 reset-names = "gpu"; 952 status = "disabled"; 953 954 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 955 }; 956 957 sysram@30000000 { 958 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 959 reg = <0x0 0x30000000 0x0 0x50000>; 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 963 964 cpu_bpmp_tx: shmem@4e000 { 965 compatible = "nvidia,tegra186-bpmp-shmem"; 966 reg = <0x0 0x4e000 0x0 0x1000>; 967 label = "cpu-bpmp-tx"; 968 pool; 969 }; 970 971 cpu_bpmp_rx: shmem@4f000 { 972 compatible = "nvidia,tegra186-bpmp-shmem"; 973 reg = <0x0 0x4f000 0x0 0x1000>; 974 label = "cpu-bpmp-rx"; 975 pool; 976 }; 977 }; 978 979 cpus { 980 #address-cells = <1>; 981 #size-cells = <0>; 982 983 cpu@0 { 984 compatible = "nvidia,tegra186-denver", "arm,armv8"; 985 device_type = "cpu"; 986 reg = <0x000>; 987 }; 988 989 cpu@1 { 990 compatible = "nvidia,tegra186-denver", "arm,armv8"; 991 device_type = "cpu"; 992 reg = <0x001>; 993 }; 994 995 cpu@2 { 996 compatible = "arm,cortex-a57", "arm,armv8"; 997 device_type = "cpu"; 998 reg = <0x100>; 999 }; 1000 1001 cpu@3 { 1002 compatible = "arm,cortex-a57", "arm,armv8"; 1003 device_type = "cpu"; 1004 reg = <0x101>; 1005 }; 1006 1007 cpu@4 { 1008 compatible = "arm,cortex-a57", "arm,armv8"; 1009 device_type = "cpu"; 1010 reg = <0x102>; 1011 }; 1012 1013 cpu@5 { 1014 compatible = "arm,cortex-a57", "arm,armv8"; 1015 device_type = "cpu"; 1016 reg = <0x103>; 1017 }; 1018 }; 1019 1020 bpmp: bpmp { 1021 compatible = "nvidia,tegra186-bpmp"; 1022 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1023 TEGRA_HSP_DB_MASTER_BPMP>; 1024 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1025 #clock-cells = <1>; 1026 #reset-cells = <1>; 1027 #power-domain-cells = <1>; 1028 1029 bpmp_i2c: i2c { 1030 compatible = "nvidia,tegra186-bpmp-i2c"; 1031 nvidia,bpmp-bus-id = <5>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 bpmp_thermal: thermal { 1038 compatible = "nvidia,tegra186-bpmp-thermal"; 1039 #thermal-sensor-cells = <1>; 1040 }; 1041 }; 1042 1043 thermal-zones { 1044 a57 { 1045 polling-delay = <0>; 1046 polling-delay-passive = <1000>; 1047 1048 thermal-sensors = 1049 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1050 1051 trips { 1052 critical { 1053 temperature = <101000>; 1054 hysteresis = <0>; 1055 type = "critical"; 1056 }; 1057 }; 1058 1059 cooling-maps { 1060 }; 1061 }; 1062 1063 denver { 1064 polling-delay = <0>; 1065 polling-delay-passive = <1000>; 1066 1067 thermal-sensors = 1068 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1069 1070 trips { 1071 critical { 1072 temperature = <101000>; 1073 hysteresis = <0>; 1074 type = "critical"; 1075 }; 1076 }; 1077 1078 cooling-maps { 1079 }; 1080 }; 1081 1082 gpu { 1083 polling-delay = <0>; 1084 polling-delay-passive = <1000>; 1085 1086 thermal-sensors = 1087 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1088 1089 trips { 1090 critical { 1091 temperature = <101000>; 1092 hysteresis = <0>; 1093 type = "critical"; 1094 }; 1095 }; 1096 1097 cooling-maps { 1098 }; 1099 }; 1100 1101 pll { 1102 polling-delay = <0>; 1103 polling-delay-passive = <1000>; 1104 1105 thermal-sensors = 1106 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1107 1108 trips { 1109 critical { 1110 temperature = <101000>; 1111 hysteresis = <0>; 1112 type = "critical"; 1113 }; 1114 }; 1115 1116 cooling-maps { 1117 }; 1118 }; 1119 1120 always_on { 1121 polling-delay = <0>; 1122 polling-delay-passive = <1000>; 1123 1124 thermal-sensors = 1125 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1126 1127 trips { 1128 critical { 1129 temperature = <101000>; 1130 hysteresis = <0>; 1131 type = "critical"; 1132 }; 1133 }; 1134 1135 cooling-maps { 1136 }; 1137 }; 1138 }; 1139 1140 timer { 1141 compatible = "arm,armv8-timer"; 1142 interrupts = <GIC_PPI 13 1143 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1144 <GIC_PPI 14 1145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1146 <GIC_PPI 11 1147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1148 <GIC_PPI 10 1149 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1150 interrupt-parent = <&gic>; 1151 }; 1152}; 1153