#
503f5fed |
| 01-Feb-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: fix g12a buses
Fix apb, cbus, hiu and periph regions which are not aligned with the documentation and the information provided by Amlogic
Fixes: 9c8c52f7cb4f ("arm64: dts: meson-
arm64: dts: meson: fix g12a buses
Fix apb, cbus, hiu and periph regions which are not aligned with the documentation and the information provided by Amlogic
Fixes: 9c8c52f7cb4f ("arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support") Cc: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v4.19.16 |
|
#
31af04cd |
| 14-Jan-2019 |
Rob Herring <robh@kernel.org> |
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fal
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms.
This fixes warnings generated by the DT schema.
Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
show more ...
|
Revision tags: v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10 |
|
#
9c8c52f7 |
| 21-Sep-2018 |
Jianxin Pan <jianxin.pan@amlogic.com> |
arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC, which describe components as follows: Reserve Memory, CPU, GIC, IR
arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC, which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
|
#
8eef8bca |
| 04-Oct-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
arm64: dts: meson: g12a: add cooling properties Add missing #colling-cells field for G12A SoC Add cooling-map for passive and hot trip point Tested-by: Christian Hewitt <christi
arm64: dts: meson: g12a: add cooling properties Add missing #colling-cells field for G12A SoC Add cooling-map for passive and hot trip point Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
|
#
2871626b |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: factor the power domain. The power domain declared in the g12a and g12b dtsi are the same. Move the declaration of these power domains in the g12 common dtsi.
arm64: dts: meson: g12: factor the power domain. The power domain declared in the g12a and g12b dtsi are the same. Move the declaration of these power domains in the g12 common dtsi. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
9ed437d6 |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: add a g12 layer While the sm1 is very close to the g12a/b family, somethings apply differently on the g12a/b and not the sm1. This introduce a new layer of dt
arm64: dts: meson: g12: add a g12 layer While the sm1 is very close to the g12a/b family, somethings apply differently on the g12a/b and not the sm1. This introduce a new layer of dtsi for part which apply to the g12a and g12b but not the sm1. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.2.11, v5.2.10 |
|
#
f4f1c8d9 |
| 23-Aug-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12: add Everything-Else power domain controller Replace the VPU-centric power domain controller by the generic system-wide Everything-Else power domain controller and
arm64: dts: meson-g12: add Everything-Else power domain controller Replace the VPU-centric power domain controller by the generic system-wide Everything-Else power domain controller and setup the right power-domains properties on the VPU, Ethernet & USB nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> [khilman: minor subject edit: add dts] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5 |
|
#
b190056f |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12a: add cpus OPP table Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8
arm64: dts: meson-g12a: add cpus OPP table Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8GHz - mid-speed: up to 1,908GHz - high-speed: up to 2.1GHz And the S905X2 opp voltages are slightly higher than the S905D2 OPP voltages for the low-speed table. This adds the conservative OPP table with the S905X2 higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an Amlogic U200 Reference Board, SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
1499218c |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi To simplify the representation of differences betweem the G12A and G12B SoCs, move the common nodes into a meson-g12-co
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi To simplify the representation of differences betweem the G12A and G12B SoCs, move the common nodes into a meson-g12-common.dtsi file and express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi. This separation will help for DVFS and future Amlogic SM1 Family support. The sd_emmc_a quirk is added in the g12a/g12b since since it's already known the sd_emmc_a controller is fixed in the next SM1 SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16 |
|
#
3d4bacdc |
| 25-Jun-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12a: add missing dwc2 phy-names The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG controller gets the PHY but width by probing the associated phy.
arm64: dts: meson-g12a: add missing dwc2 phy-names The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG controller gets the PHY but width by probing the associated phy. By default it will use 16bit wide settings if a phy is not specified, in our case we specified the phy, but not the phy-names. The dwc2 bindings specifies that if phys is present, phy-names shall be "usb2-phy". Adding phy-names = "usb2-phy" solves the OTG PHY bus configuration. Fixes: 9baf7d6be730 ("arm64: dts: meson: g12a: Add G12A USB nodes") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9 |
|
#
9a3f3714 |
| 10-Jun-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: sort sdio nodes correctly Fix sdio node order in the soc device tree Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller") Signed-off-by:
arm64: dts: meson: g12a: sort sdio nodes correctly Fix sdio node order in the soc device tree Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.8 |
|
#
568465c3 |
| 08-Jun-2019 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
arm64: dts: meson: g12a: add the GPIO interrupt controller GPIO interrupts are used for the external Ethernet RGMII PHY interrupt line. Add the GPIO interrupt controller so we can de
arm64: dts: meson: g12a: add the GPIO interrupt controller GPIO interrupts are used for the external Ethernet RGMII PHY interrupt line. Add the GPIO interrupt controller so we can describe that connection in the dts files. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.7 |
|
#
8a6b3ca2 |
| 03-Jun-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add SDIO controller The Amlogic G12A SDIO Controller has a bug preventing direct DDR access, add the port A (SDIO) pinctrl and controller nodes and mark this spe
arm64: dts: meson: g12a: add SDIO controller The Amlogic G12A SDIO Controller has a bug preventing direct DDR access, add the port A (SDIO) pinctrl and controller nodes and mark this specific controller with the amlogic,dram-access-quirk property. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.6 |
|
#
1b2f377b |
| 27-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: Add hwrng node The Amlogic G12A has the hwrng module at the end of an unknown "EFUSE" bus. The hwrng is not enabled on the vendor G12A DTs, but is enabl
arm64: dts: meson: g12a: Add hwrng node The Amlogic G12A has the hwrng module at the end of an unknown "EFUSE" bus. The hwrng is not enabled on the vendor G12A DTs, but is enabled on next generation SM1 SoC family sharing the exact same memory mapping. Let's add the "EFUSE" bus and the hwrng node. This hwrng has been checked with the rng-tools rngtest FIPS tool : rngtest: starting FIPS tests... rngtest: bits received from input: 1630240032 rngtest: FIPS 140-2 successes: 81436 rngtest: FIPS 140-2 failures: 76 rngtest: FIPS 140-2(2001-10-10) Monobit: 10 rngtest: FIPS 140-2(2001-10-10) Poker: 6 rngtest: FIPS 140-2(2001-10-10) Runs: 26 rngtest: FIPS 140-2(2001-10-10) Long run: 34 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=3.784; avg=5687.521; max=19073.486)Mibits/s rngtest: FIPS tests speed: (min=47.684; avg=52.348; max=52.835)Mibits/s rngtest: Program run time: 30000987 microseconds Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.5, v5.1.4 |
|
#
47b65cb8 |
| 20-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: add drive strength for eth pins With the X96 Max board using an external Gigabit Ethernet PHY, add the same driver strength to the Ethernet pins as the vendor
arm64: dts: meson: g12a: add drive strength for eth pins With the X96 Max board using an external Gigabit Ethernet PHY, add the same driver strength to the Ethernet pins as the vendor tree. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
d9b9640b |
| 20-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: add drive-strength hdmi ddc pins With the default boot settings, the DDC drive strength is too weak, set the driver-strengh to 4mA to avoid errors on the DDC lin
arm64: dts: meson: g12a: add drive-strength hdmi ddc pins With the default boot settings, the DDC drive strength is too weak, set the driver-strengh to 4mA to avoid errors on the DDC line. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
280c17df |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add mdio multiplexer Add the g12a mdio multiplexer which allows to connect to either an external phy through the SoC pins or the internal 10/100 phy Sig
arm64: dts: meson: g12a: add mdio multiplexer Add the g12a mdio multiplexer which allows to connect to either an external phy through the SoC pins or the internal 10/100 phy Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
3293252f |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add ethernet pinctrl definitions Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
arm64: dts: meson: g12a: add ethernet pinctrl definitions Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
a466a867 |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add ethernet mac controller Add the synopsys ethernet mac controller embedded in the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
arm64: dts: meson: g12a: add ethernet mac controller Add the synopsys ethernet mac controller embedded in the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.3 |
|
#
d7556f49 |
| 16-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add tohdmitx Add the hdmitx glue device linking the SoC audio interfaces to the embedded Synopsys hdmi controller. Signed-off-by: Jerome Brunet <jbrunet
arm64: dts: meson: g12a: add tohdmitx Add the hdmitx glue device linking the SoC audio interfaces to the embedded Synopsys hdmi controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
Revision tags: v5.1.2 |
|
#
b894a8f1 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: enable hdmi_tx sound dai provider At the moment the sysnopsys hdmi i2s driver provides a single playback DAI. Add the corresponding sound-dai-cell to the hdmi de
arm64: dts: meson: g12a: enable hdmi_tx sound dai provider At the moment the sysnopsys hdmi i2s driver provides a single playback DAI. Add the corresponding sound-dai-cell to the hdmi device node. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
e3d3b132 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add spdifin Add the spdif input device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@
arm64: dts: meson: g12a: add spdifin Add the spdif input device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
9c5dc032 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add pdm Add the pdm device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com
arm64: dts: meson: g12a: add pdm Add the pdm device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
649675db |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add spdifouts Add the devices nodes and pinctrl definitions for the spdif outputs of the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.
arm64: dts: meson: g12a: add spdifouts Add the devices nodes and pinctrl definitions for the spdif outputs of the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
#
1ff38c86 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add tdm Add the devices and pinctrl definitions for the tdm interfaces of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> S
arm64: dts: meson: g12a: add tdm Add the devices and pinctrl definitions for the tdm interfaces of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|