1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 ethmac: ethernet@ff3f0000 { 141 compatible = "amlogic,meson-axg-dwmac", 142 "snps,dwmac-3.70a", 143 "snps,dwmac"; 144 reg = <0x0 0xff3f0000 0x0 0x10000 145 0x0 0xff634540 0x0 0x8>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "macirq"; 148 clocks = <&clkc CLKID_ETH>, 149 <&clkc CLKID_FCLK_DIV2>, 150 <&clkc CLKID_MPLL2>; 151 clock-names = "stmmaceth", "clkin0", "clkin1"; 152 status = "disabled"; 153 154 mdio0: mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "snps,dwmac-mdio"; 158 }; 159 }; 160 161 apb: bus@ff600000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xff600000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 167 168 hdmi_tx: hdmi-tx@0 { 169 compatible = "amlogic,meson-g12a-dw-hdmi"; 170 reg = <0x0 0x0 0x0 0x10000>; 171 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 172 resets = <&reset RESET_HDMITX_CAPB3>, 173 <&reset RESET_HDMITX_PHY>, 174 <&reset RESET_HDMITX>; 175 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 176 clocks = <&clkc CLKID_HDMI>, 177 <&clkc CLKID_HTX_PCLK>, 178 <&clkc CLKID_VPU_INTR>; 179 clock-names = "isfr", "iahb", "venci"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 185 /* VPU VENC Input */ 186 hdmi_tx_venc_port: port@0 { 187 reg = <0>; 188 189 hdmi_tx_in: endpoint { 190 remote-endpoint = <&hdmi_tx_out>; 191 }; 192 }; 193 194 /* TMDS Output */ 195 hdmi_tx_tmds_port: port@1 { 196 reg = <1>; 197 }; 198 }; 199 200 periphs: bus@34400 { 201 compatible = "simple-bus"; 202 reg = <0x0 0x34400 0x0 0x400>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 206 207 periphs_pinctrl: pinctrl@40 { 208 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges; 212 213 gpio: bank@40 { 214 reg = <0x0 0x40 0x0 0x4c>, 215 <0x0 0xe8 0x0 0x18>, 216 <0x0 0x120 0x0 0x18>, 217 <0x0 0x2c0 0x0 0x40>, 218 <0x0 0x340 0x0 0x1c>; 219 reg-names = "gpio", 220 "pull", 221 "pull-enable", 222 "mux", 223 "ds"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&periphs_pinctrl 0 0 86>; 227 }; 228 229 cec_ao_a_h_pins: cec_ao_a_h { 230 mux { 231 groups = "cec_ao_a_h"; 232 function = "cec_ao_a_h"; 233 bias-disable; 234 }; 235 }; 236 237 cec_ao_b_h_pins: cec_ao_b_h { 238 mux { 239 groups = "cec_ao_b_h"; 240 function = "cec_ao_b_h"; 241 bias-disable; 242 }; 243 }; 244 245 emmc_pins: emmc { 246 mux-0 { 247 groups = "emmc_nand_d0", 248 "emmc_nand_d1", 249 "emmc_nand_d2", 250 "emmc_nand_d3", 251 "emmc_nand_d4", 252 "emmc_nand_d5", 253 "emmc_nand_d6", 254 "emmc_nand_d7", 255 "emmc_cmd"; 256 function = "emmc"; 257 bias-pull-up; 258 drive-strength-microamp = <4000>; 259 }; 260 261 mux-1 { 262 groups = "emmc_clk"; 263 function = "emmc"; 264 bias-disable; 265 drive-strength-microamp = <4000>; 266 }; 267 }; 268 269 emmc_ds_pins: emmc-ds { 270 mux { 271 groups = "emmc_nand_ds"; 272 function = "emmc"; 273 bias-pull-down; 274 drive-strength-microamp = <4000>; 275 }; 276 }; 277 278 emmc_clk_gate_pins: emmc_clk_gate { 279 mux { 280 groups = "BOOT_8"; 281 function = "gpio_periphs"; 282 bias-pull-down; 283 drive-strength-microamp = <4000>; 284 }; 285 }; 286 287 hdmitx_ddc_pins: hdmitx_ddc { 288 mux { 289 groups = "hdmitx_sda", 290 "hdmitx_sck"; 291 function = "hdmitx"; 292 bias-disable; 293 }; 294 }; 295 296 hdmitx_hpd_pins: hdmitx_hpd { 297 mux { 298 groups = "hdmitx_hpd_in"; 299 function = "hdmitx"; 300 bias-disable; 301 }; 302 }; 303 304 305 i2c0_sda_c_pins: i2c0-sda-c { 306 mux { 307 groups = "i2c0_sda_c"; 308 function = "i2c0"; 309 bias-disable; 310 drive-strength-microamp = <3000>; 311 312 }; 313 }; 314 315 i2c0_sck_c_pins: i2c0-sck-c { 316 mux { 317 groups = "i2c0_sck_c"; 318 function = "i2c0"; 319 bias-disable; 320 drive-strength-microamp = <3000>; 321 }; 322 }; 323 324 i2c0_sda_z0_pins: i2c0-sda-z0 { 325 mux { 326 groups = "i2c0_sda_z0"; 327 function = "i2c0"; 328 bias-disable; 329 drive-strength-microamp = <3000>; 330 }; 331 }; 332 333 i2c0_sck_z1_pins: i2c0-sck-z1 { 334 mux { 335 groups = "i2c0_sck_z1"; 336 function = "i2c0"; 337 bias-disable; 338 drive-strength-microamp = <3000>; 339 }; 340 }; 341 342 i2c0_sda_z7_pins: i2c0-sda-z7 { 343 mux { 344 groups = "i2c0_sda_z7"; 345 function = "i2c0"; 346 bias-disable; 347 drive-strength-microamp = <3000>; 348 }; 349 }; 350 351 i2c0_sda_z8_pins: i2c0-sda-z8 { 352 mux { 353 groups = "i2c0_sda_z8"; 354 function = "i2c0"; 355 bias-disable; 356 drive-strength-microamp = <3000>; 357 }; 358 }; 359 360 i2c1_sda_x_pins: i2c1-sda-x { 361 mux { 362 groups = "i2c1_sda_x"; 363 function = "i2c1"; 364 bias-disable; 365 drive-strength-microamp = <3000>; 366 }; 367 }; 368 369 i2c1_sck_x_pins: i2c1-sck-x { 370 mux { 371 groups = "i2c1_sck_x"; 372 function = "i2c1"; 373 bias-disable; 374 drive-strength-microamp = <3000>; 375 }; 376 }; 377 378 i2c1_sda_h2_pins: i2c1-sda-h2 { 379 mux { 380 groups = "i2c1_sda_h2"; 381 function = "i2c1"; 382 bias-disable; 383 drive-strength-microamp = <3000>; 384 }; 385 }; 386 387 i2c1_sck_h3_pins: i2c1-sck-h3 { 388 mux { 389 groups = "i2c1_sck_h3"; 390 function = "i2c1"; 391 bias-disable; 392 drive-strength-microamp = <3000>; 393 }; 394 }; 395 396 i2c1_sda_h6_pins: i2c1-sda-h6 { 397 mux { 398 groups = "i2c1_sda_h6"; 399 function = "i2c1"; 400 bias-disable; 401 drive-strength-microamp = <3000>; 402 }; 403 }; 404 405 i2c1_sck_h7_pins: i2c1-sck-h7 { 406 mux { 407 groups = "i2c1_sck_h7"; 408 function = "i2c1"; 409 bias-disable; 410 drive-strength-microamp = <3000>; 411 }; 412 }; 413 414 i2c2_sda_x_pins: i2c2-sda-x { 415 mux { 416 groups = "i2c2_sda_x"; 417 function = "i2c2"; 418 bias-disable; 419 drive-strength-microamp = <3000>; 420 }; 421 }; 422 423 i2c2_sck_x_pins: i2c2-sck-x { 424 mux { 425 groups = "i2c2_sck_x"; 426 function = "i2c2"; 427 bias-disable; 428 drive-strength-microamp = <3000>; 429 }; 430 }; 431 432 i2c2_sda_z_pins: i2c2-sda-z { 433 mux { 434 groups = "i2c2_sda_z"; 435 function = "i2c2"; 436 bias-disable; 437 drive-strength-microamp = <3000>; 438 }; 439 }; 440 441 i2c2_sck_z_pins: i2c2-sck-z { 442 mux { 443 groups = "i2c2_sck_z"; 444 function = "i2c2"; 445 bias-disable; 446 drive-strength-microamp = <3000>; 447 }; 448 }; 449 450 i2c3_sda_h_pins: i2c3-sda-h { 451 mux { 452 groups = "i2c3_sda_h"; 453 function = "i2c3"; 454 bias-disable; 455 drive-strength-microamp = <3000>; 456 }; 457 }; 458 459 i2c3_sck_h_pins: i2c3-sck-h { 460 mux { 461 groups = "i2c3_sck_h"; 462 function = "i2c3"; 463 bias-disable; 464 drive-strength-microamp = <3000>; 465 }; 466 }; 467 468 i2c3_sda_a_pins: i2c3-sda-a { 469 mux { 470 groups = "i2c3_sda_a"; 471 function = "i2c3"; 472 bias-disable; 473 drive-strength-microamp = <3000>; 474 }; 475 }; 476 477 i2c3_sck_a_pins: i2c3-sck-a { 478 mux { 479 groups = "i2c3_sck_a"; 480 function = "i2c3"; 481 bias-disable; 482 drive-strength-microamp = <3000>; 483 }; 484 }; 485 486 mclk0_a_pins: mclk0-a { 487 mux { 488 groups = "mclk0_a"; 489 function = "mclk0"; 490 bias-disable; 491 drive-strength-microamp = <3000>; 492 }; 493 }; 494 495 mclk1_a_pins: mclk1-a { 496 mux { 497 groups = "mclk1_a"; 498 function = "mclk1"; 499 bias-disable; 500 drive-strength-microamp = <3000>; 501 }; 502 }; 503 504 mclk1_x_pins: mclk1-x { 505 mux { 506 groups = "mclk1_x"; 507 function = "mclk1"; 508 bias-disable; 509 drive-strength-microamp = <3000>; 510 }; 511 }; 512 513 mclk1_z_pins: mclk1-z { 514 mux { 515 groups = "mclk1_z"; 516 function = "mclk1"; 517 bias-disable; 518 drive-strength-microamp = <3000>; 519 }; 520 }; 521 522 pdm_din0_a_pins: pdm-din0-a { 523 mux { 524 groups = "pdm_din0_a"; 525 function = "pdm"; 526 bias-disable; 527 }; 528 }; 529 530 pdm_din0_c_pins: pdm-din0-c { 531 mux { 532 groups = "pdm_din0_c"; 533 function = "pdm"; 534 bias-disable; 535 }; 536 }; 537 538 pdm_din0_x_pins: pdm-din0-x { 539 mux { 540 groups = "pdm_din0_x"; 541 function = "pdm"; 542 bias-disable; 543 }; 544 }; 545 546 pdm_din0_z_pins: pdm-din0-z { 547 mux { 548 groups = "pdm_din0_z"; 549 function = "pdm"; 550 bias-disable; 551 }; 552 }; 553 554 pdm_din1_a_pins: pdm-din1-a { 555 mux { 556 groups = "pdm_din1_a"; 557 function = "pdm"; 558 bias-disable; 559 }; 560 }; 561 562 pdm_din1_c_pins: pdm-din1-c { 563 mux { 564 groups = "pdm_din1_c"; 565 function = "pdm"; 566 bias-disable; 567 }; 568 }; 569 570 pdm_din1_x_pins: pdm-din1-x { 571 mux { 572 groups = "pdm_din1_x"; 573 function = "pdm"; 574 bias-disable; 575 }; 576 }; 577 578 pdm_din1_z_pins: pdm-din1-z { 579 mux { 580 groups = "pdm_din1_z"; 581 function = "pdm"; 582 bias-disable; 583 }; 584 }; 585 586 pdm_din2_a_pins: pdm-din2-a { 587 mux { 588 groups = "pdm_din2_a"; 589 function = "pdm"; 590 bias-disable; 591 }; 592 }; 593 594 pdm_din2_c_pins: pdm-din2-c { 595 mux { 596 groups = "pdm_din2_c"; 597 function = "pdm"; 598 bias-disable; 599 }; 600 }; 601 602 pdm_din2_x_pins: pdm-din2-x { 603 mux { 604 groups = "pdm_din2_x"; 605 function = "pdm"; 606 bias-disable; 607 }; 608 }; 609 610 pdm_din2_z_pins: pdm-din2-z { 611 mux { 612 groups = "pdm_din2_z"; 613 function = "pdm"; 614 bias-disable; 615 }; 616 }; 617 618 pdm_din3_a_pins: pdm-din3-a { 619 mux { 620 groups = "pdm_din3_a"; 621 function = "pdm"; 622 bias-disable; 623 }; 624 }; 625 626 pdm_din3_c_pins: pdm-din3-c { 627 mux { 628 groups = "pdm_din3_c"; 629 function = "pdm"; 630 bias-disable; 631 }; 632 }; 633 634 pdm_din3_x_pins: pdm-din3-x { 635 mux { 636 groups = "pdm_din3_x"; 637 function = "pdm"; 638 bias-disable; 639 }; 640 }; 641 642 pdm_din3_z_pins: pdm-din3-z { 643 mux { 644 groups = "pdm_din3_z"; 645 function = "pdm"; 646 bias-disable; 647 }; 648 }; 649 650 pdm_dclk_a_pins: pdm-dclk-a { 651 mux { 652 groups = "pdm_dclk_a"; 653 function = "pdm"; 654 bias-disable; 655 drive-strength-microamp = <500>; 656 }; 657 }; 658 659 pdm_dclk_c_pins: pdm-dclk-c { 660 mux { 661 groups = "pdm_dclk_c"; 662 function = "pdm"; 663 bias-disable; 664 drive-strength-microamp = <500>; 665 }; 666 }; 667 668 pdm_dclk_x_pins: pdm-dclk-x { 669 mux { 670 groups = "pdm_dclk_x"; 671 function = "pdm"; 672 bias-disable; 673 drive-strength-microamp = <500>; 674 }; 675 }; 676 677 pdm_dclk_z_pins: pdm-dclk-z { 678 mux { 679 groups = "pdm_dclk_z"; 680 function = "pdm"; 681 bias-disable; 682 drive-strength-microamp = <500>; 683 }; 684 }; 685 686 pwm_a_pins: pwm-a { 687 mux { 688 groups = "pwm_a"; 689 function = "pwm_a"; 690 bias-disable; 691 }; 692 }; 693 694 pwm_b_x7_pins: pwm-b-x7 { 695 mux { 696 groups = "pwm_b_x7"; 697 function = "pwm_b"; 698 bias-disable; 699 }; 700 }; 701 702 pwm_b_x19_pins: pwm-b-x19 { 703 mux { 704 groups = "pwm_b_x19"; 705 function = "pwm_b"; 706 bias-disable; 707 }; 708 }; 709 710 pwm_c_c_pins: pwm-c-c { 711 mux { 712 groups = "pwm_c_c"; 713 function = "pwm_c"; 714 bias-disable; 715 }; 716 }; 717 718 pwm_c_x5_pins: pwm-c-x5 { 719 mux { 720 groups = "pwm_c_x5"; 721 function = "pwm_c"; 722 bias-disable; 723 }; 724 }; 725 726 pwm_c_x8_pins: pwm-c-x8 { 727 mux { 728 groups = "pwm_c_x8"; 729 function = "pwm_c"; 730 bias-disable; 731 }; 732 }; 733 734 pwm_d_x3_pins: pwm-d-x3 { 735 mux { 736 groups = "pwm_d_x3"; 737 function = "pwm_d"; 738 bias-disable; 739 }; 740 }; 741 742 pwm_d_x6_pins: pwm-d-x6 { 743 mux { 744 groups = "pwm_d_x6"; 745 function = "pwm_d"; 746 bias-disable; 747 }; 748 }; 749 750 pwm_e_pins: pwm-e { 751 mux { 752 groups = "pwm_e"; 753 function = "pwm_e"; 754 bias-disable; 755 }; 756 }; 757 758 pwm_f_x_pins: pwm-f-x { 759 mux { 760 groups = "pwm_f_x"; 761 function = "pwm_f"; 762 bias-disable; 763 }; 764 }; 765 766 pwm_f_h_pins: pwm-f-h { 767 mux { 768 groups = "pwm_f_h"; 769 function = "pwm_f"; 770 bias-disable; 771 }; 772 }; 773 774 sdcard_c_pins: sdcard_c { 775 mux-0 { 776 groups = "sdcard_d0_c", 777 "sdcard_d1_c", 778 "sdcard_d2_c", 779 "sdcard_d3_c", 780 "sdcard_cmd_c"; 781 function = "sdcard"; 782 bias-pull-up; 783 drive-strength-microamp = <4000>; 784 }; 785 786 mux-1 { 787 groups = "sdcard_clk_c"; 788 function = "sdcard"; 789 bias-disable; 790 drive-strength-microamp = <4000>; 791 }; 792 }; 793 794 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 795 mux { 796 groups = "GPIOC_4"; 797 function = "gpio_periphs"; 798 bias-pull-down; 799 drive-strength-microamp = <4000>; 800 }; 801 }; 802 803 sdcard_z_pins: sdcard_z { 804 mux-0 { 805 groups = "sdcard_d0_z", 806 "sdcard_d1_z", 807 "sdcard_d2_z", 808 "sdcard_d3_z", 809 "sdcard_cmd_z"; 810 function = "sdcard"; 811 bias-pull-up; 812 drive-strength-microamp = <4000>; 813 }; 814 815 mux-1 { 816 groups = "sdcard_clk_z"; 817 function = "sdcard"; 818 bias-disable; 819 drive-strength-microamp = <4000>; 820 }; 821 }; 822 823 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 824 mux { 825 groups = "GPIOZ_6"; 826 function = "gpio_periphs"; 827 bias-pull-down; 828 drive-strength-microamp = <4000>; 829 }; 830 }; 831 832 spdif_in_a10_pins: spdif-in-a10 { 833 mux { 834 groups = "spdif_in_a10"; 835 function = "spdif_in"; 836 bias-disable; 837 }; 838 }; 839 840 spdif_in_a12_pins: spdif-in-a12 { 841 mux { 842 groups = "spdif_in_a12"; 843 function = "spdif_in"; 844 bias-disable; 845 }; 846 }; 847 848 spdif_in_h_pins: spdif-in-h { 849 mux { 850 groups = "spdif_in_h"; 851 function = "spdif_in"; 852 bias-disable; 853 }; 854 }; 855 856 spdif_out_h_pins: spdif-out-h { 857 mux { 858 groups = "spdif_out_h"; 859 function = "spdif_out"; 860 drive-strength-microamp = <500>; 861 bias-disable; 862 }; 863 }; 864 865 spdif_out_a11_pins: spdif-out-a11 { 866 mux { 867 groups = "spdif_out_a11"; 868 function = "spdif_out"; 869 drive-strength-microamp = <500>; 870 bias-disable; 871 }; 872 }; 873 874 spdif_out_a13_pins: spdif-out-a13 { 875 mux { 876 groups = "spdif_out_a13"; 877 function = "spdif_out"; 878 drive-strength-microamp = <500>; 879 bias-disable; 880 }; 881 }; 882 883 tdm_a_din0_pins: tdm-a-din0 { 884 mux { 885 groups = "tdm_a_din0"; 886 function = "tdm_a"; 887 bias-disable; 888 }; 889 }; 890 891 892 tdm_a_din1_pins: tdm-a-din1 { 893 mux { 894 groups = "tdm_a_din1"; 895 function = "tdm_a"; 896 bias-disable; 897 }; 898 }; 899 900 tdm_a_dout0_pins: tdm-a-dout0 { 901 mux { 902 groups = "tdm_a_dout0"; 903 function = "tdm_a"; 904 bias-disable; 905 drive-strength-microamp = <3000>; 906 }; 907 }; 908 909 tdm_a_dout1_pins: tdm-a-dout1 { 910 mux { 911 groups = "tdm_a_dout1"; 912 function = "tdm_a"; 913 bias-disable; 914 drive-strength-microamp = <3000>; 915 }; 916 }; 917 918 tdm_a_fs_pins: tdm-a-fs { 919 mux { 920 groups = "tdm_a_fs"; 921 function = "tdm_a"; 922 bias-disable; 923 drive-strength-microamp = <3000>; 924 }; 925 }; 926 927 tdm_a_sclk_pins: tdm-a-sclk { 928 mux { 929 groups = "tdm_a_sclk"; 930 function = "tdm_a"; 931 bias-disable; 932 drive-strength-microamp = <3000>; 933 }; 934 }; 935 936 tdm_a_slv_fs_pins: tdm-a-slv-fs { 937 mux { 938 groups = "tdm_a_slv_fs"; 939 function = "tdm_a"; 940 bias-disable; 941 }; 942 }; 943 944 945 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 946 mux { 947 groups = "tdm_a_slv_sclk"; 948 function = "tdm_a"; 949 bias-disable; 950 }; 951 }; 952 953 tdm_b_din0_pins: tdm-b-din0 { 954 mux { 955 groups = "tdm_b_din0"; 956 function = "tdm_b"; 957 bias-disable; 958 }; 959 }; 960 961 tdm_b_din1_pins: tdm-b-din1 { 962 mux { 963 groups = "tdm_b_din1"; 964 function = "tdm_b"; 965 bias-disable; 966 }; 967 }; 968 969 tdm_b_din2_pins: tdm-b-din2 { 970 mux { 971 groups = "tdm_b_din2"; 972 function = "tdm_b"; 973 bias-disable; 974 }; 975 }; 976 977 tdm_b_din3_a_pins: tdm-b-din3-a { 978 mux { 979 groups = "tdm_b_din3_a"; 980 function = "tdm_b"; 981 bias-disable; 982 }; 983 }; 984 985 tdm_b_din3_h_pins: tdm-b-din3-h { 986 mux { 987 groups = "tdm_b_din3_h"; 988 function = "tdm_b"; 989 bias-disable; 990 }; 991 }; 992 993 tdm_b_dout0_pins: tdm-b-dout0 { 994 mux { 995 groups = "tdm_b_dout0"; 996 function = "tdm_b"; 997 bias-disable; 998 drive-strength-microamp = <3000>; 999 }; 1000 }; 1001 1002 tdm_b_dout1_pins: tdm-b-dout1 { 1003 mux { 1004 groups = "tdm_b_dout1"; 1005 function = "tdm_b"; 1006 bias-disable; 1007 drive-strength-microamp = <3000>; 1008 }; 1009 }; 1010 1011 tdm_b_dout2_pins: tdm-b-dout2 { 1012 mux { 1013 groups = "tdm_b_dout2"; 1014 function = "tdm_b"; 1015 bias-disable; 1016 drive-strength-microamp = <3000>; 1017 }; 1018 }; 1019 1020 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1021 mux { 1022 groups = "tdm_b_dout3_a"; 1023 function = "tdm_b"; 1024 bias-disable; 1025 drive-strength-microamp = <3000>; 1026 }; 1027 }; 1028 1029 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1030 mux { 1031 groups = "tdm_b_dout3_h"; 1032 function = "tdm_b"; 1033 bias-disable; 1034 drive-strength-microamp = <3000>; 1035 }; 1036 }; 1037 1038 tdm_b_fs_pins: tdm-b-fs { 1039 mux { 1040 groups = "tdm_b_fs"; 1041 function = "tdm_b"; 1042 bias-disable; 1043 drive-strength-microamp = <3000>; 1044 }; 1045 }; 1046 1047 tdm_b_sclk_pins: tdm-b-sclk { 1048 mux { 1049 groups = "tdm_b_sclk"; 1050 function = "tdm_b"; 1051 bias-disable; 1052 drive-strength-microamp = <3000>; 1053 }; 1054 }; 1055 1056 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1057 mux { 1058 groups = "tdm_b_slv_fs"; 1059 function = "tdm_b"; 1060 bias-disable; 1061 }; 1062 }; 1063 1064 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1065 mux { 1066 groups = "tdm_b_slv_sclk"; 1067 function = "tdm_b"; 1068 bias-disable; 1069 }; 1070 }; 1071 1072 tdm_c_din0_a_pins: tdm-c-din0-a { 1073 mux { 1074 groups = "tdm_c_din0_a"; 1075 function = "tdm_c"; 1076 bias-disable; 1077 }; 1078 }; 1079 1080 tdm_c_din0_z_pins: tdm-c-din0-z { 1081 mux { 1082 groups = "tdm_c_din0_z"; 1083 function = "tdm_c"; 1084 bias-disable; 1085 }; 1086 }; 1087 1088 tdm_c_din1_a_pins: tdm-c-din1-a { 1089 mux { 1090 groups = "tdm_c_din1_a"; 1091 function = "tdm_c"; 1092 bias-disable; 1093 }; 1094 }; 1095 1096 tdm_c_din1_z_pins: tdm-c-din1-z { 1097 mux { 1098 groups = "tdm_c_din1_z"; 1099 function = "tdm_c"; 1100 bias-disable; 1101 }; 1102 }; 1103 1104 tdm_c_din2_a_pins: tdm-c-din2-a { 1105 mux { 1106 groups = "tdm_c_din2_a"; 1107 function = "tdm_c"; 1108 bias-disable; 1109 }; 1110 }; 1111 1112 eth_leds_pins: eth-leds { 1113 mux { 1114 groups = "eth_link_led", 1115 "eth_act_led"; 1116 function = "eth"; 1117 bias-disable; 1118 }; 1119 }; 1120 1121 eth_pins: eth { 1122 mux { 1123 groups = "eth_mdio", 1124 "eth_mdc", 1125 "eth_rgmii_rx_clk", 1126 "eth_rx_dv", 1127 "eth_rxd0", 1128 "eth_rxd1", 1129 "eth_txen", 1130 "eth_txd0", 1131 "eth_txd1"; 1132 function = "eth"; 1133 bias-disable; 1134 }; 1135 }; 1136 1137 eth_rgmii_pins: eth-rgmii { 1138 mux { 1139 groups = "eth_rxd2_rgmii", 1140 "eth_rxd3_rgmii", 1141 "eth_rgmii_tx_clk", 1142 "eth_txd2_rgmii", 1143 "eth_txd3_rgmii"; 1144 function = "eth"; 1145 bias-disable; 1146 }; 1147 }; 1148 1149 tdm_c_din2_z_pins: tdm-c-din2-z { 1150 mux { 1151 groups = "tdm_c_din2_z"; 1152 function = "tdm_c"; 1153 bias-disable; 1154 }; 1155 }; 1156 1157 tdm_c_din3_a_pins: tdm-c-din3-a { 1158 mux { 1159 groups = "tdm_c_din3_a"; 1160 function = "tdm_c"; 1161 bias-disable; 1162 }; 1163 }; 1164 1165 tdm_c_din3_z_pins: tdm-c-din3-z { 1166 mux { 1167 groups = "tdm_c_din3_z"; 1168 function = "tdm_c"; 1169 bias-disable; 1170 }; 1171 }; 1172 1173 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1174 mux { 1175 groups = "tdm_c_dout0_a"; 1176 function = "tdm_c"; 1177 bias-disable; 1178 drive-strength-microamp = <3000>; 1179 }; 1180 }; 1181 1182 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1183 mux { 1184 groups = "tdm_c_dout0_z"; 1185 function = "tdm_c"; 1186 bias-disable; 1187 drive-strength-microamp = <3000>; 1188 }; 1189 }; 1190 1191 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1192 mux { 1193 groups = "tdm_c_dout1_a"; 1194 function = "tdm_c"; 1195 bias-disable; 1196 drive-strength-microamp = <3000>; 1197 }; 1198 }; 1199 1200 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1201 mux { 1202 groups = "tdm_c_dout1_z"; 1203 function = "tdm_c"; 1204 bias-disable; 1205 drive-strength-microamp = <3000>; 1206 }; 1207 }; 1208 1209 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1210 mux { 1211 groups = "tdm_c_dout2_a"; 1212 function = "tdm_c"; 1213 bias-disable; 1214 drive-strength-microamp = <3000>; 1215 }; 1216 }; 1217 1218 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1219 mux { 1220 groups = "tdm_c_dout2_z"; 1221 function = "tdm_c"; 1222 bias-disable; 1223 drive-strength-microamp = <3000>; 1224 }; 1225 }; 1226 1227 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1228 mux { 1229 groups = "tdm_c_dout3_a"; 1230 function = "tdm_c"; 1231 bias-disable; 1232 drive-strength-microamp = <3000>; 1233 }; 1234 }; 1235 1236 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1237 mux { 1238 groups = "tdm_c_dout3_z"; 1239 function = "tdm_c"; 1240 bias-disable; 1241 drive-strength-microamp = <3000>; 1242 }; 1243 }; 1244 1245 tdm_c_fs_a_pins: tdm-c-fs-a { 1246 mux { 1247 groups = "tdm_c_fs_a"; 1248 function = "tdm_c"; 1249 bias-disable; 1250 drive-strength-microamp = <3000>; 1251 }; 1252 }; 1253 1254 tdm_c_fs_z_pins: tdm-c-fs-z { 1255 mux { 1256 groups = "tdm_c_fs_z"; 1257 function = "tdm_c"; 1258 bias-disable; 1259 drive-strength-microamp = <3000>; 1260 }; 1261 }; 1262 1263 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1264 mux { 1265 groups = "tdm_c_sclk_a"; 1266 function = "tdm_c"; 1267 bias-disable; 1268 drive-strength-microamp = <3000>; 1269 }; 1270 }; 1271 1272 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1273 mux { 1274 groups = "tdm_c_sclk_z"; 1275 function = "tdm_c"; 1276 bias-disable; 1277 drive-strength-microamp = <3000>; 1278 }; 1279 }; 1280 1281 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1282 mux { 1283 groups = "tdm_c_slv_fs_a"; 1284 function = "tdm_c"; 1285 bias-disable; 1286 }; 1287 }; 1288 1289 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1290 mux { 1291 groups = "tdm_c_slv_fs_z"; 1292 function = "tdm_c"; 1293 bias-disable; 1294 }; 1295 }; 1296 1297 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1298 mux { 1299 groups = "tdm_c_slv_sclk_a"; 1300 function = "tdm_c"; 1301 bias-disable; 1302 }; 1303 }; 1304 1305 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1306 mux { 1307 groups = "tdm_c_slv_sclk_z"; 1308 function = "tdm_c"; 1309 bias-disable; 1310 }; 1311 }; 1312 1313 uart_a_pins: uart-a { 1314 mux { 1315 groups = "uart_a_tx", 1316 "uart_a_rx"; 1317 function = "uart_a"; 1318 bias-disable; 1319 }; 1320 }; 1321 1322 uart_a_cts_rts_pins: uart-a-cts-rts { 1323 mux { 1324 groups = "uart_a_cts", 1325 "uart_a_rts"; 1326 function = "uart_a"; 1327 bias-disable; 1328 }; 1329 }; 1330 1331 uart_b_pins: uart-b { 1332 mux { 1333 groups = "uart_b_tx", 1334 "uart_b_rx"; 1335 function = "uart_b"; 1336 bias-disable; 1337 }; 1338 }; 1339 1340 uart_c_pins: uart-c { 1341 mux { 1342 groups = "uart_c_tx", 1343 "uart_c_rx"; 1344 function = "uart_c"; 1345 bias-disable; 1346 }; 1347 }; 1348 1349 uart_c_cts_rts_pins: uart-c-cts-rts { 1350 mux { 1351 groups = "uart_c_cts", 1352 "uart_c_rts"; 1353 function = "uart_c"; 1354 bias-disable; 1355 }; 1356 }; 1357 }; 1358 }; 1359 1360 usb2_phy0: phy@36000 { 1361 compatible = "amlogic,g12a-usb2-phy"; 1362 reg = <0x0 0x36000 0x0 0x2000>; 1363 clocks = <&xtal>; 1364 clock-names = "xtal"; 1365 resets = <&reset RESET_USB_PHY20>; 1366 reset-names = "phy"; 1367 #phy-cells = <0>; 1368 }; 1369 1370 dmc: bus@38000 { 1371 compatible = "simple-bus"; 1372 reg = <0x0 0x38000 0x0 0x400>; 1373 #address-cells = <2>; 1374 #size-cells = <2>; 1375 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1376 1377 canvas: video-lut@48 { 1378 compatible = "amlogic,canvas"; 1379 reg = <0x0 0x48 0x0 0x14>; 1380 }; 1381 }; 1382 1383 usb2_phy1: phy@3a000 { 1384 compatible = "amlogic,g12a-usb2-phy"; 1385 reg = <0x0 0x3a000 0x0 0x2000>; 1386 clocks = <&xtal>; 1387 clock-names = "xtal"; 1388 resets = <&reset RESET_USB_PHY21>; 1389 reset-names = "phy"; 1390 #phy-cells = <0>; 1391 }; 1392 1393 hiu: bus@3c000 { 1394 compatible = "simple-bus"; 1395 reg = <0x0 0x3c000 0x0 0x1400>; 1396 #address-cells = <2>; 1397 #size-cells = <2>; 1398 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1399 1400 hhi: system-controller@0 { 1401 compatible = "amlogic,meson-gx-hhi-sysctrl", 1402 "simple-mfd", "syscon"; 1403 reg = <0 0 0 0x400>; 1404 1405 clkc: clock-controller { 1406 compatible = "amlogic,g12a-clkc"; 1407 #clock-cells = <1>; 1408 clocks = <&xtal>; 1409 clock-names = "xtal"; 1410 }; 1411 }; 1412 }; 1413 1414 pdm: audio-controller@40000 { 1415 compatible = "amlogic,g12a-pdm", 1416 "amlogic,axg-pdm"; 1417 reg = <0x0 0x40000 0x0 0x34>; 1418 #sound-dai-cells = <0>; 1419 sound-name-prefix = "PDM"; 1420 clocks = <&clkc_audio AUD_CLKID_PDM>, 1421 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1422 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1423 clock-names = "pclk", "dclk", "sysclk"; 1424 status = "disabled"; 1425 }; 1426 1427 audio: bus@42000 { 1428 compatible = "simple-bus"; 1429 reg = <0x0 0x42000 0x0 0x2000>; 1430 #address-cells = <2>; 1431 #size-cells = <2>; 1432 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1433 1434 clkc_audio: clock-controller@0 { 1435 status = "disabled"; 1436 compatible = "amlogic,g12a-audio-clkc"; 1437 reg = <0x0 0x0 0x0 0xb4>; 1438 #clock-cells = <1>; 1439 1440 clocks = <&clkc CLKID_AUDIO>, 1441 <&clkc CLKID_MPLL0>, 1442 <&clkc CLKID_MPLL1>, 1443 <&clkc CLKID_MPLL2>, 1444 <&clkc CLKID_MPLL3>, 1445 <&clkc CLKID_HIFI_PLL>, 1446 <&clkc CLKID_FCLK_DIV3>, 1447 <&clkc CLKID_FCLK_DIV4>, 1448 <&clkc CLKID_GP0_PLL>; 1449 clock-names = "pclk", 1450 "mst_in0", 1451 "mst_in1", 1452 "mst_in2", 1453 "mst_in3", 1454 "mst_in4", 1455 "mst_in5", 1456 "mst_in6", 1457 "mst_in7"; 1458 1459 resets = <&reset RESET_AUDIO>; 1460 }; 1461 1462 toddr_a: audio-controller@100 { 1463 compatible = "amlogic,g12a-toddr", 1464 "amlogic,axg-toddr"; 1465 reg = <0x0 0x100 0x0 0x1c>; 1466 #sound-dai-cells = <0>; 1467 sound-name-prefix = "TODDR_A"; 1468 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1469 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1470 resets = <&arb AXG_ARB_TODDR_A>; 1471 status = "disabled"; 1472 }; 1473 1474 toddr_b: audio-controller@140 { 1475 compatible = "amlogic,g12a-toddr", 1476 "amlogic,axg-toddr"; 1477 reg = <0x0 0x140 0x0 0x1c>; 1478 #sound-dai-cells = <0>; 1479 sound-name-prefix = "TODDR_B"; 1480 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1481 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1482 resets = <&arb AXG_ARB_TODDR_B>; 1483 status = "disabled"; 1484 }; 1485 1486 toddr_c: audio-controller@180 { 1487 compatible = "amlogic,g12a-toddr", 1488 "amlogic,axg-toddr"; 1489 reg = <0x0 0x180 0x0 0x1c>; 1490 #sound-dai-cells = <0>; 1491 sound-name-prefix = "TODDR_C"; 1492 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1493 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1494 resets = <&arb AXG_ARB_TODDR_C>; 1495 status = "disabled"; 1496 }; 1497 1498 frddr_a: audio-controller@1c0 { 1499 compatible = "amlogic,g12a-frddr", 1500 "amlogic,axg-frddr"; 1501 reg = <0x0 0x1c0 0x0 0x1c>; 1502 #sound-dai-cells = <0>; 1503 sound-name-prefix = "FRDDR_A"; 1504 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1505 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1506 resets = <&arb AXG_ARB_FRDDR_A>; 1507 status = "disabled"; 1508 }; 1509 1510 frddr_b: audio-controller@200 { 1511 compatible = "amlogic,g12a-frddr", 1512 "amlogic,axg-frddr"; 1513 reg = <0x0 0x200 0x0 0x1c>; 1514 #sound-dai-cells = <0>; 1515 sound-name-prefix = "FRDDR_B"; 1516 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1517 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1518 resets = <&arb AXG_ARB_FRDDR_B>; 1519 status = "disabled"; 1520 }; 1521 1522 frddr_c: audio-controller@240 { 1523 compatible = "amlogic,g12a-frddr", 1524 "amlogic,axg-frddr"; 1525 reg = <0x0 0x240 0x0 0x1c>; 1526 #sound-dai-cells = <0>; 1527 sound-name-prefix = "FRDDR_C"; 1528 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1529 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1530 resets = <&arb AXG_ARB_FRDDR_C>; 1531 status = "disabled"; 1532 }; 1533 1534 arb: reset-controller@280 { 1535 status = "disabled"; 1536 compatible = "amlogic,meson-axg-audio-arb"; 1537 reg = <0x0 0x280 0x0 0x4>; 1538 #reset-cells = <1>; 1539 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1540 }; 1541 1542 tdmin_a: audio-controller@300 { 1543 compatible = "amlogic,g12a-tdmin", 1544 "amlogic,axg-tdmin"; 1545 reg = <0x0 0x300 0x0 0x40>; 1546 sound-name-prefix = "TDMIN_A"; 1547 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1548 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1549 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1550 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1551 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1552 clock-names = "pclk", "sclk", "sclk_sel", 1553 "lrclk", "lrclk_sel"; 1554 status = "disabled"; 1555 }; 1556 1557 tdmin_b: audio-controller@340 { 1558 compatible = "amlogic,g12a-tdmin", 1559 "amlogic,axg-tdmin"; 1560 reg = <0x0 0x340 0x0 0x40>; 1561 sound-name-prefix = "TDMIN_B"; 1562 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1563 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1564 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1565 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1566 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1567 clock-names = "pclk", "sclk", "sclk_sel", 1568 "lrclk", "lrclk_sel"; 1569 status = "disabled"; 1570 }; 1571 1572 tdmin_c: audio-controller@380 { 1573 compatible = "amlogic,g12a-tdmin", 1574 "amlogic,axg-tdmin"; 1575 reg = <0x0 0x380 0x0 0x40>; 1576 sound-name-prefix = "TDMIN_C"; 1577 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1578 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1579 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1580 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1581 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1582 clock-names = "pclk", "sclk", "sclk_sel", 1583 "lrclk", "lrclk_sel"; 1584 status = "disabled"; 1585 }; 1586 1587 tdmin_lb: audio-controller@3c0 { 1588 compatible = "amlogic,g12a-tdmin", 1589 "amlogic,axg-tdmin"; 1590 reg = <0x0 0x3c0 0x0 0x40>; 1591 sound-name-prefix = "TDMIN_LB"; 1592 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1593 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1594 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1595 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1596 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1597 clock-names = "pclk", "sclk", "sclk_sel", 1598 "lrclk", "lrclk_sel"; 1599 status = "disabled"; 1600 }; 1601 1602 spdifin: audio-controller@400 { 1603 compatible = "amlogic,g12a-spdifin", 1604 "amlogic,axg-spdifin"; 1605 reg = <0x0 0x400 0x0 0x30>; 1606 #sound-dai-cells = <0>; 1607 sound-name-prefix = "SPDIFIN"; 1608 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1609 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1610 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1611 clock-names = "pclk", "refclk"; 1612 status = "disabled"; 1613 }; 1614 1615 spdifout: audio-controller@480 { 1616 compatible = "amlogic,g12a-spdifout", 1617 "amlogic,axg-spdifout"; 1618 reg = <0x0 0x480 0x0 0x50>; 1619 #sound-dai-cells = <0>; 1620 sound-name-prefix = "SPDIFOUT"; 1621 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1622 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1623 clock-names = "pclk", "mclk"; 1624 status = "disabled"; 1625 }; 1626 1627 tdmout_a: audio-controller@500 { 1628 compatible = "amlogic,g12a-tdmout"; 1629 reg = <0x0 0x500 0x0 0x40>; 1630 sound-name-prefix = "TDMOUT_A"; 1631 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1632 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1633 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1634 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1635 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1636 clock-names = "pclk", "sclk", "sclk_sel", 1637 "lrclk", "lrclk_sel"; 1638 status = "disabled"; 1639 }; 1640 1641 tdmout_b: audio-controller@540 { 1642 compatible = "amlogic,g12a-tdmout"; 1643 reg = <0x0 0x540 0x0 0x40>; 1644 sound-name-prefix = "TDMOUT_B"; 1645 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1646 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1647 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1648 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1649 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1650 clock-names = "pclk", "sclk", "sclk_sel", 1651 "lrclk", "lrclk_sel"; 1652 status = "disabled"; 1653 }; 1654 1655 tdmout_c: audio-controller@580 { 1656 compatible = "amlogic,g12a-tdmout"; 1657 reg = <0x0 0x580 0x0 0x40>; 1658 sound-name-prefix = "TDMOUT_C"; 1659 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1660 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1661 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1662 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1663 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1664 clock-names = "pclk", "sclk", "sclk_sel", 1665 "lrclk", "lrclk_sel"; 1666 status = "disabled"; 1667 }; 1668 1669 spdifout_b: audio-controller@680 { 1670 compatible = "amlogic,g12a-spdifout", 1671 "amlogic,axg-spdifout"; 1672 reg = <0x0 0x680 0x0 0x50>; 1673 #sound-dai-cells = <0>; 1674 sound-name-prefix = "SPDIFOUT_B"; 1675 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1676 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1677 clock-names = "pclk", "mclk"; 1678 status = "disabled"; 1679 }; 1680 1681 tohdmitx: audio-controller@744 { 1682 compatible = "amlogic,g12a-tohdmitx"; 1683 reg = <0x0 0x744 0x0 0x4>; 1684 #sound-dai-cells = <1>; 1685 sound-name-prefix = "TOHDMITX"; 1686 status = "disabled"; 1687 }; 1688 }; 1689 1690 usb3_pcie_phy: phy@46000 { 1691 compatible = "amlogic,g12a-usb3-pcie-phy"; 1692 reg = <0x0 0x46000 0x0 0x2000>; 1693 clocks = <&clkc CLKID_PCIE_PLL>; 1694 clock-names = "ref_clk"; 1695 resets = <&reset RESET_PCIE_PHY>; 1696 reset-names = "phy"; 1697 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1698 assigned-clock-rates = <100000000>; 1699 #phy-cells = <1>; 1700 }; 1701 1702 eth_phy: mdio-multiplexer@4c000 { 1703 compatible = "amlogic,g12a-mdio-mux"; 1704 reg = <0x0 0x4c000 0x0 0xa4>; 1705 clocks = <&clkc CLKID_ETH_PHY>, 1706 <&xtal>, 1707 <&clkc CLKID_MPLL_50M>; 1708 clock-names = "pclk", "clkin0", "clkin1"; 1709 mdio-parent-bus = <&mdio0>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 1713 ext_mdio: mdio@0 { 1714 reg = <0>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 }; 1718 1719 int_mdio: mdio@1 { 1720 reg = <1>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 internal_ephy: ethernet_phy@8 { 1725 compatible = "ethernet-phy-id0180.3301", 1726 "ethernet-phy-ieee802.3-c22"; 1727 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1728 reg = <8>; 1729 max-speed = <100>; 1730 }; 1731 }; 1732 }; 1733 }; 1734 1735 aobus: bus@ff800000 { 1736 compatible = "simple-bus"; 1737 reg = <0x0 0xff800000 0x0 0x100000>; 1738 #address-cells = <2>; 1739 #size-cells = <2>; 1740 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1741 1742 rti: sys-ctrl@0 { 1743 compatible = "amlogic,meson-gx-ao-sysctrl", 1744 "simple-mfd", "syscon"; 1745 reg = <0x0 0x0 0x0 0x100>; 1746 #address-cells = <2>; 1747 #size-cells = <2>; 1748 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1749 1750 clkc_AO: clock-controller { 1751 compatible = "amlogic,meson-g12a-aoclkc"; 1752 #clock-cells = <1>; 1753 #reset-cells = <1>; 1754 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1755 clock-names = "xtal", "mpeg-clk"; 1756 }; 1757 1758 pwrc_vpu: power-controller-vpu { 1759 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1760 #power-domain-cells = <0>; 1761 amlogic,hhi-sysctrl = <&hhi>; 1762 resets = <&reset RESET_VIU>, 1763 <&reset RESET_VENC>, 1764 <&reset RESET_VCBUS>, 1765 <&reset RESET_BT656>, 1766 <&reset RESET_RDMA>, 1767 <&reset RESET_VENCI>, 1768 <&reset RESET_VENCP>, 1769 <&reset RESET_VDAC>, 1770 <&reset RESET_VDI6>, 1771 <&reset RESET_VENCL>, 1772 <&reset RESET_VID_LOCK>; 1773 clocks = <&clkc CLKID_VPU>, 1774 <&clkc CLKID_VAPB>; 1775 clock-names = "vpu", "vapb"; 1776 /* 1777 * VPU clocking is provided by two identical clock paths 1778 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1779 * free mux to safely change frequency while running. 1780 * Same for VAPB but with a final gate after the glitch free mux. 1781 */ 1782 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1783 <&clkc CLKID_VPU_0>, 1784 <&clkc CLKID_VPU>, /* Glitch free mux */ 1785 <&clkc CLKID_VAPB_0_SEL>, 1786 <&clkc CLKID_VAPB_0>, 1787 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1788 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1789 <0>, /* Do Nothing */ 1790 <&clkc CLKID_VPU_0>, 1791 <&clkc CLKID_FCLK_DIV4>, 1792 <0>, /* Do Nothing */ 1793 <&clkc CLKID_VAPB_0>; 1794 assigned-clock-rates = <0>, /* Do Nothing */ 1795 <666666666>, 1796 <0>, /* Do Nothing */ 1797 <0>, /* Do Nothing */ 1798 <250000000>, 1799 <0>; /* Do Nothing */ 1800 }; 1801 1802 ao_pinctrl: pinctrl@14 { 1803 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1804 #address-cells = <2>; 1805 #size-cells = <2>; 1806 ranges; 1807 1808 gpio_ao: bank@14 { 1809 reg = <0x0 0x14 0x0 0x8>, 1810 <0x0 0x1c 0x0 0x8>, 1811 <0x0 0x24 0x0 0x14>; 1812 reg-names = "mux", 1813 "ds", 1814 "gpio"; 1815 gpio-controller; 1816 #gpio-cells = <2>; 1817 gpio-ranges = <&ao_pinctrl 0 0 15>; 1818 }; 1819 1820 i2c_ao_sck_pins: i2c_ao_sck_pins { 1821 mux { 1822 groups = "i2c_ao_sck"; 1823 function = "i2c_ao"; 1824 bias-disable; 1825 drive-strength-microamp = <3000>; 1826 }; 1827 }; 1828 1829 i2c_ao_sda_pins: i2c_ao_sda { 1830 mux { 1831 groups = "i2c_ao_sda"; 1832 function = "i2c_ao"; 1833 bias-disable; 1834 drive-strength-microamp = <3000>; 1835 }; 1836 }; 1837 1838 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1839 mux { 1840 groups = "i2c_ao_sck_e"; 1841 function = "i2c_ao"; 1842 bias-disable; 1843 drive-strength-microamp = <3000>; 1844 }; 1845 }; 1846 1847 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1848 mux { 1849 groups = "i2c_ao_sda_e"; 1850 function = "i2c_ao"; 1851 bias-disable; 1852 drive-strength-microamp = <3000>; 1853 }; 1854 }; 1855 1856 mclk0_ao_pins: mclk0-ao { 1857 mux { 1858 groups = "mclk0_ao"; 1859 function = "mclk0_ao"; 1860 bias-disable; 1861 drive-strength-microamp = <3000>; 1862 }; 1863 }; 1864 1865 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1866 mux { 1867 groups = "tdm_ao_b_din0"; 1868 function = "tdm_ao_b"; 1869 bias-disable; 1870 }; 1871 }; 1872 1873 spdif_ao_out_pins: spdif-ao-out { 1874 mux { 1875 groups = "spdif_ao_out"; 1876 function = "spdif_ao_out"; 1877 drive-strength-microamp = <500>; 1878 bias-disable; 1879 }; 1880 }; 1881 1882 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1883 mux { 1884 groups = "tdm_ao_b_din1"; 1885 function = "tdm_ao_b"; 1886 bias-disable; 1887 }; 1888 }; 1889 1890 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1891 mux { 1892 groups = "tdm_ao_b_din2"; 1893 function = "tdm_ao_b"; 1894 bias-disable; 1895 }; 1896 }; 1897 1898 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1899 mux { 1900 groups = "tdm_ao_b_dout0"; 1901 function = "tdm_ao_b"; 1902 bias-disable; 1903 drive-strength-microamp = <3000>; 1904 }; 1905 }; 1906 1907 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1908 mux { 1909 groups = "tdm_ao_b_dout1"; 1910 function = "tdm_ao_b"; 1911 bias-disable; 1912 drive-strength-microamp = <3000>; 1913 }; 1914 }; 1915 1916 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1917 mux { 1918 groups = "tdm_ao_b_dout2"; 1919 function = "tdm_ao_b"; 1920 bias-disable; 1921 drive-strength-microamp = <3000>; 1922 }; 1923 }; 1924 1925 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1926 mux { 1927 groups = "tdm_ao_b_fs"; 1928 function = "tdm_ao_b"; 1929 bias-disable; 1930 drive-strength-microamp = <3000>; 1931 }; 1932 }; 1933 1934 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1935 mux { 1936 groups = "tdm_ao_b_sclk"; 1937 function = "tdm_ao_b"; 1938 bias-disable; 1939 drive-strength-microamp = <3000>; 1940 }; 1941 }; 1942 1943 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1944 mux { 1945 groups = "tdm_ao_b_slv_fs"; 1946 function = "tdm_ao_b"; 1947 bias-disable; 1948 }; 1949 }; 1950 1951 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1952 mux { 1953 groups = "tdm_ao_b_slv_sclk"; 1954 function = "tdm_ao_b"; 1955 bias-disable; 1956 }; 1957 }; 1958 1959 uart_ao_a_pins: uart-a-ao { 1960 mux { 1961 groups = "uart_ao_a_tx", 1962 "uart_ao_a_rx"; 1963 function = "uart_ao_a"; 1964 bias-disable; 1965 }; 1966 }; 1967 1968 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1969 mux { 1970 groups = "uart_ao_a_cts", 1971 "uart_ao_a_rts"; 1972 function = "uart_ao_a"; 1973 bias-disable; 1974 }; 1975 }; 1976 1977 pwm_ao_a_pins: pwm-ao-a { 1978 mux { 1979 groups = "pwm_ao_a"; 1980 function = "pwm_ao_a"; 1981 bias-disable; 1982 }; 1983 }; 1984 1985 pwm_ao_b_pins: pwm-ao-b { 1986 mux { 1987 groups = "pwm_ao_b"; 1988 function = "pwm_ao_b"; 1989 bias-disable; 1990 }; 1991 }; 1992 1993 pwm_ao_c_4_pins: pwm-ao-c-4 { 1994 mux { 1995 groups = "pwm_ao_c_4"; 1996 function = "pwm_ao_c"; 1997 bias-disable; 1998 }; 1999 }; 2000 2001 pwm_ao_c_6_pins: pwm-ao-c-6 { 2002 mux { 2003 groups = "pwm_ao_c_6"; 2004 function = "pwm_ao_c"; 2005 bias-disable; 2006 }; 2007 }; 2008 2009 pwm_ao_d_5_pins: pwm-ao-d-5 { 2010 mux { 2011 groups = "pwm_ao_d_5"; 2012 function = "pwm_ao_d"; 2013 bias-disable; 2014 }; 2015 }; 2016 2017 pwm_ao_d_10_pins: pwm-ao-d-10 { 2018 mux { 2019 groups = "pwm_ao_d_10"; 2020 function = "pwm_ao_d"; 2021 bias-disable; 2022 }; 2023 }; 2024 2025 pwm_ao_d_e_pins: pwm-ao-d-e { 2026 mux { 2027 groups = "pwm_ao_d_e"; 2028 function = "pwm_ao_d"; 2029 }; 2030 }; 2031 2032 remote_input_ao_pins: remote-input-ao { 2033 mux { 2034 groups = "remote_ao_input"; 2035 function = "remote_ao_input"; 2036 bias-disable; 2037 }; 2038 }; 2039 }; 2040 }; 2041 2042 cec_AO: cec@100 { 2043 compatible = "amlogic,meson-gx-ao-cec"; 2044 reg = <0x0 0x00100 0x0 0x14>; 2045 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2046 clocks = <&clkc_AO CLKID_AO_CEC>; 2047 clock-names = "core"; 2048 status = "disabled"; 2049 }; 2050 2051 sec_AO: ao-secure@140 { 2052 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2053 reg = <0x0 0x140 0x0 0x140>; 2054 amlogic,has-chip-id; 2055 }; 2056 2057 cecb_AO: cec@280 { 2058 compatible = "amlogic,meson-g12a-ao-cec"; 2059 reg = <0x0 0x00280 0x0 0x1c>; 2060 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2061 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2062 clock-names = "oscin"; 2063 status = "disabled"; 2064 }; 2065 2066 pwm_AO_cd: pwm@2000 { 2067 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2068 reg = <0x0 0x2000 0x0 0x20>; 2069 #pwm-cells = <3>; 2070 status = "disabled"; 2071 }; 2072 2073 uart_AO: serial@3000 { 2074 compatible = "amlogic,meson-gx-uart", 2075 "amlogic,meson-ao-uart"; 2076 reg = <0x0 0x3000 0x0 0x18>; 2077 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2078 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2079 clock-names = "xtal", "pclk", "baud"; 2080 status = "disabled"; 2081 }; 2082 2083 uart_AO_B: serial@4000 { 2084 compatible = "amlogic,meson-gx-uart", 2085 "amlogic,meson-ao-uart"; 2086 reg = <0x0 0x4000 0x0 0x18>; 2087 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2088 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2089 clock-names = "xtal", "pclk", "baud"; 2090 status = "disabled"; 2091 }; 2092 2093 i2c_AO: i2c@5000 { 2094 compatible = "amlogic,meson-axg-i2c"; 2095 status = "disabled"; 2096 reg = <0x0 0x05000 0x0 0x20>; 2097 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 clocks = <&clkc CLKID_I2C>; 2101 }; 2102 2103 pwm_AO_ab: pwm@7000 { 2104 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2105 reg = <0x0 0x7000 0x0 0x20>; 2106 #pwm-cells = <3>; 2107 status = "disabled"; 2108 }; 2109 2110 ir: ir@8000 { 2111 compatible = "amlogic,meson-gxbb-ir"; 2112 reg = <0x0 0x8000 0x0 0x20>; 2113 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2114 status = "disabled"; 2115 }; 2116 2117 saradc: adc@9000 { 2118 compatible = "amlogic,meson-g12a-saradc", 2119 "amlogic,meson-saradc"; 2120 reg = <0x0 0x9000 0x0 0x48>; 2121 #io-channel-cells = <1>; 2122 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2123 clocks = <&xtal>, 2124 <&clkc_AO CLKID_AO_SAR_ADC>, 2125 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2126 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2127 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2128 status = "disabled"; 2129 }; 2130 }; 2131 2132 vpu: vpu@ff900000 { 2133 compatible = "amlogic,meson-g12a-vpu"; 2134 reg = <0x0 0xff900000 0x0 0x100000>, 2135 <0x0 0xff63c000 0x0 0x1000>; 2136 reg-names = "vpu", "hhi"; 2137 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 amlogic,canvas = <&canvas>; 2141 power-domains = <&pwrc_vpu>; 2142 2143 /* CVBS VDAC output port */ 2144 cvbs_vdac_port: port@0 { 2145 reg = <0>; 2146 }; 2147 2148 /* HDMI-TX output port */ 2149 hdmi_tx_port: port@1 { 2150 reg = <1>; 2151 2152 hdmi_tx_out: endpoint { 2153 remote-endpoint = <&hdmi_tx_in>; 2154 }; 2155 }; 2156 }; 2157 2158 gic: interrupt-controller@ffc01000 { 2159 compatible = "arm,gic-400"; 2160 reg = <0x0 0xffc01000 0 0x1000>, 2161 <0x0 0xffc02000 0 0x2000>, 2162 <0x0 0xffc04000 0 0x2000>, 2163 <0x0 0xffc06000 0 0x2000>; 2164 interrupt-controller; 2165 interrupts = <GIC_PPI 9 2166 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2167 #interrupt-cells = <3>; 2168 #address-cells = <0>; 2169 }; 2170 2171 cbus: bus@ffd00000 { 2172 compatible = "simple-bus"; 2173 reg = <0x0 0xffd00000 0x0 0x100000>; 2174 #address-cells = <2>; 2175 #size-cells = <2>; 2176 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2177 2178 reset: reset-controller@1004 { 2179 compatible = "amlogic,meson-g12a-reset", 2180 "amlogic,meson-axg-reset"; 2181 reg = <0x0 0x1004 0x0 0x9c>; 2182 #reset-cells = <1>; 2183 }; 2184 2185 pwm_ef: pwm@19000 { 2186 compatible = "amlogic,meson-g12a-ee-pwm"; 2187 reg = <0x0 0x19000 0x0 0x20>; 2188 #pwm-cells = <3>; 2189 status = "disabled"; 2190 }; 2191 2192 pwm_cd: pwm@1a000 { 2193 compatible = "amlogic,meson-g12a-ee-pwm"; 2194 reg = <0x0 0x1a000 0x0 0x20>; 2195 #pwm-cells = <3>; 2196 status = "disabled"; 2197 }; 2198 2199 pwm_ab: pwm@1b000 { 2200 compatible = "amlogic,meson-g12a-ee-pwm"; 2201 reg = <0x0 0x1b000 0x0 0x20>; 2202 #pwm-cells = <3>; 2203 status = "disabled"; 2204 }; 2205 2206 i2c3: i2c@1c000 { 2207 compatible = "amlogic,meson-axg-i2c"; 2208 status = "disabled"; 2209 reg = <0x0 0x1c000 0x0 0x20>; 2210 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2211 #address-cells = <1>; 2212 #size-cells = <0>; 2213 clocks = <&clkc CLKID_I2C>; 2214 }; 2215 2216 i2c2: i2c@1d000 { 2217 compatible = "amlogic,meson-axg-i2c"; 2218 status = "disabled"; 2219 reg = <0x0 0x1d000 0x0 0x20>; 2220 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 clocks = <&clkc CLKID_I2C>; 2224 }; 2225 2226 i2c1: i2c@1e000 { 2227 compatible = "amlogic,meson-axg-i2c"; 2228 status = "disabled"; 2229 reg = <0x0 0x1e000 0x0 0x20>; 2230 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 clocks = <&clkc CLKID_I2C>; 2234 }; 2235 2236 i2c0: i2c@1f000 { 2237 compatible = "amlogic,meson-axg-i2c"; 2238 status = "disabled"; 2239 reg = <0x0 0x1f000 0x0 0x20>; 2240 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 clocks = <&clkc CLKID_I2C>; 2244 }; 2245 2246 clk_msr: clock-measure@18000 { 2247 compatible = "amlogic,meson-g12a-clk-measure"; 2248 reg = <0x0 0x18000 0x0 0x10>; 2249 }; 2250 2251 uart_C: serial@22000 { 2252 compatible = "amlogic,meson-gx-uart"; 2253 reg = <0x0 0x22000 0x0 0x18>; 2254 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2255 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2256 clock-names = "xtal", "pclk", "baud"; 2257 status = "disabled"; 2258 }; 2259 2260 uart_B: serial@23000 { 2261 compatible = "amlogic,meson-gx-uart"; 2262 reg = <0x0 0x23000 0x0 0x18>; 2263 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2264 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2265 clock-names = "xtal", "pclk", "baud"; 2266 status = "disabled"; 2267 }; 2268 2269 uart_A: serial@24000 { 2270 compatible = "amlogic,meson-gx-uart"; 2271 reg = <0x0 0x24000 0x0 0x18>; 2272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2273 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2274 clock-names = "xtal", "pclk", "baud"; 2275 status = "disabled"; 2276 }; 2277 }; 2278 2279 sd_emmc_b: sd@ffe05000 { 2280 compatible = "amlogic,meson-axg-mmc"; 2281 reg = <0x0 0xffe05000 0x0 0x800>; 2282 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2283 status = "disabled"; 2284 clocks = <&clkc CLKID_SD_EMMC_B>, 2285 <&clkc CLKID_SD_EMMC_B_CLK0>, 2286 <&clkc CLKID_FCLK_DIV2>; 2287 clock-names = "core", "clkin0", "clkin1"; 2288 resets = <&reset RESET_SD_EMMC_B>; 2289 }; 2290 2291 sd_emmc_c: mmc@ffe07000 { 2292 compatible = "amlogic,meson-axg-mmc"; 2293 reg = <0x0 0xffe07000 0x0 0x800>; 2294 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2295 status = "disabled"; 2296 clocks = <&clkc CLKID_SD_EMMC_C>, 2297 <&clkc CLKID_SD_EMMC_C_CLK0>, 2298 <&clkc CLKID_FCLK_DIV2>; 2299 clock-names = "core", "clkin0", "clkin1"; 2300 resets = <&reset RESET_SD_EMMC_C>; 2301 }; 2302 2303 usb: usb@ffe09000 { 2304 status = "disabled"; 2305 compatible = "amlogic,meson-g12a-usb-ctrl"; 2306 reg = <0x0 0xffe09000 0x0 0xa0>; 2307 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2308 #address-cells = <2>; 2309 #size-cells = <2>; 2310 ranges; 2311 2312 clocks = <&clkc CLKID_USB>; 2313 resets = <&reset RESET_USB>; 2314 2315 dr_mode = "otg"; 2316 2317 phys = <&usb2_phy0>, <&usb2_phy1>, 2318 <&usb3_pcie_phy PHY_TYPE_USB3>; 2319 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2320 2321 dwc2: usb@ff400000 { 2322 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2323 reg = <0x0 0xff400000 0x0 0x40000>; 2324 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2325 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2326 clock-names = "ddr"; 2327 phys = <&usb2_phy1>; 2328 dr_mode = "peripheral"; 2329 g-rx-fifo-size = <192>; 2330 g-np-tx-fifo-size = <128>; 2331 g-tx-fifo-size = <128 128 16 16 16>; 2332 }; 2333 2334 dwc3: usb@ff500000 { 2335 compatible = "snps,dwc3"; 2336 reg = <0x0 0xff500000 0x0 0x100000>; 2337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2338 dr_mode = "host"; 2339 snps,dis_u2_susphy_quirk; 2340 snps,quirk-frame-length-adjustment; 2341 }; 2342 }; 2343 2344 mali: gpu@ffe40000 { 2345 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2346 reg = <0x0 0xffe40000 0x0 0x40000>; 2347 interrupt-parent = <&gic>; 2348 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-names = "gpu", "mmu", "job"; 2352 clocks = <&clkc CLKID_MALI>; 2353 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2354 2355 /* 2356 * Mali clocking is provided by two identical clock paths 2357 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2358 * free mux to safely change frequency while running. 2359 */ 2360 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2361 <&clkc CLKID_MALI_0>, 2362 <&clkc CLKID_MALI>; /* Glitch free mux */ 2363 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2364 <0>, /* Do Nothing */ 2365 <&clkc CLKID_MALI_0>; 2366 assigned-clock-rates = <0>, /* Do Nothing */ 2367 <800000000>, 2368 <0>; /* Do Nothing */ 2369 }; 2370 }; 2371 2372 timer { 2373 compatible = "arm,armv8-timer"; 2374 interrupts = <GIC_PPI 13 2375 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2376 <GIC_PPI 14 2377 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2378 <GIC_PPI 11 2379 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2380 <GIC_PPI 10 2381 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2382 }; 2383 2384 xtal: xtal-clk { 2385 compatible = "fixed-clock"; 2386 clock-frequency = <24000000>; 2387 clock-output-names = "xtal"; 2388 #clock-cells = <0>; 2389 }; 2390 2391}; 2392