1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 ethmac: ethernet@ff3f0000 { 141 compatible = "amlogic,meson-axg-dwmac", 142 "snps,dwmac-3.70a", 143 "snps,dwmac"; 144 reg = <0x0 0xff3f0000 0x0 0x10000 145 0x0 0xff634540 0x0 0x8>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "macirq"; 148 clocks = <&clkc CLKID_ETH>, 149 <&clkc CLKID_FCLK_DIV2>, 150 <&clkc CLKID_MPLL2>; 151 clock-names = "stmmaceth", "clkin0", "clkin1"; 152 status = "disabled"; 153 154 mdio0: mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "snps,dwmac-mdio"; 158 }; 159 }; 160 161 apb: bus@ff600000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xff600000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 167 168 hdmi_tx: hdmi-tx@0 { 169 compatible = "amlogic,meson-g12a-dw-hdmi"; 170 reg = <0x0 0x0 0x0 0x10000>; 171 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 172 resets = <&reset RESET_HDMITX_CAPB3>, 173 <&reset RESET_HDMITX_PHY>, 174 <&reset RESET_HDMITX>; 175 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 176 clocks = <&clkc CLKID_HDMI>, 177 <&clkc CLKID_HTX_PCLK>, 178 <&clkc CLKID_VPU_INTR>; 179 clock-names = "isfr", "iahb", "venci"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 185 /* VPU VENC Input */ 186 hdmi_tx_venc_port: port@0 { 187 reg = <0>; 188 189 hdmi_tx_in: endpoint { 190 remote-endpoint = <&hdmi_tx_out>; 191 }; 192 }; 193 194 /* TMDS Output */ 195 hdmi_tx_tmds_port: port@1 { 196 reg = <1>; 197 }; 198 }; 199 200 periphs: bus@34400 { 201 compatible = "simple-bus"; 202 reg = <0x0 0x34400 0x0 0x400>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 206 207 periphs_pinctrl: pinctrl@40 { 208 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges; 212 213 gpio: bank@40 { 214 reg = <0x0 0x40 0x0 0x4c>, 215 <0x0 0xe8 0x0 0x18>, 216 <0x0 0x120 0x0 0x18>, 217 <0x0 0x2c0 0x0 0x40>, 218 <0x0 0x340 0x0 0x1c>; 219 reg-names = "gpio", 220 "pull", 221 "pull-enable", 222 "mux", 223 "ds"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&periphs_pinctrl 0 0 86>; 227 }; 228 229 cec_ao_a_h_pins: cec_ao_a_h { 230 mux { 231 groups = "cec_ao_a_h"; 232 function = "cec_ao_a_h"; 233 bias-disable; 234 }; 235 }; 236 237 cec_ao_b_h_pins: cec_ao_b_h { 238 mux { 239 groups = "cec_ao_b_h"; 240 function = "cec_ao_b_h"; 241 bias-disable; 242 }; 243 }; 244 245 emmc_pins: emmc { 246 mux-0 { 247 groups = "emmc_nand_d0", 248 "emmc_nand_d1", 249 "emmc_nand_d2", 250 "emmc_nand_d3", 251 "emmc_nand_d4", 252 "emmc_nand_d5", 253 "emmc_nand_d6", 254 "emmc_nand_d7", 255 "emmc_cmd"; 256 function = "emmc"; 257 bias-pull-up; 258 drive-strength-microamp = <4000>; 259 }; 260 261 mux-1 { 262 groups = "emmc_clk"; 263 function = "emmc"; 264 bias-disable; 265 drive-strength-microamp = <4000>; 266 }; 267 }; 268 269 emmc_ds_pins: emmc-ds { 270 mux { 271 groups = "emmc_nand_ds"; 272 function = "emmc"; 273 bias-pull-down; 274 drive-strength-microamp = <4000>; 275 }; 276 }; 277 278 emmc_clk_gate_pins: emmc_clk_gate { 279 mux { 280 groups = "BOOT_8"; 281 function = "gpio_periphs"; 282 bias-pull-down; 283 drive-strength-microamp = <4000>; 284 }; 285 }; 286 287 hdmitx_ddc_pins: hdmitx_ddc { 288 mux { 289 groups = "hdmitx_sda", 290 "hdmitx_sck"; 291 function = "hdmitx"; 292 bias-disable; 293 drive-strength-microamp = <4000>; 294 }; 295 }; 296 297 hdmitx_hpd_pins: hdmitx_hpd { 298 mux { 299 groups = "hdmitx_hpd_in"; 300 function = "hdmitx"; 301 bias-disable; 302 }; 303 }; 304 305 306 i2c0_sda_c_pins: i2c0-sda-c { 307 mux { 308 groups = "i2c0_sda_c"; 309 function = "i2c0"; 310 bias-disable; 311 drive-strength-microamp = <3000>; 312 313 }; 314 }; 315 316 i2c0_sck_c_pins: i2c0-sck-c { 317 mux { 318 groups = "i2c0_sck_c"; 319 function = "i2c0"; 320 bias-disable; 321 drive-strength-microamp = <3000>; 322 }; 323 }; 324 325 i2c0_sda_z0_pins: i2c0-sda-z0 { 326 mux { 327 groups = "i2c0_sda_z0"; 328 function = "i2c0"; 329 bias-disable; 330 drive-strength-microamp = <3000>; 331 }; 332 }; 333 334 i2c0_sck_z1_pins: i2c0-sck-z1 { 335 mux { 336 groups = "i2c0_sck_z1"; 337 function = "i2c0"; 338 bias-disable; 339 drive-strength-microamp = <3000>; 340 }; 341 }; 342 343 i2c0_sda_z7_pins: i2c0-sda-z7 { 344 mux { 345 groups = "i2c0_sda_z7"; 346 function = "i2c0"; 347 bias-disable; 348 drive-strength-microamp = <3000>; 349 }; 350 }; 351 352 i2c0_sda_z8_pins: i2c0-sda-z8 { 353 mux { 354 groups = "i2c0_sda_z8"; 355 function = "i2c0"; 356 bias-disable; 357 drive-strength-microamp = <3000>; 358 }; 359 }; 360 361 i2c1_sda_x_pins: i2c1-sda-x { 362 mux { 363 groups = "i2c1_sda_x"; 364 function = "i2c1"; 365 bias-disable; 366 drive-strength-microamp = <3000>; 367 }; 368 }; 369 370 i2c1_sck_x_pins: i2c1-sck-x { 371 mux { 372 groups = "i2c1_sck_x"; 373 function = "i2c1"; 374 bias-disable; 375 drive-strength-microamp = <3000>; 376 }; 377 }; 378 379 i2c1_sda_h2_pins: i2c1-sda-h2 { 380 mux { 381 groups = "i2c1_sda_h2"; 382 function = "i2c1"; 383 bias-disable; 384 drive-strength-microamp = <3000>; 385 }; 386 }; 387 388 i2c1_sck_h3_pins: i2c1-sck-h3 { 389 mux { 390 groups = "i2c1_sck_h3"; 391 function = "i2c1"; 392 bias-disable; 393 drive-strength-microamp = <3000>; 394 }; 395 }; 396 397 i2c1_sda_h6_pins: i2c1-sda-h6 { 398 mux { 399 groups = "i2c1_sda_h6"; 400 function = "i2c1"; 401 bias-disable; 402 drive-strength-microamp = <3000>; 403 }; 404 }; 405 406 i2c1_sck_h7_pins: i2c1-sck-h7 { 407 mux { 408 groups = "i2c1_sck_h7"; 409 function = "i2c1"; 410 bias-disable; 411 drive-strength-microamp = <3000>; 412 }; 413 }; 414 415 i2c2_sda_x_pins: i2c2-sda-x { 416 mux { 417 groups = "i2c2_sda_x"; 418 function = "i2c2"; 419 bias-disable; 420 drive-strength-microamp = <3000>; 421 }; 422 }; 423 424 i2c2_sck_x_pins: i2c2-sck-x { 425 mux { 426 groups = "i2c2_sck_x"; 427 function = "i2c2"; 428 bias-disable; 429 drive-strength-microamp = <3000>; 430 }; 431 }; 432 433 i2c2_sda_z_pins: i2c2-sda-z { 434 mux { 435 groups = "i2c2_sda_z"; 436 function = "i2c2"; 437 bias-disable; 438 drive-strength-microamp = <3000>; 439 }; 440 }; 441 442 i2c2_sck_z_pins: i2c2-sck-z { 443 mux { 444 groups = "i2c2_sck_z"; 445 function = "i2c2"; 446 bias-disable; 447 drive-strength-microamp = <3000>; 448 }; 449 }; 450 451 i2c3_sda_h_pins: i2c3-sda-h { 452 mux { 453 groups = "i2c3_sda_h"; 454 function = "i2c3"; 455 bias-disable; 456 drive-strength-microamp = <3000>; 457 }; 458 }; 459 460 i2c3_sck_h_pins: i2c3-sck-h { 461 mux { 462 groups = "i2c3_sck_h"; 463 function = "i2c3"; 464 bias-disable; 465 drive-strength-microamp = <3000>; 466 }; 467 }; 468 469 i2c3_sda_a_pins: i2c3-sda-a { 470 mux { 471 groups = "i2c3_sda_a"; 472 function = "i2c3"; 473 bias-disable; 474 drive-strength-microamp = <3000>; 475 }; 476 }; 477 478 i2c3_sck_a_pins: i2c3-sck-a { 479 mux { 480 groups = "i2c3_sck_a"; 481 function = "i2c3"; 482 bias-disable; 483 drive-strength-microamp = <3000>; 484 }; 485 }; 486 487 mclk0_a_pins: mclk0-a { 488 mux { 489 groups = "mclk0_a"; 490 function = "mclk0"; 491 bias-disable; 492 drive-strength-microamp = <3000>; 493 }; 494 }; 495 496 mclk1_a_pins: mclk1-a { 497 mux { 498 groups = "mclk1_a"; 499 function = "mclk1"; 500 bias-disable; 501 drive-strength-microamp = <3000>; 502 }; 503 }; 504 505 mclk1_x_pins: mclk1-x { 506 mux { 507 groups = "mclk1_x"; 508 function = "mclk1"; 509 bias-disable; 510 drive-strength-microamp = <3000>; 511 }; 512 }; 513 514 mclk1_z_pins: mclk1-z { 515 mux { 516 groups = "mclk1_z"; 517 function = "mclk1"; 518 bias-disable; 519 drive-strength-microamp = <3000>; 520 }; 521 }; 522 523 pdm_din0_a_pins: pdm-din0-a { 524 mux { 525 groups = "pdm_din0_a"; 526 function = "pdm"; 527 bias-disable; 528 }; 529 }; 530 531 pdm_din0_c_pins: pdm-din0-c { 532 mux { 533 groups = "pdm_din0_c"; 534 function = "pdm"; 535 bias-disable; 536 }; 537 }; 538 539 pdm_din0_x_pins: pdm-din0-x { 540 mux { 541 groups = "pdm_din0_x"; 542 function = "pdm"; 543 bias-disable; 544 }; 545 }; 546 547 pdm_din0_z_pins: pdm-din0-z { 548 mux { 549 groups = "pdm_din0_z"; 550 function = "pdm"; 551 bias-disable; 552 }; 553 }; 554 555 pdm_din1_a_pins: pdm-din1-a { 556 mux { 557 groups = "pdm_din1_a"; 558 function = "pdm"; 559 bias-disable; 560 }; 561 }; 562 563 pdm_din1_c_pins: pdm-din1-c { 564 mux { 565 groups = "pdm_din1_c"; 566 function = "pdm"; 567 bias-disable; 568 }; 569 }; 570 571 pdm_din1_x_pins: pdm-din1-x { 572 mux { 573 groups = "pdm_din1_x"; 574 function = "pdm"; 575 bias-disable; 576 }; 577 }; 578 579 pdm_din1_z_pins: pdm-din1-z { 580 mux { 581 groups = "pdm_din1_z"; 582 function = "pdm"; 583 bias-disable; 584 }; 585 }; 586 587 pdm_din2_a_pins: pdm-din2-a { 588 mux { 589 groups = "pdm_din2_a"; 590 function = "pdm"; 591 bias-disable; 592 }; 593 }; 594 595 pdm_din2_c_pins: pdm-din2-c { 596 mux { 597 groups = "pdm_din2_c"; 598 function = "pdm"; 599 bias-disable; 600 }; 601 }; 602 603 pdm_din2_x_pins: pdm-din2-x { 604 mux { 605 groups = "pdm_din2_x"; 606 function = "pdm"; 607 bias-disable; 608 }; 609 }; 610 611 pdm_din2_z_pins: pdm-din2-z { 612 mux { 613 groups = "pdm_din2_z"; 614 function = "pdm"; 615 bias-disable; 616 }; 617 }; 618 619 pdm_din3_a_pins: pdm-din3-a { 620 mux { 621 groups = "pdm_din3_a"; 622 function = "pdm"; 623 bias-disable; 624 }; 625 }; 626 627 pdm_din3_c_pins: pdm-din3-c { 628 mux { 629 groups = "pdm_din3_c"; 630 function = "pdm"; 631 bias-disable; 632 }; 633 }; 634 635 pdm_din3_x_pins: pdm-din3-x { 636 mux { 637 groups = "pdm_din3_x"; 638 function = "pdm"; 639 bias-disable; 640 }; 641 }; 642 643 pdm_din3_z_pins: pdm-din3-z { 644 mux { 645 groups = "pdm_din3_z"; 646 function = "pdm"; 647 bias-disable; 648 }; 649 }; 650 651 pdm_dclk_a_pins: pdm-dclk-a { 652 mux { 653 groups = "pdm_dclk_a"; 654 function = "pdm"; 655 bias-disable; 656 drive-strength-microamp = <500>; 657 }; 658 }; 659 660 pdm_dclk_c_pins: pdm-dclk-c { 661 mux { 662 groups = "pdm_dclk_c"; 663 function = "pdm"; 664 bias-disable; 665 drive-strength-microamp = <500>; 666 }; 667 }; 668 669 pdm_dclk_x_pins: pdm-dclk-x { 670 mux { 671 groups = "pdm_dclk_x"; 672 function = "pdm"; 673 bias-disable; 674 drive-strength-microamp = <500>; 675 }; 676 }; 677 678 pdm_dclk_z_pins: pdm-dclk-z { 679 mux { 680 groups = "pdm_dclk_z"; 681 function = "pdm"; 682 bias-disable; 683 drive-strength-microamp = <500>; 684 }; 685 }; 686 687 pwm_a_pins: pwm-a { 688 mux { 689 groups = "pwm_a"; 690 function = "pwm_a"; 691 bias-disable; 692 }; 693 }; 694 695 pwm_b_x7_pins: pwm-b-x7 { 696 mux { 697 groups = "pwm_b_x7"; 698 function = "pwm_b"; 699 bias-disable; 700 }; 701 }; 702 703 pwm_b_x19_pins: pwm-b-x19 { 704 mux { 705 groups = "pwm_b_x19"; 706 function = "pwm_b"; 707 bias-disable; 708 }; 709 }; 710 711 pwm_c_c_pins: pwm-c-c { 712 mux { 713 groups = "pwm_c_c"; 714 function = "pwm_c"; 715 bias-disable; 716 }; 717 }; 718 719 pwm_c_x5_pins: pwm-c-x5 { 720 mux { 721 groups = "pwm_c_x5"; 722 function = "pwm_c"; 723 bias-disable; 724 }; 725 }; 726 727 pwm_c_x8_pins: pwm-c-x8 { 728 mux { 729 groups = "pwm_c_x8"; 730 function = "pwm_c"; 731 bias-disable; 732 }; 733 }; 734 735 pwm_d_x3_pins: pwm-d-x3 { 736 mux { 737 groups = "pwm_d_x3"; 738 function = "pwm_d"; 739 bias-disable; 740 }; 741 }; 742 743 pwm_d_x6_pins: pwm-d-x6 { 744 mux { 745 groups = "pwm_d_x6"; 746 function = "pwm_d"; 747 bias-disable; 748 }; 749 }; 750 751 pwm_e_pins: pwm-e { 752 mux { 753 groups = "pwm_e"; 754 function = "pwm_e"; 755 bias-disable; 756 }; 757 }; 758 759 pwm_f_x_pins: pwm-f-x { 760 mux { 761 groups = "pwm_f_x"; 762 function = "pwm_f"; 763 bias-disable; 764 }; 765 }; 766 767 pwm_f_h_pins: pwm-f-h { 768 mux { 769 groups = "pwm_f_h"; 770 function = "pwm_f"; 771 bias-disable; 772 }; 773 }; 774 775 sdcard_c_pins: sdcard_c { 776 mux-0 { 777 groups = "sdcard_d0_c", 778 "sdcard_d1_c", 779 "sdcard_d2_c", 780 "sdcard_d3_c", 781 "sdcard_cmd_c"; 782 function = "sdcard"; 783 bias-pull-up; 784 drive-strength-microamp = <4000>; 785 }; 786 787 mux-1 { 788 groups = "sdcard_clk_c"; 789 function = "sdcard"; 790 bias-disable; 791 drive-strength-microamp = <4000>; 792 }; 793 }; 794 795 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 796 mux { 797 groups = "GPIOC_4"; 798 function = "gpio_periphs"; 799 bias-pull-down; 800 drive-strength-microamp = <4000>; 801 }; 802 }; 803 804 sdcard_z_pins: sdcard_z { 805 mux-0 { 806 groups = "sdcard_d0_z", 807 "sdcard_d1_z", 808 "sdcard_d2_z", 809 "sdcard_d3_z", 810 "sdcard_cmd_z"; 811 function = "sdcard"; 812 bias-pull-up; 813 drive-strength-microamp = <4000>; 814 }; 815 816 mux-1 { 817 groups = "sdcard_clk_z"; 818 function = "sdcard"; 819 bias-disable; 820 drive-strength-microamp = <4000>; 821 }; 822 }; 823 824 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 825 mux { 826 groups = "GPIOZ_6"; 827 function = "gpio_periphs"; 828 bias-pull-down; 829 drive-strength-microamp = <4000>; 830 }; 831 }; 832 833 spdif_in_a10_pins: spdif-in-a10 { 834 mux { 835 groups = "spdif_in_a10"; 836 function = "spdif_in"; 837 bias-disable; 838 }; 839 }; 840 841 spdif_in_a12_pins: spdif-in-a12 { 842 mux { 843 groups = "spdif_in_a12"; 844 function = "spdif_in"; 845 bias-disable; 846 }; 847 }; 848 849 spdif_in_h_pins: spdif-in-h { 850 mux { 851 groups = "spdif_in_h"; 852 function = "spdif_in"; 853 bias-disable; 854 }; 855 }; 856 857 spdif_out_h_pins: spdif-out-h { 858 mux { 859 groups = "spdif_out_h"; 860 function = "spdif_out"; 861 drive-strength-microamp = <500>; 862 bias-disable; 863 }; 864 }; 865 866 spdif_out_a11_pins: spdif-out-a11 { 867 mux { 868 groups = "spdif_out_a11"; 869 function = "spdif_out"; 870 drive-strength-microamp = <500>; 871 bias-disable; 872 }; 873 }; 874 875 spdif_out_a13_pins: spdif-out-a13 { 876 mux { 877 groups = "spdif_out_a13"; 878 function = "spdif_out"; 879 drive-strength-microamp = <500>; 880 bias-disable; 881 }; 882 }; 883 884 tdm_a_din0_pins: tdm-a-din0 { 885 mux { 886 groups = "tdm_a_din0"; 887 function = "tdm_a"; 888 bias-disable; 889 }; 890 }; 891 892 893 tdm_a_din1_pins: tdm-a-din1 { 894 mux { 895 groups = "tdm_a_din1"; 896 function = "tdm_a"; 897 bias-disable; 898 }; 899 }; 900 901 tdm_a_dout0_pins: tdm-a-dout0 { 902 mux { 903 groups = "tdm_a_dout0"; 904 function = "tdm_a"; 905 bias-disable; 906 drive-strength-microamp = <3000>; 907 }; 908 }; 909 910 tdm_a_dout1_pins: tdm-a-dout1 { 911 mux { 912 groups = "tdm_a_dout1"; 913 function = "tdm_a"; 914 bias-disable; 915 drive-strength-microamp = <3000>; 916 }; 917 }; 918 919 tdm_a_fs_pins: tdm-a-fs { 920 mux { 921 groups = "tdm_a_fs"; 922 function = "tdm_a"; 923 bias-disable; 924 drive-strength-microamp = <3000>; 925 }; 926 }; 927 928 tdm_a_sclk_pins: tdm-a-sclk { 929 mux { 930 groups = "tdm_a_sclk"; 931 function = "tdm_a"; 932 bias-disable; 933 drive-strength-microamp = <3000>; 934 }; 935 }; 936 937 tdm_a_slv_fs_pins: tdm-a-slv-fs { 938 mux { 939 groups = "tdm_a_slv_fs"; 940 function = "tdm_a"; 941 bias-disable; 942 }; 943 }; 944 945 946 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 947 mux { 948 groups = "tdm_a_slv_sclk"; 949 function = "tdm_a"; 950 bias-disable; 951 }; 952 }; 953 954 tdm_b_din0_pins: tdm-b-din0 { 955 mux { 956 groups = "tdm_b_din0"; 957 function = "tdm_b"; 958 bias-disable; 959 }; 960 }; 961 962 tdm_b_din1_pins: tdm-b-din1 { 963 mux { 964 groups = "tdm_b_din1"; 965 function = "tdm_b"; 966 bias-disable; 967 }; 968 }; 969 970 tdm_b_din2_pins: tdm-b-din2 { 971 mux { 972 groups = "tdm_b_din2"; 973 function = "tdm_b"; 974 bias-disable; 975 }; 976 }; 977 978 tdm_b_din3_a_pins: tdm-b-din3-a { 979 mux { 980 groups = "tdm_b_din3_a"; 981 function = "tdm_b"; 982 bias-disable; 983 }; 984 }; 985 986 tdm_b_din3_h_pins: tdm-b-din3-h { 987 mux { 988 groups = "tdm_b_din3_h"; 989 function = "tdm_b"; 990 bias-disable; 991 }; 992 }; 993 994 tdm_b_dout0_pins: tdm-b-dout0 { 995 mux { 996 groups = "tdm_b_dout0"; 997 function = "tdm_b"; 998 bias-disable; 999 drive-strength-microamp = <3000>; 1000 }; 1001 }; 1002 1003 tdm_b_dout1_pins: tdm-b-dout1 { 1004 mux { 1005 groups = "tdm_b_dout1"; 1006 function = "tdm_b"; 1007 bias-disable; 1008 drive-strength-microamp = <3000>; 1009 }; 1010 }; 1011 1012 tdm_b_dout2_pins: tdm-b-dout2 { 1013 mux { 1014 groups = "tdm_b_dout2"; 1015 function = "tdm_b"; 1016 bias-disable; 1017 drive-strength-microamp = <3000>; 1018 }; 1019 }; 1020 1021 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1022 mux { 1023 groups = "tdm_b_dout3_a"; 1024 function = "tdm_b"; 1025 bias-disable; 1026 drive-strength-microamp = <3000>; 1027 }; 1028 }; 1029 1030 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1031 mux { 1032 groups = "tdm_b_dout3_h"; 1033 function = "tdm_b"; 1034 bias-disable; 1035 drive-strength-microamp = <3000>; 1036 }; 1037 }; 1038 1039 tdm_b_fs_pins: tdm-b-fs { 1040 mux { 1041 groups = "tdm_b_fs"; 1042 function = "tdm_b"; 1043 bias-disable; 1044 drive-strength-microamp = <3000>; 1045 }; 1046 }; 1047 1048 tdm_b_sclk_pins: tdm-b-sclk { 1049 mux { 1050 groups = "tdm_b_sclk"; 1051 function = "tdm_b"; 1052 bias-disable; 1053 drive-strength-microamp = <3000>; 1054 }; 1055 }; 1056 1057 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1058 mux { 1059 groups = "tdm_b_slv_fs"; 1060 function = "tdm_b"; 1061 bias-disable; 1062 }; 1063 }; 1064 1065 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1066 mux { 1067 groups = "tdm_b_slv_sclk"; 1068 function = "tdm_b"; 1069 bias-disable; 1070 }; 1071 }; 1072 1073 tdm_c_din0_a_pins: tdm-c-din0-a { 1074 mux { 1075 groups = "tdm_c_din0_a"; 1076 function = "tdm_c"; 1077 bias-disable; 1078 }; 1079 }; 1080 1081 tdm_c_din0_z_pins: tdm-c-din0-z { 1082 mux { 1083 groups = "tdm_c_din0_z"; 1084 function = "tdm_c"; 1085 bias-disable; 1086 }; 1087 }; 1088 1089 tdm_c_din1_a_pins: tdm-c-din1-a { 1090 mux { 1091 groups = "tdm_c_din1_a"; 1092 function = "tdm_c"; 1093 bias-disable; 1094 }; 1095 }; 1096 1097 tdm_c_din1_z_pins: tdm-c-din1-z { 1098 mux { 1099 groups = "tdm_c_din1_z"; 1100 function = "tdm_c"; 1101 bias-disable; 1102 }; 1103 }; 1104 1105 tdm_c_din2_a_pins: tdm-c-din2-a { 1106 mux { 1107 groups = "tdm_c_din2_a"; 1108 function = "tdm_c"; 1109 bias-disable; 1110 }; 1111 }; 1112 1113 eth_leds_pins: eth-leds { 1114 mux { 1115 groups = "eth_link_led", 1116 "eth_act_led"; 1117 function = "eth"; 1118 bias-disable; 1119 }; 1120 }; 1121 1122 eth_pins: eth { 1123 mux { 1124 groups = "eth_mdio", 1125 "eth_mdc", 1126 "eth_rgmii_rx_clk", 1127 "eth_rx_dv", 1128 "eth_rxd0", 1129 "eth_rxd1", 1130 "eth_txen", 1131 "eth_txd0", 1132 "eth_txd1"; 1133 function = "eth"; 1134 bias-disable; 1135 }; 1136 }; 1137 1138 eth_rgmii_pins: eth-rgmii { 1139 mux { 1140 groups = "eth_rxd2_rgmii", 1141 "eth_rxd3_rgmii", 1142 "eth_rgmii_tx_clk", 1143 "eth_txd2_rgmii", 1144 "eth_txd3_rgmii"; 1145 function = "eth"; 1146 bias-disable; 1147 }; 1148 }; 1149 1150 tdm_c_din2_z_pins: tdm-c-din2-z { 1151 mux { 1152 groups = "tdm_c_din2_z"; 1153 function = "tdm_c"; 1154 bias-disable; 1155 }; 1156 }; 1157 1158 tdm_c_din3_a_pins: tdm-c-din3-a { 1159 mux { 1160 groups = "tdm_c_din3_a"; 1161 function = "tdm_c"; 1162 bias-disable; 1163 }; 1164 }; 1165 1166 tdm_c_din3_z_pins: tdm-c-din3-z { 1167 mux { 1168 groups = "tdm_c_din3_z"; 1169 function = "tdm_c"; 1170 bias-disable; 1171 }; 1172 }; 1173 1174 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1175 mux { 1176 groups = "tdm_c_dout0_a"; 1177 function = "tdm_c"; 1178 bias-disable; 1179 drive-strength-microamp = <3000>; 1180 }; 1181 }; 1182 1183 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1184 mux { 1185 groups = "tdm_c_dout0_z"; 1186 function = "tdm_c"; 1187 bias-disable; 1188 drive-strength-microamp = <3000>; 1189 }; 1190 }; 1191 1192 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1193 mux { 1194 groups = "tdm_c_dout1_a"; 1195 function = "tdm_c"; 1196 bias-disable; 1197 drive-strength-microamp = <3000>; 1198 }; 1199 }; 1200 1201 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1202 mux { 1203 groups = "tdm_c_dout1_z"; 1204 function = "tdm_c"; 1205 bias-disable; 1206 drive-strength-microamp = <3000>; 1207 }; 1208 }; 1209 1210 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1211 mux { 1212 groups = "tdm_c_dout2_a"; 1213 function = "tdm_c"; 1214 bias-disable; 1215 drive-strength-microamp = <3000>; 1216 }; 1217 }; 1218 1219 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1220 mux { 1221 groups = "tdm_c_dout2_z"; 1222 function = "tdm_c"; 1223 bias-disable; 1224 drive-strength-microamp = <3000>; 1225 }; 1226 }; 1227 1228 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1229 mux { 1230 groups = "tdm_c_dout3_a"; 1231 function = "tdm_c"; 1232 bias-disable; 1233 drive-strength-microamp = <3000>; 1234 }; 1235 }; 1236 1237 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1238 mux { 1239 groups = "tdm_c_dout3_z"; 1240 function = "tdm_c"; 1241 bias-disable; 1242 drive-strength-microamp = <3000>; 1243 }; 1244 }; 1245 1246 tdm_c_fs_a_pins: tdm-c-fs-a { 1247 mux { 1248 groups = "tdm_c_fs_a"; 1249 function = "tdm_c"; 1250 bias-disable; 1251 drive-strength-microamp = <3000>; 1252 }; 1253 }; 1254 1255 tdm_c_fs_z_pins: tdm-c-fs-z { 1256 mux { 1257 groups = "tdm_c_fs_z"; 1258 function = "tdm_c"; 1259 bias-disable; 1260 drive-strength-microamp = <3000>; 1261 }; 1262 }; 1263 1264 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1265 mux { 1266 groups = "tdm_c_sclk_a"; 1267 function = "tdm_c"; 1268 bias-disable; 1269 drive-strength-microamp = <3000>; 1270 }; 1271 }; 1272 1273 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1274 mux { 1275 groups = "tdm_c_sclk_z"; 1276 function = "tdm_c"; 1277 bias-disable; 1278 drive-strength-microamp = <3000>; 1279 }; 1280 }; 1281 1282 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1283 mux { 1284 groups = "tdm_c_slv_fs_a"; 1285 function = "tdm_c"; 1286 bias-disable; 1287 }; 1288 }; 1289 1290 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1291 mux { 1292 groups = "tdm_c_slv_fs_z"; 1293 function = "tdm_c"; 1294 bias-disable; 1295 }; 1296 }; 1297 1298 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1299 mux { 1300 groups = "tdm_c_slv_sclk_a"; 1301 function = "tdm_c"; 1302 bias-disable; 1303 }; 1304 }; 1305 1306 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1307 mux { 1308 groups = "tdm_c_slv_sclk_z"; 1309 function = "tdm_c"; 1310 bias-disable; 1311 }; 1312 }; 1313 1314 uart_a_pins: uart-a { 1315 mux { 1316 groups = "uart_a_tx", 1317 "uart_a_rx"; 1318 function = "uart_a"; 1319 bias-disable; 1320 }; 1321 }; 1322 1323 uart_a_cts_rts_pins: uart-a-cts-rts { 1324 mux { 1325 groups = "uart_a_cts", 1326 "uart_a_rts"; 1327 function = "uart_a"; 1328 bias-disable; 1329 }; 1330 }; 1331 1332 uart_b_pins: uart-b { 1333 mux { 1334 groups = "uart_b_tx", 1335 "uart_b_rx"; 1336 function = "uart_b"; 1337 bias-disable; 1338 }; 1339 }; 1340 1341 uart_c_pins: uart-c { 1342 mux { 1343 groups = "uart_c_tx", 1344 "uart_c_rx"; 1345 function = "uart_c"; 1346 bias-disable; 1347 }; 1348 }; 1349 1350 uart_c_cts_rts_pins: uart-c-cts-rts { 1351 mux { 1352 groups = "uart_c_cts", 1353 "uart_c_rts"; 1354 function = "uart_c"; 1355 bias-disable; 1356 }; 1357 }; 1358 }; 1359 }; 1360 1361 usb2_phy0: phy@36000 { 1362 compatible = "amlogic,g12a-usb2-phy"; 1363 reg = <0x0 0x36000 0x0 0x2000>; 1364 clocks = <&xtal>; 1365 clock-names = "xtal"; 1366 resets = <&reset RESET_USB_PHY20>; 1367 reset-names = "phy"; 1368 #phy-cells = <0>; 1369 }; 1370 1371 dmc: bus@38000 { 1372 compatible = "simple-bus"; 1373 reg = <0x0 0x38000 0x0 0x400>; 1374 #address-cells = <2>; 1375 #size-cells = <2>; 1376 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1377 1378 canvas: video-lut@48 { 1379 compatible = "amlogic,canvas"; 1380 reg = <0x0 0x48 0x0 0x14>; 1381 }; 1382 }; 1383 1384 usb2_phy1: phy@3a000 { 1385 compatible = "amlogic,g12a-usb2-phy"; 1386 reg = <0x0 0x3a000 0x0 0x2000>; 1387 clocks = <&xtal>; 1388 clock-names = "xtal"; 1389 resets = <&reset RESET_USB_PHY21>; 1390 reset-names = "phy"; 1391 #phy-cells = <0>; 1392 }; 1393 1394 hiu: bus@3c000 { 1395 compatible = "simple-bus"; 1396 reg = <0x0 0x3c000 0x0 0x1400>; 1397 #address-cells = <2>; 1398 #size-cells = <2>; 1399 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1400 1401 hhi: system-controller@0 { 1402 compatible = "amlogic,meson-gx-hhi-sysctrl", 1403 "simple-mfd", "syscon"; 1404 reg = <0 0 0 0x400>; 1405 1406 clkc: clock-controller { 1407 compatible = "amlogic,g12a-clkc"; 1408 #clock-cells = <1>; 1409 clocks = <&xtal>; 1410 clock-names = "xtal"; 1411 }; 1412 }; 1413 }; 1414 1415 pdm: audio-controller@40000 { 1416 compatible = "amlogic,g12a-pdm", 1417 "amlogic,axg-pdm"; 1418 reg = <0x0 0x40000 0x0 0x34>; 1419 #sound-dai-cells = <0>; 1420 sound-name-prefix = "PDM"; 1421 clocks = <&clkc_audio AUD_CLKID_PDM>, 1422 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1423 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1424 clock-names = "pclk", "dclk", "sysclk"; 1425 status = "disabled"; 1426 }; 1427 1428 audio: bus@42000 { 1429 compatible = "simple-bus"; 1430 reg = <0x0 0x42000 0x0 0x2000>; 1431 #address-cells = <2>; 1432 #size-cells = <2>; 1433 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1434 1435 clkc_audio: clock-controller@0 { 1436 status = "disabled"; 1437 compatible = "amlogic,g12a-audio-clkc"; 1438 reg = <0x0 0x0 0x0 0xb4>; 1439 #clock-cells = <1>; 1440 1441 clocks = <&clkc CLKID_AUDIO>, 1442 <&clkc CLKID_MPLL0>, 1443 <&clkc CLKID_MPLL1>, 1444 <&clkc CLKID_MPLL2>, 1445 <&clkc CLKID_MPLL3>, 1446 <&clkc CLKID_HIFI_PLL>, 1447 <&clkc CLKID_FCLK_DIV3>, 1448 <&clkc CLKID_FCLK_DIV4>, 1449 <&clkc CLKID_GP0_PLL>; 1450 clock-names = "pclk", 1451 "mst_in0", 1452 "mst_in1", 1453 "mst_in2", 1454 "mst_in3", 1455 "mst_in4", 1456 "mst_in5", 1457 "mst_in6", 1458 "mst_in7"; 1459 1460 resets = <&reset RESET_AUDIO>; 1461 }; 1462 1463 toddr_a: audio-controller@100 { 1464 compatible = "amlogic,g12a-toddr", 1465 "amlogic,axg-toddr"; 1466 reg = <0x0 0x100 0x0 0x1c>; 1467 #sound-dai-cells = <0>; 1468 sound-name-prefix = "TODDR_A"; 1469 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1470 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1471 resets = <&arb AXG_ARB_TODDR_A>; 1472 status = "disabled"; 1473 }; 1474 1475 toddr_b: audio-controller@140 { 1476 compatible = "amlogic,g12a-toddr", 1477 "amlogic,axg-toddr"; 1478 reg = <0x0 0x140 0x0 0x1c>; 1479 #sound-dai-cells = <0>; 1480 sound-name-prefix = "TODDR_B"; 1481 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1482 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1483 resets = <&arb AXG_ARB_TODDR_B>; 1484 status = "disabled"; 1485 }; 1486 1487 toddr_c: audio-controller@180 { 1488 compatible = "amlogic,g12a-toddr", 1489 "amlogic,axg-toddr"; 1490 reg = <0x0 0x180 0x0 0x1c>; 1491 #sound-dai-cells = <0>; 1492 sound-name-prefix = "TODDR_C"; 1493 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1494 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1495 resets = <&arb AXG_ARB_TODDR_C>; 1496 status = "disabled"; 1497 }; 1498 1499 frddr_a: audio-controller@1c0 { 1500 compatible = "amlogic,g12a-frddr", 1501 "amlogic,axg-frddr"; 1502 reg = <0x0 0x1c0 0x0 0x1c>; 1503 #sound-dai-cells = <0>; 1504 sound-name-prefix = "FRDDR_A"; 1505 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1506 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1507 resets = <&arb AXG_ARB_FRDDR_A>; 1508 status = "disabled"; 1509 }; 1510 1511 frddr_b: audio-controller@200 { 1512 compatible = "amlogic,g12a-frddr", 1513 "amlogic,axg-frddr"; 1514 reg = <0x0 0x200 0x0 0x1c>; 1515 #sound-dai-cells = <0>; 1516 sound-name-prefix = "FRDDR_B"; 1517 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1518 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1519 resets = <&arb AXG_ARB_FRDDR_B>; 1520 status = "disabled"; 1521 }; 1522 1523 frddr_c: audio-controller@240 { 1524 compatible = "amlogic,g12a-frddr", 1525 "amlogic,axg-frddr"; 1526 reg = <0x0 0x240 0x0 0x1c>; 1527 #sound-dai-cells = <0>; 1528 sound-name-prefix = "FRDDR_C"; 1529 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1530 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1531 resets = <&arb AXG_ARB_FRDDR_C>; 1532 status = "disabled"; 1533 }; 1534 1535 arb: reset-controller@280 { 1536 status = "disabled"; 1537 compatible = "amlogic,meson-axg-audio-arb"; 1538 reg = <0x0 0x280 0x0 0x4>; 1539 #reset-cells = <1>; 1540 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1541 }; 1542 1543 tdmin_a: audio-controller@300 { 1544 compatible = "amlogic,g12a-tdmin", 1545 "amlogic,axg-tdmin"; 1546 reg = <0x0 0x300 0x0 0x40>; 1547 sound-name-prefix = "TDMIN_A"; 1548 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1549 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1550 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1551 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1552 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1553 clock-names = "pclk", "sclk", "sclk_sel", 1554 "lrclk", "lrclk_sel"; 1555 status = "disabled"; 1556 }; 1557 1558 tdmin_b: audio-controller@340 { 1559 compatible = "amlogic,g12a-tdmin", 1560 "amlogic,axg-tdmin"; 1561 reg = <0x0 0x340 0x0 0x40>; 1562 sound-name-prefix = "TDMIN_B"; 1563 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1564 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1565 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1566 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1567 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1568 clock-names = "pclk", "sclk", "sclk_sel", 1569 "lrclk", "lrclk_sel"; 1570 status = "disabled"; 1571 }; 1572 1573 tdmin_c: audio-controller@380 { 1574 compatible = "amlogic,g12a-tdmin", 1575 "amlogic,axg-tdmin"; 1576 reg = <0x0 0x380 0x0 0x40>; 1577 sound-name-prefix = "TDMIN_C"; 1578 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1579 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1580 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1581 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1582 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1583 clock-names = "pclk", "sclk", "sclk_sel", 1584 "lrclk", "lrclk_sel"; 1585 status = "disabled"; 1586 }; 1587 1588 tdmin_lb: audio-controller@3c0 { 1589 compatible = "amlogic,g12a-tdmin", 1590 "amlogic,axg-tdmin"; 1591 reg = <0x0 0x3c0 0x0 0x40>; 1592 sound-name-prefix = "TDMIN_LB"; 1593 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1594 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1595 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1596 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1597 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1598 clock-names = "pclk", "sclk", "sclk_sel", 1599 "lrclk", "lrclk_sel"; 1600 status = "disabled"; 1601 }; 1602 1603 spdifin: audio-controller@400 { 1604 compatible = "amlogic,g12a-spdifin", 1605 "amlogic,axg-spdifin"; 1606 reg = <0x0 0x400 0x0 0x30>; 1607 #sound-dai-cells = <0>; 1608 sound-name-prefix = "SPDIFIN"; 1609 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1610 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1611 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1612 clock-names = "pclk", "refclk"; 1613 status = "disabled"; 1614 }; 1615 1616 spdifout: audio-controller@480 { 1617 compatible = "amlogic,g12a-spdifout", 1618 "amlogic,axg-spdifout"; 1619 reg = <0x0 0x480 0x0 0x50>; 1620 #sound-dai-cells = <0>; 1621 sound-name-prefix = "SPDIFOUT"; 1622 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1623 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1624 clock-names = "pclk", "mclk"; 1625 status = "disabled"; 1626 }; 1627 1628 tdmout_a: audio-controller@500 { 1629 compatible = "amlogic,g12a-tdmout"; 1630 reg = <0x0 0x500 0x0 0x40>; 1631 sound-name-prefix = "TDMOUT_A"; 1632 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1633 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1634 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1635 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1636 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1637 clock-names = "pclk", "sclk", "sclk_sel", 1638 "lrclk", "lrclk_sel"; 1639 status = "disabled"; 1640 }; 1641 1642 tdmout_b: audio-controller@540 { 1643 compatible = "amlogic,g12a-tdmout"; 1644 reg = <0x0 0x540 0x0 0x40>; 1645 sound-name-prefix = "TDMOUT_B"; 1646 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1647 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1648 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1649 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1650 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1651 clock-names = "pclk", "sclk", "sclk_sel", 1652 "lrclk", "lrclk_sel"; 1653 status = "disabled"; 1654 }; 1655 1656 tdmout_c: audio-controller@580 { 1657 compatible = "amlogic,g12a-tdmout"; 1658 reg = <0x0 0x580 0x0 0x40>; 1659 sound-name-prefix = "TDMOUT_C"; 1660 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1661 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1662 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1663 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1664 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1665 clock-names = "pclk", "sclk", "sclk_sel", 1666 "lrclk", "lrclk_sel"; 1667 status = "disabled"; 1668 }; 1669 1670 spdifout_b: audio-controller@680 { 1671 compatible = "amlogic,g12a-spdifout", 1672 "amlogic,axg-spdifout"; 1673 reg = <0x0 0x680 0x0 0x50>; 1674 #sound-dai-cells = <0>; 1675 sound-name-prefix = "SPDIFOUT_B"; 1676 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1677 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1678 clock-names = "pclk", "mclk"; 1679 status = "disabled"; 1680 }; 1681 1682 tohdmitx: audio-controller@744 { 1683 compatible = "amlogic,g12a-tohdmitx"; 1684 reg = <0x0 0x744 0x0 0x4>; 1685 #sound-dai-cells = <1>; 1686 sound-name-prefix = "TOHDMITX"; 1687 status = "disabled"; 1688 }; 1689 }; 1690 1691 usb3_pcie_phy: phy@46000 { 1692 compatible = "amlogic,g12a-usb3-pcie-phy"; 1693 reg = <0x0 0x46000 0x0 0x2000>; 1694 clocks = <&clkc CLKID_PCIE_PLL>; 1695 clock-names = "ref_clk"; 1696 resets = <&reset RESET_PCIE_PHY>; 1697 reset-names = "phy"; 1698 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1699 assigned-clock-rates = <100000000>; 1700 #phy-cells = <1>; 1701 }; 1702 1703 eth_phy: mdio-multiplexer@4c000 { 1704 compatible = "amlogic,g12a-mdio-mux"; 1705 reg = <0x0 0x4c000 0x0 0xa4>; 1706 clocks = <&clkc CLKID_ETH_PHY>, 1707 <&xtal>, 1708 <&clkc CLKID_MPLL_50M>; 1709 clock-names = "pclk", "clkin0", "clkin1"; 1710 mdio-parent-bus = <&mdio0>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 ext_mdio: mdio@0 { 1715 reg = <0>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 }; 1719 1720 int_mdio: mdio@1 { 1721 reg = <1>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 1725 internal_ephy: ethernet_phy@8 { 1726 compatible = "ethernet-phy-id0180.3301", 1727 "ethernet-phy-ieee802.3-c22"; 1728 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1729 reg = <8>; 1730 max-speed = <100>; 1731 }; 1732 }; 1733 }; 1734 }; 1735 1736 aobus: bus@ff800000 { 1737 compatible = "simple-bus"; 1738 reg = <0x0 0xff800000 0x0 0x100000>; 1739 #address-cells = <2>; 1740 #size-cells = <2>; 1741 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1742 1743 rti: sys-ctrl@0 { 1744 compatible = "amlogic,meson-gx-ao-sysctrl", 1745 "simple-mfd", "syscon"; 1746 reg = <0x0 0x0 0x0 0x100>; 1747 #address-cells = <2>; 1748 #size-cells = <2>; 1749 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1750 1751 clkc_AO: clock-controller { 1752 compatible = "amlogic,meson-g12a-aoclkc"; 1753 #clock-cells = <1>; 1754 #reset-cells = <1>; 1755 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1756 clock-names = "xtal", "mpeg-clk"; 1757 }; 1758 1759 pwrc_vpu: power-controller-vpu { 1760 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1761 #power-domain-cells = <0>; 1762 amlogic,hhi-sysctrl = <&hhi>; 1763 resets = <&reset RESET_VIU>, 1764 <&reset RESET_VENC>, 1765 <&reset RESET_VCBUS>, 1766 <&reset RESET_BT656>, 1767 <&reset RESET_RDMA>, 1768 <&reset RESET_VENCI>, 1769 <&reset RESET_VENCP>, 1770 <&reset RESET_VDAC>, 1771 <&reset RESET_VDI6>, 1772 <&reset RESET_VENCL>, 1773 <&reset RESET_VID_LOCK>; 1774 clocks = <&clkc CLKID_VPU>, 1775 <&clkc CLKID_VAPB>; 1776 clock-names = "vpu", "vapb"; 1777 /* 1778 * VPU clocking is provided by two identical clock paths 1779 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1780 * free mux to safely change frequency while running. 1781 * Same for VAPB but with a final gate after the glitch free mux. 1782 */ 1783 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1784 <&clkc CLKID_VPU_0>, 1785 <&clkc CLKID_VPU>, /* Glitch free mux */ 1786 <&clkc CLKID_VAPB_0_SEL>, 1787 <&clkc CLKID_VAPB_0>, 1788 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1789 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1790 <0>, /* Do Nothing */ 1791 <&clkc CLKID_VPU_0>, 1792 <&clkc CLKID_FCLK_DIV4>, 1793 <0>, /* Do Nothing */ 1794 <&clkc CLKID_VAPB_0>; 1795 assigned-clock-rates = <0>, /* Do Nothing */ 1796 <666666666>, 1797 <0>, /* Do Nothing */ 1798 <0>, /* Do Nothing */ 1799 <250000000>, 1800 <0>; /* Do Nothing */ 1801 }; 1802 1803 ao_pinctrl: pinctrl@14 { 1804 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1805 #address-cells = <2>; 1806 #size-cells = <2>; 1807 ranges; 1808 1809 gpio_ao: bank@14 { 1810 reg = <0x0 0x14 0x0 0x8>, 1811 <0x0 0x1c 0x0 0x8>, 1812 <0x0 0x24 0x0 0x14>; 1813 reg-names = "mux", 1814 "ds", 1815 "gpio"; 1816 gpio-controller; 1817 #gpio-cells = <2>; 1818 gpio-ranges = <&ao_pinctrl 0 0 15>; 1819 }; 1820 1821 i2c_ao_sck_pins: i2c_ao_sck_pins { 1822 mux { 1823 groups = "i2c_ao_sck"; 1824 function = "i2c_ao"; 1825 bias-disable; 1826 drive-strength-microamp = <3000>; 1827 }; 1828 }; 1829 1830 i2c_ao_sda_pins: i2c_ao_sda { 1831 mux { 1832 groups = "i2c_ao_sda"; 1833 function = "i2c_ao"; 1834 bias-disable; 1835 drive-strength-microamp = <3000>; 1836 }; 1837 }; 1838 1839 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1840 mux { 1841 groups = "i2c_ao_sck_e"; 1842 function = "i2c_ao"; 1843 bias-disable; 1844 drive-strength-microamp = <3000>; 1845 }; 1846 }; 1847 1848 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1849 mux { 1850 groups = "i2c_ao_sda_e"; 1851 function = "i2c_ao"; 1852 bias-disable; 1853 drive-strength-microamp = <3000>; 1854 }; 1855 }; 1856 1857 mclk0_ao_pins: mclk0-ao { 1858 mux { 1859 groups = "mclk0_ao"; 1860 function = "mclk0_ao"; 1861 bias-disable; 1862 drive-strength-microamp = <3000>; 1863 }; 1864 }; 1865 1866 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1867 mux { 1868 groups = "tdm_ao_b_din0"; 1869 function = "tdm_ao_b"; 1870 bias-disable; 1871 }; 1872 }; 1873 1874 spdif_ao_out_pins: spdif-ao-out { 1875 mux { 1876 groups = "spdif_ao_out"; 1877 function = "spdif_ao_out"; 1878 drive-strength-microamp = <500>; 1879 bias-disable; 1880 }; 1881 }; 1882 1883 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1884 mux { 1885 groups = "tdm_ao_b_din1"; 1886 function = "tdm_ao_b"; 1887 bias-disable; 1888 }; 1889 }; 1890 1891 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1892 mux { 1893 groups = "tdm_ao_b_din2"; 1894 function = "tdm_ao_b"; 1895 bias-disable; 1896 }; 1897 }; 1898 1899 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1900 mux { 1901 groups = "tdm_ao_b_dout0"; 1902 function = "tdm_ao_b"; 1903 bias-disable; 1904 drive-strength-microamp = <3000>; 1905 }; 1906 }; 1907 1908 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1909 mux { 1910 groups = "tdm_ao_b_dout1"; 1911 function = "tdm_ao_b"; 1912 bias-disable; 1913 drive-strength-microamp = <3000>; 1914 }; 1915 }; 1916 1917 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1918 mux { 1919 groups = "tdm_ao_b_dout2"; 1920 function = "tdm_ao_b"; 1921 bias-disable; 1922 drive-strength-microamp = <3000>; 1923 }; 1924 }; 1925 1926 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1927 mux { 1928 groups = "tdm_ao_b_fs"; 1929 function = "tdm_ao_b"; 1930 bias-disable; 1931 drive-strength-microamp = <3000>; 1932 }; 1933 }; 1934 1935 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1936 mux { 1937 groups = "tdm_ao_b_sclk"; 1938 function = "tdm_ao_b"; 1939 bias-disable; 1940 drive-strength-microamp = <3000>; 1941 }; 1942 }; 1943 1944 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1945 mux { 1946 groups = "tdm_ao_b_slv_fs"; 1947 function = "tdm_ao_b"; 1948 bias-disable; 1949 }; 1950 }; 1951 1952 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1953 mux { 1954 groups = "tdm_ao_b_slv_sclk"; 1955 function = "tdm_ao_b"; 1956 bias-disable; 1957 }; 1958 }; 1959 1960 uart_ao_a_pins: uart-a-ao { 1961 mux { 1962 groups = "uart_ao_a_tx", 1963 "uart_ao_a_rx"; 1964 function = "uart_ao_a"; 1965 bias-disable; 1966 }; 1967 }; 1968 1969 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1970 mux { 1971 groups = "uart_ao_a_cts", 1972 "uart_ao_a_rts"; 1973 function = "uart_ao_a"; 1974 bias-disable; 1975 }; 1976 }; 1977 1978 pwm_ao_a_pins: pwm-ao-a { 1979 mux { 1980 groups = "pwm_ao_a"; 1981 function = "pwm_ao_a"; 1982 bias-disable; 1983 }; 1984 }; 1985 1986 pwm_ao_b_pins: pwm-ao-b { 1987 mux { 1988 groups = "pwm_ao_b"; 1989 function = "pwm_ao_b"; 1990 bias-disable; 1991 }; 1992 }; 1993 1994 pwm_ao_c_4_pins: pwm-ao-c-4 { 1995 mux { 1996 groups = "pwm_ao_c_4"; 1997 function = "pwm_ao_c"; 1998 bias-disable; 1999 }; 2000 }; 2001 2002 pwm_ao_c_6_pins: pwm-ao-c-6 { 2003 mux { 2004 groups = "pwm_ao_c_6"; 2005 function = "pwm_ao_c"; 2006 bias-disable; 2007 }; 2008 }; 2009 2010 pwm_ao_d_5_pins: pwm-ao-d-5 { 2011 mux { 2012 groups = "pwm_ao_d_5"; 2013 function = "pwm_ao_d"; 2014 bias-disable; 2015 }; 2016 }; 2017 2018 pwm_ao_d_10_pins: pwm-ao-d-10 { 2019 mux { 2020 groups = "pwm_ao_d_10"; 2021 function = "pwm_ao_d"; 2022 bias-disable; 2023 }; 2024 }; 2025 2026 pwm_ao_d_e_pins: pwm-ao-d-e { 2027 mux { 2028 groups = "pwm_ao_d_e"; 2029 function = "pwm_ao_d"; 2030 }; 2031 }; 2032 2033 remote_input_ao_pins: remote-input-ao { 2034 mux { 2035 groups = "remote_ao_input"; 2036 function = "remote_ao_input"; 2037 bias-disable; 2038 }; 2039 }; 2040 }; 2041 }; 2042 2043 cec_AO: cec@100 { 2044 compatible = "amlogic,meson-gx-ao-cec"; 2045 reg = <0x0 0x00100 0x0 0x14>; 2046 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2047 clocks = <&clkc_AO CLKID_AO_CEC>; 2048 clock-names = "core"; 2049 status = "disabled"; 2050 }; 2051 2052 sec_AO: ao-secure@140 { 2053 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2054 reg = <0x0 0x140 0x0 0x140>; 2055 amlogic,has-chip-id; 2056 }; 2057 2058 cecb_AO: cec@280 { 2059 compatible = "amlogic,meson-g12a-ao-cec"; 2060 reg = <0x0 0x00280 0x0 0x1c>; 2061 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2062 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2063 clock-names = "oscin"; 2064 status = "disabled"; 2065 }; 2066 2067 pwm_AO_cd: pwm@2000 { 2068 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2069 reg = <0x0 0x2000 0x0 0x20>; 2070 #pwm-cells = <3>; 2071 status = "disabled"; 2072 }; 2073 2074 uart_AO: serial@3000 { 2075 compatible = "amlogic,meson-gx-uart", 2076 "amlogic,meson-ao-uart"; 2077 reg = <0x0 0x3000 0x0 0x18>; 2078 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2079 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2080 clock-names = "xtal", "pclk", "baud"; 2081 status = "disabled"; 2082 }; 2083 2084 uart_AO_B: serial@4000 { 2085 compatible = "amlogic,meson-gx-uart", 2086 "amlogic,meson-ao-uart"; 2087 reg = <0x0 0x4000 0x0 0x18>; 2088 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2089 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2090 clock-names = "xtal", "pclk", "baud"; 2091 status = "disabled"; 2092 }; 2093 2094 i2c_AO: i2c@5000 { 2095 compatible = "amlogic,meson-axg-i2c"; 2096 status = "disabled"; 2097 reg = <0x0 0x05000 0x0 0x20>; 2098 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2099 #address-cells = <1>; 2100 #size-cells = <0>; 2101 clocks = <&clkc CLKID_I2C>; 2102 }; 2103 2104 pwm_AO_ab: pwm@7000 { 2105 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2106 reg = <0x0 0x7000 0x0 0x20>; 2107 #pwm-cells = <3>; 2108 status = "disabled"; 2109 }; 2110 2111 ir: ir@8000 { 2112 compatible = "amlogic,meson-gxbb-ir"; 2113 reg = <0x0 0x8000 0x0 0x20>; 2114 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2115 status = "disabled"; 2116 }; 2117 2118 saradc: adc@9000 { 2119 compatible = "amlogic,meson-g12a-saradc", 2120 "amlogic,meson-saradc"; 2121 reg = <0x0 0x9000 0x0 0x48>; 2122 #io-channel-cells = <1>; 2123 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2124 clocks = <&xtal>, 2125 <&clkc_AO CLKID_AO_SAR_ADC>, 2126 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2127 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2128 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2129 status = "disabled"; 2130 }; 2131 }; 2132 2133 vpu: vpu@ff900000 { 2134 compatible = "amlogic,meson-g12a-vpu"; 2135 reg = <0x0 0xff900000 0x0 0x100000>, 2136 <0x0 0xff63c000 0x0 0x1000>; 2137 reg-names = "vpu", "hhi"; 2138 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 amlogic,canvas = <&canvas>; 2142 power-domains = <&pwrc_vpu>; 2143 2144 /* CVBS VDAC output port */ 2145 cvbs_vdac_port: port@0 { 2146 reg = <0>; 2147 }; 2148 2149 /* HDMI-TX output port */ 2150 hdmi_tx_port: port@1 { 2151 reg = <1>; 2152 2153 hdmi_tx_out: endpoint { 2154 remote-endpoint = <&hdmi_tx_in>; 2155 }; 2156 }; 2157 }; 2158 2159 gic: interrupt-controller@ffc01000 { 2160 compatible = "arm,gic-400"; 2161 reg = <0x0 0xffc01000 0 0x1000>, 2162 <0x0 0xffc02000 0 0x2000>, 2163 <0x0 0xffc04000 0 0x2000>, 2164 <0x0 0xffc06000 0 0x2000>; 2165 interrupt-controller; 2166 interrupts = <GIC_PPI 9 2167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2168 #interrupt-cells = <3>; 2169 #address-cells = <0>; 2170 }; 2171 2172 cbus: bus@ffd00000 { 2173 compatible = "simple-bus"; 2174 reg = <0x0 0xffd00000 0x0 0x100000>; 2175 #address-cells = <2>; 2176 #size-cells = <2>; 2177 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2178 2179 reset: reset-controller@1004 { 2180 compatible = "amlogic,meson-g12a-reset", 2181 "amlogic,meson-axg-reset"; 2182 reg = <0x0 0x1004 0x0 0x9c>; 2183 #reset-cells = <1>; 2184 }; 2185 2186 pwm_ef: pwm@19000 { 2187 compatible = "amlogic,meson-g12a-ee-pwm"; 2188 reg = <0x0 0x19000 0x0 0x20>; 2189 #pwm-cells = <3>; 2190 status = "disabled"; 2191 }; 2192 2193 pwm_cd: pwm@1a000 { 2194 compatible = "amlogic,meson-g12a-ee-pwm"; 2195 reg = <0x0 0x1a000 0x0 0x20>; 2196 #pwm-cells = <3>; 2197 status = "disabled"; 2198 }; 2199 2200 pwm_ab: pwm@1b000 { 2201 compatible = "amlogic,meson-g12a-ee-pwm"; 2202 reg = <0x0 0x1b000 0x0 0x20>; 2203 #pwm-cells = <3>; 2204 status = "disabled"; 2205 }; 2206 2207 i2c3: i2c@1c000 { 2208 compatible = "amlogic,meson-axg-i2c"; 2209 status = "disabled"; 2210 reg = <0x0 0x1c000 0x0 0x20>; 2211 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2212 #address-cells = <1>; 2213 #size-cells = <0>; 2214 clocks = <&clkc CLKID_I2C>; 2215 }; 2216 2217 i2c2: i2c@1d000 { 2218 compatible = "amlogic,meson-axg-i2c"; 2219 status = "disabled"; 2220 reg = <0x0 0x1d000 0x0 0x20>; 2221 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2222 #address-cells = <1>; 2223 #size-cells = <0>; 2224 clocks = <&clkc CLKID_I2C>; 2225 }; 2226 2227 i2c1: i2c@1e000 { 2228 compatible = "amlogic,meson-axg-i2c"; 2229 status = "disabled"; 2230 reg = <0x0 0x1e000 0x0 0x20>; 2231 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 clocks = <&clkc CLKID_I2C>; 2235 }; 2236 2237 i2c0: i2c@1f000 { 2238 compatible = "amlogic,meson-axg-i2c"; 2239 status = "disabled"; 2240 reg = <0x0 0x1f000 0x0 0x20>; 2241 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2242 #address-cells = <1>; 2243 #size-cells = <0>; 2244 clocks = <&clkc CLKID_I2C>; 2245 }; 2246 2247 clk_msr: clock-measure@18000 { 2248 compatible = "amlogic,meson-g12a-clk-measure"; 2249 reg = <0x0 0x18000 0x0 0x10>; 2250 }; 2251 2252 uart_C: serial@22000 { 2253 compatible = "amlogic,meson-gx-uart"; 2254 reg = <0x0 0x22000 0x0 0x18>; 2255 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2256 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2257 clock-names = "xtal", "pclk", "baud"; 2258 status = "disabled"; 2259 }; 2260 2261 uart_B: serial@23000 { 2262 compatible = "amlogic,meson-gx-uart"; 2263 reg = <0x0 0x23000 0x0 0x18>; 2264 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2265 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2266 clock-names = "xtal", "pclk", "baud"; 2267 status = "disabled"; 2268 }; 2269 2270 uart_A: serial@24000 { 2271 compatible = "amlogic,meson-gx-uart"; 2272 reg = <0x0 0x24000 0x0 0x18>; 2273 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2274 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2275 clock-names = "xtal", "pclk", "baud"; 2276 status = "disabled"; 2277 }; 2278 }; 2279 2280 sd_emmc_b: sd@ffe05000 { 2281 compatible = "amlogic,meson-axg-mmc"; 2282 reg = <0x0 0xffe05000 0x0 0x800>; 2283 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2284 status = "disabled"; 2285 clocks = <&clkc CLKID_SD_EMMC_B>, 2286 <&clkc CLKID_SD_EMMC_B_CLK0>, 2287 <&clkc CLKID_FCLK_DIV2>; 2288 clock-names = "core", "clkin0", "clkin1"; 2289 resets = <&reset RESET_SD_EMMC_B>; 2290 }; 2291 2292 sd_emmc_c: mmc@ffe07000 { 2293 compatible = "amlogic,meson-axg-mmc"; 2294 reg = <0x0 0xffe07000 0x0 0x800>; 2295 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2296 status = "disabled"; 2297 clocks = <&clkc CLKID_SD_EMMC_C>, 2298 <&clkc CLKID_SD_EMMC_C_CLK0>, 2299 <&clkc CLKID_FCLK_DIV2>; 2300 clock-names = "core", "clkin0", "clkin1"; 2301 resets = <&reset RESET_SD_EMMC_C>; 2302 }; 2303 2304 usb: usb@ffe09000 { 2305 status = "disabled"; 2306 compatible = "amlogic,meson-g12a-usb-ctrl"; 2307 reg = <0x0 0xffe09000 0x0 0xa0>; 2308 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2309 #address-cells = <2>; 2310 #size-cells = <2>; 2311 ranges; 2312 2313 clocks = <&clkc CLKID_USB>; 2314 resets = <&reset RESET_USB>; 2315 2316 dr_mode = "otg"; 2317 2318 phys = <&usb2_phy0>, <&usb2_phy1>, 2319 <&usb3_pcie_phy PHY_TYPE_USB3>; 2320 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2321 2322 dwc2: usb@ff400000 { 2323 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2324 reg = <0x0 0xff400000 0x0 0x40000>; 2325 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2327 clock-names = "ddr"; 2328 phys = <&usb2_phy1>; 2329 dr_mode = "peripheral"; 2330 g-rx-fifo-size = <192>; 2331 g-np-tx-fifo-size = <128>; 2332 g-tx-fifo-size = <128 128 16 16 16>; 2333 }; 2334 2335 dwc3: usb@ff500000 { 2336 compatible = "snps,dwc3"; 2337 reg = <0x0 0xff500000 0x0 0x100000>; 2338 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2339 dr_mode = "host"; 2340 snps,dis_u2_susphy_quirk; 2341 snps,quirk-frame-length-adjustment; 2342 }; 2343 }; 2344 2345 mali: gpu@ffe40000 { 2346 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2347 reg = <0x0 0xffe40000 0x0 0x40000>; 2348 interrupt-parent = <&gic>; 2349 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2352 interrupt-names = "gpu", "mmu", "job"; 2353 clocks = <&clkc CLKID_MALI>; 2354 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2355 2356 /* 2357 * Mali clocking is provided by two identical clock paths 2358 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2359 * free mux to safely change frequency while running. 2360 */ 2361 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2362 <&clkc CLKID_MALI_0>, 2363 <&clkc CLKID_MALI>; /* Glitch free mux */ 2364 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2365 <0>, /* Do Nothing */ 2366 <&clkc CLKID_MALI_0>; 2367 assigned-clock-rates = <0>, /* Do Nothing */ 2368 <800000000>, 2369 <0>; /* Do Nothing */ 2370 }; 2371 }; 2372 2373 timer { 2374 compatible = "arm,armv8-timer"; 2375 interrupts = <GIC_PPI 13 2376 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2377 <GIC_PPI 14 2378 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2379 <GIC_PPI 11 2380 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2381 <GIC_PPI 10 2382 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2383 }; 2384 2385 xtal: xtal-clk { 2386 compatible = "fixed-clock"; 2387 clock-frequency = <24000000>; 2388 clock-output-names = "xtal"; 2389 #clock-cells = <0>; 2390 }; 2391 2392}; 2393