1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 ethmac: ethernet@ff3f0000 { 141 compatible = "amlogic,meson-axg-dwmac", 142 "snps,dwmac-3.70a", 143 "snps,dwmac"; 144 reg = <0x0 0xff3f0000 0x0 0x10000 145 0x0 0xff634540 0x0 0x8>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "macirq"; 148 clocks = <&clkc CLKID_ETH>, 149 <&clkc CLKID_FCLK_DIV2>, 150 <&clkc CLKID_MPLL2>; 151 clock-names = "stmmaceth", "clkin0", "clkin1"; 152 status = "disabled"; 153 154 mdio0: mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "snps,dwmac-mdio"; 158 }; 159 }; 160 161 apb: bus@ff600000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xff600000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 167 168 hdmi_tx: hdmi-tx@0 { 169 compatible = "amlogic,meson-g12a-dw-hdmi"; 170 reg = <0x0 0x0 0x0 0x10000>; 171 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 172 resets = <&reset RESET_HDMITX_CAPB3>, 173 <&reset RESET_HDMITX_PHY>, 174 <&reset RESET_HDMITX>; 175 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 176 clocks = <&clkc CLKID_HDMI>, 177 <&clkc CLKID_HTX_PCLK>, 178 <&clkc CLKID_VPU_INTR>; 179 clock-names = "isfr", "iahb", "venci"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 185 /* VPU VENC Input */ 186 hdmi_tx_venc_port: port@0 { 187 reg = <0>; 188 189 hdmi_tx_in: endpoint { 190 remote-endpoint = <&hdmi_tx_out>; 191 }; 192 }; 193 194 /* TMDS Output */ 195 hdmi_tx_tmds_port: port@1 { 196 reg = <1>; 197 }; 198 }; 199 200 periphs: bus@34400 { 201 compatible = "simple-bus"; 202 reg = <0x0 0x34400 0x0 0x400>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 206 207 periphs_pinctrl: pinctrl@40 { 208 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges; 212 213 gpio: bank@40 { 214 reg = <0x0 0x40 0x0 0x4c>, 215 <0x0 0xe8 0x0 0x18>, 216 <0x0 0x120 0x0 0x18>, 217 <0x0 0x2c0 0x0 0x40>, 218 <0x0 0x340 0x0 0x1c>; 219 reg-names = "gpio", 220 "pull", 221 "pull-enable", 222 "mux", 223 "ds"; 224 gpio-controller; 225 #gpio-cells = <2>; 226 gpio-ranges = <&periphs_pinctrl 0 0 86>; 227 }; 228 229 cec_ao_a_h_pins: cec_ao_a_h { 230 mux { 231 groups = "cec_ao_a_h"; 232 function = "cec_ao_a_h"; 233 bias-disable; 234 }; 235 }; 236 237 cec_ao_b_h_pins: cec_ao_b_h { 238 mux { 239 groups = "cec_ao_b_h"; 240 function = "cec_ao_b_h"; 241 bias-disable; 242 }; 243 }; 244 245 emmc_pins: emmc { 246 mux-0 { 247 groups = "emmc_nand_d0", 248 "emmc_nand_d1", 249 "emmc_nand_d2", 250 "emmc_nand_d3", 251 "emmc_nand_d4", 252 "emmc_nand_d5", 253 "emmc_nand_d6", 254 "emmc_nand_d7", 255 "emmc_cmd"; 256 function = "emmc"; 257 bias-pull-up; 258 drive-strength-microamp = <4000>; 259 }; 260 261 mux-1 { 262 groups = "emmc_clk"; 263 function = "emmc"; 264 bias-disable; 265 drive-strength-microamp = <4000>; 266 }; 267 }; 268 269 emmc_ds_pins: emmc-ds { 270 mux { 271 groups = "emmc_nand_ds"; 272 function = "emmc"; 273 bias-pull-down; 274 drive-strength-microamp = <4000>; 275 }; 276 }; 277 278 emmc_clk_gate_pins: emmc_clk_gate { 279 mux { 280 groups = "BOOT_8"; 281 function = "gpio_periphs"; 282 bias-pull-down; 283 drive-strength-microamp = <4000>; 284 }; 285 }; 286 287 hdmitx_ddc_pins: hdmitx_ddc { 288 mux { 289 groups = "hdmitx_sda", 290 "hdmitx_sck"; 291 function = "hdmitx"; 292 bias-disable; 293 drive-strength-microamp = <4000>; 294 }; 295 }; 296 297 hdmitx_hpd_pins: hdmitx_hpd { 298 mux { 299 groups = "hdmitx_hpd_in"; 300 function = "hdmitx"; 301 bias-disable; 302 }; 303 }; 304 305 306 i2c0_sda_c_pins: i2c0-sda-c { 307 mux { 308 groups = "i2c0_sda_c"; 309 function = "i2c0"; 310 bias-disable; 311 drive-strength-microamp = <3000>; 312 313 }; 314 }; 315 316 i2c0_sck_c_pins: i2c0-sck-c { 317 mux { 318 groups = "i2c0_sck_c"; 319 function = "i2c0"; 320 bias-disable; 321 drive-strength-microamp = <3000>; 322 }; 323 }; 324 325 i2c0_sda_z0_pins: i2c0-sda-z0 { 326 mux { 327 groups = "i2c0_sda_z0"; 328 function = "i2c0"; 329 bias-disable; 330 drive-strength-microamp = <3000>; 331 }; 332 }; 333 334 i2c0_sck_z1_pins: i2c0-sck-z1 { 335 mux { 336 groups = "i2c0_sck_z1"; 337 function = "i2c0"; 338 bias-disable; 339 drive-strength-microamp = <3000>; 340 }; 341 }; 342 343 i2c0_sda_z7_pins: i2c0-sda-z7 { 344 mux { 345 groups = "i2c0_sda_z7"; 346 function = "i2c0"; 347 bias-disable; 348 drive-strength-microamp = <3000>; 349 }; 350 }; 351 352 i2c0_sda_z8_pins: i2c0-sda-z8 { 353 mux { 354 groups = "i2c0_sda_z8"; 355 function = "i2c0"; 356 bias-disable; 357 drive-strength-microamp = <3000>; 358 }; 359 }; 360 361 i2c1_sda_x_pins: i2c1-sda-x { 362 mux { 363 groups = "i2c1_sda_x"; 364 function = "i2c1"; 365 bias-disable; 366 drive-strength-microamp = <3000>; 367 }; 368 }; 369 370 i2c1_sck_x_pins: i2c1-sck-x { 371 mux { 372 groups = "i2c1_sck_x"; 373 function = "i2c1"; 374 bias-disable; 375 drive-strength-microamp = <3000>; 376 }; 377 }; 378 379 i2c1_sda_h2_pins: i2c1-sda-h2 { 380 mux { 381 groups = "i2c1_sda_h2"; 382 function = "i2c1"; 383 bias-disable; 384 drive-strength-microamp = <3000>; 385 }; 386 }; 387 388 i2c1_sck_h3_pins: i2c1-sck-h3 { 389 mux { 390 groups = "i2c1_sck_h3"; 391 function = "i2c1"; 392 bias-disable; 393 drive-strength-microamp = <3000>; 394 }; 395 }; 396 397 i2c1_sda_h6_pins: i2c1-sda-h6 { 398 mux { 399 groups = "i2c1_sda_h6"; 400 function = "i2c1"; 401 bias-disable; 402 drive-strength-microamp = <3000>; 403 }; 404 }; 405 406 i2c1_sck_h7_pins: i2c1-sck-h7 { 407 mux { 408 groups = "i2c1_sck_h7"; 409 function = "i2c1"; 410 bias-disable; 411 drive-strength-microamp = <3000>; 412 }; 413 }; 414 415 i2c2_sda_x_pins: i2c2-sda-x { 416 mux { 417 groups = "i2c2_sda_x"; 418 function = "i2c2"; 419 bias-disable; 420 drive-strength-microamp = <3000>; 421 }; 422 }; 423 424 i2c2_sck_x_pins: i2c2-sck-x { 425 mux { 426 groups = "i2c2_sck_x"; 427 function = "i2c2"; 428 bias-disable; 429 drive-strength-microamp = <3000>; 430 }; 431 }; 432 433 i2c2_sda_z_pins: i2c2-sda-z { 434 mux { 435 groups = "i2c2_sda_z"; 436 function = "i2c2"; 437 bias-disable; 438 drive-strength-microamp = <3000>; 439 }; 440 }; 441 442 i2c2_sck_z_pins: i2c2-sck-z { 443 mux { 444 groups = "i2c2_sck_z"; 445 function = "i2c2"; 446 bias-disable; 447 drive-strength-microamp = <3000>; 448 }; 449 }; 450 451 i2c3_sda_h_pins: i2c3-sda-h { 452 mux { 453 groups = "i2c3_sda_h"; 454 function = "i2c3"; 455 bias-disable; 456 drive-strength-microamp = <3000>; 457 }; 458 }; 459 460 i2c3_sck_h_pins: i2c3-sck-h { 461 mux { 462 groups = "i2c3_sck_h"; 463 function = "i2c3"; 464 bias-disable; 465 drive-strength-microamp = <3000>; 466 }; 467 }; 468 469 i2c3_sda_a_pins: i2c3-sda-a { 470 mux { 471 groups = "i2c3_sda_a"; 472 function = "i2c3"; 473 bias-disable; 474 drive-strength-microamp = <3000>; 475 }; 476 }; 477 478 i2c3_sck_a_pins: i2c3-sck-a { 479 mux { 480 groups = "i2c3_sck_a"; 481 function = "i2c3"; 482 bias-disable; 483 drive-strength-microamp = <3000>; 484 }; 485 }; 486 487 mclk0_a_pins: mclk0-a { 488 mux { 489 groups = "mclk0_a"; 490 function = "mclk0"; 491 bias-disable; 492 drive-strength-microamp = <3000>; 493 }; 494 }; 495 496 mclk1_a_pins: mclk1-a { 497 mux { 498 groups = "mclk1_a"; 499 function = "mclk1"; 500 bias-disable; 501 drive-strength-microamp = <3000>; 502 }; 503 }; 504 505 mclk1_x_pins: mclk1-x { 506 mux { 507 groups = "mclk1_x"; 508 function = "mclk1"; 509 bias-disable; 510 drive-strength-microamp = <3000>; 511 }; 512 }; 513 514 mclk1_z_pins: mclk1-z { 515 mux { 516 groups = "mclk1_z"; 517 function = "mclk1"; 518 bias-disable; 519 drive-strength-microamp = <3000>; 520 }; 521 }; 522 523 pdm_din0_a_pins: pdm-din0-a { 524 mux { 525 groups = "pdm_din0_a"; 526 function = "pdm"; 527 bias-disable; 528 }; 529 }; 530 531 pdm_din0_c_pins: pdm-din0-c { 532 mux { 533 groups = "pdm_din0_c"; 534 function = "pdm"; 535 bias-disable; 536 }; 537 }; 538 539 pdm_din0_x_pins: pdm-din0-x { 540 mux { 541 groups = "pdm_din0_x"; 542 function = "pdm"; 543 bias-disable; 544 }; 545 }; 546 547 pdm_din0_z_pins: pdm-din0-z { 548 mux { 549 groups = "pdm_din0_z"; 550 function = "pdm"; 551 bias-disable; 552 }; 553 }; 554 555 pdm_din1_a_pins: pdm-din1-a { 556 mux { 557 groups = "pdm_din1_a"; 558 function = "pdm"; 559 bias-disable; 560 }; 561 }; 562 563 pdm_din1_c_pins: pdm-din1-c { 564 mux { 565 groups = "pdm_din1_c"; 566 function = "pdm"; 567 bias-disable; 568 }; 569 }; 570 571 pdm_din1_x_pins: pdm-din1-x { 572 mux { 573 groups = "pdm_din1_x"; 574 function = "pdm"; 575 bias-disable; 576 }; 577 }; 578 579 pdm_din1_z_pins: pdm-din1-z { 580 mux { 581 groups = "pdm_din1_z"; 582 function = "pdm"; 583 bias-disable; 584 }; 585 }; 586 587 pdm_din2_a_pins: pdm-din2-a { 588 mux { 589 groups = "pdm_din2_a"; 590 function = "pdm"; 591 bias-disable; 592 }; 593 }; 594 595 pdm_din2_c_pins: pdm-din2-c { 596 mux { 597 groups = "pdm_din2_c"; 598 function = "pdm"; 599 bias-disable; 600 }; 601 }; 602 603 pdm_din2_x_pins: pdm-din2-x { 604 mux { 605 groups = "pdm_din2_x"; 606 function = "pdm"; 607 bias-disable; 608 }; 609 }; 610 611 pdm_din2_z_pins: pdm-din2-z { 612 mux { 613 groups = "pdm_din2_z"; 614 function = "pdm"; 615 bias-disable; 616 }; 617 }; 618 619 pdm_din3_a_pins: pdm-din3-a { 620 mux { 621 groups = "pdm_din3_a"; 622 function = "pdm"; 623 bias-disable; 624 }; 625 }; 626 627 pdm_din3_c_pins: pdm-din3-c { 628 mux { 629 groups = "pdm_din3_c"; 630 function = "pdm"; 631 bias-disable; 632 }; 633 }; 634 635 pdm_din3_x_pins: pdm-din3-x { 636 mux { 637 groups = "pdm_din3_x"; 638 function = "pdm"; 639 bias-disable; 640 }; 641 }; 642 643 pdm_din3_z_pins: pdm-din3-z { 644 mux { 645 groups = "pdm_din3_z"; 646 function = "pdm"; 647 bias-disable; 648 }; 649 }; 650 651 pdm_dclk_a_pins: pdm-dclk-a { 652 mux { 653 groups = "pdm_dclk_a"; 654 function = "pdm"; 655 bias-disable; 656 drive-strength-microamp = <500>; 657 }; 658 }; 659 660 pdm_dclk_c_pins: pdm-dclk-c { 661 mux { 662 groups = "pdm_dclk_c"; 663 function = "pdm"; 664 bias-disable; 665 drive-strength-microamp = <500>; 666 }; 667 }; 668 669 pdm_dclk_x_pins: pdm-dclk-x { 670 mux { 671 groups = "pdm_dclk_x"; 672 function = "pdm"; 673 bias-disable; 674 drive-strength-microamp = <500>; 675 }; 676 }; 677 678 pdm_dclk_z_pins: pdm-dclk-z { 679 mux { 680 groups = "pdm_dclk_z"; 681 function = "pdm"; 682 bias-disable; 683 drive-strength-microamp = <500>; 684 }; 685 }; 686 687 pwm_a_pins: pwm-a { 688 mux { 689 groups = "pwm_a"; 690 function = "pwm_a"; 691 bias-disable; 692 }; 693 }; 694 695 pwm_b_x7_pins: pwm-b-x7 { 696 mux { 697 groups = "pwm_b_x7"; 698 function = "pwm_b"; 699 bias-disable; 700 }; 701 }; 702 703 pwm_b_x19_pins: pwm-b-x19 { 704 mux { 705 groups = "pwm_b_x19"; 706 function = "pwm_b"; 707 bias-disable; 708 }; 709 }; 710 711 pwm_c_c_pins: pwm-c-c { 712 mux { 713 groups = "pwm_c_c"; 714 function = "pwm_c"; 715 bias-disable; 716 }; 717 }; 718 719 pwm_c_x5_pins: pwm-c-x5 { 720 mux { 721 groups = "pwm_c_x5"; 722 function = "pwm_c"; 723 bias-disable; 724 }; 725 }; 726 727 pwm_c_x8_pins: pwm-c-x8 { 728 mux { 729 groups = "pwm_c_x8"; 730 function = "pwm_c"; 731 bias-disable; 732 }; 733 }; 734 735 pwm_d_x3_pins: pwm-d-x3 { 736 mux { 737 groups = "pwm_d_x3"; 738 function = "pwm_d"; 739 bias-disable; 740 }; 741 }; 742 743 pwm_d_x6_pins: pwm-d-x6 { 744 mux { 745 groups = "pwm_d_x6"; 746 function = "pwm_d"; 747 bias-disable; 748 }; 749 }; 750 751 pwm_e_pins: pwm-e { 752 mux { 753 groups = "pwm_e"; 754 function = "pwm_e"; 755 bias-disable; 756 }; 757 }; 758 759 pwm_f_x_pins: pwm-f-x { 760 mux { 761 groups = "pwm_f_x"; 762 function = "pwm_f"; 763 bias-disable; 764 }; 765 }; 766 767 pwm_f_h_pins: pwm-f-h { 768 mux { 769 groups = "pwm_f_h"; 770 function = "pwm_f"; 771 bias-disable; 772 }; 773 }; 774 775 sdcard_c_pins: sdcard_c { 776 mux-0 { 777 groups = "sdcard_d0_c", 778 "sdcard_d1_c", 779 "sdcard_d2_c", 780 "sdcard_d3_c", 781 "sdcard_cmd_c"; 782 function = "sdcard"; 783 bias-pull-up; 784 drive-strength-microamp = <4000>; 785 }; 786 787 mux-1 { 788 groups = "sdcard_clk_c"; 789 function = "sdcard"; 790 bias-disable; 791 drive-strength-microamp = <4000>; 792 }; 793 }; 794 795 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 796 mux { 797 groups = "GPIOC_4"; 798 function = "gpio_periphs"; 799 bias-pull-down; 800 drive-strength-microamp = <4000>; 801 }; 802 }; 803 804 sdcard_z_pins: sdcard_z { 805 mux-0 { 806 groups = "sdcard_d0_z", 807 "sdcard_d1_z", 808 "sdcard_d2_z", 809 "sdcard_d3_z", 810 "sdcard_cmd_z"; 811 function = "sdcard"; 812 bias-pull-up; 813 drive-strength-microamp = <4000>; 814 }; 815 816 mux-1 { 817 groups = "sdcard_clk_z"; 818 function = "sdcard"; 819 bias-disable; 820 drive-strength-microamp = <4000>; 821 }; 822 }; 823 824 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 825 mux { 826 groups = "GPIOZ_6"; 827 function = "gpio_periphs"; 828 bias-pull-down; 829 drive-strength-microamp = <4000>; 830 }; 831 }; 832 833 spdif_in_a10_pins: spdif-in-a10 { 834 mux { 835 groups = "spdif_in_a10"; 836 function = "spdif_in"; 837 bias-disable; 838 }; 839 }; 840 841 spdif_in_a12_pins: spdif-in-a12 { 842 mux { 843 groups = "spdif_in_a12"; 844 function = "spdif_in"; 845 bias-disable; 846 }; 847 }; 848 849 spdif_in_h_pins: spdif-in-h { 850 mux { 851 groups = "spdif_in_h"; 852 function = "spdif_in"; 853 bias-disable; 854 }; 855 }; 856 857 spdif_out_h_pins: spdif-out-h { 858 mux { 859 groups = "spdif_out_h"; 860 function = "spdif_out"; 861 drive-strength-microamp = <500>; 862 bias-disable; 863 }; 864 }; 865 866 spdif_out_a11_pins: spdif-out-a11 { 867 mux { 868 groups = "spdif_out_a11"; 869 function = "spdif_out"; 870 drive-strength-microamp = <500>; 871 bias-disable; 872 }; 873 }; 874 875 spdif_out_a13_pins: spdif-out-a13 { 876 mux { 877 groups = "spdif_out_a13"; 878 function = "spdif_out"; 879 drive-strength-microamp = <500>; 880 bias-disable; 881 }; 882 }; 883 884 tdm_a_din0_pins: tdm-a-din0 { 885 mux { 886 groups = "tdm_a_din0"; 887 function = "tdm_a"; 888 bias-disable; 889 }; 890 }; 891 892 893 tdm_a_din1_pins: tdm-a-din1 { 894 mux { 895 groups = "tdm_a_din1"; 896 function = "tdm_a"; 897 bias-disable; 898 }; 899 }; 900 901 tdm_a_dout0_pins: tdm-a-dout0 { 902 mux { 903 groups = "tdm_a_dout0"; 904 function = "tdm_a"; 905 bias-disable; 906 drive-strength-microamp = <3000>; 907 }; 908 }; 909 910 tdm_a_dout1_pins: tdm-a-dout1 { 911 mux { 912 groups = "tdm_a_dout1"; 913 function = "tdm_a"; 914 bias-disable; 915 drive-strength-microamp = <3000>; 916 }; 917 }; 918 919 tdm_a_fs_pins: tdm-a-fs { 920 mux { 921 groups = "tdm_a_fs"; 922 function = "tdm_a"; 923 bias-disable; 924 drive-strength-microamp = <3000>; 925 }; 926 }; 927 928 tdm_a_sclk_pins: tdm-a-sclk { 929 mux { 930 groups = "tdm_a_sclk"; 931 function = "tdm_a"; 932 bias-disable; 933 drive-strength-microamp = <3000>; 934 }; 935 }; 936 937 tdm_a_slv_fs_pins: tdm-a-slv-fs { 938 mux { 939 groups = "tdm_a_slv_fs"; 940 function = "tdm_a"; 941 bias-disable; 942 }; 943 }; 944 945 946 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 947 mux { 948 groups = "tdm_a_slv_sclk"; 949 function = "tdm_a"; 950 bias-disable; 951 }; 952 }; 953 954 tdm_b_din0_pins: tdm-b-din0 { 955 mux { 956 groups = "tdm_b_din0"; 957 function = "tdm_b"; 958 bias-disable; 959 }; 960 }; 961 962 tdm_b_din1_pins: tdm-b-din1 { 963 mux { 964 groups = "tdm_b_din1"; 965 function = "tdm_b"; 966 bias-disable; 967 }; 968 }; 969 970 tdm_b_din2_pins: tdm-b-din2 { 971 mux { 972 groups = "tdm_b_din2"; 973 function = "tdm_b"; 974 bias-disable; 975 }; 976 }; 977 978 tdm_b_din3_a_pins: tdm-b-din3-a { 979 mux { 980 groups = "tdm_b_din3_a"; 981 function = "tdm_b"; 982 bias-disable; 983 }; 984 }; 985 986 tdm_b_din3_h_pins: tdm-b-din3-h { 987 mux { 988 groups = "tdm_b_din3_h"; 989 function = "tdm_b"; 990 bias-disable; 991 }; 992 }; 993 994 tdm_b_dout0_pins: tdm-b-dout0 { 995 mux { 996 groups = "tdm_b_dout0"; 997 function = "tdm_b"; 998 bias-disable; 999 drive-strength-microamp = <3000>; 1000 }; 1001 }; 1002 1003 tdm_b_dout1_pins: tdm-b-dout1 { 1004 mux { 1005 groups = "tdm_b_dout1"; 1006 function = "tdm_b"; 1007 bias-disable; 1008 drive-strength-microamp = <3000>; 1009 }; 1010 }; 1011 1012 tdm_b_dout2_pins: tdm-b-dout2 { 1013 mux { 1014 groups = "tdm_b_dout2"; 1015 function = "tdm_b"; 1016 bias-disable; 1017 drive-strength-microamp = <3000>; 1018 }; 1019 }; 1020 1021 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1022 mux { 1023 groups = "tdm_b_dout3_a"; 1024 function = "tdm_b"; 1025 bias-disable; 1026 drive-strength-microamp = <3000>; 1027 }; 1028 }; 1029 1030 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1031 mux { 1032 groups = "tdm_b_dout3_h"; 1033 function = "tdm_b"; 1034 bias-disable; 1035 drive-strength-microamp = <3000>; 1036 }; 1037 }; 1038 1039 tdm_b_fs_pins: tdm-b-fs { 1040 mux { 1041 groups = "tdm_b_fs"; 1042 function = "tdm_b"; 1043 bias-disable; 1044 drive-strength-microamp = <3000>; 1045 }; 1046 }; 1047 1048 tdm_b_sclk_pins: tdm-b-sclk { 1049 mux { 1050 groups = "tdm_b_sclk"; 1051 function = "tdm_b"; 1052 bias-disable; 1053 drive-strength-microamp = <3000>; 1054 }; 1055 }; 1056 1057 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1058 mux { 1059 groups = "tdm_b_slv_fs"; 1060 function = "tdm_b"; 1061 bias-disable; 1062 }; 1063 }; 1064 1065 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1066 mux { 1067 groups = "tdm_b_slv_sclk"; 1068 function = "tdm_b"; 1069 bias-disable; 1070 }; 1071 }; 1072 1073 tdm_c_din0_a_pins: tdm-c-din0-a { 1074 mux { 1075 groups = "tdm_c_din0_a"; 1076 function = "tdm_c"; 1077 bias-disable; 1078 }; 1079 }; 1080 1081 tdm_c_din0_z_pins: tdm-c-din0-z { 1082 mux { 1083 groups = "tdm_c_din0_z"; 1084 function = "tdm_c"; 1085 bias-disable; 1086 }; 1087 }; 1088 1089 tdm_c_din1_a_pins: tdm-c-din1-a { 1090 mux { 1091 groups = "tdm_c_din1_a"; 1092 function = "tdm_c"; 1093 bias-disable; 1094 }; 1095 }; 1096 1097 tdm_c_din1_z_pins: tdm-c-din1-z { 1098 mux { 1099 groups = "tdm_c_din1_z"; 1100 function = "tdm_c"; 1101 bias-disable; 1102 }; 1103 }; 1104 1105 tdm_c_din2_a_pins: tdm-c-din2-a { 1106 mux { 1107 groups = "tdm_c_din2_a"; 1108 function = "tdm_c"; 1109 bias-disable; 1110 }; 1111 }; 1112 1113 eth_leds_pins: eth-leds { 1114 mux { 1115 groups = "eth_link_led", 1116 "eth_act_led"; 1117 function = "eth"; 1118 bias-disable; 1119 }; 1120 }; 1121 1122 eth_pins: eth { 1123 mux { 1124 groups = "eth_mdio", 1125 "eth_mdc", 1126 "eth_rgmii_rx_clk", 1127 "eth_rx_dv", 1128 "eth_rxd0", 1129 "eth_rxd1", 1130 "eth_txen", 1131 "eth_txd0", 1132 "eth_txd1"; 1133 function = "eth"; 1134 drive-strength-microamp = <4000>; 1135 bias-disable; 1136 }; 1137 }; 1138 1139 eth_rgmii_pins: eth-rgmii { 1140 mux { 1141 groups = "eth_rxd2_rgmii", 1142 "eth_rxd3_rgmii", 1143 "eth_rgmii_tx_clk", 1144 "eth_txd2_rgmii", 1145 "eth_txd3_rgmii"; 1146 function = "eth"; 1147 drive-strength-microamp = <4000>; 1148 bias-disable; 1149 }; 1150 }; 1151 1152 tdm_c_din2_z_pins: tdm-c-din2-z { 1153 mux { 1154 groups = "tdm_c_din2_z"; 1155 function = "tdm_c"; 1156 bias-disable; 1157 }; 1158 }; 1159 1160 tdm_c_din3_a_pins: tdm-c-din3-a { 1161 mux { 1162 groups = "tdm_c_din3_a"; 1163 function = "tdm_c"; 1164 bias-disable; 1165 }; 1166 }; 1167 1168 tdm_c_din3_z_pins: tdm-c-din3-z { 1169 mux { 1170 groups = "tdm_c_din3_z"; 1171 function = "tdm_c"; 1172 bias-disable; 1173 }; 1174 }; 1175 1176 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1177 mux { 1178 groups = "tdm_c_dout0_a"; 1179 function = "tdm_c"; 1180 bias-disable; 1181 drive-strength-microamp = <3000>; 1182 }; 1183 }; 1184 1185 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1186 mux { 1187 groups = "tdm_c_dout0_z"; 1188 function = "tdm_c"; 1189 bias-disable; 1190 drive-strength-microamp = <3000>; 1191 }; 1192 }; 1193 1194 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1195 mux { 1196 groups = "tdm_c_dout1_a"; 1197 function = "tdm_c"; 1198 bias-disable; 1199 drive-strength-microamp = <3000>; 1200 }; 1201 }; 1202 1203 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1204 mux { 1205 groups = "tdm_c_dout1_z"; 1206 function = "tdm_c"; 1207 bias-disable; 1208 drive-strength-microamp = <3000>; 1209 }; 1210 }; 1211 1212 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1213 mux { 1214 groups = "tdm_c_dout2_a"; 1215 function = "tdm_c"; 1216 bias-disable; 1217 drive-strength-microamp = <3000>; 1218 }; 1219 }; 1220 1221 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1222 mux { 1223 groups = "tdm_c_dout2_z"; 1224 function = "tdm_c"; 1225 bias-disable; 1226 drive-strength-microamp = <3000>; 1227 }; 1228 }; 1229 1230 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1231 mux { 1232 groups = "tdm_c_dout3_a"; 1233 function = "tdm_c"; 1234 bias-disable; 1235 drive-strength-microamp = <3000>; 1236 }; 1237 }; 1238 1239 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1240 mux { 1241 groups = "tdm_c_dout3_z"; 1242 function = "tdm_c"; 1243 bias-disable; 1244 drive-strength-microamp = <3000>; 1245 }; 1246 }; 1247 1248 tdm_c_fs_a_pins: tdm-c-fs-a { 1249 mux { 1250 groups = "tdm_c_fs_a"; 1251 function = "tdm_c"; 1252 bias-disable; 1253 drive-strength-microamp = <3000>; 1254 }; 1255 }; 1256 1257 tdm_c_fs_z_pins: tdm-c-fs-z { 1258 mux { 1259 groups = "tdm_c_fs_z"; 1260 function = "tdm_c"; 1261 bias-disable; 1262 drive-strength-microamp = <3000>; 1263 }; 1264 }; 1265 1266 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1267 mux { 1268 groups = "tdm_c_sclk_a"; 1269 function = "tdm_c"; 1270 bias-disable; 1271 drive-strength-microamp = <3000>; 1272 }; 1273 }; 1274 1275 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1276 mux { 1277 groups = "tdm_c_sclk_z"; 1278 function = "tdm_c"; 1279 bias-disable; 1280 drive-strength-microamp = <3000>; 1281 }; 1282 }; 1283 1284 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1285 mux { 1286 groups = "tdm_c_slv_fs_a"; 1287 function = "tdm_c"; 1288 bias-disable; 1289 }; 1290 }; 1291 1292 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1293 mux { 1294 groups = "tdm_c_slv_fs_z"; 1295 function = "tdm_c"; 1296 bias-disable; 1297 }; 1298 }; 1299 1300 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1301 mux { 1302 groups = "tdm_c_slv_sclk_a"; 1303 function = "tdm_c"; 1304 bias-disable; 1305 }; 1306 }; 1307 1308 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1309 mux { 1310 groups = "tdm_c_slv_sclk_z"; 1311 function = "tdm_c"; 1312 bias-disable; 1313 }; 1314 }; 1315 1316 uart_a_pins: uart-a { 1317 mux { 1318 groups = "uart_a_tx", 1319 "uart_a_rx"; 1320 function = "uart_a"; 1321 bias-disable; 1322 }; 1323 }; 1324 1325 uart_a_cts_rts_pins: uart-a-cts-rts { 1326 mux { 1327 groups = "uart_a_cts", 1328 "uart_a_rts"; 1329 function = "uart_a"; 1330 bias-disable; 1331 }; 1332 }; 1333 1334 uart_b_pins: uart-b { 1335 mux { 1336 groups = "uart_b_tx", 1337 "uart_b_rx"; 1338 function = "uart_b"; 1339 bias-disable; 1340 }; 1341 }; 1342 1343 uart_c_pins: uart-c { 1344 mux { 1345 groups = "uart_c_tx", 1346 "uart_c_rx"; 1347 function = "uart_c"; 1348 bias-disable; 1349 }; 1350 }; 1351 1352 uart_c_cts_rts_pins: uart-c-cts-rts { 1353 mux { 1354 groups = "uart_c_cts", 1355 "uart_c_rts"; 1356 function = "uart_c"; 1357 bias-disable; 1358 }; 1359 }; 1360 }; 1361 }; 1362 1363 usb2_phy0: phy@36000 { 1364 compatible = "amlogic,g12a-usb2-phy"; 1365 reg = <0x0 0x36000 0x0 0x2000>; 1366 clocks = <&xtal>; 1367 clock-names = "xtal"; 1368 resets = <&reset RESET_USB_PHY20>; 1369 reset-names = "phy"; 1370 #phy-cells = <0>; 1371 }; 1372 1373 dmc: bus@38000 { 1374 compatible = "simple-bus"; 1375 reg = <0x0 0x38000 0x0 0x400>; 1376 #address-cells = <2>; 1377 #size-cells = <2>; 1378 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1379 1380 canvas: video-lut@48 { 1381 compatible = "amlogic,canvas"; 1382 reg = <0x0 0x48 0x0 0x14>; 1383 }; 1384 }; 1385 1386 usb2_phy1: phy@3a000 { 1387 compatible = "amlogic,g12a-usb2-phy"; 1388 reg = <0x0 0x3a000 0x0 0x2000>; 1389 clocks = <&xtal>; 1390 clock-names = "xtal"; 1391 resets = <&reset RESET_USB_PHY21>; 1392 reset-names = "phy"; 1393 #phy-cells = <0>; 1394 }; 1395 1396 hiu: bus@3c000 { 1397 compatible = "simple-bus"; 1398 reg = <0x0 0x3c000 0x0 0x1400>; 1399 #address-cells = <2>; 1400 #size-cells = <2>; 1401 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1402 1403 hhi: system-controller@0 { 1404 compatible = "amlogic,meson-gx-hhi-sysctrl", 1405 "simple-mfd", "syscon"; 1406 reg = <0 0 0 0x400>; 1407 1408 clkc: clock-controller { 1409 compatible = "amlogic,g12a-clkc"; 1410 #clock-cells = <1>; 1411 clocks = <&xtal>; 1412 clock-names = "xtal"; 1413 }; 1414 }; 1415 }; 1416 1417 pdm: audio-controller@40000 { 1418 compatible = "amlogic,g12a-pdm", 1419 "amlogic,axg-pdm"; 1420 reg = <0x0 0x40000 0x0 0x34>; 1421 #sound-dai-cells = <0>; 1422 sound-name-prefix = "PDM"; 1423 clocks = <&clkc_audio AUD_CLKID_PDM>, 1424 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1425 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1426 clock-names = "pclk", "dclk", "sysclk"; 1427 status = "disabled"; 1428 }; 1429 1430 audio: bus@42000 { 1431 compatible = "simple-bus"; 1432 reg = <0x0 0x42000 0x0 0x2000>; 1433 #address-cells = <2>; 1434 #size-cells = <2>; 1435 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1436 1437 clkc_audio: clock-controller@0 { 1438 status = "disabled"; 1439 compatible = "amlogic,g12a-audio-clkc"; 1440 reg = <0x0 0x0 0x0 0xb4>; 1441 #clock-cells = <1>; 1442 1443 clocks = <&clkc CLKID_AUDIO>, 1444 <&clkc CLKID_MPLL0>, 1445 <&clkc CLKID_MPLL1>, 1446 <&clkc CLKID_MPLL2>, 1447 <&clkc CLKID_MPLL3>, 1448 <&clkc CLKID_HIFI_PLL>, 1449 <&clkc CLKID_FCLK_DIV3>, 1450 <&clkc CLKID_FCLK_DIV4>, 1451 <&clkc CLKID_GP0_PLL>; 1452 clock-names = "pclk", 1453 "mst_in0", 1454 "mst_in1", 1455 "mst_in2", 1456 "mst_in3", 1457 "mst_in4", 1458 "mst_in5", 1459 "mst_in6", 1460 "mst_in7"; 1461 1462 resets = <&reset RESET_AUDIO>; 1463 }; 1464 1465 toddr_a: audio-controller@100 { 1466 compatible = "amlogic,g12a-toddr", 1467 "amlogic,axg-toddr"; 1468 reg = <0x0 0x100 0x0 0x1c>; 1469 #sound-dai-cells = <0>; 1470 sound-name-prefix = "TODDR_A"; 1471 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1472 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1473 resets = <&arb AXG_ARB_TODDR_A>; 1474 status = "disabled"; 1475 }; 1476 1477 toddr_b: audio-controller@140 { 1478 compatible = "amlogic,g12a-toddr", 1479 "amlogic,axg-toddr"; 1480 reg = <0x0 0x140 0x0 0x1c>; 1481 #sound-dai-cells = <0>; 1482 sound-name-prefix = "TODDR_B"; 1483 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1484 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1485 resets = <&arb AXG_ARB_TODDR_B>; 1486 status = "disabled"; 1487 }; 1488 1489 toddr_c: audio-controller@180 { 1490 compatible = "amlogic,g12a-toddr", 1491 "amlogic,axg-toddr"; 1492 reg = <0x0 0x180 0x0 0x1c>; 1493 #sound-dai-cells = <0>; 1494 sound-name-prefix = "TODDR_C"; 1495 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1496 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1497 resets = <&arb AXG_ARB_TODDR_C>; 1498 status = "disabled"; 1499 }; 1500 1501 frddr_a: audio-controller@1c0 { 1502 compatible = "amlogic,g12a-frddr", 1503 "amlogic,axg-frddr"; 1504 reg = <0x0 0x1c0 0x0 0x1c>; 1505 #sound-dai-cells = <0>; 1506 sound-name-prefix = "FRDDR_A"; 1507 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1508 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1509 resets = <&arb AXG_ARB_FRDDR_A>; 1510 status = "disabled"; 1511 }; 1512 1513 frddr_b: audio-controller@200 { 1514 compatible = "amlogic,g12a-frddr", 1515 "amlogic,axg-frddr"; 1516 reg = <0x0 0x200 0x0 0x1c>; 1517 #sound-dai-cells = <0>; 1518 sound-name-prefix = "FRDDR_B"; 1519 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1520 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1521 resets = <&arb AXG_ARB_FRDDR_B>; 1522 status = "disabled"; 1523 }; 1524 1525 frddr_c: audio-controller@240 { 1526 compatible = "amlogic,g12a-frddr", 1527 "amlogic,axg-frddr"; 1528 reg = <0x0 0x240 0x0 0x1c>; 1529 #sound-dai-cells = <0>; 1530 sound-name-prefix = "FRDDR_C"; 1531 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1532 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1533 resets = <&arb AXG_ARB_FRDDR_C>; 1534 status = "disabled"; 1535 }; 1536 1537 arb: reset-controller@280 { 1538 status = "disabled"; 1539 compatible = "amlogic,meson-axg-audio-arb"; 1540 reg = <0x0 0x280 0x0 0x4>; 1541 #reset-cells = <1>; 1542 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1543 }; 1544 1545 tdmin_a: audio-controller@300 { 1546 compatible = "amlogic,g12a-tdmin", 1547 "amlogic,axg-tdmin"; 1548 reg = <0x0 0x300 0x0 0x40>; 1549 sound-name-prefix = "TDMIN_A"; 1550 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1551 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1552 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1553 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1554 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1555 clock-names = "pclk", "sclk", "sclk_sel", 1556 "lrclk", "lrclk_sel"; 1557 status = "disabled"; 1558 }; 1559 1560 tdmin_b: audio-controller@340 { 1561 compatible = "amlogic,g12a-tdmin", 1562 "amlogic,axg-tdmin"; 1563 reg = <0x0 0x340 0x0 0x40>; 1564 sound-name-prefix = "TDMIN_B"; 1565 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1566 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1567 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1568 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1569 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1570 clock-names = "pclk", "sclk", "sclk_sel", 1571 "lrclk", "lrclk_sel"; 1572 status = "disabled"; 1573 }; 1574 1575 tdmin_c: audio-controller@380 { 1576 compatible = "amlogic,g12a-tdmin", 1577 "amlogic,axg-tdmin"; 1578 reg = <0x0 0x380 0x0 0x40>; 1579 sound-name-prefix = "TDMIN_C"; 1580 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1581 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1582 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1583 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1584 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1585 clock-names = "pclk", "sclk", "sclk_sel", 1586 "lrclk", "lrclk_sel"; 1587 status = "disabled"; 1588 }; 1589 1590 tdmin_lb: audio-controller@3c0 { 1591 compatible = "amlogic,g12a-tdmin", 1592 "amlogic,axg-tdmin"; 1593 reg = <0x0 0x3c0 0x0 0x40>; 1594 sound-name-prefix = "TDMIN_LB"; 1595 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1596 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1597 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1598 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1599 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1600 clock-names = "pclk", "sclk", "sclk_sel", 1601 "lrclk", "lrclk_sel"; 1602 status = "disabled"; 1603 }; 1604 1605 spdifin: audio-controller@400 { 1606 compatible = "amlogic,g12a-spdifin", 1607 "amlogic,axg-spdifin"; 1608 reg = <0x0 0x400 0x0 0x30>; 1609 #sound-dai-cells = <0>; 1610 sound-name-prefix = "SPDIFIN"; 1611 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1612 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1613 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1614 clock-names = "pclk", "refclk"; 1615 status = "disabled"; 1616 }; 1617 1618 spdifout: audio-controller@480 { 1619 compatible = "amlogic,g12a-spdifout", 1620 "amlogic,axg-spdifout"; 1621 reg = <0x0 0x480 0x0 0x50>; 1622 #sound-dai-cells = <0>; 1623 sound-name-prefix = "SPDIFOUT"; 1624 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1625 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1626 clock-names = "pclk", "mclk"; 1627 status = "disabled"; 1628 }; 1629 1630 tdmout_a: audio-controller@500 { 1631 compatible = "amlogic,g12a-tdmout"; 1632 reg = <0x0 0x500 0x0 0x40>; 1633 sound-name-prefix = "TDMOUT_A"; 1634 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1635 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1636 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1637 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1638 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1639 clock-names = "pclk", "sclk", "sclk_sel", 1640 "lrclk", "lrclk_sel"; 1641 status = "disabled"; 1642 }; 1643 1644 tdmout_b: audio-controller@540 { 1645 compatible = "amlogic,g12a-tdmout"; 1646 reg = <0x0 0x540 0x0 0x40>; 1647 sound-name-prefix = "TDMOUT_B"; 1648 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1649 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1650 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1651 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1652 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1653 clock-names = "pclk", "sclk", "sclk_sel", 1654 "lrclk", "lrclk_sel"; 1655 status = "disabled"; 1656 }; 1657 1658 tdmout_c: audio-controller@580 { 1659 compatible = "amlogic,g12a-tdmout"; 1660 reg = <0x0 0x580 0x0 0x40>; 1661 sound-name-prefix = "TDMOUT_C"; 1662 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1663 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1664 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1665 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1666 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1667 clock-names = "pclk", "sclk", "sclk_sel", 1668 "lrclk", "lrclk_sel"; 1669 status = "disabled"; 1670 }; 1671 1672 spdifout_b: audio-controller@680 { 1673 compatible = "amlogic,g12a-spdifout", 1674 "amlogic,axg-spdifout"; 1675 reg = <0x0 0x680 0x0 0x50>; 1676 #sound-dai-cells = <0>; 1677 sound-name-prefix = "SPDIFOUT_B"; 1678 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1679 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1680 clock-names = "pclk", "mclk"; 1681 status = "disabled"; 1682 }; 1683 1684 tohdmitx: audio-controller@744 { 1685 compatible = "amlogic,g12a-tohdmitx"; 1686 reg = <0x0 0x744 0x0 0x4>; 1687 #sound-dai-cells = <1>; 1688 sound-name-prefix = "TOHDMITX"; 1689 status = "disabled"; 1690 }; 1691 }; 1692 1693 usb3_pcie_phy: phy@46000 { 1694 compatible = "amlogic,g12a-usb3-pcie-phy"; 1695 reg = <0x0 0x46000 0x0 0x2000>; 1696 clocks = <&clkc CLKID_PCIE_PLL>; 1697 clock-names = "ref_clk"; 1698 resets = <&reset RESET_PCIE_PHY>; 1699 reset-names = "phy"; 1700 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1701 assigned-clock-rates = <100000000>; 1702 #phy-cells = <1>; 1703 }; 1704 1705 eth_phy: mdio-multiplexer@4c000 { 1706 compatible = "amlogic,g12a-mdio-mux"; 1707 reg = <0x0 0x4c000 0x0 0xa4>; 1708 clocks = <&clkc CLKID_ETH_PHY>, 1709 <&xtal>, 1710 <&clkc CLKID_MPLL_50M>; 1711 clock-names = "pclk", "clkin0", "clkin1"; 1712 mdio-parent-bus = <&mdio0>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 ext_mdio: mdio@0 { 1717 reg = <0>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 }; 1721 1722 int_mdio: mdio@1 { 1723 reg = <1>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 1727 internal_ephy: ethernet_phy@8 { 1728 compatible = "ethernet-phy-id0180.3301", 1729 "ethernet-phy-ieee802.3-c22"; 1730 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1731 reg = <8>; 1732 max-speed = <100>; 1733 }; 1734 }; 1735 }; 1736 }; 1737 1738 aobus: bus@ff800000 { 1739 compatible = "simple-bus"; 1740 reg = <0x0 0xff800000 0x0 0x100000>; 1741 #address-cells = <2>; 1742 #size-cells = <2>; 1743 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1744 1745 rti: sys-ctrl@0 { 1746 compatible = "amlogic,meson-gx-ao-sysctrl", 1747 "simple-mfd", "syscon"; 1748 reg = <0x0 0x0 0x0 0x100>; 1749 #address-cells = <2>; 1750 #size-cells = <2>; 1751 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1752 1753 clkc_AO: clock-controller { 1754 compatible = "amlogic,meson-g12a-aoclkc"; 1755 #clock-cells = <1>; 1756 #reset-cells = <1>; 1757 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1758 clock-names = "xtal", "mpeg-clk"; 1759 }; 1760 1761 pwrc_vpu: power-controller-vpu { 1762 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1763 #power-domain-cells = <0>; 1764 amlogic,hhi-sysctrl = <&hhi>; 1765 resets = <&reset RESET_VIU>, 1766 <&reset RESET_VENC>, 1767 <&reset RESET_VCBUS>, 1768 <&reset RESET_BT656>, 1769 <&reset RESET_RDMA>, 1770 <&reset RESET_VENCI>, 1771 <&reset RESET_VENCP>, 1772 <&reset RESET_VDAC>, 1773 <&reset RESET_VDI6>, 1774 <&reset RESET_VENCL>, 1775 <&reset RESET_VID_LOCK>; 1776 clocks = <&clkc CLKID_VPU>, 1777 <&clkc CLKID_VAPB>; 1778 clock-names = "vpu", "vapb"; 1779 /* 1780 * VPU clocking is provided by two identical clock paths 1781 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1782 * free mux to safely change frequency while running. 1783 * Same for VAPB but with a final gate after the glitch free mux. 1784 */ 1785 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1786 <&clkc CLKID_VPU_0>, 1787 <&clkc CLKID_VPU>, /* Glitch free mux */ 1788 <&clkc CLKID_VAPB_0_SEL>, 1789 <&clkc CLKID_VAPB_0>, 1790 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1791 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1792 <0>, /* Do Nothing */ 1793 <&clkc CLKID_VPU_0>, 1794 <&clkc CLKID_FCLK_DIV4>, 1795 <0>, /* Do Nothing */ 1796 <&clkc CLKID_VAPB_0>; 1797 assigned-clock-rates = <0>, /* Do Nothing */ 1798 <666666666>, 1799 <0>, /* Do Nothing */ 1800 <0>, /* Do Nothing */ 1801 <250000000>, 1802 <0>; /* Do Nothing */ 1803 }; 1804 1805 ao_pinctrl: pinctrl@14 { 1806 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1807 #address-cells = <2>; 1808 #size-cells = <2>; 1809 ranges; 1810 1811 gpio_ao: bank@14 { 1812 reg = <0x0 0x14 0x0 0x8>, 1813 <0x0 0x1c 0x0 0x8>, 1814 <0x0 0x24 0x0 0x14>; 1815 reg-names = "mux", 1816 "ds", 1817 "gpio"; 1818 gpio-controller; 1819 #gpio-cells = <2>; 1820 gpio-ranges = <&ao_pinctrl 0 0 15>; 1821 }; 1822 1823 i2c_ao_sck_pins: i2c_ao_sck_pins { 1824 mux { 1825 groups = "i2c_ao_sck"; 1826 function = "i2c_ao"; 1827 bias-disable; 1828 drive-strength-microamp = <3000>; 1829 }; 1830 }; 1831 1832 i2c_ao_sda_pins: i2c_ao_sda { 1833 mux { 1834 groups = "i2c_ao_sda"; 1835 function = "i2c_ao"; 1836 bias-disable; 1837 drive-strength-microamp = <3000>; 1838 }; 1839 }; 1840 1841 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1842 mux { 1843 groups = "i2c_ao_sck_e"; 1844 function = "i2c_ao"; 1845 bias-disable; 1846 drive-strength-microamp = <3000>; 1847 }; 1848 }; 1849 1850 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1851 mux { 1852 groups = "i2c_ao_sda_e"; 1853 function = "i2c_ao"; 1854 bias-disable; 1855 drive-strength-microamp = <3000>; 1856 }; 1857 }; 1858 1859 mclk0_ao_pins: mclk0-ao { 1860 mux { 1861 groups = "mclk0_ao"; 1862 function = "mclk0_ao"; 1863 bias-disable; 1864 drive-strength-microamp = <3000>; 1865 }; 1866 }; 1867 1868 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1869 mux { 1870 groups = "tdm_ao_b_din0"; 1871 function = "tdm_ao_b"; 1872 bias-disable; 1873 }; 1874 }; 1875 1876 spdif_ao_out_pins: spdif-ao-out { 1877 mux { 1878 groups = "spdif_ao_out"; 1879 function = "spdif_ao_out"; 1880 drive-strength-microamp = <500>; 1881 bias-disable; 1882 }; 1883 }; 1884 1885 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1886 mux { 1887 groups = "tdm_ao_b_din1"; 1888 function = "tdm_ao_b"; 1889 bias-disable; 1890 }; 1891 }; 1892 1893 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1894 mux { 1895 groups = "tdm_ao_b_din2"; 1896 function = "tdm_ao_b"; 1897 bias-disable; 1898 }; 1899 }; 1900 1901 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1902 mux { 1903 groups = "tdm_ao_b_dout0"; 1904 function = "tdm_ao_b"; 1905 bias-disable; 1906 drive-strength-microamp = <3000>; 1907 }; 1908 }; 1909 1910 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1911 mux { 1912 groups = "tdm_ao_b_dout1"; 1913 function = "tdm_ao_b"; 1914 bias-disable; 1915 drive-strength-microamp = <3000>; 1916 }; 1917 }; 1918 1919 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1920 mux { 1921 groups = "tdm_ao_b_dout2"; 1922 function = "tdm_ao_b"; 1923 bias-disable; 1924 drive-strength-microamp = <3000>; 1925 }; 1926 }; 1927 1928 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1929 mux { 1930 groups = "tdm_ao_b_fs"; 1931 function = "tdm_ao_b"; 1932 bias-disable; 1933 drive-strength-microamp = <3000>; 1934 }; 1935 }; 1936 1937 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1938 mux { 1939 groups = "tdm_ao_b_sclk"; 1940 function = "tdm_ao_b"; 1941 bias-disable; 1942 drive-strength-microamp = <3000>; 1943 }; 1944 }; 1945 1946 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1947 mux { 1948 groups = "tdm_ao_b_slv_fs"; 1949 function = "tdm_ao_b"; 1950 bias-disable; 1951 }; 1952 }; 1953 1954 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1955 mux { 1956 groups = "tdm_ao_b_slv_sclk"; 1957 function = "tdm_ao_b"; 1958 bias-disable; 1959 }; 1960 }; 1961 1962 uart_ao_a_pins: uart-a-ao { 1963 mux { 1964 groups = "uart_ao_a_tx", 1965 "uart_ao_a_rx"; 1966 function = "uart_ao_a"; 1967 bias-disable; 1968 }; 1969 }; 1970 1971 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1972 mux { 1973 groups = "uart_ao_a_cts", 1974 "uart_ao_a_rts"; 1975 function = "uart_ao_a"; 1976 bias-disable; 1977 }; 1978 }; 1979 1980 pwm_ao_a_pins: pwm-ao-a { 1981 mux { 1982 groups = "pwm_ao_a"; 1983 function = "pwm_ao_a"; 1984 bias-disable; 1985 }; 1986 }; 1987 1988 pwm_ao_b_pins: pwm-ao-b { 1989 mux { 1990 groups = "pwm_ao_b"; 1991 function = "pwm_ao_b"; 1992 bias-disable; 1993 }; 1994 }; 1995 1996 pwm_ao_c_4_pins: pwm-ao-c-4 { 1997 mux { 1998 groups = "pwm_ao_c_4"; 1999 function = "pwm_ao_c"; 2000 bias-disable; 2001 }; 2002 }; 2003 2004 pwm_ao_c_6_pins: pwm-ao-c-6 { 2005 mux { 2006 groups = "pwm_ao_c_6"; 2007 function = "pwm_ao_c"; 2008 bias-disable; 2009 }; 2010 }; 2011 2012 pwm_ao_d_5_pins: pwm-ao-d-5 { 2013 mux { 2014 groups = "pwm_ao_d_5"; 2015 function = "pwm_ao_d"; 2016 bias-disable; 2017 }; 2018 }; 2019 2020 pwm_ao_d_10_pins: pwm-ao-d-10 { 2021 mux { 2022 groups = "pwm_ao_d_10"; 2023 function = "pwm_ao_d"; 2024 bias-disable; 2025 }; 2026 }; 2027 2028 pwm_ao_d_e_pins: pwm-ao-d-e { 2029 mux { 2030 groups = "pwm_ao_d_e"; 2031 function = "pwm_ao_d"; 2032 }; 2033 }; 2034 2035 remote_input_ao_pins: remote-input-ao { 2036 mux { 2037 groups = "remote_ao_input"; 2038 function = "remote_ao_input"; 2039 bias-disable; 2040 }; 2041 }; 2042 }; 2043 }; 2044 2045 cec_AO: cec@100 { 2046 compatible = "amlogic,meson-gx-ao-cec"; 2047 reg = <0x0 0x00100 0x0 0x14>; 2048 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2049 clocks = <&clkc_AO CLKID_AO_CEC>; 2050 clock-names = "core"; 2051 status = "disabled"; 2052 }; 2053 2054 sec_AO: ao-secure@140 { 2055 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2056 reg = <0x0 0x140 0x0 0x140>; 2057 amlogic,has-chip-id; 2058 }; 2059 2060 cecb_AO: cec@280 { 2061 compatible = "amlogic,meson-g12a-ao-cec"; 2062 reg = <0x0 0x00280 0x0 0x1c>; 2063 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2064 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2065 clock-names = "oscin"; 2066 status = "disabled"; 2067 }; 2068 2069 pwm_AO_cd: pwm@2000 { 2070 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2071 reg = <0x0 0x2000 0x0 0x20>; 2072 #pwm-cells = <3>; 2073 status = "disabled"; 2074 }; 2075 2076 uart_AO: serial@3000 { 2077 compatible = "amlogic,meson-gx-uart", 2078 "amlogic,meson-ao-uart"; 2079 reg = <0x0 0x3000 0x0 0x18>; 2080 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2081 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2082 clock-names = "xtal", "pclk", "baud"; 2083 status = "disabled"; 2084 }; 2085 2086 uart_AO_B: serial@4000 { 2087 compatible = "amlogic,meson-gx-uart", 2088 "amlogic,meson-ao-uart"; 2089 reg = <0x0 0x4000 0x0 0x18>; 2090 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2091 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2092 clock-names = "xtal", "pclk", "baud"; 2093 status = "disabled"; 2094 }; 2095 2096 i2c_AO: i2c@5000 { 2097 compatible = "amlogic,meson-axg-i2c"; 2098 status = "disabled"; 2099 reg = <0x0 0x05000 0x0 0x20>; 2100 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2101 #address-cells = <1>; 2102 #size-cells = <0>; 2103 clocks = <&clkc CLKID_I2C>; 2104 }; 2105 2106 pwm_AO_ab: pwm@7000 { 2107 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2108 reg = <0x0 0x7000 0x0 0x20>; 2109 #pwm-cells = <3>; 2110 status = "disabled"; 2111 }; 2112 2113 ir: ir@8000 { 2114 compatible = "amlogic,meson-gxbb-ir"; 2115 reg = <0x0 0x8000 0x0 0x20>; 2116 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2117 status = "disabled"; 2118 }; 2119 2120 saradc: adc@9000 { 2121 compatible = "amlogic,meson-g12a-saradc", 2122 "amlogic,meson-saradc"; 2123 reg = <0x0 0x9000 0x0 0x48>; 2124 #io-channel-cells = <1>; 2125 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2126 clocks = <&xtal>, 2127 <&clkc_AO CLKID_AO_SAR_ADC>, 2128 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2129 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2130 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2131 status = "disabled"; 2132 }; 2133 }; 2134 2135 vpu: vpu@ff900000 { 2136 compatible = "amlogic,meson-g12a-vpu"; 2137 reg = <0x0 0xff900000 0x0 0x100000>, 2138 <0x0 0xff63c000 0x0 0x1000>; 2139 reg-names = "vpu", "hhi"; 2140 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 amlogic,canvas = <&canvas>; 2144 power-domains = <&pwrc_vpu>; 2145 2146 /* CVBS VDAC output port */ 2147 cvbs_vdac_port: port@0 { 2148 reg = <0>; 2149 }; 2150 2151 /* HDMI-TX output port */ 2152 hdmi_tx_port: port@1 { 2153 reg = <1>; 2154 2155 hdmi_tx_out: endpoint { 2156 remote-endpoint = <&hdmi_tx_in>; 2157 }; 2158 }; 2159 }; 2160 2161 gic: interrupt-controller@ffc01000 { 2162 compatible = "arm,gic-400"; 2163 reg = <0x0 0xffc01000 0 0x1000>, 2164 <0x0 0xffc02000 0 0x2000>, 2165 <0x0 0xffc04000 0 0x2000>, 2166 <0x0 0xffc06000 0 0x2000>; 2167 interrupt-controller; 2168 interrupts = <GIC_PPI 9 2169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2170 #interrupt-cells = <3>; 2171 #address-cells = <0>; 2172 }; 2173 2174 cbus: bus@ffd00000 { 2175 compatible = "simple-bus"; 2176 reg = <0x0 0xffd00000 0x0 0x100000>; 2177 #address-cells = <2>; 2178 #size-cells = <2>; 2179 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2180 2181 reset: reset-controller@1004 { 2182 compatible = "amlogic,meson-g12a-reset", 2183 "amlogic,meson-axg-reset"; 2184 reg = <0x0 0x1004 0x0 0x9c>; 2185 #reset-cells = <1>; 2186 }; 2187 2188 pwm_ef: pwm@19000 { 2189 compatible = "amlogic,meson-g12a-ee-pwm"; 2190 reg = <0x0 0x19000 0x0 0x20>; 2191 #pwm-cells = <3>; 2192 status = "disabled"; 2193 }; 2194 2195 pwm_cd: pwm@1a000 { 2196 compatible = "amlogic,meson-g12a-ee-pwm"; 2197 reg = <0x0 0x1a000 0x0 0x20>; 2198 #pwm-cells = <3>; 2199 status = "disabled"; 2200 }; 2201 2202 pwm_ab: pwm@1b000 { 2203 compatible = "amlogic,meson-g12a-ee-pwm"; 2204 reg = <0x0 0x1b000 0x0 0x20>; 2205 #pwm-cells = <3>; 2206 status = "disabled"; 2207 }; 2208 2209 i2c3: i2c@1c000 { 2210 compatible = "amlogic,meson-axg-i2c"; 2211 status = "disabled"; 2212 reg = <0x0 0x1c000 0x0 0x20>; 2213 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2214 #address-cells = <1>; 2215 #size-cells = <0>; 2216 clocks = <&clkc CLKID_I2C>; 2217 }; 2218 2219 i2c2: i2c@1d000 { 2220 compatible = "amlogic,meson-axg-i2c"; 2221 status = "disabled"; 2222 reg = <0x0 0x1d000 0x0 0x20>; 2223 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 clocks = <&clkc CLKID_I2C>; 2227 }; 2228 2229 i2c1: i2c@1e000 { 2230 compatible = "amlogic,meson-axg-i2c"; 2231 status = "disabled"; 2232 reg = <0x0 0x1e000 0x0 0x20>; 2233 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2234 #address-cells = <1>; 2235 #size-cells = <0>; 2236 clocks = <&clkc CLKID_I2C>; 2237 }; 2238 2239 i2c0: i2c@1f000 { 2240 compatible = "amlogic,meson-axg-i2c"; 2241 status = "disabled"; 2242 reg = <0x0 0x1f000 0x0 0x20>; 2243 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2244 #address-cells = <1>; 2245 #size-cells = <0>; 2246 clocks = <&clkc CLKID_I2C>; 2247 }; 2248 2249 clk_msr: clock-measure@18000 { 2250 compatible = "amlogic,meson-g12a-clk-measure"; 2251 reg = <0x0 0x18000 0x0 0x10>; 2252 }; 2253 2254 uart_C: serial@22000 { 2255 compatible = "amlogic,meson-gx-uart"; 2256 reg = <0x0 0x22000 0x0 0x18>; 2257 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2258 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2259 clock-names = "xtal", "pclk", "baud"; 2260 status = "disabled"; 2261 }; 2262 2263 uart_B: serial@23000 { 2264 compatible = "amlogic,meson-gx-uart"; 2265 reg = <0x0 0x23000 0x0 0x18>; 2266 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2267 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2268 clock-names = "xtal", "pclk", "baud"; 2269 status = "disabled"; 2270 }; 2271 2272 uart_A: serial@24000 { 2273 compatible = "amlogic,meson-gx-uart"; 2274 reg = <0x0 0x24000 0x0 0x18>; 2275 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2276 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2277 clock-names = "xtal", "pclk", "baud"; 2278 status = "disabled"; 2279 }; 2280 }; 2281 2282 sd_emmc_b: sd@ffe05000 { 2283 compatible = "amlogic,meson-axg-mmc"; 2284 reg = <0x0 0xffe05000 0x0 0x800>; 2285 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2286 status = "disabled"; 2287 clocks = <&clkc CLKID_SD_EMMC_B>, 2288 <&clkc CLKID_SD_EMMC_B_CLK0>, 2289 <&clkc CLKID_FCLK_DIV2>; 2290 clock-names = "core", "clkin0", "clkin1"; 2291 resets = <&reset RESET_SD_EMMC_B>; 2292 }; 2293 2294 sd_emmc_c: mmc@ffe07000 { 2295 compatible = "amlogic,meson-axg-mmc"; 2296 reg = <0x0 0xffe07000 0x0 0x800>; 2297 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2298 status = "disabled"; 2299 clocks = <&clkc CLKID_SD_EMMC_C>, 2300 <&clkc CLKID_SD_EMMC_C_CLK0>, 2301 <&clkc CLKID_FCLK_DIV2>; 2302 clock-names = "core", "clkin0", "clkin1"; 2303 resets = <&reset RESET_SD_EMMC_C>; 2304 }; 2305 2306 usb: usb@ffe09000 { 2307 status = "disabled"; 2308 compatible = "amlogic,meson-g12a-usb-ctrl"; 2309 reg = <0x0 0xffe09000 0x0 0xa0>; 2310 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2311 #address-cells = <2>; 2312 #size-cells = <2>; 2313 ranges; 2314 2315 clocks = <&clkc CLKID_USB>; 2316 resets = <&reset RESET_USB>; 2317 2318 dr_mode = "otg"; 2319 2320 phys = <&usb2_phy0>, <&usb2_phy1>, 2321 <&usb3_pcie_phy PHY_TYPE_USB3>; 2322 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2323 2324 dwc2: usb@ff400000 { 2325 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2326 reg = <0x0 0xff400000 0x0 0x40000>; 2327 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2328 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2329 clock-names = "ddr"; 2330 phys = <&usb2_phy1>; 2331 dr_mode = "peripheral"; 2332 g-rx-fifo-size = <192>; 2333 g-np-tx-fifo-size = <128>; 2334 g-tx-fifo-size = <128 128 16 16 16>; 2335 }; 2336 2337 dwc3: usb@ff500000 { 2338 compatible = "snps,dwc3"; 2339 reg = <0x0 0xff500000 0x0 0x100000>; 2340 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2341 dr_mode = "host"; 2342 snps,dis_u2_susphy_quirk; 2343 snps,quirk-frame-length-adjustment; 2344 }; 2345 }; 2346 2347 mali: gpu@ffe40000 { 2348 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2349 reg = <0x0 0xffe40000 0x0 0x40000>; 2350 interrupt-parent = <&gic>; 2351 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2354 interrupt-names = "gpu", "mmu", "job"; 2355 clocks = <&clkc CLKID_MALI>; 2356 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2357 2358 /* 2359 * Mali clocking is provided by two identical clock paths 2360 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2361 * free mux to safely change frequency while running. 2362 */ 2363 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2364 <&clkc CLKID_MALI_0>, 2365 <&clkc CLKID_MALI>; /* Glitch free mux */ 2366 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2367 <0>, /* Do Nothing */ 2368 <&clkc CLKID_MALI_0>; 2369 assigned-clock-rates = <0>, /* Do Nothing */ 2370 <800000000>, 2371 <0>; /* Do Nothing */ 2372 }; 2373 }; 2374 2375 timer { 2376 compatible = "arm,armv8-timer"; 2377 interrupts = <GIC_PPI 13 2378 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2379 <GIC_PPI 14 2380 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2381 <GIC_PPI 11 2382 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2383 <GIC_PPI 10 2384 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2385 }; 2386 2387 xtal: xtal-clk { 2388 compatible = "fixed-clock"; 2389 clock-frequency = <24000000>; 2390 clock-output-names = "xtal"; 2391 #clock-cells = <0>; 2392 }; 2393 2394}; 2395