1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 ethmac: ethernet@ff3f0000 { 141 compatible = "amlogic,meson-axg-dwmac", 142 "snps,dwmac-3.70a", 143 "snps,dwmac"; 144 reg = <0x0 0xff3f0000 0x0 0x10000 145 0x0 0xff634540 0x0 0x8>; 146 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "macirq"; 148 clocks = <&clkc CLKID_ETH>, 149 <&clkc CLKID_FCLK_DIV2>, 150 <&clkc CLKID_MPLL2>; 151 clock-names = "stmmaceth", "clkin0", "clkin1"; 152 status = "disabled"; 153 154 mdio0: mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "snps,dwmac-mdio"; 158 }; 159 }; 160 161 apb: bus@ff600000 { 162 compatible = "simple-bus"; 163 reg = <0x0 0xff600000 0x0 0x200000>; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 167 168 hdmi_tx: hdmi-tx@0 { 169 compatible = "amlogic,meson-g12a-dw-hdmi"; 170 reg = <0x0 0x0 0x0 0x10000>; 171 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 172 resets = <&reset RESET_HDMITX_CAPB3>, 173 <&reset RESET_HDMITX_PHY>, 174 <&reset RESET_HDMITX>; 175 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 176 clocks = <&clkc CLKID_HDMI>, 177 <&clkc CLKID_HTX_PCLK>, 178 <&clkc CLKID_VPU_INTR>; 179 clock-names = "isfr", "iahb", "venci"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 185 /* VPU VENC Input */ 186 hdmi_tx_venc_port: port@0 { 187 reg = <0>; 188 189 hdmi_tx_in: endpoint { 190 remote-endpoint = <&hdmi_tx_out>; 191 }; 192 }; 193 194 /* TMDS Output */ 195 hdmi_tx_tmds_port: port@1 { 196 reg = <1>; 197 }; 198 }; 199 200 apb_efuse: bus@30000 { 201 compatible = "simple-bus"; 202 reg = <0x0 0x30000 0x0 0x2000>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 206 207 hwrng: rng@218 { 208 compatible = "amlogic,meson-rng"; 209 reg = <0x0 0x218 0x0 0x4>; 210 }; 211 }; 212 213 periphs: bus@34400 { 214 compatible = "simple-bus"; 215 reg = <0x0 0x34400 0x0 0x400>; 216 #address-cells = <2>; 217 #size-cells = <2>; 218 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 219 220 periphs_pinctrl: pinctrl@40 { 221 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 222 #address-cells = <2>; 223 #size-cells = <2>; 224 ranges; 225 226 gpio: bank@40 { 227 reg = <0x0 0x40 0x0 0x4c>, 228 <0x0 0xe8 0x0 0x18>, 229 <0x0 0x120 0x0 0x18>, 230 <0x0 0x2c0 0x0 0x40>, 231 <0x0 0x340 0x0 0x1c>; 232 reg-names = "gpio", 233 "pull", 234 "pull-enable", 235 "mux", 236 "ds"; 237 gpio-controller; 238 #gpio-cells = <2>; 239 gpio-ranges = <&periphs_pinctrl 0 0 86>; 240 }; 241 242 cec_ao_a_h_pins: cec_ao_a_h { 243 mux { 244 groups = "cec_ao_a_h"; 245 function = "cec_ao_a_h"; 246 bias-disable; 247 }; 248 }; 249 250 cec_ao_b_h_pins: cec_ao_b_h { 251 mux { 252 groups = "cec_ao_b_h"; 253 function = "cec_ao_b_h"; 254 bias-disable; 255 }; 256 }; 257 258 emmc_pins: emmc { 259 mux-0 { 260 groups = "emmc_nand_d0", 261 "emmc_nand_d1", 262 "emmc_nand_d2", 263 "emmc_nand_d3", 264 "emmc_nand_d4", 265 "emmc_nand_d5", 266 "emmc_nand_d6", 267 "emmc_nand_d7", 268 "emmc_cmd"; 269 function = "emmc"; 270 bias-pull-up; 271 drive-strength-microamp = <4000>; 272 }; 273 274 mux-1 { 275 groups = "emmc_clk"; 276 function = "emmc"; 277 bias-disable; 278 drive-strength-microamp = <4000>; 279 }; 280 }; 281 282 emmc_ds_pins: emmc-ds { 283 mux { 284 groups = "emmc_nand_ds"; 285 function = "emmc"; 286 bias-pull-down; 287 drive-strength-microamp = <4000>; 288 }; 289 }; 290 291 emmc_clk_gate_pins: emmc_clk_gate { 292 mux { 293 groups = "BOOT_8"; 294 function = "gpio_periphs"; 295 bias-pull-down; 296 drive-strength-microamp = <4000>; 297 }; 298 }; 299 300 hdmitx_ddc_pins: hdmitx_ddc { 301 mux { 302 groups = "hdmitx_sda", 303 "hdmitx_sck"; 304 function = "hdmitx"; 305 bias-disable; 306 drive-strength-microamp = <4000>; 307 }; 308 }; 309 310 hdmitx_hpd_pins: hdmitx_hpd { 311 mux { 312 groups = "hdmitx_hpd_in"; 313 function = "hdmitx"; 314 bias-disable; 315 }; 316 }; 317 318 319 i2c0_sda_c_pins: i2c0-sda-c { 320 mux { 321 groups = "i2c0_sda_c"; 322 function = "i2c0"; 323 bias-disable; 324 drive-strength-microamp = <3000>; 325 326 }; 327 }; 328 329 i2c0_sck_c_pins: i2c0-sck-c { 330 mux { 331 groups = "i2c0_sck_c"; 332 function = "i2c0"; 333 bias-disable; 334 drive-strength-microamp = <3000>; 335 }; 336 }; 337 338 i2c0_sda_z0_pins: i2c0-sda-z0 { 339 mux { 340 groups = "i2c0_sda_z0"; 341 function = "i2c0"; 342 bias-disable; 343 drive-strength-microamp = <3000>; 344 }; 345 }; 346 347 i2c0_sck_z1_pins: i2c0-sck-z1 { 348 mux { 349 groups = "i2c0_sck_z1"; 350 function = "i2c0"; 351 bias-disable; 352 drive-strength-microamp = <3000>; 353 }; 354 }; 355 356 i2c0_sda_z7_pins: i2c0-sda-z7 { 357 mux { 358 groups = "i2c0_sda_z7"; 359 function = "i2c0"; 360 bias-disable; 361 drive-strength-microamp = <3000>; 362 }; 363 }; 364 365 i2c0_sda_z8_pins: i2c0-sda-z8 { 366 mux { 367 groups = "i2c0_sda_z8"; 368 function = "i2c0"; 369 bias-disable; 370 drive-strength-microamp = <3000>; 371 }; 372 }; 373 374 i2c1_sda_x_pins: i2c1-sda-x { 375 mux { 376 groups = "i2c1_sda_x"; 377 function = "i2c1"; 378 bias-disable; 379 drive-strength-microamp = <3000>; 380 }; 381 }; 382 383 i2c1_sck_x_pins: i2c1-sck-x { 384 mux { 385 groups = "i2c1_sck_x"; 386 function = "i2c1"; 387 bias-disable; 388 drive-strength-microamp = <3000>; 389 }; 390 }; 391 392 i2c1_sda_h2_pins: i2c1-sda-h2 { 393 mux { 394 groups = "i2c1_sda_h2"; 395 function = "i2c1"; 396 bias-disable; 397 drive-strength-microamp = <3000>; 398 }; 399 }; 400 401 i2c1_sck_h3_pins: i2c1-sck-h3 { 402 mux { 403 groups = "i2c1_sck_h3"; 404 function = "i2c1"; 405 bias-disable; 406 drive-strength-microamp = <3000>; 407 }; 408 }; 409 410 i2c1_sda_h6_pins: i2c1-sda-h6 { 411 mux { 412 groups = "i2c1_sda_h6"; 413 function = "i2c1"; 414 bias-disable; 415 drive-strength-microamp = <3000>; 416 }; 417 }; 418 419 i2c1_sck_h7_pins: i2c1-sck-h7 { 420 mux { 421 groups = "i2c1_sck_h7"; 422 function = "i2c1"; 423 bias-disable; 424 drive-strength-microamp = <3000>; 425 }; 426 }; 427 428 i2c2_sda_x_pins: i2c2-sda-x { 429 mux { 430 groups = "i2c2_sda_x"; 431 function = "i2c2"; 432 bias-disable; 433 drive-strength-microamp = <3000>; 434 }; 435 }; 436 437 i2c2_sck_x_pins: i2c2-sck-x { 438 mux { 439 groups = "i2c2_sck_x"; 440 function = "i2c2"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c2_sda_z_pins: i2c2-sda-z { 447 mux { 448 groups = "i2c2_sda_z"; 449 function = "i2c2"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c2_sck_z_pins: i2c2-sck-z { 456 mux { 457 groups = "i2c2_sck_z"; 458 function = "i2c2"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 i2c3_sda_h_pins: i2c3-sda-h { 465 mux { 466 groups = "i2c3_sda_h"; 467 function = "i2c3"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 i2c3_sck_h_pins: i2c3-sck-h { 474 mux { 475 groups = "i2c3_sck_h"; 476 function = "i2c3"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 i2c3_sda_a_pins: i2c3-sda-a { 483 mux { 484 groups = "i2c3_sda_a"; 485 function = "i2c3"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 i2c3_sck_a_pins: i2c3-sck-a { 492 mux { 493 groups = "i2c3_sck_a"; 494 function = "i2c3"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 mclk0_a_pins: mclk0-a { 501 mux { 502 groups = "mclk0_a"; 503 function = "mclk0"; 504 bias-disable; 505 drive-strength-microamp = <3000>; 506 }; 507 }; 508 509 mclk1_a_pins: mclk1-a { 510 mux { 511 groups = "mclk1_a"; 512 function = "mclk1"; 513 bias-disable; 514 drive-strength-microamp = <3000>; 515 }; 516 }; 517 518 mclk1_x_pins: mclk1-x { 519 mux { 520 groups = "mclk1_x"; 521 function = "mclk1"; 522 bias-disable; 523 drive-strength-microamp = <3000>; 524 }; 525 }; 526 527 mclk1_z_pins: mclk1-z { 528 mux { 529 groups = "mclk1_z"; 530 function = "mclk1"; 531 bias-disable; 532 drive-strength-microamp = <3000>; 533 }; 534 }; 535 536 pdm_din0_a_pins: pdm-din0-a { 537 mux { 538 groups = "pdm_din0_a"; 539 function = "pdm"; 540 bias-disable; 541 }; 542 }; 543 544 pdm_din0_c_pins: pdm-din0-c { 545 mux { 546 groups = "pdm_din0_c"; 547 function = "pdm"; 548 bias-disable; 549 }; 550 }; 551 552 pdm_din0_x_pins: pdm-din0-x { 553 mux { 554 groups = "pdm_din0_x"; 555 function = "pdm"; 556 bias-disable; 557 }; 558 }; 559 560 pdm_din0_z_pins: pdm-din0-z { 561 mux { 562 groups = "pdm_din0_z"; 563 function = "pdm"; 564 bias-disable; 565 }; 566 }; 567 568 pdm_din1_a_pins: pdm-din1-a { 569 mux { 570 groups = "pdm_din1_a"; 571 function = "pdm"; 572 bias-disable; 573 }; 574 }; 575 576 pdm_din1_c_pins: pdm-din1-c { 577 mux { 578 groups = "pdm_din1_c"; 579 function = "pdm"; 580 bias-disable; 581 }; 582 }; 583 584 pdm_din1_x_pins: pdm-din1-x { 585 mux { 586 groups = "pdm_din1_x"; 587 function = "pdm"; 588 bias-disable; 589 }; 590 }; 591 592 pdm_din1_z_pins: pdm-din1-z { 593 mux { 594 groups = "pdm_din1_z"; 595 function = "pdm"; 596 bias-disable; 597 }; 598 }; 599 600 pdm_din2_a_pins: pdm-din2-a { 601 mux { 602 groups = "pdm_din2_a"; 603 function = "pdm"; 604 bias-disable; 605 }; 606 }; 607 608 pdm_din2_c_pins: pdm-din2-c { 609 mux { 610 groups = "pdm_din2_c"; 611 function = "pdm"; 612 bias-disable; 613 }; 614 }; 615 616 pdm_din2_x_pins: pdm-din2-x { 617 mux { 618 groups = "pdm_din2_x"; 619 function = "pdm"; 620 bias-disable; 621 }; 622 }; 623 624 pdm_din2_z_pins: pdm-din2-z { 625 mux { 626 groups = "pdm_din2_z"; 627 function = "pdm"; 628 bias-disable; 629 }; 630 }; 631 632 pdm_din3_a_pins: pdm-din3-a { 633 mux { 634 groups = "pdm_din3_a"; 635 function = "pdm"; 636 bias-disable; 637 }; 638 }; 639 640 pdm_din3_c_pins: pdm-din3-c { 641 mux { 642 groups = "pdm_din3_c"; 643 function = "pdm"; 644 bias-disable; 645 }; 646 }; 647 648 pdm_din3_x_pins: pdm-din3-x { 649 mux { 650 groups = "pdm_din3_x"; 651 function = "pdm"; 652 bias-disable; 653 }; 654 }; 655 656 pdm_din3_z_pins: pdm-din3-z { 657 mux { 658 groups = "pdm_din3_z"; 659 function = "pdm"; 660 bias-disable; 661 }; 662 }; 663 664 pdm_dclk_a_pins: pdm-dclk-a { 665 mux { 666 groups = "pdm_dclk_a"; 667 function = "pdm"; 668 bias-disable; 669 drive-strength-microamp = <500>; 670 }; 671 }; 672 673 pdm_dclk_c_pins: pdm-dclk-c { 674 mux { 675 groups = "pdm_dclk_c"; 676 function = "pdm"; 677 bias-disable; 678 drive-strength-microamp = <500>; 679 }; 680 }; 681 682 pdm_dclk_x_pins: pdm-dclk-x { 683 mux { 684 groups = "pdm_dclk_x"; 685 function = "pdm"; 686 bias-disable; 687 drive-strength-microamp = <500>; 688 }; 689 }; 690 691 pdm_dclk_z_pins: pdm-dclk-z { 692 mux { 693 groups = "pdm_dclk_z"; 694 function = "pdm"; 695 bias-disable; 696 drive-strength-microamp = <500>; 697 }; 698 }; 699 700 pwm_a_pins: pwm-a { 701 mux { 702 groups = "pwm_a"; 703 function = "pwm_a"; 704 bias-disable; 705 }; 706 }; 707 708 pwm_b_x7_pins: pwm-b-x7 { 709 mux { 710 groups = "pwm_b_x7"; 711 function = "pwm_b"; 712 bias-disable; 713 }; 714 }; 715 716 pwm_b_x19_pins: pwm-b-x19 { 717 mux { 718 groups = "pwm_b_x19"; 719 function = "pwm_b"; 720 bias-disable; 721 }; 722 }; 723 724 pwm_c_c_pins: pwm-c-c { 725 mux { 726 groups = "pwm_c_c"; 727 function = "pwm_c"; 728 bias-disable; 729 }; 730 }; 731 732 pwm_c_x5_pins: pwm-c-x5 { 733 mux { 734 groups = "pwm_c_x5"; 735 function = "pwm_c"; 736 bias-disable; 737 }; 738 }; 739 740 pwm_c_x8_pins: pwm-c-x8 { 741 mux { 742 groups = "pwm_c_x8"; 743 function = "pwm_c"; 744 bias-disable; 745 }; 746 }; 747 748 pwm_d_x3_pins: pwm-d-x3 { 749 mux { 750 groups = "pwm_d_x3"; 751 function = "pwm_d"; 752 bias-disable; 753 }; 754 }; 755 756 pwm_d_x6_pins: pwm-d-x6 { 757 mux { 758 groups = "pwm_d_x6"; 759 function = "pwm_d"; 760 bias-disable; 761 }; 762 }; 763 764 pwm_e_pins: pwm-e { 765 mux { 766 groups = "pwm_e"; 767 function = "pwm_e"; 768 bias-disable; 769 }; 770 }; 771 772 pwm_f_x_pins: pwm-f-x { 773 mux { 774 groups = "pwm_f_x"; 775 function = "pwm_f"; 776 bias-disable; 777 }; 778 }; 779 780 pwm_f_h_pins: pwm-f-h { 781 mux { 782 groups = "pwm_f_h"; 783 function = "pwm_f"; 784 bias-disable; 785 }; 786 }; 787 788 sdcard_c_pins: sdcard_c { 789 mux-0 { 790 groups = "sdcard_d0_c", 791 "sdcard_d1_c", 792 "sdcard_d2_c", 793 "sdcard_d3_c", 794 "sdcard_cmd_c"; 795 function = "sdcard"; 796 bias-pull-up; 797 drive-strength-microamp = <4000>; 798 }; 799 800 mux-1 { 801 groups = "sdcard_clk_c"; 802 function = "sdcard"; 803 bias-disable; 804 drive-strength-microamp = <4000>; 805 }; 806 }; 807 808 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 809 mux { 810 groups = "GPIOC_4"; 811 function = "gpio_periphs"; 812 bias-pull-down; 813 drive-strength-microamp = <4000>; 814 }; 815 }; 816 817 sdcard_z_pins: sdcard_z { 818 mux-0 { 819 groups = "sdcard_d0_z", 820 "sdcard_d1_z", 821 "sdcard_d2_z", 822 "sdcard_d3_z", 823 "sdcard_cmd_z"; 824 function = "sdcard"; 825 bias-pull-up; 826 drive-strength-microamp = <4000>; 827 }; 828 829 mux-1 { 830 groups = "sdcard_clk_z"; 831 function = "sdcard"; 832 bias-disable; 833 drive-strength-microamp = <4000>; 834 }; 835 }; 836 837 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 838 mux { 839 groups = "GPIOZ_6"; 840 function = "gpio_periphs"; 841 bias-pull-down; 842 drive-strength-microamp = <4000>; 843 }; 844 }; 845 846 spdif_in_a10_pins: spdif-in-a10 { 847 mux { 848 groups = "spdif_in_a10"; 849 function = "spdif_in"; 850 bias-disable; 851 }; 852 }; 853 854 spdif_in_a12_pins: spdif-in-a12 { 855 mux { 856 groups = "spdif_in_a12"; 857 function = "spdif_in"; 858 bias-disable; 859 }; 860 }; 861 862 spdif_in_h_pins: spdif-in-h { 863 mux { 864 groups = "spdif_in_h"; 865 function = "spdif_in"; 866 bias-disable; 867 }; 868 }; 869 870 spdif_out_h_pins: spdif-out-h { 871 mux { 872 groups = "spdif_out_h"; 873 function = "spdif_out"; 874 drive-strength-microamp = <500>; 875 bias-disable; 876 }; 877 }; 878 879 spdif_out_a11_pins: spdif-out-a11 { 880 mux { 881 groups = "spdif_out_a11"; 882 function = "spdif_out"; 883 drive-strength-microamp = <500>; 884 bias-disable; 885 }; 886 }; 887 888 spdif_out_a13_pins: spdif-out-a13 { 889 mux { 890 groups = "spdif_out_a13"; 891 function = "spdif_out"; 892 drive-strength-microamp = <500>; 893 bias-disable; 894 }; 895 }; 896 897 tdm_a_din0_pins: tdm-a-din0 { 898 mux { 899 groups = "tdm_a_din0"; 900 function = "tdm_a"; 901 bias-disable; 902 }; 903 }; 904 905 906 tdm_a_din1_pins: tdm-a-din1 { 907 mux { 908 groups = "tdm_a_din1"; 909 function = "tdm_a"; 910 bias-disable; 911 }; 912 }; 913 914 tdm_a_dout0_pins: tdm-a-dout0 { 915 mux { 916 groups = "tdm_a_dout0"; 917 function = "tdm_a"; 918 bias-disable; 919 drive-strength-microamp = <3000>; 920 }; 921 }; 922 923 tdm_a_dout1_pins: tdm-a-dout1 { 924 mux { 925 groups = "tdm_a_dout1"; 926 function = "tdm_a"; 927 bias-disable; 928 drive-strength-microamp = <3000>; 929 }; 930 }; 931 932 tdm_a_fs_pins: tdm-a-fs { 933 mux { 934 groups = "tdm_a_fs"; 935 function = "tdm_a"; 936 bias-disable; 937 drive-strength-microamp = <3000>; 938 }; 939 }; 940 941 tdm_a_sclk_pins: tdm-a-sclk { 942 mux { 943 groups = "tdm_a_sclk"; 944 function = "tdm_a"; 945 bias-disable; 946 drive-strength-microamp = <3000>; 947 }; 948 }; 949 950 tdm_a_slv_fs_pins: tdm-a-slv-fs { 951 mux { 952 groups = "tdm_a_slv_fs"; 953 function = "tdm_a"; 954 bias-disable; 955 }; 956 }; 957 958 959 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 960 mux { 961 groups = "tdm_a_slv_sclk"; 962 function = "tdm_a"; 963 bias-disable; 964 }; 965 }; 966 967 tdm_b_din0_pins: tdm-b-din0 { 968 mux { 969 groups = "tdm_b_din0"; 970 function = "tdm_b"; 971 bias-disable; 972 }; 973 }; 974 975 tdm_b_din1_pins: tdm-b-din1 { 976 mux { 977 groups = "tdm_b_din1"; 978 function = "tdm_b"; 979 bias-disable; 980 }; 981 }; 982 983 tdm_b_din2_pins: tdm-b-din2 { 984 mux { 985 groups = "tdm_b_din2"; 986 function = "tdm_b"; 987 bias-disable; 988 }; 989 }; 990 991 tdm_b_din3_a_pins: tdm-b-din3-a { 992 mux { 993 groups = "tdm_b_din3_a"; 994 function = "tdm_b"; 995 bias-disable; 996 }; 997 }; 998 999 tdm_b_din3_h_pins: tdm-b-din3-h { 1000 mux { 1001 groups = "tdm_b_din3_h"; 1002 function = "tdm_b"; 1003 bias-disable; 1004 }; 1005 }; 1006 1007 tdm_b_dout0_pins: tdm-b-dout0 { 1008 mux { 1009 groups = "tdm_b_dout0"; 1010 function = "tdm_b"; 1011 bias-disable; 1012 drive-strength-microamp = <3000>; 1013 }; 1014 }; 1015 1016 tdm_b_dout1_pins: tdm-b-dout1 { 1017 mux { 1018 groups = "tdm_b_dout1"; 1019 function = "tdm_b"; 1020 bias-disable; 1021 drive-strength-microamp = <3000>; 1022 }; 1023 }; 1024 1025 tdm_b_dout2_pins: tdm-b-dout2 { 1026 mux { 1027 groups = "tdm_b_dout2"; 1028 function = "tdm_b"; 1029 bias-disable; 1030 drive-strength-microamp = <3000>; 1031 }; 1032 }; 1033 1034 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1035 mux { 1036 groups = "tdm_b_dout3_a"; 1037 function = "tdm_b"; 1038 bias-disable; 1039 drive-strength-microamp = <3000>; 1040 }; 1041 }; 1042 1043 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1044 mux { 1045 groups = "tdm_b_dout3_h"; 1046 function = "tdm_b"; 1047 bias-disable; 1048 drive-strength-microamp = <3000>; 1049 }; 1050 }; 1051 1052 tdm_b_fs_pins: tdm-b-fs { 1053 mux { 1054 groups = "tdm_b_fs"; 1055 function = "tdm_b"; 1056 bias-disable; 1057 drive-strength-microamp = <3000>; 1058 }; 1059 }; 1060 1061 tdm_b_sclk_pins: tdm-b-sclk { 1062 mux { 1063 groups = "tdm_b_sclk"; 1064 function = "tdm_b"; 1065 bias-disable; 1066 drive-strength-microamp = <3000>; 1067 }; 1068 }; 1069 1070 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1071 mux { 1072 groups = "tdm_b_slv_fs"; 1073 function = "tdm_b"; 1074 bias-disable; 1075 }; 1076 }; 1077 1078 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1079 mux { 1080 groups = "tdm_b_slv_sclk"; 1081 function = "tdm_b"; 1082 bias-disable; 1083 }; 1084 }; 1085 1086 tdm_c_din0_a_pins: tdm-c-din0-a { 1087 mux { 1088 groups = "tdm_c_din0_a"; 1089 function = "tdm_c"; 1090 bias-disable; 1091 }; 1092 }; 1093 1094 tdm_c_din0_z_pins: tdm-c-din0-z { 1095 mux { 1096 groups = "tdm_c_din0_z"; 1097 function = "tdm_c"; 1098 bias-disable; 1099 }; 1100 }; 1101 1102 tdm_c_din1_a_pins: tdm-c-din1-a { 1103 mux { 1104 groups = "tdm_c_din1_a"; 1105 function = "tdm_c"; 1106 bias-disable; 1107 }; 1108 }; 1109 1110 tdm_c_din1_z_pins: tdm-c-din1-z { 1111 mux { 1112 groups = "tdm_c_din1_z"; 1113 function = "tdm_c"; 1114 bias-disable; 1115 }; 1116 }; 1117 1118 tdm_c_din2_a_pins: tdm-c-din2-a { 1119 mux { 1120 groups = "tdm_c_din2_a"; 1121 function = "tdm_c"; 1122 bias-disable; 1123 }; 1124 }; 1125 1126 eth_leds_pins: eth-leds { 1127 mux { 1128 groups = "eth_link_led", 1129 "eth_act_led"; 1130 function = "eth"; 1131 bias-disable; 1132 }; 1133 }; 1134 1135 eth_pins: eth { 1136 mux { 1137 groups = "eth_mdio", 1138 "eth_mdc", 1139 "eth_rgmii_rx_clk", 1140 "eth_rx_dv", 1141 "eth_rxd0", 1142 "eth_rxd1", 1143 "eth_txen", 1144 "eth_txd0", 1145 "eth_txd1"; 1146 function = "eth"; 1147 drive-strength-microamp = <4000>; 1148 bias-disable; 1149 }; 1150 }; 1151 1152 eth_rgmii_pins: eth-rgmii { 1153 mux { 1154 groups = "eth_rxd2_rgmii", 1155 "eth_rxd3_rgmii", 1156 "eth_rgmii_tx_clk", 1157 "eth_txd2_rgmii", 1158 "eth_txd3_rgmii"; 1159 function = "eth"; 1160 drive-strength-microamp = <4000>; 1161 bias-disable; 1162 }; 1163 }; 1164 1165 tdm_c_din2_z_pins: tdm-c-din2-z { 1166 mux { 1167 groups = "tdm_c_din2_z"; 1168 function = "tdm_c"; 1169 bias-disable; 1170 }; 1171 }; 1172 1173 tdm_c_din3_a_pins: tdm-c-din3-a { 1174 mux { 1175 groups = "tdm_c_din3_a"; 1176 function = "tdm_c"; 1177 bias-disable; 1178 }; 1179 }; 1180 1181 tdm_c_din3_z_pins: tdm-c-din3-z { 1182 mux { 1183 groups = "tdm_c_din3_z"; 1184 function = "tdm_c"; 1185 bias-disable; 1186 }; 1187 }; 1188 1189 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1190 mux { 1191 groups = "tdm_c_dout0_a"; 1192 function = "tdm_c"; 1193 bias-disable; 1194 drive-strength-microamp = <3000>; 1195 }; 1196 }; 1197 1198 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1199 mux { 1200 groups = "tdm_c_dout0_z"; 1201 function = "tdm_c"; 1202 bias-disable; 1203 drive-strength-microamp = <3000>; 1204 }; 1205 }; 1206 1207 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1208 mux { 1209 groups = "tdm_c_dout1_a"; 1210 function = "tdm_c"; 1211 bias-disable; 1212 drive-strength-microamp = <3000>; 1213 }; 1214 }; 1215 1216 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1217 mux { 1218 groups = "tdm_c_dout1_z"; 1219 function = "tdm_c"; 1220 bias-disable; 1221 drive-strength-microamp = <3000>; 1222 }; 1223 }; 1224 1225 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1226 mux { 1227 groups = "tdm_c_dout2_a"; 1228 function = "tdm_c"; 1229 bias-disable; 1230 drive-strength-microamp = <3000>; 1231 }; 1232 }; 1233 1234 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1235 mux { 1236 groups = "tdm_c_dout2_z"; 1237 function = "tdm_c"; 1238 bias-disable; 1239 drive-strength-microamp = <3000>; 1240 }; 1241 }; 1242 1243 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1244 mux { 1245 groups = "tdm_c_dout3_a"; 1246 function = "tdm_c"; 1247 bias-disable; 1248 drive-strength-microamp = <3000>; 1249 }; 1250 }; 1251 1252 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1253 mux { 1254 groups = "tdm_c_dout3_z"; 1255 function = "tdm_c"; 1256 bias-disable; 1257 drive-strength-microamp = <3000>; 1258 }; 1259 }; 1260 1261 tdm_c_fs_a_pins: tdm-c-fs-a { 1262 mux { 1263 groups = "tdm_c_fs_a"; 1264 function = "tdm_c"; 1265 bias-disable; 1266 drive-strength-microamp = <3000>; 1267 }; 1268 }; 1269 1270 tdm_c_fs_z_pins: tdm-c-fs-z { 1271 mux { 1272 groups = "tdm_c_fs_z"; 1273 function = "tdm_c"; 1274 bias-disable; 1275 drive-strength-microamp = <3000>; 1276 }; 1277 }; 1278 1279 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1280 mux { 1281 groups = "tdm_c_sclk_a"; 1282 function = "tdm_c"; 1283 bias-disable; 1284 drive-strength-microamp = <3000>; 1285 }; 1286 }; 1287 1288 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1289 mux { 1290 groups = "tdm_c_sclk_z"; 1291 function = "tdm_c"; 1292 bias-disable; 1293 drive-strength-microamp = <3000>; 1294 }; 1295 }; 1296 1297 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1298 mux { 1299 groups = "tdm_c_slv_fs_a"; 1300 function = "tdm_c"; 1301 bias-disable; 1302 }; 1303 }; 1304 1305 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1306 mux { 1307 groups = "tdm_c_slv_fs_z"; 1308 function = "tdm_c"; 1309 bias-disable; 1310 }; 1311 }; 1312 1313 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1314 mux { 1315 groups = "tdm_c_slv_sclk_a"; 1316 function = "tdm_c"; 1317 bias-disable; 1318 }; 1319 }; 1320 1321 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1322 mux { 1323 groups = "tdm_c_slv_sclk_z"; 1324 function = "tdm_c"; 1325 bias-disable; 1326 }; 1327 }; 1328 1329 sdio_pins: sdio { 1330 mux { 1331 groups = "sdio_d0", 1332 "sdio_d1", 1333 "sdio_d2", 1334 "sdio_d3", 1335 "sdio_cmd", 1336 "sdio_clk"; 1337 function = "sdio"; 1338 bias-disable; 1339 drive-strength-microamp = <4000>; 1340 }; 1341 }; 1342 1343 sdio_clk_gate_pins: sdio_clk_gate { 1344 mux { 1345 groups = "GPIOX_4"; 1346 function = "gpio_periphs"; 1347 bias-pull-down; 1348 drive-strength-microamp = <4000>; 1349 }; 1350 }; 1351 1352 1353 uart_a_pins: uart-a { 1354 mux { 1355 groups = "uart_a_tx", 1356 "uart_a_rx"; 1357 function = "uart_a"; 1358 bias-disable; 1359 }; 1360 }; 1361 1362 uart_a_cts_rts_pins: uart-a-cts-rts { 1363 mux { 1364 groups = "uart_a_cts", 1365 "uart_a_rts"; 1366 function = "uart_a"; 1367 bias-disable; 1368 }; 1369 }; 1370 1371 uart_b_pins: uart-b { 1372 mux { 1373 groups = "uart_b_tx", 1374 "uart_b_rx"; 1375 function = "uart_b"; 1376 bias-disable; 1377 }; 1378 }; 1379 1380 uart_c_pins: uart-c { 1381 mux { 1382 groups = "uart_c_tx", 1383 "uart_c_rx"; 1384 function = "uart_c"; 1385 bias-disable; 1386 }; 1387 }; 1388 1389 uart_c_cts_rts_pins: uart-c-cts-rts { 1390 mux { 1391 groups = "uart_c_cts", 1392 "uart_c_rts"; 1393 function = "uart_c"; 1394 bias-disable; 1395 }; 1396 }; 1397 }; 1398 }; 1399 1400 usb2_phy0: phy@36000 { 1401 compatible = "amlogic,g12a-usb2-phy"; 1402 reg = <0x0 0x36000 0x0 0x2000>; 1403 clocks = <&xtal>; 1404 clock-names = "xtal"; 1405 resets = <&reset RESET_USB_PHY20>; 1406 reset-names = "phy"; 1407 #phy-cells = <0>; 1408 }; 1409 1410 dmc: bus@38000 { 1411 compatible = "simple-bus"; 1412 reg = <0x0 0x38000 0x0 0x400>; 1413 #address-cells = <2>; 1414 #size-cells = <2>; 1415 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1416 1417 canvas: video-lut@48 { 1418 compatible = "amlogic,canvas"; 1419 reg = <0x0 0x48 0x0 0x14>; 1420 }; 1421 }; 1422 1423 usb2_phy1: phy@3a000 { 1424 compatible = "amlogic,g12a-usb2-phy"; 1425 reg = <0x0 0x3a000 0x0 0x2000>; 1426 clocks = <&xtal>; 1427 clock-names = "xtal"; 1428 resets = <&reset RESET_USB_PHY21>; 1429 reset-names = "phy"; 1430 #phy-cells = <0>; 1431 }; 1432 1433 hiu: bus@3c000 { 1434 compatible = "simple-bus"; 1435 reg = <0x0 0x3c000 0x0 0x1400>; 1436 #address-cells = <2>; 1437 #size-cells = <2>; 1438 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1439 1440 hhi: system-controller@0 { 1441 compatible = "amlogic,meson-gx-hhi-sysctrl", 1442 "simple-mfd", "syscon"; 1443 reg = <0 0 0 0x400>; 1444 1445 clkc: clock-controller { 1446 compatible = "amlogic,g12a-clkc"; 1447 #clock-cells = <1>; 1448 clocks = <&xtal>; 1449 clock-names = "xtal"; 1450 }; 1451 }; 1452 }; 1453 1454 pdm: audio-controller@40000 { 1455 compatible = "amlogic,g12a-pdm", 1456 "amlogic,axg-pdm"; 1457 reg = <0x0 0x40000 0x0 0x34>; 1458 #sound-dai-cells = <0>; 1459 sound-name-prefix = "PDM"; 1460 clocks = <&clkc_audio AUD_CLKID_PDM>, 1461 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1462 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1463 clock-names = "pclk", "dclk", "sysclk"; 1464 status = "disabled"; 1465 }; 1466 1467 audio: bus@42000 { 1468 compatible = "simple-bus"; 1469 reg = <0x0 0x42000 0x0 0x2000>; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1473 1474 clkc_audio: clock-controller@0 { 1475 status = "disabled"; 1476 compatible = "amlogic,g12a-audio-clkc"; 1477 reg = <0x0 0x0 0x0 0xb4>; 1478 #clock-cells = <1>; 1479 1480 clocks = <&clkc CLKID_AUDIO>, 1481 <&clkc CLKID_MPLL0>, 1482 <&clkc CLKID_MPLL1>, 1483 <&clkc CLKID_MPLL2>, 1484 <&clkc CLKID_MPLL3>, 1485 <&clkc CLKID_HIFI_PLL>, 1486 <&clkc CLKID_FCLK_DIV3>, 1487 <&clkc CLKID_FCLK_DIV4>, 1488 <&clkc CLKID_GP0_PLL>; 1489 clock-names = "pclk", 1490 "mst_in0", 1491 "mst_in1", 1492 "mst_in2", 1493 "mst_in3", 1494 "mst_in4", 1495 "mst_in5", 1496 "mst_in6", 1497 "mst_in7"; 1498 1499 resets = <&reset RESET_AUDIO>; 1500 }; 1501 1502 toddr_a: audio-controller@100 { 1503 compatible = "amlogic,g12a-toddr", 1504 "amlogic,axg-toddr"; 1505 reg = <0x0 0x100 0x0 0x1c>; 1506 #sound-dai-cells = <0>; 1507 sound-name-prefix = "TODDR_A"; 1508 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1509 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1510 resets = <&arb AXG_ARB_TODDR_A>; 1511 status = "disabled"; 1512 }; 1513 1514 toddr_b: audio-controller@140 { 1515 compatible = "amlogic,g12a-toddr", 1516 "amlogic,axg-toddr"; 1517 reg = <0x0 0x140 0x0 0x1c>; 1518 #sound-dai-cells = <0>; 1519 sound-name-prefix = "TODDR_B"; 1520 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1521 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1522 resets = <&arb AXG_ARB_TODDR_B>; 1523 status = "disabled"; 1524 }; 1525 1526 toddr_c: audio-controller@180 { 1527 compatible = "amlogic,g12a-toddr", 1528 "amlogic,axg-toddr"; 1529 reg = <0x0 0x180 0x0 0x1c>; 1530 #sound-dai-cells = <0>; 1531 sound-name-prefix = "TODDR_C"; 1532 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1533 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1534 resets = <&arb AXG_ARB_TODDR_C>; 1535 status = "disabled"; 1536 }; 1537 1538 frddr_a: audio-controller@1c0 { 1539 compatible = "amlogic,g12a-frddr", 1540 "amlogic,axg-frddr"; 1541 reg = <0x0 0x1c0 0x0 0x1c>; 1542 #sound-dai-cells = <0>; 1543 sound-name-prefix = "FRDDR_A"; 1544 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1545 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1546 resets = <&arb AXG_ARB_FRDDR_A>; 1547 status = "disabled"; 1548 }; 1549 1550 frddr_b: audio-controller@200 { 1551 compatible = "amlogic,g12a-frddr", 1552 "amlogic,axg-frddr"; 1553 reg = <0x0 0x200 0x0 0x1c>; 1554 #sound-dai-cells = <0>; 1555 sound-name-prefix = "FRDDR_B"; 1556 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1557 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1558 resets = <&arb AXG_ARB_FRDDR_B>; 1559 status = "disabled"; 1560 }; 1561 1562 frddr_c: audio-controller@240 { 1563 compatible = "amlogic,g12a-frddr", 1564 "amlogic,axg-frddr"; 1565 reg = <0x0 0x240 0x0 0x1c>; 1566 #sound-dai-cells = <0>; 1567 sound-name-prefix = "FRDDR_C"; 1568 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1569 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1570 resets = <&arb AXG_ARB_FRDDR_C>; 1571 status = "disabled"; 1572 }; 1573 1574 arb: reset-controller@280 { 1575 status = "disabled"; 1576 compatible = "amlogic,meson-axg-audio-arb"; 1577 reg = <0x0 0x280 0x0 0x4>; 1578 #reset-cells = <1>; 1579 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1580 }; 1581 1582 tdmin_a: audio-controller@300 { 1583 compatible = "amlogic,g12a-tdmin", 1584 "amlogic,axg-tdmin"; 1585 reg = <0x0 0x300 0x0 0x40>; 1586 sound-name-prefix = "TDMIN_A"; 1587 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1588 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1589 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1590 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1591 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1592 clock-names = "pclk", "sclk", "sclk_sel", 1593 "lrclk", "lrclk_sel"; 1594 status = "disabled"; 1595 }; 1596 1597 tdmin_b: audio-controller@340 { 1598 compatible = "amlogic,g12a-tdmin", 1599 "amlogic,axg-tdmin"; 1600 reg = <0x0 0x340 0x0 0x40>; 1601 sound-name-prefix = "TDMIN_B"; 1602 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1603 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1604 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1605 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1606 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1607 clock-names = "pclk", "sclk", "sclk_sel", 1608 "lrclk", "lrclk_sel"; 1609 status = "disabled"; 1610 }; 1611 1612 tdmin_c: audio-controller@380 { 1613 compatible = "amlogic,g12a-tdmin", 1614 "amlogic,axg-tdmin"; 1615 reg = <0x0 0x380 0x0 0x40>; 1616 sound-name-prefix = "TDMIN_C"; 1617 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1618 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1619 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1620 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1621 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1622 clock-names = "pclk", "sclk", "sclk_sel", 1623 "lrclk", "lrclk_sel"; 1624 status = "disabled"; 1625 }; 1626 1627 tdmin_lb: audio-controller@3c0 { 1628 compatible = "amlogic,g12a-tdmin", 1629 "amlogic,axg-tdmin"; 1630 reg = <0x0 0x3c0 0x0 0x40>; 1631 sound-name-prefix = "TDMIN_LB"; 1632 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1633 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1634 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1635 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1636 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1637 clock-names = "pclk", "sclk", "sclk_sel", 1638 "lrclk", "lrclk_sel"; 1639 status = "disabled"; 1640 }; 1641 1642 spdifin: audio-controller@400 { 1643 compatible = "amlogic,g12a-spdifin", 1644 "amlogic,axg-spdifin"; 1645 reg = <0x0 0x400 0x0 0x30>; 1646 #sound-dai-cells = <0>; 1647 sound-name-prefix = "SPDIFIN"; 1648 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1649 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1650 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1651 clock-names = "pclk", "refclk"; 1652 status = "disabled"; 1653 }; 1654 1655 spdifout: audio-controller@480 { 1656 compatible = "amlogic,g12a-spdifout", 1657 "amlogic,axg-spdifout"; 1658 reg = <0x0 0x480 0x0 0x50>; 1659 #sound-dai-cells = <0>; 1660 sound-name-prefix = "SPDIFOUT"; 1661 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1662 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1663 clock-names = "pclk", "mclk"; 1664 status = "disabled"; 1665 }; 1666 1667 tdmout_a: audio-controller@500 { 1668 compatible = "amlogic,g12a-tdmout"; 1669 reg = <0x0 0x500 0x0 0x40>; 1670 sound-name-prefix = "TDMOUT_A"; 1671 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1672 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1673 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1674 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1675 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1676 clock-names = "pclk", "sclk", "sclk_sel", 1677 "lrclk", "lrclk_sel"; 1678 status = "disabled"; 1679 }; 1680 1681 tdmout_b: audio-controller@540 { 1682 compatible = "amlogic,g12a-tdmout"; 1683 reg = <0x0 0x540 0x0 0x40>; 1684 sound-name-prefix = "TDMOUT_B"; 1685 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1686 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1687 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1688 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1689 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1690 clock-names = "pclk", "sclk", "sclk_sel", 1691 "lrclk", "lrclk_sel"; 1692 status = "disabled"; 1693 }; 1694 1695 tdmout_c: audio-controller@580 { 1696 compatible = "amlogic,g12a-tdmout"; 1697 reg = <0x0 0x580 0x0 0x40>; 1698 sound-name-prefix = "TDMOUT_C"; 1699 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1700 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1701 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1702 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1703 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1704 clock-names = "pclk", "sclk", "sclk_sel", 1705 "lrclk", "lrclk_sel"; 1706 status = "disabled"; 1707 }; 1708 1709 spdifout_b: audio-controller@680 { 1710 compatible = "amlogic,g12a-spdifout", 1711 "amlogic,axg-spdifout"; 1712 reg = <0x0 0x680 0x0 0x50>; 1713 #sound-dai-cells = <0>; 1714 sound-name-prefix = "SPDIFOUT_B"; 1715 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1716 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1717 clock-names = "pclk", "mclk"; 1718 status = "disabled"; 1719 }; 1720 1721 tohdmitx: audio-controller@744 { 1722 compatible = "amlogic,g12a-tohdmitx"; 1723 reg = <0x0 0x744 0x0 0x4>; 1724 #sound-dai-cells = <1>; 1725 sound-name-prefix = "TOHDMITX"; 1726 status = "disabled"; 1727 }; 1728 }; 1729 1730 usb3_pcie_phy: phy@46000 { 1731 compatible = "amlogic,g12a-usb3-pcie-phy"; 1732 reg = <0x0 0x46000 0x0 0x2000>; 1733 clocks = <&clkc CLKID_PCIE_PLL>; 1734 clock-names = "ref_clk"; 1735 resets = <&reset RESET_PCIE_PHY>; 1736 reset-names = "phy"; 1737 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1738 assigned-clock-rates = <100000000>; 1739 #phy-cells = <1>; 1740 }; 1741 1742 eth_phy: mdio-multiplexer@4c000 { 1743 compatible = "amlogic,g12a-mdio-mux"; 1744 reg = <0x0 0x4c000 0x0 0xa4>; 1745 clocks = <&clkc CLKID_ETH_PHY>, 1746 <&xtal>, 1747 <&clkc CLKID_MPLL_50M>; 1748 clock-names = "pclk", "clkin0", "clkin1"; 1749 mdio-parent-bus = <&mdio0>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 1753 ext_mdio: mdio@0 { 1754 reg = <0>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 }; 1758 1759 int_mdio: mdio@1 { 1760 reg = <1>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 1764 internal_ephy: ethernet_phy@8 { 1765 compatible = "ethernet-phy-id0180.3301", 1766 "ethernet-phy-ieee802.3-c22"; 1767 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1768 reg = <8>; 1769 max-speed = <100>; 1770 }; 1771 }; 1772 }; 1773 }; 1774 1775 aobus: bus@ff800000 { 1776 compatible = "simple-bus"; 1777 reg = <0x0 0xff800000 0x0 0x100000>; 1778 #address-cells = <2>; 1779 #size-cells = <2>; 1780 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1781 1782 rti: sys-ctrl@0 { 1783 compatible = "amlogic,meson-gx-ao-sysctrl", 1784 "simple-mfd", "syscon"; 1785 reg = <0x0 0x0 0x0 0x100>; 1786 #address-cells = <2>; 1787 #size-cells = <2>; 1788 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1789 1790 clkc_AO: clock-controller { 1791 compatible = "amlogic,meson-g12a-aoclkc"; 1792 #clock-cells = <1>; 1793 #reset-cells = <1>; 1794 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1795 clock-names = "xtal", "mpeg-clk"; 1796 }; 1797 1798 pwrc_vpu: power-controller-vpu { 1799 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1800 #power-domain-cells = <0>; 1801 amlogic,hhi-sysctrl = <&hhi>; 1802 resets = <&reset RESET_VIU>, 1803 <&reset RESET_VENC>, 1804 <&reset RESET_VCBUS>, 1805 <&reset RESET_BT656>, 1806 <&reset RESET_RDMA>, 1807 <&reset RESET_VENCI>, 1808 <&reset RESET_VENCP>, 1809 <&reset RESET_VDAC>, 1810 <&reset RESET_VDI6>, 1811 <&reset RESET_VENCL>, 1812 <&reset RESET_VID_LOCK>; 1813 clocks = <&clkc CLKID_VPU>, 1814 <&clkc CLKID_VAPB>; 1815 clock-names = "vpu", "vapb"; 1816 /* 1817 * VPU clocking is provided by two identical clock paths 1818 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1819 * free mux to safely change frequency while running. 1820 * Same for VAPB but with a final gate after the glitch free mux. 1821 */ 1822 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1823 <&clkc CLKID_VPU_0>, 1824 <&clkc CLKID_VPU>, /* Glitch free mux */ 1825 <&clkc CLKID_VAPB_0_SEL>, 1826 <&clkc CLKID_VAPB_0>, 1827 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1828 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1829 <0>, /* Do Nothing */ 1830 <&clkc CLKID_VPU_0>, 1831 <&clkc CLKID_FCLK_DIV4>, 1832 <0>, /* Do Nothing */ 1833 <&clkc CLKID_VAPB_0>; 1834 assigned-clock-rates = <0>, /* Do Nothing */ 1835 <666666666>, 1836 <0>, /* Do Nothing */ 1837 <0>, /* Do Nothing */ 1838 <250000000>, 1839 <0>; /* Do Nothing */ 1840 }; 1841 1842 ao_pinctrl: pinctrl@14 { 1843 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1844 #address-cells = <2>; 1845 #size-cells = <2>; 1846 ranges; 1847 1848 gpio_ao: bank@14 { 1849 reg = <0x0 0x14 0x0 0x8>, 1850 <0x0 0x1c 0x0 0x8>, 1851 <0x0 0x24 0x0 0x14>; 1852 reg-names = "mux", 1853 "ds", 1854 "gpio"; 1855 gpio-controller; 1856 #gpio-cells = <2>; 1857 gpio-ranges = <&ao_pinctrl 0 0 15>; 1858 }; 1859 1860 i2c_ao_sck_pins: i2c_ao_sck_pins { 1861 mux { 1862 groups = "i2c_ao_sck"; 1863 function = "i2c_ao"; 1864 bias-disable; 1865 drive-strength-microamp = <3000>; 1866 }; 1867 }; 1868 1869 i2c_ao_sda_pins: i2c_ao_sda { 1870 mux { 1871 groups = "i2c_ao_sda"; 1872 function = "i2c_ao"; 1873 bias-disable; 1874 drive-strength-microamp = <3000>; 1875 }; 1876 }; 1877 1878 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1879 mux { 1880 groups = "i2c_ao_sck_e"; 1881 function = "i2c_ao"; 1882 bias-disable; 1883 drive-strength-microamp = <3000>; 1884 }; 1885 }; 1886 1887 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1888 mux { 1889 groups = "i2c_ao_sda_e"; 1890 function = "i2c_ao"; 1891 bias-disable; 1892 drive-strength-microamp = <3000>; 1893 }; 1894 }; 1895 1896 mclk0_ao_pins: mclk0-ao { 1897 mux { 1898 groups = "mclk0_ao"; 1899 function = "mclk0_ao"; 1900 bias-disable; 1901 drive-strength-microamp = <3000>; 1902 }; 1903 }; 1904 1905 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1906 mux { 1907 groups = "tdm_ao_b_din0"; 1908 function = "tdm_ao_b"; 1909 bias-disable; 1910 }; 1911 }; 1912 1913 spdif_ao_out_pins: spdif-ao-out { 1914 mux { 1915 groups = "spdif_ao_out"; 1916 function = "spdif_ao_out"; 1917 drive-strength-microamp = <500>; 1918 bias-disable; 1919 }; 1920 }; 1921 1922 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1923 mux { 1924 groups = "tdm_ao_b_din1"; 1925 function = "tdm_ao_b"; 1926 bias-disable; 1927 }; 1928 }; 1929 1930 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1931 mux { 1932 groups = "tdm_ao_b_din2"; 1933 function = "tdm_ao_b"; 1934 bias-disable; 1935 }; 1936 }; 1937 1938 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1939 mux { 1940 groups = "tdm_ao_b_dout0"; 1941 function = "tdm_ao_b"; 1942 bias-disable; 1943 drive-strength-microamp = <3000>; 1944 }; 1945 }; 1946 1947 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1948 mux { 1949 groups = "tdm_ao_b_dout1"; 1950 function = "tdm_ao_b"; 1951 bias-disable; 1952 drive-strength-microamp = <3000>; 1953 }; 1954 }; 1955 1956 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1957 mux { 1958 groups = "tdm_ao_b_dout2"; 1959 function = "tdm_ao_b"; 1960 bias-disable; 1961 drive-strength-microamp = <3000>; 1962 }; 1963 }; 1964 1965 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1966 mux { 1967 groups = "tdm_ao_b_fs"; 1968 function = "tdm_ao_b"; 1969 bias-disable; 1970 drive-strength-microamp = <3000>; 1971 }; 1972 }; 1973 1974 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1975 mux { 1976 groups = "tdm_ao_b_sclk"; 1977 function = "tdm_ao_b"; 1978 bias-disable; 1979 drive-strength-microamp = <3000>; 1980 }; 1981 }; 1982 1983 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1984 mux { 1985 groups = "tdm_ao_b_slv_fs"; 1986 function = "tdm_ao_b"; 1987 bias-disable; 1988 }; 1989 }; 1990 1991 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1992 mux { 1993 groups = "tdm_ao_b_slv_sclk"; 1994 function = "tdm_ao_b"; 1995 bias-disable; 1996 }; 1997 }; 1998 1999 uart_ao_a_pins: uart-a-ao { 2000 mux { 2001 groups = "uart_ao_a_tx", 2002 "uart_ao_a_rx"; 2003 function = "uart_ao_a"; 2004 bias-disable; 2005 }; 2006 }; 2007 2008 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 2009 mux { 2010 groups = "uart_ao_a_cts", 2011 "uart_ao_a_rts"; 2012 function = "uart_ao_a"; 2013 bias-disable; 2014 }; 2015 }; 2016 2017 pwm_ao_a_pins: pwm-ao-a { 2018 mux { 2019 groups = "pwm_ao_a"; 2020 function = "pwm_ao_a"; 2021 bias-disable; 2022 }; 2023 }; 2024 2025 pwm_ao_b_pins: pwm-ao-b { 2026 mux { 2027 groups = "pwm_ao_b"; 2028 function = "pwm_ao_b"; 2029 bias-disable; 2030 }; 2031 }; 2032 2033 pwm_ao_c_4_pins: pwm-ao-c-4 { 2034 mux { 2035 groups = "pwm_ao_c_4"; 2036 function = "pwm_ao_c"; 2037 bias-disable; 2038 }; 2039 }; 2040 2041 pwm_ao_c_6_pins: pwm-ao-c-6 { 2042 mux { 2043 groups = "pwm_ao_c_6"; 2044 function = "pwm_ao_c"; 2045 bias-disable; 2046 }; 2047 }; 2048 2049 pwm_ao_d_5_pins: pwm-ao-d-5 { 2050 mux { 2051 groups = "pwm_ao_d_5"; 2052 function = "pwm_ao_d"; 2053 bias-disable; 2054 }; 2055 }; 2056 2057 pwm_ao_d_10_pins: pwm-ao-d-10 { 2058 mux { 2059 groups = "pwm_ao_d_10"; 2060 function = "pwm_ao_d"; 2061 bias-disable; 2062 }; 2063 }; 2064 2065 pwm_ao_d_e_pins: pwm-ao-d-e { 2066 mux { 2067 groups = "pwm_ao_d_e"; 2068 function = "pwm_ao_d"; 2069 }; 2070 }; 2071 2072 remote_input_ao_pins: remote-input-ao { 2073 mux { 2074 groups = "remote_ao_input"; 2075 function = "remote_ao_input"; 2076 bias-disable; 2077 }; 2078 }; 2079 }; 2080 }; 2081 2082 cec_AO: cec@100 { 2083 compatible = "amlogic,meson-gx-ao-cec"; 2084 reg = <0x0 0x00100 0x0 0x14>; 2085 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2086 clocks = <&clkc_AO CLKID_AO_CEC>; 2087 clock-names = "core"; 2088 status = "disabled"; 2089 }; 2090 2091 sec_AO: ao-secure@140 { 2092 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2093 reg = <0x0 0x140 0x0 0x140>; 2094 amlogic,has-chip-id; 2095 }; 2096 2097 cecb_AO: cec@280 { 2098 compatible = "amlogic,meson-g12a-ao-cec"; 2099 reg = <0x0 0x00280 0x0 0x1c>; 2100 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2101 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2102 clock-names = "oscin"; 2103 status = "disabled"; 2104 }; 2105 2106 pwm_AO_cd: pwm@2000 { 2107 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2108 reg = <0x0 0x2000 0x0 0x20>; 2109 #pwm-cells = <3>; 2110 status = "disabled"; 2111 }; 2112 2113 uart_AO: serial@3000 { 2114 compatible = "amlogic,meson-gx-uart", 2115 "amlogic,meson-ao-uart"; 2116 reg = <0x0 0x3000 0x0 0x18>; 2117 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2118 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2119 clock-names = "xtal", "pclk", "baud"; 2120 status = "disabled"; 2121 }; 2122 2123 uart_AO_B: serial@4000 { 2124 compatible = "amlogic,meson-gx-uart", 2125 "amlogic,meson-ao-uart"; 2126 reg = <0x0 0x4000 0x0 0x18>; 2127 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2128 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2129 clock-names = "xtal", "pclk", "baud"; 2130 status = "disabled"; 2131 }; 2132 2133 i2c_AO: i2c@5000 { 2134 compatible = "amlogic,meson-axg-i2c"; 2135 status = "disabled"; 2136 reg = <0x0 0x05000 0x0 0x20>; 2137 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 clocks = <&clkc CLKID_I2C>; 2141 }; 2142 2143 pwm_AO_ab: pwm@7000 { 2144 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2145 reg = <0x0 0x7000 0x0 0x20>; 2146 #pwm-cells = <3>; 2147 status = "disabled"; 2148 }; 2149 2150 ir: ir@8000 { 2151 compatible = "amlogic,meson-gxbb-ir"; 2152 reg = <0x0 0x8000 0x0 0x20>; 2153 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2154 status = "disabled"; 2155 }; 2156 2157 saradc: adc@9000 { 2158 compatible = "amlogic,meson-g12a-saradc", 2159 "amlogic,meson-saradc"; 2160 reg = <0x0 0x9000 0x0 0x48>; 2161 #io-channel-cells = <1>; 2162 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2163 clocks = <&xtal>, 2164 <&clkc_AO CLKID_AO_SAR_ADC>, 2165 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2166 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2167 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2168 status = "disabled"; 2169 }; 2170 }; 2171 2172 vpu: vpu@ff900000 { 2173 compatible = "amlogic,meson-g12a-vpu"; 2174 reg = <0x0 0xff900000 0x0 0x100000>, 2175 <0x0 0xff63c000 0x0 0x1000>; 2176 reg-names = "vpu", "hhi"; 2177 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2178 #address-cells = <1>; 2179 #size-cells = <0>; 2180 amlogic,canvas = <&canvas>; 2181 power-domains = <&pwrc_vpu>; 2182 2183 /* CVBS VDAC output port */ 2184 cvbs_vdac_port: port@0 { 2185 reg = <0>; 2186 }; 2187 2188 /* HDMI-TX output port */ 2189 hdmi_tx_port: port@1 { 2190 reg = <1>; 2191 2192 hdmi_tx_out: endpoint { 2193 remote-endpoint = <&hdmi_tx_in>; 2194 }; 2195 }; 2196 }; 2197 2198 gic: interrupt-controller@ffc01000 { 2199 compatible = "arm,gic-400"; 2200 reg = <0x0 0xffc01000 0 0x1000>, 2201 <0x0 0xffc02000 0 0x2000>, 2202 <0x0 0xffc04000 0 0x2000>, 2203 <0x0 0xffc06000 0 0x2000>; 2204 interrupt-controller; 2205 interrupts = <GIC_PPI 9 2206 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2207 #interrupt-cells = <3>; 2208 #address-cells = <0>; 2209 }; 2210 2211 cbus: bus@ffd00000 { 2212 compatible = "simple-bus"; 2213 reg = <0x0 0xffd00000 0x0 0x100000>; 2214 #address-cells = <2>; 2215 #size-cells = <2>; 2216 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2217 2218 reset: reset-controller@1004 { 2219 compatible = "amlogic,meson-g12a-reset", 2220 "amlogic,meson-axg-reset"; 2221 reg = <0x0 0x1004 0x0 0x9c>; 2222 #reset-cells = <1>; 2223 }; 2224 2225 pwm_ef: pwm@19000 { 2226 compatible = "amlogic,meson-g12a-ee-pwm"; 2227 reg = <0x0 0x19000 0x0 0x20>; 2228 #pwm-cells = <3>; 2229 status = "disabled"; 2230 }; 2231 2232 pwm_cd: pwm@1a000 { 2233 compatible = "amlogic,meson-g12a-ee-pwm"; 2234 reg = <0x0 0x1a000 0x0 0x20>; 2235 #pwm-cells = <3>; 2236 status = "disabled"; 2237 }; 2238 2239 pwm_ab: pwm@1b000 { 2240 compatible = "amlogic,meson-g12a-ee-pwm"; 2241 reg = <0x0 0x1b000 0x0 0x20>; 2242 #pwm-cells = <3>; 2243 status = "disabled"; 2244 }; 2245 2246 i2c3: i2c@1c000 { 2247 compatible = "amlogic,meson-axg-i2c"; 2248 status = "disabled"; 2249 reg = <0x0 0x1c000 0x0 0x20>; 2250 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2251 #address-cells = <1>; 2252 #size-cells = <0>; 2253 clocks = <&clkc CLKID_I2C>; 2254 }; 2255 2256 i2c2: i2c@1d000 { 2257 compatible = "amlogic,meson-axg-i2c"; 2258 status = "disabled"; 2259 reg = <0x0 0x1d000 0x0 0x20>; 2260 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 clocks = <&clkc CLKID_I2C>; 2264 }; 2265 2266 i2c1: i2c@1e000 { 2267 compatible = "amlogic,meson-axg-i2c"; 2268 status = "disabled"; 2269 reg = <0x0 0x1e000 0x0 0x20>; 2270 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 clocks = <&clkc CLKID_I2C>; 2274 }; 2275 2276 i2c0: i2c@1f000 { 2277 compatible = "amlogic,meson-axg-i2c"; 2278 status = "disabled"; 2279 reg = <0x0 0x1f000 0x0 0x20>; 2280 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2281 #address-cells = <1>; 2282 #size-cells = <0>; 2283 clocks = <&clkc CLKID_I2C>; 2284 }; 2285 2286 clk_msr: clock-measure@18000 { 2287 compatible = "amlogic,meson-g12a-clk-measure"; 2288 reg = <0x0 0x18000 0x0 0x10>; 2289 }; 2290 2291 uart_C: serial@22000 { 2292 compatible = "amlogic,meson-gx-uart"; 2293 reg = <0x0 0x22000 0x0 0x18>; 2294 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2295 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2296 clock-names = "xtal", "pclk", "baud"; 2297 status = "disabled"; 2298 }; 2299 2300 uart_B: serial@23000 { 2301 compatible = "amlogic,meson-gx-uart"; 2302 reg = <0x0 0x23000 0x0 0x18>; 2303 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2304 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2305 clock-names = "xtal", "pclk", "baud"; 2306 status = "disabled"; 2307 }; 2308 2309 uart_A: serial@24000 { 2310 compatible = "amlogic,meson-gx-uart"; 2311 reg = <0x0 0x24000 0x0 0x18>; 2312 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2313 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2314 clock-names = "xtal", "pclk", "baud"; 2315 status = "disabled"; 2316 }; 2317 }; 2318 2319 sd_emmc_b: sd@ffe05000 { 2320 compatible = "amlogic,meson-axg-mmc"; 2321 reg = <0x0 0xffe05000 0x0 0x800>; 2322 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2323 status = "disabled"; 2324 clocks = <&clkc CLKID_SD_EMMC_B>, 2325 <&clkc CLKID_SD_EMMC_B_CLK0>, 2326 <&clkc CLKID_FCLK_DIV2>; 2327 clock-names = "core", "clkin0", "clkin1"; 2328 resets = <&reset RESET_SD_EMMC_B>; 2329 }; 2330 2331 sd_emmc_c: mmc@ffe07000 { 2332 compatible = "amlogic,meson-axg-mmc"; 2333 reg = <0x0 0xffe07000 0x0 0x800>; 2334 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2335 status = "disabled"; 2336 clocks = <&clkc CLKID_SD_EMMC_C>, 2337 <&clkc CLKID_SD_EMMC_C_CLK0>, 2338 <&clkc CLKID_FCLK_DIV2>; 2339 clock-names = "core", "clkin0", "clkin1"; 2340 resets = <&reset RESET_SD_EMMC_C>; 2341 }; 2342 2343 sd_emmc_a: sd@ffe03000 { 2344 compatible = "amlogic,meson-axg-mmc"; 2345 reg = <0x0 0xffe03000 0x0 0x800>; 2346 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2347 status = "disabled"; 2348 clocks = <&clkc CLKID_SD_EMMC_A>, 2349 <&clkc CLKID_SD_EMMC_A_CLK0>, 2350 <&clkc CLKID_FCLK_DIV2>; 2351 clock-names = "core", "clkin0", "clkin1"; 2352 resets = <&reset RESET_SD_EMMC_A>; 2353 amlogic,dram-access-quirk; 2354 }; 2355 2356 usb: usb@ffe09000 { 2357 status = "disabled"; 2358 compatible = "amlogic,meson-g12a-usb-ctrl"; 2359 reg = <0x0 0xffe09000 0x0 0xa0>; 2360 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2361 #address-cells = <2>; 2362 #size-cells = <2>; 2363 ranges; 2364 2365 clocks = <&clkc CLKID_USB>; 2366 resets = <&reset RESET_USB>; 2367 2368 dr_mode = "otg"; 2369 2370 phys = <&usb2_phy0>, <&usb2_phy1>, 2371 <&usb3_pcie_phy PHY_TYPE_USB3>; 2372 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2373 2374 dwc2: usb@ff400000 { 2375 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2376 reg = <0x0 0xff400000 0x0 0x40000>; 2377 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2378 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2379 clock-names = "ddr"; 2380 phys = <&usb2_phy1>; 2381 dr_mode = "peripheral"; 2382 g-rx-fifo-size = <192>; 2383 g-np-tx-fifo-size = <128>; 2384 g-tx-fifo-size = <128 128 16 16 16>; 2385 }; 2386 2387 dwc3: usb@ff500000 { 2388 compatible = "snps,dwc3"; 2389 reg = <0x0 0xff500000 0x0 0x100000>; 2390 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2391 dr_mode = "host"; 2392 snps,dis_u2_susphy_quirk; 2393 snps,quirk-frame-length-adjustment; 2394 }; 2395 }; 2396 2397 mali: gpu@ffe40000 { 2398 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2399 reg = <0x0 0xffe40000 0x0 0x40000>; 2400 interrupt-parent = <&gic>; 2401 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2404 interrupt-names = "gpu", "mmu", "job"; 2405 clocks = <&clkc CLKID_MALI>; 2406 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2407 2408 /* 2409 * Mali clocking is provided by two identical clock paths 2410 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2411 * free mux to safely change frequency while running. 2412 */ 2413 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2414 <&clkc CLKID_MALI_0>, 2415 <&clkc CLKID_MALI>; /* Glitch free mux */ 2416 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2417 <0>, /* Do Nothing */ 2418 <&clkc CLKID_MALI_0>; 2419 assigned-clock-rates = <0>, /* Do Nothing */ 2420 <800000000>, 2421 <0>; /* Do Nothing */ 2422 }; 2423 }; 2424 2425 timer { 2426 compatible = "arm,armv8-timer"; 2427 interrupts = <GIC_PPI 13 2428 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2429 <GIC_PPI 14 2430 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2431 <GIC_PPI 11 2432 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2433 <GIC_PPI 10 2434 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2435 }; 2436 2437 xtal: xtal-clk { 2438 compatible = "fixed-clock"; 2439 clock-frequency = <24000000>; 2440 clock-output-names = "xtal"; 2441 #clock-cells = <0>; 2442 }; 2443 2444}; 2445