1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 apb: bus@ff600000 { 141 compatible = "simple-bus"; 142 reg = <0x0 0xff600000 0x0 0x200000>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 146 147 hdmi_tx: hdmi-tx@0 { 148 compatible = "amlogic,meson-g12a-dw-hdmi"; 149 reg = <0x0 0x0 0x0 0x10000>; 150 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 151 resets = <&reset RESET_HDMITX_CAPB3>, 152 <&reset RESET_HDMITX_PHY>, 153 <&reset RESET_HDMITX>; 154 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 155 clocks = <&clkc CLKID_HDMI>, 156 <&clkc CLKID_HTX_PCLK>, 157 <&clkc CLKID_VPU_INTR>; 158 clock-names = "isfr", "iahb", "venci"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 163 /* VPU VENC Input */ 164 hdmi_tx_venc_port: port@0 { 165 reg = <0>; 166 167 hdmi_tx_in: endpoint { 168 remote-endpoint = <&hdmi_tx_out>; 169 }; 170 }; 171 172 /* TMDS Output */ 173 hdmi_tx_tmds_port: port@1 { 174 reg = <1>; 175 }; 176 }; 177 178 periphs: bus@34400 { 179 compatible = "simple-bus"; 180 reg = <0x0 0x34400 0x0 0x400>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 184 185 periphs_pinctrl: pinctrl@40 { 186 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 gpio: bank@40 { 192 reg = <0x0 0x40 0x0 0x4c>, 193 <0x0 0xe8 0x0 0x18>, 194 <0x0 0x120 0x0 0x18>, 195 <0x0 0x2c0 0x0 0x40>, 196 <0x0 0x340 0x0 0x1c>; 197 reg-names = "gpio", 198 "pull", 199 "pull-enable", 200 "mux", 201 "ds"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&periphs_pinctrl 0 0 86>; 205 }; 206 207 cec_ao_a_h_pins: cec_ao_a_h { 208 mux { 209 groups = "cec_ao_a_h"; 210 function = "cec_ao_a_h"; 211 bias-disable; 212 }; 213 }; 214 215 cec_ao_b_h_pins: cec_ao_b_h { 216 mux { 217 groups = "cec_ao_b_h"; 218 function = "cec_ao_b_h"; 219 bias-disable; 220 }; 221 }; 222 223 emmc_pins: emmc { 224 mux-0 { 225 groups = "emmc_nand_d0", 226 "emmc_nand_d1", 227 "emmc_nand_d2", 228 "emmc_nand_d3", 229 "emmc_nand_d4", 230 "emmc_nand_d5", 231 "emmc_nand_d6", 232 "emmc_nand_d7", 233 "emmc_cmd"; 234 function = "emmc"; 235 bias-pull-up; 236 drive-strength-microamp = <4000>; 237 }; 238 239 mux-1 { 240 groups = "emmc_clk"; 241 function = "emmc"; 242 bias-disable; 243 drive-strength-microamp = <4000>; 244 }; 245 }; 246 247 emmc_ds_pins: emmc-ds { 248 mux { 249 groups = "emmc_nand_ds"; 250 function = "emmc"; 251 bias-pull-down; 252 drive-strength-microamp = <4000>; 253 }; 254 }; 255 256 emmc_clk_gate_pins: emmc_clk_gate { 257 mux { 258 groups = "BOOT_8"; 259 function = "gpio_periphs"; 260 bias-pull-down; 261 drive-strength-microamp = <4000>; 262 }; 263 }; 264 265 hdmitx_ddc_pins: hdmitx_ddc { 266 mux { 267 groups = "hdmitx_sda", 268 "hdmitx_sck"; 269 function = "hdmitx"; 270 bias-disable; 271 }; 272 }; 273 274 hdmitx_hpd_pins: hdmitx_hpd { 275 mux { 276 groups = "hdmitx_hpd_in"; 277 function = "hdmitx"; 278 bias-disable; 279 }; 280 }; 281 282 283 i2c0_sda_c_pins: i2c0-sda-c { 284 mux { 285 groups = "i2c0_sda_c"; 286 function = "i2c0"; 287 bias-disable; 288 drive-strength-microamp = <3000>; 289 290 }; 291 }; 292 293 i2c0_sck_c_pins: i2c0-sck-c { 294 mux { 295 groups = "i2c0_sck_c"; 296 function = "i2c0"; 297 bias-disable; 298 drive-strength-microamp = <3000>; 299 }; 300 }; 301 302 i2c0_sda_z0_pins: i2c0-sda-z0 { 303 mux { 304 groups = "i2c0_sda_z0"; 305 function = "i2c0"; 306 bias-disable; 307 drive-strength-microamp = <3000>; 308 }; 309 }; 310 311 i2c0_sck_z1_pins: i2c0-sck-z1 { 312 mux { 313 groups = "i2c0_sck_z1"; 314 function = "i2c0"; 315 bias-disable; 316 drive-strength-microamp = <3000>; 317 }; 318 }; 319 320 i2c0_sda_z7_pins: i2c0-sda-z7 { 321 mux { 322 groups = "i2c0_sda_z7"; 323 function = "i2c0"; 324 bias-disable; 325 drive-strength-microamp = <3000>; 326 }; 327 }; 328 329 i2c0_sda_z8_pins: i2c0-sda-z8 { 330 mux { 331 groups = "i2c0_sda_z8"; 332 function = "i2c0"; 333 bias-disable; 334 drive-strength-microamp = <3000>; 335 }; 336 }; 337 338 i2c1_sda_x_pins: i2c1-sda-x { 339 mux { 340 groups = "i2c1_sda_x"; 341 function = "i2c1"; 342 bias-disable; 343 drive-strength-microamp = <3000>; 344 }; 345 }; 346 347 i2c1_sck_x_pins: i2c1-sck-x { 348 mux { 349 groups = "i2c1_sck_x"; 350 function = "i2c1"; 351 bias-disable; 352 drive-strength-microamp = <3000>; 353 }; 354 }; 355 356 i2c1_sda_h2_pins: i2c1-sda-h2 { 357 mux { 358 groups = "i2c1_sda_h2"; 359 function = "i2c1"; 360 bias-disable; 361 drive-strength-microamp = <3000>; 362 }; 363 }; 364 365 i2c1_sck_h3_pins: i2c1-sck-h3 { 366 mux { 367 groups = "i2c1_sck_h3"; 368 function = "i2c1"; 369 bias-disable; 370 drive-strength-microamp = <3000>; 371 }; 372 }; 373 374 i2c1_sda_h6_pins: i2c1-sda-h6 { 375 mux { 376 groups = "i2c1_sda_h6"; 377 function = "i2c1"; 378 bias-disable; 379 drive-strength-microamp = <3000>; 380 }; 381 }; 382 383 i2c1_sck_h7_pins: i2c1-sck-h7 { 384 mux { 385 groups = "i2c1_sck_h7"; 386 function = "i2c1"; 387 bias-disable; 388 drive-strength-microamp = <3000>; 389 }; 390 }; 391 392 i2c2_sda_x_pins: i2c2-sda-x { 393 mux { 394 groups = "i2c2_sda_x"; 395 function = "i2c2"; 396 bias-disable; 397 drive-strength-microamp = <3000>; 398 }; 399 }; 400 401 i2c2_sck_x_pins: i2c2-sck-x { 402 mux { 403 groups = "i2c2_sck_x"; 404 function = "i2c2"; 405 bias-disable; 406 drive-strength-microamp = <3000>; 407 }; 408 }; 409 410 i2c2_sda_z_pins: i2c2-sda-z { 411 mux { 412 groups = "i2c2_sda_z"; 413 function = "i2c2"; 414 bias-disable; 415 drive-strength-microamp = <3000>; 416 }; 417 }; 418 419 i2c2_sck_z_pins: i2c2-sck-z { 420 mux { 421 groups = "i2c2_sck_z"; 422 function = "i2c2"; 423 bias-disable; 424 drive-strength-microamp = <3000>; 425 }; 426 }; 427 428 i2c3_sda_h_pins: i2c3-sda-h { 429 mux { 430 groups = "i2c3_sda_h"; 431 function = "i2c3"; 432 bias-disable; 433 drive-strength-microamp = <3000>; 434 }; 435 }; 436 437 i2c3_sck_h_pins: i2c3-sck-h { 438 mux { 439 groups = "i2c3_sck_h"; 440 function = "i2c3"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c3_sda_a_pins: i2c3-sda-a { 447 mux { 448 groups = "i2c3_sda_a"; 449 function = "i2c3"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c3_sck_a_pins: i2c3-sck-a { 456 mux { 457 groups = "i2c3_sck_a"; 458 function = "i2c3"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 mclk0_a_pins: mclk0-a { 465 mux { 466 groups = "mclk0_a"; 467 function = "mclk0"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 mclk1_a_pins: mclk1-a { 474 mux { 475 groups = "mclk1_a"; 476 function = "mclk1"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 mclk1_x_pins: mclk1-x { 483 mux { 484 groups = "mclk1_x"; 485 function = "mclk1"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 mclk1_z_pins: mclk1-z { 492 mux { 493 groups = "mclk1_z"; 494 function = "mclk1"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 pdm_din0_a_pins: pdm-din0-a { 501 mux { 502 groups = "pdm_din0_a"; 503 function = "pdm"; 504 bias-disable; 505 }; 506 }; 507 508 pdm_din0_c_pins: pdm-din0-c { 509 mux { 510 groups = "pdm_din0_c"; 511 function = "pdm"; 512 bias-disable; 513 }; 514 }; 515 516 pdm_din0_x_pins: pdm-din0-x { 517 mux { 518 groups = "pdm_din0_x"; 519 function = "pdm"; 520 bias-disable; 521 }; 522 }; 523 524 pdm_din0_z_pins: pdm-din0-z { 525 mux { 526 groups = "pdm_din0_z"; 527 function = "pdm"; 528 bias-disable; 529 }; 530 }; 531 532 pdm_din1_a_pins: pdm-din1-a { 533 mux { 534 groups = "pdm_din1_a"; 535 function = "pdm"; 536 bias-disable; 537 }; 538 }; 539 540 pdm_din1_c_pins: pdm-din1-c { 541 mux { 542 groups = "pdm_din1_c"; 543 function = "pdm"; 544 bias-disable; 545 }; 546 }; 547 548 pdm_din1_x_pins: pdm-din1-x { 549 mux { 550 groups = "pdm_din1_x"; 551 function = "pdm"; 552 bias-disable; 553 }; 554 }; 555 556 pdm_din1_z_pins: pdm-din1-z { 557 mux { 558 groups = "pdm_din1_z"; 559 function = "pdm"; 560 bias-disable; 561 }; 562 }; 563 564 pdm_din2_a_pins: pdm-din2-a { 565 mux { 566 groups = "pdm_din2_a"; 567 function = "pdm"; 568 bias-disable; 569 }; 570 }; 571 572 pdm_din2_c_pins: pdm-din2-c { 573 mux { 574 groups = "pdm_din2_c"; 575 function = "pdm"; 576 bias-disable; 577 }; 578 }; 579 580 pdm_din2_x_pins: pdm-din2-x { 581 mux { 582 groups = "pdm_din2_x"; 583 function = "pdm"; 584 bias-disable; 585 }; 586 }; 587 588 pdm_din2_z_pins: pdm-din2-z { 589 mux { 590 groups = "pdm_din2_z"; 591 function = "pdm"; 592 bias-disable; 593 }; 594 }; 595 596 pdm_din3_a_pins: pdm-din3-a { 597 mux { 598 groups = "pdm_din3_a"; 599 function = "pdm"; 600 bias-disable; 601 }; 602 }; 603 604 pdm_din3_c_pins: pdm-din3-c { 605 mux { 606 groups = "pdm_din3_c"; 607 function = "pdm"; 608 bias-disable; 609 }; 610 }; 611 612 pdm_din3_x_pins: pdm-din3-x { 613 mux { 614 groups = "pdm_din3_x"; 615 function = "pdm"; 616 bias-disable; 617 }; 618 }; 619 620 pdm_din3_z_pins: pdm-din3-z { 621 mux { 622 groups = "pdm_din3_z"; 623 function = "pdm"; 624 bias-disable; 625 }; 626 }; 627 628 pdm_dclk_a_pins: pdm-dclk-a { 629 mux { 630 groups = "pdm_dclk_a"; 631 function = "pdm"; 632 bias-disable; 633 drive-strength-microamp = <500>; 634 }; 635 }; 636 637 pdm_dclk_c_pins: pdm-dclk-c { 638 mux { 639 groups = "pdm_dclk_c"; 640 function = "pdm"; 641 bias-disable; 642 drive-strength-microamp = <500>; 643 }; 644 }; 645 646 pdm_dclk_x_pins: pdm-dclk-x { 647 mux { 648 groups = "pdm_dclk_x"; 649 function = "pdm"; 650 bias-disable; 651 drive-strength-microamp = <500>; 652 }; 653 }; 654 655 pdm_dclk_z_pins: pdm-dclk-z { 656 mux { 657 groups = "pdm_dclk_z"; 658 function = "pdm"; 659 bias-disable; 660 drive-strength-microamp = <500>; 661 }; 662 }; 663 664 pwm_a_pins: pwm-a { 665 mux { 666 groups = "pwm_a"; 667 function = "pwm_a"; 668 bias-disable; 669 }; 670 }; 671 672 pwm_b_x7_pins: pwm-b-x7 { 673 mux { 674 groups = "pwm_b_x7"; 675 function = "pwm_b"; 676 bias-disable; 677 }; 678 }; 679 680 pwm_b_x19_pins: pwm-b-x19 { 681 mux { 682 groups = "pwm_b_x19"; 683 function = "pwm_b"; 684 bias-disable; 685 }; 686 }; 687 688 pwm_c_c_pins: pwm-c-c { 689 mux { 690 groups = "pwm_c_c"; 691 function = "pwm_c"; 692 bias-disable; 693 }; 694 }; 695 696 pwm_c_x5_pins: pwm-c-x5 { 697 mux { 698 groups = "pwm_c_x5"; 699 function = "pwm_c"; 700 bias-disable; 701 }; 702 }; 703 704 pwm_c_x8_pins: pwm-c-x8 { 705 mux { 706 groups = "pwm_c_x8"; 707 function = "pwm_c"; 708 bias-disable; 709 }; 710 }; 711 712 pwm_d_x3_pins: pwm-d-x3 { 713 mux { 714 groups = "pwm_d_x3"; 715 function = "pwm_d"; 716 bias-disable; 717 }; 718 }; 719 720 pwm_d_x6_pins: pwm-d-x6 { 721 mux { 722 groups = "pwm_d_x6"; 723 function = "pwm_d"; 724 bias-disable; 725 }; 726 }; 727 728 pwm_e_pins: pwm-e { 729 mux { 730 groups = "pwm_e"; 731 function = "pwm_e"; 732 bias-disable; 733 }; 734 }; 735 736 pwm_f_x_pins: pwm-f-x { 737 mux { 738 groups = "pwm_f_x"; 739 function = "pwm_f"; 740 bias-disable; 741 }; 742 }; 743 744 pwm_f_h_pins: pwm-f-h { 745 mux { 746 groups = "pwm_f_h"; 747 function = "pwm_f"; 748 bias-disable; 749 }; 750 }; 751 752 sdcard_c_pins: sdcard_c { 753 mux-0 { 754 groups = "sdcard_d0_c", 755 "sdcard_d1_c", 756 "sdcard_d2_c", 757 "sdcard_d3_c", 758 "sdcard_cmd_c"; 759 function = "sdcard"; 760 bias-pull-up; 761 drive-strength-microamp = <4000>; 762 }; 763 764 mux-1 { 765 groups = "sdcard_clk_c"; 766 function = "sdcard"; 767 bias-disable; 768 drive-strength-microamp = <4000>; 769 }; 770 }; 771 772 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 773 mux { 774 groups = "GPIOC_4"; 775 function = "gpio_periphs"; 776 bias-pull-down; 777 drive-strength-microamp = <4000>; 778 }; 779 }; 780 781 sdcard_z_pins: sdcard_z { 782 mux-0 { 783 groups = "sdcard_d0_z", 784 "sdcard_d1_z", 785 "sdcard_d2_z", 786 "sdcard_d3_z", 787 "sdcard_cmd_z"; 788 function = "sdcard"; 789 bias-pull-up; 790 drive-strength-microamp = <4000>; 791 }; 792 793 mux-1 { 794 groups = "sdcard_clk_z"; 795 function = "sdcard"; 796 bias-disable; 797 drive-strength-microamp = <4000>; 798 }; 799 }; 800 801 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 802 mux { 803 groups = "GPIOZ_6"; 804 function = "gpio_periphs"; 805 bias-pull-down; 806 drive-strength-microamp = <4000>; 807 }; 808 }; 809 810 spdif_in_a10_pins: spdif-in-a10 { 811 mux { 812 groups = "spdif_in_a10"; 813 function = "spdif_in"; 814 bias-disable; 815 }; 816 }; 817 818 spdif_in_a12_pins: spdif-in-a12 { 819 mux { 820 groups = "spdif_in_a12"; 821 function = "spdif_in"; 822 bias-disable; 823 }; 824 }; 825 826 spdif_in_h_pins: spdif-in-h { 827 mux { 828 groups = "spdif_in_h"; 829 function = "spdif_in"; 830 bias-disable; 831 }; 832 }; 833 834 spdif_out_h_pins: spdif-out-h { 835 mux { 836 groups = "spdif_out_h"; 837 function = "spdif_out"; 838 drive-strength-microamp = <500>; 839 bias-disable; 840 }; 841 }; 842 843 spdif_out_a11_pins: spdif-out-a11 { 844 mux { 845 groups = "spdif_out_a11"; 846 function = "spdif_out"; 847 drive-strength-microamp = <500>; 848 bias-disable; 849 }; 850 }; 851 852 spdif_out_a13_pins: spdif-out-a13 { 853 mux { 854 groups = "spdif_out_a13"; 855 function = "spdif_out"; 856 drive-strength-microamp = <500>; 857 bias-disable; 858 }; 859 }; 860 861 tdm_a_din0_pins: tdm-a-din0 { 862 mux { 863 groups = "tdm_a_din0"; 864 function = "tdm_a"; 865 bias-disable; 866 }; 867 }; 868 869 870 tdm_a_din1_pins: tdm-a-din1 { 871 mux { 872 groups = "tdm_a_din1"; 873 function = "tdm_a"; 874 bias-disable; 875 }; 876 }; 877 878 tdm_a_dout0_pins: tdm-a-dout0 { 879 mux { 880 groups = "tdm_a_dout0"; 881 function = "tdm_a"; 882 bias-disable; 883 drive-strength-microamp = <3000>; 884 }; 885 }; 886 887 tdm_a_dout1_pins: tdm-a-dout1 { 888 mux { 889 groups = "tdm_a_dout1"; 890 function = "tdm_a"; 891 bias-disable; 892 drive-strength-microamp = <3000>; 893 }; 894 }; 895 896 tdm_a_fs_pins: tdm-a-fs { 897 mux { 898 groups = "tdm_a_fs"; 899 function = "tdm_a"; 900 bias-disable; 901 drive-strength-microamp = <3000>; 902 }; 903 }; 904 905 tdm_a_sclk_pins: tdm-a-sclk { 906 mux { 907 groups = "tdm_a_sclk"; 908 function = "tdm_a"; 909 bias-disable; 910 drive-strength-microamp = <3000>; 911 }; 912 }; 913 914 tdm_a_slv_fs_pins: tdm-a-slv-fs { 915 mux { 916 groups = "tdm_a_slv_fs"; 917 function = "tdm_a"; 918 bias-disable; 919 }; 920 }; 921 922 923 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 924 mux { 925 groups = "tdm_a_slv_sclk"; 926 function = "tdm_a"; 927 bias-disable; 928 }; 929 }; 930 931 tdm_b_din0_pins: tdm-b-din0 { 932 mux { 933 groups = "tdm_b_din0"; 934 function = "tdm_b"; 935 bias-disable; 936 }; 937 }; 938 939 tdm_b_din1_pins: tdm-b-din1 { 940 mux { 941 groups = "tdm_b_din1"; 942 function = "tdm_b"; 943 bias-disable; 944 }; 945 }; 946 947 tdm_b_din2_pins: tdm-b-din2 { 948 mux { 949 groups = "tdm_b_din2"; 950 function = "tdm_b"; 951 bias-disable; 952 }; 953 }; 954 955 tdm_b_din3_a_pins: tdm-b-din3-a { 956 mux { 957 groups = "tdm_b_din3_a"; 958 function = "tdm_b"; 959 bias-disable; 960 }; 961 }; 962 963 tdm_b_din3_h_pins: tdm-b-din3-h { 964 mux { 965 groups = "tdm_b_din3_h"; 966 function = "tdm_b"; 967 bias-disable; 968 }; 969 }; 970 971 tdm_b_dout0_pins: tdm-b-dout0 { 972 mux { 973 groups = "tdm_b_dout0"; 974 function = "tdm_b"; 975 bias-disable; 976 drive-strength-microamp = <3000>; 977 }; 978 }; 979 980 tdm_b_dout1_pins: tdm-b-dout1 { 981 mux { 982 groups = "tdm_b_dout1"; 983 function = "tdm_b"; 984 bias-disable; 985 drive-strength-microamp = <3000>; 986 }; 987 }; 988 989 tdm_b_dout2_pins: tdm-b-dout2 { 990 mux { 991 groups = "tdm_b_dout2"; 992 function = "tdm_b"; 993 bias-disable; 994 drive-strength-microamp = <3000>; 995 }; 996 }; 997 998 tdm_b_dout3_a_pins: tdm-b-dout3-a { 999 mux { 1000 groups = "tdm_b_dout3_a"; 1001 function = "tdm_b"; 1002 bias-disable; 1003 drive-strength-microamp = <3000>; 1004 }; 1005 }; 1006 1007 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1008 mux { 1009 groups = "tdm_b_dout3_h"; 1010 function = "tdm_b"; 1011 bias-disable; 1012 drive-strength-microamp = <3000>; 1013 }; 1014 }; 1015 1016 tdm_b_fs_pins: tdm-b-fs { 1017 mux { 1018 groups = "tdm_b_fs"; 1019 function = "tdm_b"; 1020 bias-disable; 1021 drive-strength-microamp = <3000>; 1022 }; 1023 }; 1024 1025 tdm_b_sclk_pins: tdm-b-sclk { 1026 mux { 1027 groups = "tdm_b_sclk"; 1028 function = "tdm_b"; 1029 bias-disable; 1030 drive-strength-microamp = <3000>; 1031 }; 1032 }; 1033 1034 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1035 mux { 1036 groups = "tdm_b_slv_fs"; 1037 function = "tdm_b"; 1038 bias-disable; 1039 }; 1040 }; 1041 1042 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1043 mux { 1044 groups = "tdm_b_slv_sclk"; 1045 function = "tdm_b"; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 tdm_c_din0_a_pins: tdm-c-din0-a { 1051 mux { 1052 groups = "tdm_c_din0_a"; 1053 function = "tdm_c"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 tdm_c_din0_z_pins: tdm-c-din0-z { 1059 mux { 1060 groups = "tdm_c_din0_z"; 1061 function = "tdm_c"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 tdm_c_din1_a_pins: tdm-c-din1-a { 1067 mux { 1068 groups = "tdm_c_din1_a"; 1069 function = "tdm_c"; 1070 bias-disable; 1071 }; 1072 }; 1073 1074 tdm_c_din1_z_pins: tdm-c-din1-z { 1075 mux { 1076 groups = "tdm_c_din1_z"; 1077 function = "tdm_c"; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 tdm_c_din2_a_pins: tdm-c-din2-a { 1083 mux { 1084 groups = "tdm_c_din2_a"; 1085 function = "tdm_c"; 1086 bias-disable; 1087 }; 1088 }; 1089 1090 tdm_c_din2_z_pins: tdm-c-din2-z { 1091 mux { 1092 groups = "tdm_c_din2_z"; 1093 function = "tdm_c"; 1094 bias-disable; 1095 }; 1096 }; 1097 1098 tdm_c_din3_a_pins: tdm-c-din3-a { 1099 mux { 1100 groups = "tdm_c_din3_a"; 1101 function = "tdm_c"; 1102 bias-disable; 1103 }; 1104 }; 1105 1106 tdm_c_din3_z_pins: tdm-c-din3-z { 1107 mux { 1108 groups = "tdm_c_din3_z"; 1109 function = "tdm_c"; 1110 bias-disable; 1111 }; 1112 }; 1113 1114 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1115 mux { 1116 groups = "tdm_c_dout0_a"; 1117 function = "tdm_c"; 1118 bias-disable; 1119 drive-strength-microamp = <3000>; 1120 }; 1121 }; 1122 1123 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1124 mux { 1125 groups = "tdm_c_dout0_z"; 1126 function = "tdm_c"; 1127 bias-disable; 1128 drive-strength-microamp = <3000>; 1129 }; 1130 }; 1131 1132 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1133 mux { 1134 groups = "tdm_c_dout1_a"; 1135 function = "tdm_c"; 1136 bias-disable; 1137 drive-strength-microamp = <3000>; 1138 }; 1139 }; 1140 1141 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1142 mux { 1143 groups = "tdm_c_dout1_z"; 1144 function = "tdm_c"; 1145 bias-disable; 1146 drive-strength-microamp = <3000>; 1147 }; 1148 }; 1149 1150 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1151 mux { 1152 groups = "tdm_c_dout2_a"; 1153 function = "tdm_c"; 1154 bias-disable; 1155 drive-strength-microamp = <3000>; 1156 }; 1157 }; 1158 1159 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1160 mux { 1161 groups = "tdm_c_dout2_z"; 1162 function = "tdm_c"; 1163 bias-disable; 1164 drive-strength-microamp = <3000>; 1165 }; 1166 }; 1167 1168 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1169 mux { 1170 groups = "tdm_c_dout3_a"; 1171 function = "tdm_c"; 1172 bias-disable; 1173 drive-strength-microamp = <3000>; 1174 }; 1175 }; 1176 1177 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1178 mux { 1179 groups = "tdm_c_dout3_z"; 1180 function = "tdm_c"; 1181 bias-disable; 1182 drive-strength-microamp = <3000>; 1183 }; 1184 }; 1185 1186 tdm_c_fs_a_pins: tdm-c-fs-a { 1187 mux { 1188 groups = "tdm_c_fs_a"; 1189 function = "tdm_c"; 1190 bias-disable; 1191 drive-strength-microamp = <3000>; 1192 }; 1193 }; 1194 1195 tdm_c_fs_z_pins: tdm-c-fs-z { 1196 mux { 1197 groups = "tdm_c_fs_z"; 1198 function = "tdm_c"; 1199 bias-disable; 1200 drive-strength-microamp = <3000>; 1201 }; 1202 }; 1203 1204 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1205 mux { 1206 groups = "tdm_c_sclk_a"; 1207 function = "tdm_c"; 1208 bias-disable; 1209 drive-strength-microamp = <3000>; 1210 }; 1211 }; 1212 1213 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1214 mux { 1215 groups = "tdm_c_sclk_z"; 1216 function = "tdm_c"; 1217 bias-disable; 1218 drive-strength-microamp = <3000>; 1219 }; 1220 }; 1221 1222 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1223 mux { 1224 groups = "tdm_c_slv_fs_a"; 1225 function = "tdm_c"; 1226 bias-disable; 1227 }; 1228 }; 1229 1230 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1231 mux { 1232 groups = "tdm_c_slv_fs_z"; 1233 function = "tdm_c"; 1234 bias-disable; 1235 }; 1236 }; 1237 1238 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1239 mux { 1240 groups = "tdm_c_slv_sclk_a"; 1241 function = "tdm_c"; 1242 bias-disable; 1243 }; 1244 }; 1245 1246 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1247 mux { 1248 groups = "tdm_c_slv_sclk_z"; 1249 function = "tdm_c"; 1250 bias-disable; 1251 }; 1252 }; 1253 1254 uart_a_pins: uart-a { 1255 mux { 1256 groups = "uart_a_tx", 1257 "uart_a_rx"; 1258 function = "uart_a"; 1259 bias-disable; 1260 }; 1261 }; 1262 1263 uart_a_cts_rts_pins: uart-a-cts-rts { 1264 mux { 1265 groups = "uart_a_cts", 1266 "uart_a_rts"; 1267 function = "uart_a"; 1268 bias-disable; 1269 }; 1270 }; 1271 1272 uart_b_pins: uart-b { 1273 mux { 1274 groups = "uart_b_tx", 1275 "uart_b_rx"; 1276 function = "uart_b"; 1277 bias-disable; 1278 }; 1279 }; 1280 1281 uart_c_pins: uart-c { 1282 mux { 1283 groups = "uart_c_tx", 1284 "uart_c_rx"; 1285 function = "uart_c"; 1286 bias-disable; 1287 }; 1288 }; 1289 1290 uart_c_cts_rts_pins: uart-c-cts-rts { 1291 mux { 1292 groups = "uart_c_cts", 1293 "uart_c_rts"; 1294 function = "uart_c"; 1295 bias-disable; 1296 }; 1297 }; 1298 }; 1299 }; 1300 1301 usb2_phy0: phy@36000 { 1302 compatible = "amlogic,g12a-usb2-phy"; 1303 reg = <0x0 0x36000 0x0 0x2000>; 1304 clocks = <&xtal>; 1305 clock-names = "xtal"; 1306 resets = <&reset RESET_USB_PHY20>; 1307 reset-names = "phy"; 1308 #phy-cells = <0>; 1309 }; 1310 1311 dmc: bus@38000 { 1312 compatible = "simple-bus"; 1313 reg = <0x0 0x38000 0x0 0x400>; 1314 #address-cells = <2>; 1315 #size-cells = <2>; 1316 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1317 1318 canvas: video-lut@48 { 1319 compatible = "amlogic,canvas"; 1320 reg = <0x0 0x48 0x0 0x14>; 1321 }; 1322 }; 1323 1324 usb2_phy1: phy@3a000 { 1325 compatible = "amlogic,g12a-usb2-phy"; 1326 reg = <0x0 0x3a000 0x0 0x2000>; 1327 clocks = <&xtal>; 1328 clock-names = "xtal"; 1329 resets = <&reset RESET_USB_PHY21>; 1330 reset-names = "phy"; 1331 #phy-cells = <0>; 1332 }; 1333 1334 hiu: bus@3c000 { 1335 compatible = "simple-bus"; 1336 reg = <0x0 0x3c000 0x0 0x1400>; 1337 #address-cells = <2>; 1338 #size-cells = <2>; 1339 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1340 1341 hhi: system-controller@0 { 1342 compatible = "amlogic,meson-gx-hhi-sysctrl", 1343 "simple-mfd", "syscon"; 1344 reg = <0 0 0 0x400>; 1345 1346 clkc: clock-controller { 1347 compatible = "amlogic,g12a-clkc"; 1348 #clock-cells = <1>; 1349 clocks = <&xtal>; 1350 clock-names = "xtal"; 1351 }; 1352 }; 1353 }; 1354 1355 pdm: audio-controller@40000 { 1356 compatible = "amlogic,g12a-pdm", 1357 "amlogic,axg-pdm"; 1358 reg = <0x0 0x40000 0x0 0x34>; 1359 #sound-dai-cells = <0>; 1360 sound-name-prefix = "PDM"; 1361 clocks = <&clkc_audio AUD_CLKID_PDM>, 1362 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1363 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1364 clock-names = "pclk", "dclk", "sysclk"; 1365 status = "disabled"; 1366 }; 1367 1368 audio: bus@42000 { 1369 compatible = "simple-bus"; 1370 reg = <0x0 0x42000 0x0 0x2000>; 1371 #address-cells = <2>; 1372 #size-cells = <2>; 1373 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1374 1375 clkc_audio: clock-controller@0 { 1376 status = "disabled"; 1377 compatible = "amlogic,g12a-audio-clkc"; 1378 reg = <0x0 0x0 0x0 0xb4>; 1379 #clock-cells = <1>; 1380 1381 clocks = <&clkc CLKID_AUDIO>, 1382 <&clkc CLKID_MPLL0>, 1383 <&clkc CLKID_MPLL1>, 1384 <&clkc CLKID_MPLL2>, 1385 <&clkc CLKID_MPLL3>, 1386 <&clkc CLKID_HIFI_PLL>, 1387 <&clkc CLKID_FCLK_DIV3>, 1388 <&clkc CLKID_FCLK_DIV4>, 1389 <&clkc CLKID_GP0_PLL>; 1390 clock-names = "pclk", 1391 "mst_in0", 1392 "mst_in1", 1393 "mst_in2", 1394 "mst_in3", 1395 "mst_in4", 1396 "mst_in5", 1397 "mst_in6", 1398 "mst_in7"; 1399 1400 resets = <&reset RESET_AUDIO>; 1401 }; 1402 1403 toddr_a: audio-controller@100 { 1404 compatible = "amlogic,g12a-toddr", 1405 "amlogic,axg-toddr"; 1406 reg = <0x0 0x100 0x0 0x1c>; 1407 #sound-dai-cells = <0>; 1408 sound-name-prefix = "TODDR_A"; 1409 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1410 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1411 resets = <&arb AXG_ARB_TODDR_A>; 1412 status = "disabled"; 1413 }; 1414 1415 toddr_b: audio-controller@140 { 1416 compatible = "amlogic,g12a-toddr", 1417 "amlogic,axg-toddr"; 1418 reg = <0x0 0x140 0x0 0x1c>; 1419 #sound-dai-cells = <0>; 1420 sound-name-prefix = "TODDR_B"; 1421 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1422 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1423 resets = <&arb AXG_ARB_TODDR_B>; 1424 status = "disabled"; 1425 }; 1426 1427 toddr_c: audio-controller@180 { 1428 compatible = "amlogic,g12a-toddr", 1429 "amlogic,axg-toddr"; 1430 reg = <0x0 0x180 0x0 0x1c>; 1431 #sound-dai-cells = <0>; 1432 sound-name-prefix = "TODDR_C"; 1433 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1434 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1435 resets = <&arb AXG_ARB_TODDR_C>; 1436 status = "disabled"; 1437 }; 1438 1439 frddr_a: audio-controller@1c0 { 1440 compatible = "amlogic,g12a-frddr", 1441 "amlogic,axg-frddr"; 1442 reg = <0x0 0x1c0 0x0 0x1c>; 1443 #sound-dai-cells = <0>; 1444 sound-name-prefix = "FRDDR_A"; 1445 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1446 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1447 resets = <&arb AXG_ARB_FRDDR_A>; 1448 status = "disabled"; 1449 }; 1450 1451 frddr_b: audio-controller@200 { 1452 compatible = "amlogic,g12a-frddr", 1453 "amlogic,axg-frddr"; 1454 reg = <0x0 0x200 0x0 0x1c>; 1455 #sound-dai-cells = <0>; 1456 sound-name-prefix = "FRDDR_B"; 1457 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1458 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1459 resets = <&arb AXG_ARB_FRDDR_B>; 1460 status = "disabled"; 1461 }; 1462 1463 frddr_c: audio-controller@240 { 1464 compatible = "amlogic,g12a-frddr", 1465 "amlogic,axg-frddr"; 1466 reg = <0x0 0x240 0x0 0x1c>; 1467 #sound-dai-cells = <0>; 1468 sound-name-prefix = "FRDDR_C"; 1469 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1470 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1471 resets = <&arb AXG_ARB_FRDDR_C>; 1472 status = "disabled"; 1473 }; 1474 1475 arb: reset-controller@280 { 1476 status = "disabled"; 1477 compatible = "amlogic,meson-axg-audio-arb"; 1478 reg = <0x0 0x280 0x0 0x4>; 1479 #reset-cells = <1>; 1480 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1481 }; 1482 1483 tdmin_a: audio-controller@300 { 1484 compatible = "amlogic,g12a-tdmin", 1485 "amlogic,axg-tdmin"; 1486 reg = <0x0 0x300 0x0 0x40>; 1487 sound-name-prefix = "TDMIN_A"; 1488 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1489 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1490 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1491 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1492 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1493 clock-names = "pclk", "sclk", "sclk_sel", 1494 "lrclk", "lrclk_sel"; 1495 status = "disabled"; 1496 }; 1497 1498 tdmin_b: audio-controller@340 { 1499 compatible = "amlogic,g12a-tdmin", 1500 "amlogic,axg-tdmin"; 1501 reg = <0x0 0x340 0x0 0x40>; 1502 sound-name-prefix = "TDMIN_B"; 1503 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1504 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1505 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1506 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1507 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1508 clock-names = "pclk", "sclk", "sclk_sel", 1509 "lrclk", "lrclk_sel"; 1510 status = "disabled"; 1511 }; 1512 1513 tdmin_c: audio-controller@380 { 1514 compatible = "amlogic,g12a-tdmin", 1515 "amlogic,axg-tdmin"; 1516 reg = <0x0 0x380 0x0 0x40>; 1517 sound-name-prefix = "TDMIN_C"; 1518 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1519 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1520 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1521 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1522 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1523 clock-names = "pclk", "sclk", "sclk_sel", 1524 "lrclk", "lrclk_sel"; 1525 status = "disabled"; 1526 }; 1527 1528 tdmin_lb: audio-controller@3c0 { 1529 compatible = "amlogic,g12a-tdmin", 1530 "amlogic,axg-tdmin"; 1531 reg = <0x0 0x3c0 0x0 0x40>; 1532 sound-name-prefix = "TDMIN_LB"; 1533 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1534 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1535 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1536 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1537 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1538 clock-names = "pclk", "sclk", "sclk_sel", 1539 "lrclk", "lrclk_sel"; 1540 status = "disabled"; 1541 }; 1542 1543 spdifin: audio-controller@400 { 1544 compatible = "amlogic,g12a-spdifin", 1545 "amlogic,axg-spdifin"; 1546 reg = <0x0 0x400 0x0 0x30>; 1547 #sound-dai-cells = <0>; 1548 sound-name-prefix = "SPDIFIN"; 1549 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1550 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1551 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1552 clock-names = "pclk", "refclk"; 1553 status = "disabled"; 1554 }; 1555 1556 spdifout: audio-controller@480 { 1557 compatible = "amlogic,g12a-spdifout", 1558 "amlogic,axg-spdifout"; 1559 reg = <0x0 0x480 0x0 0x50>; 1560 #sound-dai-cells = <0>; 1561 sound-name-prefix = "SPDIFOUT"; 1562 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1563 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1564 clock-names = "pclk", "mclk"; 1565 status = "disabled"; 1566 }; 1567 1568 tdmout_a: audio-controller@500 { 1569 compatible = "amlogic,g12a-tdmout"; 1570 reg = <0x0 0x500 0x0 0x40>; 1571 sound-name-prefix = "TDMOUT_A"; 1572 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1573 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1574 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1575 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1576 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1577 clock-names = "pclk", "sclk", "sclk_sel", 1578 "lrclk", "lrclk_sel"; 1579 status = "disabled"; 1580 }; 1581 1582 tdmout_b: audio-controller@540 { 1583 compatible = "amlogic,g12a-tdmout"; 1584 reg = <0x0 0x540 0x0 0x40>; 1585 sound-name-prefix = "TDMOUT_B"; 1586 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1587 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1588 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1589 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1590 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1591 clock-names = "pclk", "sclk", "sclk_sel", 1592 "lrclk", "lrclk_sel"; 1593 status = "disabled"; 1594 }; 1595 1596 tdmout_c: audio-controller@580 { 1597 compatible = "amlogic,g12a-tdmout"; 1598 reg = <0x0 0x580 0x0 0x40>; 1599 sound-name-prefix = "TDMOUT_C"; 1600 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1601 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1602 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1603 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1604 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1605 clock-names = "pclk", "sclk", "sclk_sel", 1606 "lrclk", "lrclk_sel"; 1607 status = "disabled"; 1608 }; 1609 1610 spdifout_b: audio-controller@680 { 1611 compatible = "amlogic,g12a-spdifout", 1612 "amlogic,axg-spdifout"; 1613 reg = <0x0 0x680 0x0 0x50>; 1614 #sound-dai-cells = <0>; 1615 sound-name-prefix = "SPDIFOUT_B"; 1616 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1617 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1618 clock-names = "pclk", "mclk"; 1619 status = "disabled"; 1620 }; 1621 }; 1622 1623 usb3_pcie_phy: phy@46000 { 1624 compatible = "amlogic,g12a-usb3-pcie-phy"; 1625 reg = <0x0 0x46000 0x0 0x2000>; 1626 clocks = <&clkc CLKID_PCIE_PLL>; 1627 clock-names = "ref_clk"; 1628 resets = <&reset RESET_PCIE_PHY>; 1629 reset-names = "phy"; 1630 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1631 assigned-clock-rates = <100000000>; 1632 #phy-cells = <1>; 1633 }; 1634 }; 1635 1636 aobus: bus@ff800000 { 1637 compatible = "simple-bus"; 1638 reg = <0x0 0xff800000 0x0 0x100000>; 1639 #address-cells = <2>; 1640 #size-cells = <2>; 1641 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1642 1643 rti: sys-ctrl@0 { 1644 compatible = "amlogic,meson-gx-ao-sysctrl", 1645 "simple-mfd", "syscon"; 1646 reg = <0x0 0x0 0x0 0x100>; 1647 #address-cells = <2>; 1648 #size-cells = <2>; 1649 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1650 1651 clkc_AO: clock-controller { 1652 compatible = "amlogic,meson-g12a-aoclkc"; 1653 #clock-cells = <1>; 1654 #reset-cells = <1>; 1655 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1656 clock-names = "xtal", "mpeg-clk"; 1657 }; 1658 1659 pwrc_vpu: power-controller-vpu { 1660 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1661 #power-domain-cells = <0>; 1662 amlogic,hhi-sysctrl = <&hhi>; 1663 resets = <&reset RESET_VIU>, 1664 <&reset RESET_VENC>, 1665 <&reset RESET_VCBUS>, 1666 <&reset RESET_BT656>, 1667 <&reset RESET_RDMA>, 1668 <&reset RESET_VENCI>, 1669 <&reset RESET_VENCP>, 1670 <&reset RESET_VDAC>, 1671 <&reset RESET_VDI6>, 1672 <&reset RESET_VENCL>, 1673 <&reset RESET_VID_LOCK>; 1674 clocks = <&clkc CLKID_VPU>, 1675 <&clkc CLKID_VAPB>; 1676 clock-names = "vpu", "vapb"; 1677 /* 1678 * VPU clocking is provided by two identical clock paths 1679 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1680 * free mux to safely change frequency while running. 1681 * Same for VAPB but with a final gate after the glitch free mux. 1682 */ 1683 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1684 <&clkc CLKID_VPU_0>, 1685 <&clkc CLKID_VPU>, /* Glitch free mux */ 1686 <&clkc CLKID_VAPB_0_SEL>, 1687 <&clkc CLKID_VAPB_0>, 1688 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1689 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1690 <0>, /* Do Nothing */ 1691 <&clkc CLKID_VPU_0>, 1692 <&clkc CLKID_FCLK_DIV4>, 1693 <0>, /* Do Nothing */ 1694 <&clkc CLKID_VAPB_0>; 1695 assigned-clock-rates = <0>, /* Do Nothing */ 1696 <666666666>, 1697 <0>, /* Do Nothing */ 1698 <0>, /* Do Nothing */ 1699 <250000000>, 1700 <0>; /* Do Nothing */ 1701 }; 1702 1703 ao_pinctrl: pinctrl@14 { 1704 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1705 #address-cells = <2>; 1706 #size-cells = <2>; 1707 ranges; 1708 1709 gpio_ao: bank@14 { 1710 reg = <0x0 0x14 0x0 0x8>, 1711 <0x0 0x1c 0x0 0x8>, 1712 <0x0 0x24 0x0 0x14>; 1713 reg-names = "mux", 1714 "ds", 1715 "gpio"; 1716 gpio-controller; 1717 #gpio-cells = <2>; 1718 gpio-ranges = <&ao_pinctrl 0 0 15>; 1719 }; 1720 1721 i2c_ao_sck_pins: i2c_ao_sck_pins { 1722 mux { 1723 groups = "i2c_ao_sck"; 1724 function = "i2c_ao"; 1725 bias-disable; 1726 drive-strength-microamp = <3000>; 1727 }; 1728 }; 1729 1730 i2c_ao_sda_pins: i2c_ao_sda { 1731 mux { 1732 groups = "i2c_ao_sda"; 1733 function = "i2c_ao"; 1734 bias-disable; 1735 drive-strength-microamp = <3000>; 1736 }; 1737 }; 1738 1739 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1740 mux { 1741 groups = "i2c_ao_sck_e"; 1742 function = "i2c_ao"; 1743 bias-disable; 1744 drive-strength-microamp = <3000>; 1745 }; 1746 }; 1747 1748 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1749 mux { 1750 groups = "i2c_ao_sda_e"; 1751 function = "i2c_ao"; 1752 bias-disable; 1753 drive-strength-microamp = <3000>; 1754 }; 1755 }; 1756 1757 mclk0_ao_pins: mclk0-ao { 1758 mux { 1759 groups = "mclk0_ao"; 1760 function = "mclk0_ao"; 1761 bias-disable; 1762 drive-strength-microamp = <3000>; 1763 }; 1764 }; 1765 1766 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1767 mux { 1768 groups = "tdm_ao_b_din0"; 1769 function = "tdm_ao_b"; 1770 bias-disable; 1771 }; 1772 }; 1773 1774 spdif_ao_out_pins: spdif-ao-out { 1775 mux { 1776 groups = "spdif_ao_out"; 1777 function = "spdif_ao_out"; 1778 drive-strength-microamp = <500>; 1779 bias-disable; 1780 }; 1781 }; 1782 1783 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1784 mux { 1785 groups = "tdm_ao_b_din1"; 1786 function = "tdm_ao_b"; 1787 bias-disable; 1788 }; 1789 }; 1790 1791 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1792 mux { 1793 groups = "tdm_ao_b_din2"; 1794 function = "tdm_ao_b"; 1795 bias-disable; 1796 }; 1797 }; 1798 1799 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1800 mux { 1801 groups = "tdm_ao_b_dout0"; 1802 function = "tdm_ao_b"; 1803 bias-disable; 1804 drive-strength-microamp = <3000>; 1805 }; 1806 }; 1807 1808 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1809 mux { 1810 groups = "tdm_ao_b_dout1"; 1811 function = "tdm_ao_b"; 1812 bias-disable; 1813 drive-strength-microamp = <3000>; 1814 }; 1815 }; 1816 1817 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1818 mux { 1819 groups = "tdm_ao_b_dout2"; 1820 function = "tdm_ao_b"; 1821 bias-disable; 1822 drive-strength-microamp = <3000>; 1823 }; 1824 }; 1825 1826 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1827 mux { 1828 groups = "tdm_ao_b_fs"; 1829 function = "tdm_ao_b"; 1830 bias-disable; 1831 drive-strength-microamp = <3000>; 1832 }; 1833 }; 1834 1835 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1836 mux { 1837 groups = "tdm_ao_b_sclk"; 1838 function = "tdm_ao_b"; 1839 bias-disable; 1840 drive-strength-microamp = <3000>; 1841 }; 1842 }; 1843 1844 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1845 mux { 1846 groups = "tdm_ao_b_slv_fs"; 1847 function = "tdm_ao_b"; 1848 bias-disable; 1849 }; 1850 }; 1851 1852 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1853 mux { 1854 groups = "tdm_ao_b_slv_sclk"; 1855 function = "tdm_ao_b"; 1856 bias-disable; 1857 }; 1858 }; 1859 1860 uart_ao_a_pins: uart-a-ao { 1861 mux { 1862 groups = "uart_ao_a_tx", 1863 "uart_ao_a_rx"; 1864 function = "uart_ao_a"; 1865 bias-disable; 1866 }; 1867 }; 1868 1869 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1870 mux { 1871 groups = "uart_ao_a_cts", 1872 "uart_ao_a_rts"; 1873 function = "uart_ao_a"; 1874 bias-disable; 1875 }; 1876 }; 1877 1878 pwm_ao_a_pins: pwm-ao-a { 1879 mux { 1880 groups = "pwm_ao_a"; 1881 function = "pwm_ao_a"; 1882 bias-disable; 1883 }; 1884 }; 1885 1886 pwm_ao_b_pins: pwm-ao-b { 1887 mux { 1888 groups = "pwm_ao_b"; 1889 function = "pwm_ao_b"; 1890 bias-disable; 1891 }; 1892 }; 1893 1894 pwm_ao_c_4_pins: pwm-ao-c-4 { 1895 mux { 1896 groups = "pwm_ao_c_4"; 1897 function = "pwm_ao_c"; 1898 bias-disable; 1899 }; 1900 }; 1901 1902 pwm_ao_c_6_pins: pwm-ao-c-6 { 1903 mux { 1904 groups = "pwm_ao_c_6"; 1905 function = "pwm_ao_c"; 1906 bias-disable; 1907 }; 1908 }; 1909 1910 pwm_ao_d_5_pins: pwm-ao-d-5 { 1911 mux { 1912 groups = "pwm_ao_d_5"; 1913 function = "pwm_ao_d"; 1914 bias-disable; 1915 }; 1916 }; 1917 1918 pwm_ao_d_10_pins: pwm-ao-d-10 { 1919 mux { 1920 groups = "pwm_ao_d_10"; 1921 function = "pwm_ao_d"; 1922 bias-disable; 1923 }; 1924 }; 1925 1926 pwm_ao_d_e_pins: pwm-ao-d-e { 1927 mux { 1928 groups = "pwm_ao_d_e"; 1929 function = "pwm_ao_d"; 1930 }; 1931 }; 1932 1933 remote_input_ao_pins: remote-input-ao { 1934 mux { 1935 groups = "remote_ao_input"; 1936 function = "remote_ao_input"; 1937 bias-disable; 1938 }; 1939 }; 1940 }; 1941 }; 1942 1943 cec_AO: cec@100 { 1944 compatible = "amlogic,meson-gx-ao-cec"; 1945 reg = <0x0 0x00100 0x0 0x14>; 1946 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1947 clocks = <&clkc_AO CLKID_AO_CEC>; 1948 clock-names = "core"; 1949 status = "disabled"; 1950 }; 1951 1952 sec_AO: ao-secure@140 { 1953 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1954 reg = <0x0 0x140 0x0 0x140>; 1955 amlogic,has-chip-id; 1956 }; 1957 1958 cecb_AO: cec@280 { 1959 compatible = "amlogic,meson-g12a-ao-cec"; 1960 reg = <0x0 0x00280 0x0 0x1c>; 1961 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1962 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1963 clock-names = "oscin"; 1964 status = "disabled"; 1965 }; 1966 1967 pwm_AO_cd: pwm@2000 { 1968 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1969 reg = <0x0 0x2000 0x0 0x20>; 1970 #pwm-cells = <3>; 1971 status = "disabled"; 1972 }; 1973 1974 uart_AO: serial@3000 { 1975 compatible = "amlogic,meson-gx-uart", 1976 "amlogic,meson-ao-uart"; 1977 reg = <0x0 0x3000 0x0 0x18>; 1978 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1979 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1980 clock-names = "xtal", "pclk", "baud"; 1981 status = "disabled"; 1982 }; 1983 1984 uart_AO_B: serial@4000 { 1985 compatible = "amlogic,meson-gx-uart", 1986 "amlogic,meson-ao-uart"; 1987 reg = <0x0 0x4000 0x0 0x18>; 1988 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1989 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1990 clock-names = "xtal", "pclk", "baud"; 1991 status = "disabled"; 1992 }; 1993 1994 i2c_AO: i2c@5000 { 1995 compatible = "amlogic,meson-axg-i2c"; 1996 status = "disabled"; 1997 reg = <0x0 0x05000 0x0 0x20>; 1998 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 clocks = <&clkc CLKID_I2C>; 2002 }; 2003 2004 pwm_AO_ab: pwm@7000 { 2005 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2006 reg = <0x0 0x7000 0x0 0x20>; 2007 #pwm-cells = <3>; 2008 status = "disabled"; 2009 }; 2010 2011 ir: ir@8000 { 2012 compatible = "amlogic,meson-gxbb-ir"; 2013 reg = <0x0 0x8000 0x0 0x20>; 2014 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2015 status = "disabled"; 2016 }; 2017 2018 saradc: adc@9000 { 2019 compatible = "amlogic,meson-g12a-saradc", 2020 "amlogic,meson-saradc"; 2021 reg = <0x0 0x9000 0x0 0x48>; 2022 #io-channel-cells = <1>; 2023 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2024 clocks = <&xtal>, 2025 <&clkc_AO CLKID_AO_SAR_ADC>, 2026 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2027 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2028 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2029 status = "disabled"; 2030 }; 2031 }; 2032 2033 vpu: vpu@ff900000 { 2034 compatible = "amlogic,meson-g12a-vpu"; 2035 reg = <0x0 0xff900000 0x0 0x100000>, 2036 <0x0 0xff63c000 0x0 0x1000>; 2037 reg-names = "vpu", "hhi"; 2038 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 amlogic,canvas = <&canvas>; 2042 power-domains = <&pwrc_vpu>; 2043 2044 /* CVBS VDAC output port */ 2045 cvbs_vdac_port: port@0 { 2046 reg = <0>; 2047 }; 2048 2049 /* HDMI-TX output port */ 2050 hdmi_tx_port: port@1 { 2051 reg = <1>; 2052 2053 hdmi_tx_out: endpoint { 2054 remote-endpoint = <&hdmi_tx_in>; 2055 }; 2056 }; 2057 }; 2058 2059 gic: interrupt-controller@ffc01000 { 2060 compatible = "arm,gic-400"; 2061 reg = <0x0 0xffc01000 0 0x1000>, 2062 <0x0 0xffc02000 0 0x2000>, 2063 <0x0 0xffc04000 0 0x2000>, 2064 <0x0 0xffc06000 0 0x2000>; 2065 interrupt-controller; 2066 interrupts = <GIC_PPI 9 2067 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2068 #interrupt-cells = <3>; 2069 #address-cells = <0>; 2070 }; 2071 2072 cbus: bus@ffd00000 { 2073 compatible = "simple-bus"; 2074 reg = <0x0 0xffd00000 0x0 0x100000>; 2075 #address-cells = <2>; 2076 #size-cells = <2>; 2077 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2078 2079 reset: reset-controller@1004 { 2080 compatible = "amlogic,meson-g12a-reset", 2081 "amlogic,meson-axg-reset"; 2082 reg = <0x0 0x1004 0x0 0x9c>; 2083 #reset-cells = <1>; 2084 }; 2085 2086 pwm_ef: pwm@19000 { 2087 compatible = "amlogic,meson-g12a-ee-pwm"; 2088 reg = <0x0 0x19000 0x0 0x20>; 2089 #pwm-cells = <3>; 2090 status = "disabled"; 2091 }; 2092 2093 pwm_cd: pwm@1a000 { 2094 compatible = "amlogic,meson-g12a-ee-pwm"; 2095 reg = <0x0 0x1a000 0x0 0x20>; 2096 #pwm-cells = <3>; 2097 status = "disabled"; 2098 }; 2099 2100 pwm_ab: pwm@1b000 { 2101 compatible = "amlogic,meson-g12a-ee-pwm"; 2102 reg = <0x0 0x1b000 0x0 0x20>; 2103 #pwm-cells = <3>; 2104 status = "disabled"; 2105 }; 2106 2107 i2c3: i2c@1c000 { 2108 compatible = "amlogic,meson-axg-i2c"; 2109 status = "disabled"; 2110 reg = <0x0 0x1c000 0x0 0x20>; 2111 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 clocks = <&clkc CLKID_I2C>; 2115 }; 2116 2117 i2c2: i2c@1d000 { 2118 compatible = "amlogic,meson-axg-i2c"; 2119 status = "disabled"; 2120 reg = <0x0 0x1d000 0x0 0x20>; 2121 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 clocks = <&clkc CLKID_I2C>; 2125 }; 2126 2127 i2c1: i2c@1e000 { 2128 compatible = "amlogic,meson-axg-i2c"; 2129 status = "disabled"; 2130 reg = <0x0 0x1e000 0x0 0x20>; 2131 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 clocks = <&clkc CLKID_I2C>; 2135 }; 2136 2137 i2c0: i2c@1f000 { 2138 compatible = "amlogic,meson-axg-i2c"; 2139 status = "disabled"; 2140 reg = <0x0 0x1f000 0x0 0x20>; 2141 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2142 #address-cells = <1>; 2143 #size-cells = <0>; 2144 clocks = <&clkc CLKID_I2C>; 2145 }; 2146 2147 clk_msr: clock-measure@18000 { 2148 compatible = "amlogic,meson-g12a-clk-measure"; 2149 reg = <0x0 0x18000 0x0 0x10>; 2150 }; 2151 2152 uart_C: serial@22000 { 2153 compatible = "amlogic,meson-gx-uart"; 2154 reg = <0x0 0x22000 0x0 0x18>; 2155 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2156 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2157 clock-names = "xtal", "pclk", "baud"; 2158 status = "disabled"; 2159 }; 2160 2161 uart_B: serial@23000 { 2162 compatible = "amlogic,meson-gx-uart"; 2163 reg = <0x0 0x23000 0x0 0x18>; 2164 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2165 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2166 clock-names = "xtal", "pclk", "baud"; 2167 status = "disabled"; 2168 }; 2169 2170 uart_A: serial@24000 { 2171 compatible = "amlogic,meson-gx-uart"; 2172 reg = <0x0 0x24000 0x0 0x18>; 2173 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2174 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2175 clock-names = "xtal", "pclk", "baud"; 2176 status = "disabled"; 2177 }; 2178 }; 2179 2180 sd_emmc_b: sd@ffe05000 { 2181 compatible = "amlogic,meson-axg-mmc"; 2182 reg = <0x0 0xffe05000 0x0 0x800>; 2183 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2184 status = "disabled"; 2185 clocks = <&clkc CLKID_SD_EMMC_B>, 2186 <&clkc CLKID_SD_EMMC_B_CLK0>, 2187 <&clkc CLKID_FCLK_DIV2>; 2188 clock-names = "core", "clkin0", "clkin1"; 2189 resets = <&reset RESET_SD_EMMC_B>; 2190 }; 2191 2192 sd_emmc_c: mmc@ffe07000 { 2193 compatible = "amlogic,meson-axg-mmc"; 2194 reg = <0x0 0xffe07000 0x0 0x800>; 2195 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2196 status = "disabled"; 2197 clocks = <&clkc CLKID_SD_EMMC_C>, 2198 <&clkc CLKID_SD_EMMC_C_CLK0>, 2199 <&clkc CLKID_FCLK_DIV2>; 2200 clock-names = "core", "clkin0", "clkin1"; 2201 resets = <&reset RESET_SD_EMMC_C>; 2202 }; 2203 2204 usb: usb@ffe09000 { 2205 status = "disabled"; 2206 compatible = "amlogic,meson-g12a-usb-ctrl"; 2207 reg = <0x0 0xffe09000 0x0 0xa0>; 2208 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2209 #address-cells = <2>; 2210 #size-cells = <2>; 2211 ranges; 2212 2213 clocks = <&clkc CLKID_USB>; 2214 resets = <&reset RESET_USB>; 2215 2216 dr_mode = "otg"; 2217 2218 phys = <&usb2_phy0>, <&usb2_phy1>, 2219 <&usb3_pcie_phy PHY_TYPE_USB3>; 2220 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2221 2222 dwc2: usb@ff400000 { 2223 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2224 reg = <0x0 0xff400000 0x0 0x40000>; 2225 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2226 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2227 clock-names = "ddr"; 2228 phys = <&usb2_phy1>; 2229 dr_mode = "peripheral"; 2230 g-rx-fifo-size = <192>; 2231 g-np-tx-fifo-size = <128>; 2232 g-tx-fifo-size = <128 128 16 16 16>; 2233 }; 2234 2235 dwc3: usb@ff500000 { 2236 compatible = "snps,dwc3"; 2237 reg = <0x0 0xff500000 0x0 0x100000>; 2238 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2239 dr_mode = "host"; 2240 snps,dis_u2_susphy_quirk; 2241 snps,quirk-frame-length-adjustment; 2242 }; 2243 }; 2244 2245 mali: gpu@ffe40000 { 2246 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2247 reg = <0x0 0xffe40000 0x0 0x40000>; 2248 interrupt-parent = <&gic>; 2249 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2252 interrupt-names = "gpu", "mmu", "job"; 2253 clocks = <&clkc CLKID_MALI>; 2254 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2255 2256 /* 2257 * Mali clocking is provided by two identical clock paths 2258 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2259 * free mux to safely change frequency while running. 2260 */ 2261 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2262 <&clkc CLKID_MALI_0>, 2263 <&clkc CLKID_MALI>; /* Glitch free mux */ 2264 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2265 <0>, /* Do Nothing */ 2266 <&clkc CLKID_MALI_0>; 2267 assigned-clock-rates = <0>, /* Do Nothing */ 2268 <800000000>, 2269 <0>; /* Do Nothing */ 2270 }; 2271 }; 2272 2273 timer { 2274 compatible = "arm,armv8-timer"; 2275 interrupts = <GIC_PPI 13 2276 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2277 <GIC_PPI 14 2278 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2279 <GIC_PPI 11 2280 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2281 <GIC_PPI 10 2282 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2283 }; 2284 2285 xtal: xtal-clk { 2286 compatible = "fixed-clock"; 2287 clock-frequency = <24000000>; 2288 clock-output-names = "xtal"; 2289 #clock-cells = <0>; 2290 }; 2291 2292}; 2293