1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/phy/phy.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/clock/axg-audio-clkc.h>
9#include <dt-bindings/clock/g12a-clkc.h>
10#include <dt-bindings/clock/g12a-aoclkc.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
15
16/ {
17	compatible = "amlogic,g12a";
18
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	tdmif_a: audio-controller-0 {
24		compatible = "amlogic,axg-tdm-iface";
25		#sound-dai-cells = <0>;
26		sound-name-prefix = "TDM_A";
27		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30		clock-names = "mclk", "sclk", "lrclk";
31		status = "disabled";
32	};
33
34	tdmif_b: audio-controller-1 {
35		compatible = "amlogic,axg-tdm-iface";
36		#sound-dai-cells = <0>;
37		sound-name-prefix = "TDM_B";
38		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41		clock-names = "mclk", "sclk", "lrclk";
42		status = "disabled";
43	};
44
45	tdmif_c: audio-controller-2 {
46		compatible = "amlogic,axg-tdm-iface";
47		#sound-dai-cells = <0>;
48		sound-name-prefix = "TDM_C";
49		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52		clock-names = "mclk", "sclk", "lrclk";
53		status = "disabled";
54	};
55
56	cpus {
57		#address-cells = <0x2>;
58		#size-cells = <0x0>;
59
60		cpu0: cpu@0 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			reg = <0x0 0x0>;
64			enable-method = "psci";
65			next-level-cache = <&l2>;
66		};
67
68		cpu1: cpu@1 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53";
71			reg = <0x0 0x1>;
72			enable-method = "psci";
73			next-level-cache = <&l2>;
74		};
75
76		cpu2: cpu@2 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a53";
79			reg = <0x0 0x2>;
80			enable-method = "psci";
81			next-level-cache = <&l2>;
82		};
83
84		cpu3: cpu@3 {
85			device_type = "cpu";
86			compatible = "arm,cortex-a53";
87			reg = <0x0 0x3>;
88			enable-method = "psci";
89			next-level-cache = <&l2>;
90		};
91
92		l2: l2-cache0 {
93			compatible = "cache";
94		};
95	};
96
97	efuse: efuse {
98		compatible = "amlogic,meson-gxbb-efuse";
99		clocks = <&clkc CLKID_EFUSE>;
100		#address-cells = <1>;
101		#size-cells = <1>;
102		read-only;
103	};
104
105	psci {
106		compatible = "arm,psci-1.0";
107		method = "smc";
108	};
109
110	reserved-memory {
111		#address-cells = <2>;
112		#size-cells = <2>;
113		ranges;
114
115		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
116		secmon_reserved: secmon@5000000 {
117			reg = <0x0 0x05000000 0x0 0x300000>;
118			no-map;
119		};
120
121		linux,cma {
122			compatible = "shared-dma-pool";
123			reusable;
124			size = <0x0 0x10000000>;
125			alignment = <0x0 0x400000>;
126			linux,cma-default;
127		};
128	};
129
130	sm: secure-monitor {
131		compatible = "amlogic,meson-gxbb-sm";
132	};
133
134	soc {
135		compatible = "simple-bus";
136		#address-cells = <2>;
137		#size-cells = <2>;
138		ranges;
139
140		ethmac: ethernet@ff3f0000 {
141			compatible = "amlogic,meson-axg-dwmac",
142				     "snps,dwmac-3.70a",
143				     "snps,dwmac";
144			reg = <0x0 0xff3f0000 0x0 0x10000
145			       0x0 0xff634540 0x0 0x8>;
146			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
147			interrupt-names = "macirq";
148			clocks = <&clkc CLKID_ETH>,
149				 <&clkc CLKID_FCLK_DIV2>,
150				 <&clkc CLKID_MPLL2>;
151			clock-names = "stmmaceth", "clkin0", "clkin1";
152			status = "disabled";
153
154			mdio0: mdio {
155				#address-cells = <1>;
156				#size-cells = <0>;
157				compatible = "snps,dwmac-mdio";
158			};
159		};
160
161		apb: bus@ff600000 {
162			compatible = "simple-bus";
163			reg = <0x0 0xff600000 0x0 0x200000>;
164			#address-cells = <2>;
165			#size-cells = <2>;
166			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
167
168			hdmi_tx: hdmi-tx@0 {
169				compatible = "amlogic,meson-g12a-dw-hdmi";
170				reg = <0x0 0x0 0x0 0x10000>;
171				interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
172				resets = <&reset RESET_HDMITX_CAPB3>,
173					 <&reset RESET_HDMITX_PHY>,
174					 <&reset RESET_HDMITX>;
175				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
176				clocks = <&clkc CLKID_HDMI>,
177					 <&clkc CLKID_HTX_PCLK>,
178					 <&clkc CLKID_VPU_INTR>;
179				clock-names = "isfr", "iahb", "venci";
180				#address-cells = <1>;
181				#size-cells = <0>;
182				#sound-dai-cells = <0>;
183				status = "disabled";
184
185				/* VPU VENC Input */
186				hdmi_tx_venc_port: port@0 {
187					reg = <0>;
188
189					hdmi_tx_in: endpoint {
190						remote-endpoint = <&hdmi_tx_out>;
191					};
192				};
193
194				/* TMDS Output */
195				hdmi_tx_tmds_port: port@1 {
196					reg = <1>;
197				};
198			};
199
200			apb_efuse: bus@30000 {
201				compatible = "simple-bus";
202				reg = <0x0 0x30000 0x0 0x2000>;
203				#address-cells = <2>;
204				#size-cells = <2>;
205				ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
206
207				hwrng: rng@218 {
208					compatible = "amlogic,meson-rng";
209					reg = <0x0 0x218 0x0 0x4>;
210				};
211			};
212
213			periphs: bus@34400 {
214				compatible = "simple-bus";
215				reg = <0x0 0x34400 0x0 0x400>;
216				#address-cells = <2>;
217				#size-cells = <2>;
218				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
219
220				periphs_pinctrl: pinctrl@40 {
221					compatible = "amlogic,meson-g12a-periphs-pinctrl";
222					#address-cells = <2>;
223					#size-cells = <2>;
224					ranges;
225
226					gpio: bank@40 {
227						reg = <0x0 0x40  0x0 0x4c>,
228						      <0x0 0xe8  0x0 0x18>,
229						      <0x0 0x120 0x0 0x18>,
230						      <0x0 0x2c0 0x0 0x40>,
231						      <0x0 0x340 0x0 0x1c>;
232						reg-names = "gpio",
233							    "pull",
234							    "pull-enable",
235							    "mux",
236							    "ds";
237						gpio-controller;
238						#gpio-cells = <2>;
239						gpio-ranges = <&periphs_pinctrl 0 0 86>;
240					};
241
242					cec_ao_a_h_pins: cec_ao_a_h {
243						mux {
244							groups = "cec_ao_a_h";
245							function = "cec_ao_a_h";
246							bias-disable;
247						};
248					};
249
250					cec_ao_b_h_pins: cec_ao_b_h {
251						mux {
252							groups = "cec_ao_b_h";
253							function = "cec_ao_b_h";
254							bias-disable;
255						};
256					};
257
258					emmc_pins: emmc {
259						mux-0 {
260							groups = "emmc_nand_d0",
261								 "emmc_nand_d1",
262								 "emmc_nand_d2",
263								 "emmc_nand_d3",
264								 "emmc_nand_d4",
265								 "emmc_nand_d5",
266								 "emmc_nand_d6",
267								 "emmc_nand_d7",
268								 "emmc_cmd";
269							function = "emmc";
270							bias-pull-up;
271							drive-strength-microamp = <4000>;
272						};
273
274						mux-1 {
275							groups = "emmc_clk";
276							function = "emmc";
277							bias-disable;
278							drive-strength-microamp = <4000>;
279						};
280					};
281
282					emmc_ds_pins: emmc-ds {
283						mux {
284							groups = "emmc_nand_ds";
285							function = "emmc";
286							bias-pull-down;
287							drive-strength-microamp = <4000>;
288						};
289					};
290
291					emmc_clk_gate_pins: emmc_clk_gate {
292						mux {
293							groups = "BOOT_8";
294							function = "gpio_periphs";
295							bias-pull-down;
296							drive-strength-microamp = <4000>;
297						};
298					};
299
300					hdmitx_ddc_pins: hdmitx_ddc {
301						mux {
302							groups = "hdmitx_sda",
303								 "hdmitx_sck";
304							function = "hdmitx";
305							bias-disable;
306							drive-strength-microamp = <4000>;
307						};
308					};
309
310					hdmitx_hpd_pins: hdmitx_hpd {
311						mux {
312							groups = "hdmitx_hpd_in";
313							function = "hdmitx";
314							bias-disable;
315						};
316					};
317
318
319					i2c0_sda_c_pins: i2c0-sda-c {
320						mux {
321							groups = "i2c0_sda_c";
322							function = "i2c0";
323							bias-disable;
324							drive-strength-microamp = <3000>;
325
326						};
327					};
328
329					i2c0_sck_c_pins: i2c0-sck-c {
330						mux {
331							groups = "i2c0_sck_c";
332							function = "i2c0";
333							bias-disable;
334							drive-strength-microamp = <3000>;
335						};
336					};
337
338					i2c0_sda_z0_pins: i2c0-sda-z0 {
339						mux {
340							groups = "i2c0_sda_z0";
341							function = "i2c0";
342							bias-disable;
343							drive-strength-microamp = <3000>;
344						};
345					};
346
347					i2c0_sck_z1_pins: i2c0-sck-z1 {
348						mux {
349							groups = "i2c0_sck_z1";
350							function = "i2c0";
351							bias-disable;
352							drive-strength-microamp = <3000>;
353						};
354					};
355
356					i2c0_sda_z7_pins: i2c0-sda-z7 {
357						mux {
358							groups = "i2c0_sda_z7";
359							function = "i2c0";
360							bias-disable;
361							drive-strength-microamp = <3000>;
362						};
363					};
364
365					i2c0_sda_z8_pins: i2c0-sda-z8 {
366						mux {
367							groups = "i2c0_sda_z8";
368							function = "i2c0";
369							bias-disable;
370							drive-strength-microamp = <3000>;
371						};
372					};
373
374					i2c1_sda_x_pins: i2c1-sda-x {
375						mux {
376							groups = "i2c1_sda_x";
377							function = "i2c1";
378							bias-disable;
379							drive-strength-microamp = <3000>;
380						};
381					};
382
383					i2c1_sck_x_pins: i2c1-sck-x {
384						mux {
385							groups = "i2c1_sck_x";
386							function = "i2c1";
387							bias-disable;
388							drive-strength-microamp = <3000>;
389						};
390					};
391
392					i2c1_sda_h2_pins: i2c1-sda-h2 {
393						mux {
394							groups = "i2c1_sda_h2";
395							function = "i2c1";
396							bias-disable;
397							drive-strength-microamp = <3000>;
398						};
399					};
400
401					i2c1_sck_h3_pins: i2c1-sck-h3 {
402						mux {
403							groups = "i2c1_sck_h3";
404							function = "i2c1";
405							bias-disable;
406							drive-strength-microamp = <3000>;
407						};
408					};
409
410					i2c1_sda_h6_pins: i2c1-sda-h6 {
411						mux {
412							groups = "i2c1_sda_h6";
413							function = "i2c1";
414							bias-disable;
415							drive-strength-microamp = <3000>;
416						};
417					};
418
419					i2c1_sck_h7_pins: i2c1-sck-h7 {
420						mux {
421							groups = "i2c1_sck_h7";
422							function = "i2c1";
423							bias-disable;
424							drive-strength-microamp = <3000>;
425						};
426					};
427
428					i2c2_sda_x_pins: i2c2-sda-x {
429						mux {
430							groups = "i2c2_sda_x";
431							function = "i2c2";
432							bias-disable;
433							drive-strength-microamp = <3000>;
434						};
435					};
436
437					i2c2_sck_x_pins: i2c2-sck-x {
438						mux {
439							groups = "i2c2_sck_x";
440							function = "i2c2";
441							bias-disable;
442							drive-strength-microamp = <3000>;
443						};
444					};
445
446					i2c2_sda_z_pins: i2c2-sda-z {
447						mux {
448							groups = "i2c2_sda_z";
449							function = "i2c2";
450							bias-disable;
451							drive-strength-microamp = <3000>;
452						};
453					};
454
455					i2c2_sck_z_pins: i2c2-sck-z {
456						mux {
457							groups = "i2c2_sck_z";
458							function = "i2c2";
459							bias-disable;
460							drive-strength-microamp = <3000>;
461						};
462					};
463
464					i2c3_sda_h_pins: i2c3-sda-h {
465						mux {
466							groups = "i2c3_sda_h";
467							function = "i2c3";
468							bias-disable;
469							drive-strength-microamp = <3000>;
470						};
471					};
472
473					i2c3_sck_h_pins: i2c3-sck-h {
474						mux {
475							groups = "i2c3_sck_h";
476							function = "i2c3";
477							bias-disable;
478							drive-strength-microamp = <3000>;
479						};
480					};
481
482					i2c3_sda_a_pins: i2c3-sda-a {
483						mux {
484							groups = "i2c3_sda_a";
485							function = "i2c3";
486							bias-disable;
487							drive-strength-microamp = <3000>;
488						};
489					};
490
491					i2c3_sck_a_pins: i2c3-sck-a {
492						mux {
493							groups = "i2c3_sck_a";
494							function = "i2c3";
495							bias-disable;
496							drive-strength-microamp = <3000>;
497						};
498					};
499
500					mclk0_a_pins: mclk0-a {
501						mux {
502							groups = "mclk0_a";
503							function = "mclk0";
504							bias-disable;
505							drive-strength-microamp = <3000>;
506						};
507					};
508
509					mclk1_a_pins: mclk1-a {
510						mux {
511							groups = "mclk1_a";
512							function = "mclk1";
513							bias-disable;
514							drive-strength-microamp = <3000>;
515						};
516					};
517
518					mclk1_x_pins: mclk1-x {
519						mux {
520							groups = "mclk1_x";
521							function = "mclk1";
522							bias-disable;
523							drive-strength-microamp = <3000>;
524						};
525					};
526
527					mclk1_z_pins: mclk1-z {
528						mux {
529							groups = "mclk1_z";
530							function = "mclk1";
531							bias-disable;
532							drive-strength-microamp = <3000>;
533						};
534					};
535
536					pdm_din0_a_pins: pdm-din0-a {
537						mux {
538							groups = "pdm_din0_a";
539							function = "pdm";
540							bias-disable;
541						};
542					};
543
544					pdm_din0_c_pins: pdm-din0-c {
545						mux {
546							groups = "pdm_din0_c";
547							function = "pdm";
548							bias-disable;
549						};
550					};
551
552					pdm_din0_x_pins: pdm-din0-x {
553						mux {
554							groups = "pdm_din0_x";
555							function = "pdm";
556							bias-disable;
557						};
558					};
559
560					pdm_din0_z_pins: pdm-din0-z {
561						mux {
562							groups = "pdm_din0_z";
563							function = "pdm";
564							bias-disable;
565						};
566					};
567
568					pdm_din1_a_pins: pdm-din1-a {
569						mux {
570							groups = "pdm_din1_a";
571							function = "pdm";
572							bias-disable;
573						};
574					};
575
576					pdm_din1_c_pins: pdm-din1-c {
577						mux {
578							groups = "pdm_din1_c";
579							function = "pdm";
580							bias-disable;
581						};
582					};
583
584					pdm_din1_x_pins: pdm-din1-x {
585						mux {
586							groups = "pdm_din1_x";
587							function = "pdm";
588							bias-disable;
589						};
590					};
591
592					pdm_din1_z_pins: pdm-din1-z {
593						mux {
594							groups = "pdm_din1_z";
595							function = "pdm";
596							bias-disable;
597						};
598					};
599
600					pdm_din2_a_pins: pdm-din2-a {
601						mux {
602							groups = "pdm_din2_a";
603							function = "pdm";
604							bias-disable;
605						};
606					};
607
608					pdm_din2_c_pins: pdm-din2-c {
609						mux {
610							groups = "pdm_din2_c";
611							function = "pdm";
612							bias-disable;
613						};
614					};
615
616					pdm_din2_x_pins: pdm-din2-x {
617						mux {
618							groups = "pdm_din2_x";
619							function = "pdm";
620							bias-disable;
621						};
622					};
623
624					pdm_din2_z_pins: pdm-din2-z {
625						mux {
626							groups = "pdm_din2_z";
627							function = "pdm";
628							bias-disable;
629						};
630					};
631
632					pdm_din3_a_pins: pdm-din3-a {
633						mux {
634							groups = "pdm_din3_a";
635							function = "pdm";
636							bias-disable;
637						};
638					};
639
640					pdm_din3_c_pins: pdm-din3-c {
641						mux {
642							groups = "pdm_din3_c";
643							function = "pdm";
644							bias-disable;
645						};
646					};
647
648					pdm_din3_x_pins: pdm-din3-x {
649						mux {
650							groups = "pdm_din3_x";
651							function = "pdm";
652							bias-disable;
653						};
654					};
655
656					pdm_din3_z_pins: pdm-din3-z {
657						mux {
658							groups = "pdm_din3_z";
659							function = "pdm";
660							bias-disable;
661						};
662					};
663
664					pdm_dclk_a_pins: pdm-dclk-a {
665						mux {
666							groups = "pdm_dclk_a";
667							function = "pdm";
668							bias-disable;
669							drive-strength-microamp = <500>;
670						};
671					};
672
673					pdm_dclk_c_pins: pdm-dclk-c {
674						mux {
675							groups = "pdm_dclk_c";
676							function = "pdm";
677							bias-disable;
678							drive-strength-microamp = <500>;
679						};
680					};
681
682					pdm_dclk_x_pins: pdm-dclk-x {
683						mux {
684							groups = "pdm_dclk_x";
685							function = "pdm";
686							bias-disable;
687							drive-strength-microamp = <500>;
688						};
689					};
690
691					pdm_dclk_z_pins: pdm-dclk-z {
692						mux {
693							groups = "pdm_dclk_z";
694							function = "pdm";
695							bias-disable;
696							drive-strength-microamp = <500>;
697						};
698					};
699
700					pwm_a_pins: pwm-a {
701						mux {
702							groups = "pwm_a";
703							function = "pwm_a";
704							bias-disable;
705						};
706					};
707
708					pwm_b_x7_pins: pwm-b-x7 {
709						mux {
710							groups = "pwm_b_x7";
711							function = "pwm_b";
712							bias-disable;
713						};
714					};
715
716					pwm_b_x19_pins: pwm-b-x19 {
717						mux {
718							groups = "pwm_b_x19";
719							function = "pwm_b";
720							bias-disable;
721						};
722					};
723
724					pwm_c_c_pins: pwm-c-c {
725						mux {
726							groups = "pwm_c_c";
727							function = "pwm_c";
728							bias-disable;
729						};
730					};
731
732					pwm_c_x5_pins: pwm-c-x5 {
733						mux {
734							groups = "pwm_c_x5";
735							function = "pwm_c";
736							bias-disable;
737						};
738					};
739
740					pwm_c_x8_pins: pwm-c-x8 {
741						mux {
742							groups = "pwm_c_x8";
743							function = "pwm_c";
744							bias-disable;
745						};
746					};
747
748					pwm_d_x3_pins: pwm-d-x3 {
749						mux {
750							groups = "pwm_d_x3";
751							function = "pwm_d";
752							bias-disable;
753						};
754					};
755
756					pwm_d_x6_pins: pwm-d-x6 {
757						mux {
758							groups = "pwm_d_x6";
759							function = "pwm_d";
760							bias-disable;
761						};
762					};
763
764					pwm_e_pins: pwm-e {
765						mux {
766							groups = "pwm_e";
767							function = "pwm_e";
768							bias-disable;
769						};
770					};
771
772					pwm_f_x_pins: pwm-f-x {
773						mux {
774							groups = "pwm_f_x";
775							function = "pwm_f";
776							bias-disable;
777						};
778					};
779
780					pwm_f_h_pins: pwm-f-h {
781						mux {
782							groups = "pwm_f_h";
783							function = "pwm_f";
784							bias-disable;
785						};
786					};
787
788					sdcard_c_pins: sdcard_c {
789						mux-0 {
790							groups = "sdcard_d0_c",
791								 "sdcard_d1_c",
792								 "sdcard_d2_c",
793								 "sdcard_d3_c",
794								 "sdcard_cmd_c";
795							function = "sdcard";
796							bias-pull-up;
797							drive-strength-microamp = <4000>;
798						};
799
800						mux-1 {
801							groups = "sdcard_clk_c";
802							function = "sdcard";
803							bias-disable;
804							drive-strength-microamp = <4000>;
805						};
806					};
807
808					sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
809						mux {
810							groups = "GPIOC_4";
811							function = "gpio_periphs";
812							bias-pull-down;
813							drive-strength-microamp = <4000>;
814						};
815					};
816
817					sdcard_z_pins: sdcard_z {
818						mux-0 {
819							groups = "sdcard_d0_z",
820								 "sdcard_d1_z",
821								 "sdcard_d2_z",
822								 "sdcard_d3_z",
823								 "sdcard_cmd_z";
824							function = "sdcard";
825							bias-pull-up;
826							drive-strength-microamp = <4000>;
827						};
828
829						mux-1 {
830							groups = "sdcard_clk_z";
831							function = "sdcard";
832							bias-disable;
833							drive-strength-microamp = <4000>;
834						};
835					};
836
837					sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
838						mux {
839							groups = "GPIOZ_6";
840							function = "gpio_periphs";
841							bias-pull-down;
842							drive-strength-microamp = <4000>;
843						};
844					};
845
846					sdio_pins: sdio {
847						mux {
848							groups = "sdio_d0",
849								 "sdio_d1",
850								 "sdio_d2",
851								 "sdio_d3",
852								 "sdio_clk",
853								 "sdio_cmd";
854							function = "sdio";
855							bias-disable;
856							drive-strength-microamp = <4000>;
857						};
858					};
859
860					sdio_clk_gate_pins: sdio_clk_gate {
861						mux {
862							groups = "GPIOX_4";
863							function = "gpio_periphs";
864							bias-pull-down;
865							drive-strength-microamp = <4000>;
866						};
867					};
868
869					spdif_in_a10_pins: spdif-in-a10 {
870						mux {
871							groups = "spdif_in_a10";
872							function = "spdif_in";
873							bias-disable;
874						};
875					};
876
877					spdif_in_a12_pins: spdif-in-a12 {
878						mux {
879							groups = "spdif_in_a12";
880							function = "spdif_in";
881							bias-disable;
882						};
883					};
884
885					spdif_in_h_pins: spdif-in-h {
886						mux {
887							groups = "spdif_in_h";
888							function = "spdif_in";
889							bias-disable;
890						};
891					};
892
893					spdif_out_h_pins: spdif-out-h {
894						mux {
895							groups = "spdif_out_h";
896							function = "spdif_out";
897							drive-strength-microamp = <500>;
898							bias-disable;
899						};
900					};
901
902					spdif_out_a11_pins: spdif-out-a11 {
903						mux {
904							groups = "spdif_out_a11";
905							function = "spdif_out";
906							drive-strength-microamp = <500>;
907							bias-disable;
908						};
909					};
910
911					spdif_out_a13_pins: spdif-out-a13 {
912						mux {
913							groups = "spdif_out_a13";
914							function = "spdif_out";
915							drive-strength-microamp = <500>;
916							bias-disable;
917						};
918					};
919
920					tdm_a_din0_pins: tdm-a-din0 {
921						mux {
922							groups = "tdm_a_din0";
923							function = "tdm_a";
924							bias-disable;
925						};
926					};
927
928
929					tdm_a_din1_pins: tdm-a-din1 {
930						mux {
931							groups = "tdm_a_din1";
932							function = "tdm_a";
933							bias-disable;
934						};
935					};
936
937					tdm_a_dout0_pins: tdm-a-dout0 {
938						mux {
939							groups = "tdm_a_dout0";
940							function = "tdm_a";
941							bias-disable;
942							drive-strength-microamp = <3000>;
943						};
944					};
945
946					tdm_a_dout1_pins: tdm-a-dout1 {
947						mux {
948							groups = "tdm_a_dout1";
949							function = "tdm_a";
950							bias-disable;
951							drive-strength-microamp = <3000>;
952						};
953					};
954
955					tdm_a_fs_pins: tdm-a-fs {
956						mux {
957							groups = "tdm_a_fs";
958							function = "tdm_a";
959							bias-disable;
960							drive-strength-microamp = <3000>;
961						};
962					};
963
964					tdm_a_sclk_pins: tdm-a-sclk {
965						mux {
966							groups = "tdm_a_sclk";
967							function = "tdm_a";
968							bias-disable;
969							drive-strength-microamp = <3000>;
970						};
971					};
972
973					tdm_a_slv_fs_pins: tdm-a-slv-fs {
974						mux {
975							groups = "tdm_a_slv_fs";
976							function = "tdm_a";
977							bias-disable;
978						};
979					};
980
981
982					tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
983						mux {
984							groups = "tdm_a_slv_sclk";
985							function = "tdm_a";
986							bias-disable;
987						};
988					};
989
990					tdm_b_din0_pins: tdm-b-din0 {
991						mux {
992							groups = "tdm_b_din0";
993							function = "tdm_b";
994							bias-disable;
995						};
996					};
997
998					tdm_b_din1_pins: tdm-b-din1 {
999						mux {
1000							groups = "tdm_b_din1";
1001							function = "tdm_b";
1002							bias-disable;
1003						};
1004					};
1005
1006					tdm_b_din2_pins: tdm-b-din2 {
1007						mux {
1008							groups = "tdm_b_din2";
1009							function = "tdm_b";
1010							bias-disable;
1011						};
1012					};
1013
1014					tdm_b_din3_a_pins: tdm-b-din3-a {
1015						mux {
1016							groups = "tdm_b_din3_a";
1017							function = "tdm_b";
1018							bias-disable;
1019						};
1020					};
1021
1022					tdm_b_din3_h_pins: tdm-b-din3-h {
1023						mux {
1024							groups = "tdm_b_din3_h";
1025							function = "tdm_b";
1026							bias-disable;
1027						};
1028					};
1029
1030					tdm_b_dout0_pins: tdm-b-dout0 {
1031						mux {
1032							groups = "tdm_b_dout0";
1033							function = "tdm_b";
1034							bias-disable;
1035							drive-strength-microamp = <3000>;
1036						};
1037					};
1038
1039					tdm_b_dout1_pins: tdm-b-dout1 {
1040						mux {
1041							groups = "tdm_b_dout1";
1042							function = "tdm_b";
1043							bias-disable;
1044							drive-strength-microamp = <3000>;
1045						};
1046					};
1047
1048					tdm_b_dout2_pins: tdm-b-dout2 {
1049						mux {
1050							groups = "tdm_b_dout2";
1051							function = "tdm_b";
1052							bias-disable;
1053							drive-strength-microamp = <3000>;
1054						};
1055					};
1056
1057					tdm_b_dout3_a_pins: tdm-b-dout3-a {
1058						mux {
1059							groups = "tdm_b_dout3_a";
1060							function = "tdm_b";
1061							bias-disable;
1062							drive-strength-microamp = <3000>;
1063						};
1064					};
1065
1066					tdm_b_dout3_h_pins: tdm-b-dout3-h {
1067						mux {
1068							groups = "tdm_b_dout3_h";
1069							function = "tdm_b";
1070							bias-disable;
1071							drive-strength-microamp = <3000>;
1072						};
1073					};
1074
1075					tdm_b_fs_pins: tdm-b-fs {
1076						mux {
1077							groups = "tdm_b_fs";
1078							function = "tdm_b";
1079							bias-disable;
1080							drive-strength-microamp = <3000>;
1081						};
1082					};
1083
1084					tdm_b_sclk_pins: tdm-b-sclk {
1085						mux {
1086							groups = "tdm_b_sclk";
1087							function = "tdm_b";
1088							bias-disable;
1089							drive-strength-microamp = <3000>;
1090						};
1091					};
1092
1093					tdm_b_slv_fs_pins: tdm-b-slv-fs {
1094						mux {
1095							groups = "tdm_b_slv_fs";
1096							function = "tdm_b";
1097							bias-disable;
1098						};
1099					};
1100
1101					tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1102						mux {
1103							groups = "tdm_b_slv_sclk";
1104							function = "tdm_b";
1105							bias-disable;
1106						};
1107					};
1108
1109					tdm_c_din0_a_pins: tdm-c-din0-a {
1110						mux {
1111							groups = "tdm_c_din0_a";
1112							function = "tdm_c";
1113							bias-disable;
1114						};
1115					};
1116
1117					tdm_c_din0_z_pins: tdm-c-din0-z {
1118						mux {
1119							groups = "tdm_c_din0_z";
1120							function = "tdm_c";
1121							bias-disable;
1122						};
1123					};
1124
1125					tdm_c_din1_a_pins: tdm-c-din1-a {
1126						mux {
1127							groups = "tdm_c_din1_a";
1128							function = "tdm_c";
1129							bias-disable;
1130						};
1131					};
1132
1133					tdm_c_din1_z_pins: tdm-c-din1-z {
1134						mux {
1135							groups = "tdm_c_din1_z";
1136							function = "tdm_c";
1137							bias-disable;
1138						};
1139					};
1140
1141					tdm_c_din2_a_pins: tdm-c-din2-a {
1142						mux {
1143							groups = "tdm_c_din2_a";
1144							function = "tdm_c";
1145							bias-disable;
1146						};
1147					};
1148
1149					eth_leds_pins: eth-leds {
1150						mux {
1151							groups = "eth_link_led",
1152								 "eth_act_led";
1153							function = "eth";
1154							bias-disable;
1155						};
1156					};
1157
1158					eth_pins: eth {
1159						mux {
1160							groups = "eth_mdio",
1161								 "eth_mdc",
1162								 "eth_rgmii_rx_clk",
1163								 "eth_rx_dv",
1164								 "eth_rxd0",
1165								 "eth_rxd1",
1166								 "eth_txen",
1167								 "eth_txd0",
1168								 "eth_txd1";
1169							function = "eth";
1170							drive-strength-microamp = <4000>;
1171							bias-disable;
1172						};
1173					};
1174
1175					eth_rgmii_pins: eth-rgmii {
1176						mux {
1177							groups = "eth_rxd2_rgmii",
1178								 "eth_rxd3_rgmii",
1179								 "eth_rgmii_tx_clk",
1180								 "eth_txd2_rgmii",
1181								 "eth_txd3_rgmii";
1182							function = "eth";
1183							drive-strength-microamp = <4000>;
1184							bias-disable;
1185						};
1186					};
1187
1188					tdm_c_din2_z_pins: tdm-c-din2-z {
1189						mux {
1190							groups = "tdm_c_din2_z";
1191							function = "tdm_c";
1192							bias-disable;
1193						};
1194					};
1195
1196					tdm_c_din3_a_pins: tdm-c-din3-a {
1197						mux {
1198							groups = "tdm_c_din3_a";
1199							function = "tdm_c";
1200							bias-disable;
1201						};
1202					};
1203
1204					tdm_c_din3_z_pins: tdm-c-din3-z {
1205						mux {
1206							groups = "tdm_c_din3_z";
1207							function = "tdm_c";
1208							bias-disable;
1209						};
1210					};
1211
1212					tdm_c_dout0_a_pins: tdm-c-dout0-a {
1213						mux {
1214							groups = "tdm_c_dout0_a";
1215							function = "tdm_c";
1216							bias-disable;
1217							drive-strength-microamp = <3000>;
1218						};
1219					};
1220
1221					tdm_c_dout0_z_pins: tdm-c-dout0-z {
1222						mux {
1223							groups = "tdm_c_dout0_z";
1224							function = "tdm_c";
1225							bias-disable;
1226							drive-strength-microamp = <3000>;
1227						};
1228					};
1229
1230					tdm_c_dout1_a_pins: tdm-c-dout1-a {
1231						mux {
1232							groups = "tdm_c_dout1_a";
1233							function = "tdm_c";
1234							bias-disable;
1235							drive-strength-microamp = <3000>;
1236						};
1237					};
1238
1239					tdm_c_dout1_z_pins: tdm-c-dout1-z {
1240						mux {
1241							groups = "tdm_c_dout1_z";
1242							function = "tdm_c";
1243							bias-disable;
1244							drive-strength-microamp = <3000>;
1245						};
1246					};
1247
1248					tdm_c_dout2_a_pins: tdm-c-dout2-a {
1249						mux {
1250							groups = "tdm_c_dout2_a";
1251							function = "tdm_c";
1252							bias-disable;
1253							drive-strength-microamp = <3000>;
1254						};
1255					};
1256
1257					tdm_c_dout2_z_pins: tdm-c-dout2-z {
1258						mux {
1259							groups = "tdm_c_dout2_z";
1260							function = "tdm_c";
1261							bias-disable;
1262							drive-strength-microamp = <3000>;
1263						};
1264					};
1265
1266					tdm_c_dout3_a_pins: tdm-c-dout3-a {
1267						mux {
1268							groups = "tdm_c_dout3_a";
1269							function = "tdm_c";
1270							bias-disable;
1271							drive-strength-microamp = <3000>;
1272						};
1273					};
1274
1275					tdm_c_dout3_z_pins: tdm-c-dout3-z {
1276						mux {
1277							groups = "tdm_c_dout3_z";
1278							function = "tdm_c";
1279							bias-disable;
1280							drive-strength-microamp = <3000>;
1281						};
1282					};
1283
1284					tdm_c_fs_a_pins: tdm-c-fs-a {
1285						mux {
1286							groups = "tdm_c_fs_a";
1287							function = "tdm_c";
1288							bias-disable;
1289							drive-strength-microamp = <3000>;
1290						};
1291					};
1292
1293					tdm_c_fs_z_pins: tdm-c-fs-z {
1294						mux {
1295							groups = "tdm_c_fs_z";
1296							function = "tdm_c";
1297							bias-disable;
1298							drive-strength-microamp = <3000>;
1299						};
1300					};
1301
1302					tdm_c_sclk_a_pins: tdm-c-sclk-a {
1303						mux {
1304							groups = "tdm_c_sclk_a";
1305							function = "tdm_c";
1306							bias-disable;
1307							drive-strength-microamp = <3000>;
1308						};
1309					};
1310
1311					tdm_c_sclk_z_pins: tdm-c-sclk-z {
1312						mux {
1313							groups = "tdm_c_sclk_z";
1314							function = "tdm_c";
1315							bias-disable;
1316							drive-strength-microamp = <3000>;
1317						};
1318					};
1319
1320					tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1321						mux {
1322							groups = "tdm_c_slv_fs_a";
1323							function = "tdm_c";
1324							bias-disable;
1325						};
1326					};
1327
1328					tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1329						mux {
1330							groups = "tdm_c_slv_fs_z";
1331							function = "tdm_c";
1332							bias-disable;
1333						};
1334					};
1335
1336					tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1337						mux {
1338							groups = "tdm_c_slv_sclk_a";
1339							function = "tdm_c";
1340							bias-disable;
1341						};
1342					};
1343
1344					tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1345						mux {
1346							groups = "tdm_c_slv_sclk_z";
1347							function = "tdm_c";
1348							bias-disable;
1349						};
1350					};
1351
1352					uart_a_pins: uart-a {
1353						mux {
1354							groups = "uart_a_tx",
1355								 "uart_a_rx";
1356							function = "uart_a";
1357							bias-disable;
1358						};
1359					};
1360
1361					uart_a_cts_rts_pins: uart-a-cts-rts {
1362						mux {
1363							groups = "uart_a_cts",
1364								 "uart_a_rts";
1365							function = "uart_a";
1366							bias-disable;
1367						};
1368					};
1369
1370					uart_b_pins: uart-b {
1371						mux {
1372							groups = "uart_b_tx",
1373								 "uart_b_rx";
1374							function = "uart_b";
1375							bias-disable;
1376						};
1377					};
1378
1379					uart_c_pins: uart-c {
1380						mux {
1381							groups = "uart_c_tx",
1382								 "uart_c_rx";
1383							function = "uart_c";
1384							bias-disable;
1385						};
1386					};
1387
1388					uart_c_cts_rts_pins: uart-c-cts-rts {
1389						mux {
1390							groups = "uart_c_cts",
1391								 "uart_c_rts";
1392							function = "uart_c";
1393							bias-disable;
1394						};
1395					};
1396				};
1397			};
1398
1399			usb2_phy0: phy@36000 {
1400				compatible = "amlogic,g12a-usb2-phy";
1401				reg = <0x0 0x36000 0x0 0x2000>;
1402				clocks = <&xtal>;
1403				clock-names = "xtal";
1404				resets = <&reset RESET_USB_PHY20>;
1405				reset-names = "phy";
1406				#phy-cells = <0>;
1407			};
1408
1409			dmc: bus@38000 {
1410				compatible = "simple-bus";
1411				reg = <0x0 0x38000 0x0 0x400>;
1412				#address-cells = <2>;
1413				#size-cells = <2>;
1414				ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1415
1416				canvas: video-lut@48 {
1417					compatible = "amlogic,canvas";
1418					reg = <0x0 0x48 0x0 0x14>;
1419				};
1420			};
1421
1422			usb2_phy1: phy@3a000 {
1423				compatible = "amlogic,g12a-usb2-phy";
1424				reg = <0x0 0x3a000 0x0 0x2000>;
1425				clocks = <&xtal>;
1426				clock-names = "xtal";
1427				resets = <&reset RESET_USB_PHY21>;
1428				reset-names = "phy";
1429				#phy-cells = <0>;
1430			};
1431
1432			hiu: bus@3c000 {
1433				compatible = "simple-bus";
1434				reg = <0x0 0x3c000 0x0 0x1400>;
1435				#address-cells = <2>;
1436				#size-cells = <2>;
1437				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1438
1439				hhi: system-controller@0 {
1440					compatible = "amlogic,meson-gx-hhi-sysctrl",
1441						     "simple-mfd", "syscon";
1442					reg = <0 0 0 0x400>;
1443
1444					clkc: clock-controller {
1445						compatible = "amlogic,g12a-clkc";
1446						#clock-cells = <1>;
1447						clocks = <&xtal>;
1448						clock-names = "xtal";
1449					};
1450				};
1451			};
1452
1453			pdm: audio-controller@40000 {
1454				compatible = "amlogic,g12a-pdm",
1455					     "amlogic,axg-pdm";
1456				reg = <0x0 0x40000 0x0 0x34>;
1457				#sound-dai-cells = <0>;
1458				sound-name-prefix = "PDM";
1459				clocks = <&clkc_audio AUD_CLKID_PDM>,
1460					 <&clkc_audio AUD_CLKID_PDM_DCLK>,
1461					 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
1462				clock-names = "pclk", "dclk", "sysclk";
1463				status = "disabled";
1464			};
1465
1466			audio: bus@42000 {
1467				compatible = "simple-bus";
1468				reg = <0x0 0x42000 0x0 0x2000>;
1469				#address-cells = <2>;
1470				#size-cells = <2>;
1471				ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
1472
1473				clkc_audio: clock-controller@0 {
1474					status = "disabled";
1475					compatible = "amlogic,g12a-audio-clkc";
1476					reg = <0x0 0x0 0x0 0xb4>;
1477					#clock-cells = <1>;
1478
1479					clocks = <&clkc CLKID_AUDIO>,
1480						 <&clkc CLKID_MPLL0>,
1481						 <&clkc CLKID_MPLL1>,
1482						 <&clkc CLKID_MPLL2>,
1483						 <&clkc CLKID_MPLL3>,
1484						 <&clkc CLKID_HIFI_PLL>,
1485						 <&clkc CLKID_FCLK_DIV3>,
1486						 <&clkc CLKID_FCLK_DIV4>,
1487						 <&clkc CLKID_GP0_PLL>;
1488					clock-names = "pclk",
1489						      "mst_in0",
1490						      "mst_in1",
1491						      "mst_in2",
1492						      "mst_in3",
1493						      "mst_in4",
1494						      "mst_in5",
1495						      "mst_in6",
1496						      "mst_in7";
1497
1498					resets = <&reset RESET_AUDIO>;
1499				};
1500
1501				toddr_a: audio-controller@100 {
1502					compatible = "amlogic,g12a-toddr",
1503						     "amlogic,axg-toddr";
1504					reg = <0x0 0x100 0x0 0x1c>;
1505					#sound-dai-cells = <0>;
1506					sound-name-prefix = "TODDR_A";
1507					interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
1508					clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1509					resets = <&arb AXG_ARB_TODDR_A>;
1510					status = "disabled";
1511				};
1512
1513				toddr_b: audio-controller@140 {
1514					compatible = "amlogic,g12a-toddr",
1515						     "amlogic,axg-toddr";
1516					reg = <0x0 0x140 0x0 0x1c>;
1517					#sound-dai-cells = <0>;
1518					sound-name-prefix = "TODDR_B";
1519					interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
1520					clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1521					resets = <&arb AXG_ARB_TODDR_B>;
1522					status = "disabled";
1523				};
1524
1525				toddr_c: audio-controller@180 {
1526					compatible = "amlogic,g12a-toddr",
1527						     "amlogic,axg-toddr";
1528					reg = <0x0 0x180 0x0 0x1c>;
1529					#sound-dai-cells = <0>;
1530					sound-name-prefix = "TODDR_C";
1531					interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1532					clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1533					resets = <&arb AXG_ARB_TODDR_C>;
1534					status = "disabled";
1535				};
1536
1537				frddr_a: audio-controller@1c0 {
1538					compatible = "amlogic,g12a-frddr",
1539						     "amlogic,axg-frddr";
1540					reg = <0x0 0x1c0 0x0 0x1c>;
1541					#sound-dai-cells = <0>;
1542					sound-name-prefix = "FRDDR_A";
1543					interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
1544					clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1545					resets = <&arb AXG_ARB_FRDDR_A>;
1546					status = "disabled";
1547				};
1548
1549				frddr_b: audio-controller@200 {
1550					compatible = "amlogic,g12a-frddr",
1551						     "amlogic,axg-frddr";
1552					reg = <0x0 0x200 0x0 0x1c>;
1553					#sound-dai-cells = <0>;
1554					sound-name-prefix = "FRDDR_B";
1555					interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
1556					clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1557					resets = <&arb AXG_ARB_FRDDR_B>;
1558					status = "disabled";
1559				};
1560
1561				frddr_c: audio-controller@240 {
1562					compatible = "amlogic,g12a-frddr",
1563						     "amlogic,axg-frddr";
1564					reg = <0x0 0x240 0x0 0x1c>;
1565					#sound-dai-cells = <0>;
1566					sound-name-prefix = "FRDDR_C";
1567					interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
1568					clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1569					resets = <&arb AXG_ARB_FRDDR_C>;
1570					status = "disabled";
1571				};
1572
1573				arb: reset-controller@280 {
1574					status = "disabled";
1575					compatible = "amlogic,meson-axg-audio-arb";
1576					reg = <0x0 0x280 0x0 0x4>;
1577					#reset-cells = <1>;
1578					clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1579				};
1580
1581				tdmin_a: audio-controller@300 {
1582					compatible = "amlogic,g12a-tdmin",
1583						     "amlogic,axg-tdmin";
1584					reg = <0x0 0x300 0x0 0x40>;
1585					sound-name-prefix = "TDMIN_A";
1586					clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1587						 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1588						 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1589						 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1590						 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1591					clock-names = "pclk", "sclk", "sclk_sel",
1592						      "lrclk", "lrclk_sel";
1593					status = "disabled";
1594				};
1595
1596				tdmin_b: audio-controller@340 {
1597					compatible = "amlogic,g12a-tdmin",
1598						     "amlogic,axg-tdmin";
1599					reg = <0x0 0x340 0x0 0x40>;
1600					sound-name-prefix = "TDMIN_B";
1601					clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1602						 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1603						 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1604						 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1605						 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1606					clock-names = "pclk", "sclk", "sclk_sel",
1607						      "lrclk", "lrclk_sel";
1608					status = "disabled";
1609				};
1610
1611				tdmin_c: audio-controller@380 {
1612					compatible = "amlogic,g12a-tdmin",
1613						     "amlogic,axg-tdmin";
1614					reg = <0x0 0x380 0x0 0x40>;
1615					sound-name-prefix = "TDMIN_C";
1616					clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1617						 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1618						 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1619						 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1620						 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1621					clock-names = "pclk", "sclk", "sclk_sel",
1622						      "lrclk", "lrclk_sel";
1623					status = "disabled";
1624				};
1625
1626				tdmin_lb: audio-controller@3c0 {
1627					compatible = "amlogic,g12a-tdmin",
1628						     "amlogic,axg-tdmin";
1629					reg = <0x0 0x3c0 0x0 0x40>;
1630					sound-name-prefix = "TDMIN_LB";
1631					clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1632						 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1633						 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1634						 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1635						 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1636					clock-names = "pclk", "sclk", "sclk_sel",
1637						      "lrclk", "lrclk_sel";
1638					status = "disabled";
1639				};
1640
1641				spdifin: audio-controller@400 {
1642					compatible = "amlogic,g12a-spdifin",
1643						     "amlogic,axg-spdifin";
1644					reg = <0x0 0x400 0x0 0x30>;
1645					#sound-dai-cells = <0>;
1646					sound-name-prefix = "SPDIFIN";
1647					interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
1648					clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1649						 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1650					clock-names = "pclk", "refclk";
1651					status = "disabled";
1652				};
1653
1654				spdifout: audio-controller@480 {
1655					compatible = "amlogic,g12a-spdifout",
1656						     "amlogic,axg-spdifout";
1657					reg = <0x0 0x480 0x0 0x50>;
1658					#sound-dai-cells = <0>;
1659					sound-name-prefix = "SPDIFOUT";
1660					clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1661						 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1662					clock-names = "pclk", "mclk";
1663					status = "disabled";
1664				};
1665
1666				tdmout_a: audio-controller@500 {
1667					compatible = "amlogic,g12a-tdmout";
1668					reg = <0x0 0x500 0x0 0x40>;
1669					sound-name-prefix = "TDMOUT_A";
1670					clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1671						 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1672						 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1673						 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1674						 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1675					clock-names = "pclk", "sclk", "sclk_sel",
1676						      "lrclk", "lrclk_sel";
1677					status = "disabled";
1678				};
1679
1680				tdmout_b: audio-controller@540 {
1681					compatible = "amlogic,g12a-tdmout";
1682					reg = <0x0 0x540 0x0 0x40>;
1683					sound-name-prefix = "TDMOUT_B";
1684					clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1685						 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1686						 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1687						 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1688						 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1689					clock-names = "pclk", "sclk", "sclk_sel",
1690						      "lrclk", "lrclk_sel";
1691					status = "disabled";
1692				};
1693
1694				tdmout_c: audio-controller@580 {
1695					compatible = "amlogic,g12a-tdmout";
1696					reg = <0x0 0x580 0x0 0x40>;
1697					sound-name-prefix = "TDMOUT_C";
1698					clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1699						 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1700						 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1701						 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1702						 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1703					clock-names = "pclk", "sclk", "sclk_sel",
1704						      "lrclk", "lrclk_sel";
1705					status = "disabled";
1706				};
1707
1708				spdifout_b: audio-controller@680 {
1709					compatible = "amlogic,g12a-spdifout",
1710						     "amlogic,axg-spdifout";
1711					reg = <0x0 0x680 0x0 0x50>;
1712					#sound-dai-cells = <0>;
1713					sound-name-prefix = "SPDIFOUT_B";
1714					clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
1715						 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
1716					clock-names = "pclk", "mclk";
1717					status = "disabled";
1718				};
1719
1720				tohdmitx: audio-controller@744 {
1721					compatible = "amlogic,g12a-tohdmitx";
1722					reg = <0x0 0x744 0x0 0x4>;
1723					#sound-dai-cells = <1>;
1724					sound-name-prefix = "TOHDMITX";
1725					status = "disabled";
1726				};
1727			};
1728
1729			usb3_pcie_phy: phy@46000 {
1730				compatible = "amlogic,g12a-usb3-pcie-phy";
1731				reg = <0x0 0x46000 0x0 0x2000>;
1732				clocks = <&clkc CLKID_PCIE_PLL>;
1733				clock-names = "ref_clk";
1734				resets = <&reset RESET_PCIE_PHY>;
1735				reset-names = "phy";
1736				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1737				assigned-clock-rates = <100000000>;
1738				#phy-cells = <1>;
1739			};
1740
1741			eth_phy: mdio-multiplexer@4c000 {
1742				compatible = "amlogic,g12a-mdio-mux";
1743				reg = <0x0 0x4c000 0x0 0xa4>;
1744				clocks = <&clkc CLKID_ETH_PHY>,
1745					 <&xtal>,
1746					 <&clkc CLKID_MPLL_50M>;
1747				clock-names = "pclk", "clkin0", "clkin1";
1748				mdio-parent-bus = <&mdio0>;
1749				#address-cells = <1>;
1750				#size-cells = <0>;
1751
1752				ext_mdio: mdio@0 {
1753					reg = <0>;
1754					#address-cells = <1>;
1755					#size-cells = <0>;
1756				};
1757
1758				int_mdio: mdio@1 {
1759					reg = <1>;
1760					#address-cells = <1>;
1761					#size-cells = <0>;
1762
1763					internal_ephy: ethernet_phy@8 {
1764						compatible = "ethernet-phy-id0180.3301",
1765							     "ethernet-phy-ieee802.3-c22";
1766						interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1767						reg = <8>;
1768						max-speed = <100>;
1769					};
1770				};
1771			};
1772		};
1773
1774		aobus: bus@ff800000 {
1775			compatible = "simple-bus";
1776			reg = <0x0 0xff800000 0x0 0x100000>;
1777			#address-cells = <2>;
1778			#size-cells = <2>;
1779			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1780
1781			rti: sys-ctrl@0 {
1782				compatible = "amlogic,meson-gx-ao-sysctrl",
1783					     "simple-mfd", "syscon";
1784				reg = <0x0 0x0 0x0 0x100>;
1785				#address-cells = <2>;
1786				#size-cells = <2>;
1787				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1788
1789				clkc_AO: clock-controller {
1790					compatible = "amlogic,meson-g12a-aoclkc";
1791					#clock-cells = <1>;
1792					#reset-cells = <1>;
1793					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1794					clock-names = "xtal", "mpeg-clk";
1795				};
1796
1797				pwrc_vpu: power-controller-vpu {
1798					compatible = "amlogic,meson-g12a-pwrc-vpu";
1799					#power-domain-cells = <0>;
1800					amlogic,hhi-sysctrl = <&hhi>;
1801					resets = <&reset RESET_VIU>,
1802						 <&reset RESET_VENC>,
1803						 <&reset RESET_VCBUS>,
1804						 <&reset RESET_BT656>,
1805						 <&reset RESET_RDMA>,
1806						 <&reset RESET_VENCI>,
1807						 <&reset RESET_VENCP>,
1808						 <&reset RESET_VDAC>,
1809						 <&reset RESET_VDI6>,
1810						 <&reset RESET_VENCL>,
1811						 <&reset RESET_VID_LOCK>;
1812					clocks = <&clkc CLKID_VPU>,
1813						 <&clkc CLKID_VAPB>;
1814					clock-names = "vpu", "vapb";
1815					/*
1816					 * VPU clocking is provided by two identical clock paths
1817					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1818					 * free mux to safely change frequency while running.
1819					 * Same for VAPB but with a final gate after the glitch free mux.
1820					 */
1821					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1822							  <&clkc CLKID_VPU_0>,
1823							  <&clkc CLKID_VPU>, /* Glitch free mux */
1824							  <&clkc CLKID_VAPB_0_SEL>,
1825							  <&clkc CLKID_VAPB_0>,
1826							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1827					assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1828								 <0>, /* Do Nothing */
1829								 <&clkc CLKID_VPU_0>,
1830								 <&clkc CLKID_FCLK_DIV4>,
1831								 <0>, /* Do Nothing */
1832								 <&clkc CLKID_VAPB_0>;
1833					assigned-clock-rates = <0>, /* Do Nothing */
1834							       <666666666>,
1835							       <0>, /* Do Nothing */
1836							       <0>, /* Do Nothing */
1837							       <250000000>,
1838							       <0>; /* Do Nothing */
1839				};
1840
1841				ao_pinctrl: pinctrl@14 {
1842					compatible = "amlogic,meson-g12a-aobus-pinctrl";
1843					#address-cells = <2>;
1844					#size-cells = <2>;
1845					ranges;
1846
1847					gpio_ao: bank@14 {
1848						reg = <0x0 0x14 0x0 0x8>,
1849						      <0x0 0x1c 0x0 0x8>,
1850						      <0x0 0x24 0x0 0x14>;
1851						reg-names = "mux",
1852							    "ds",
1853							    "gpio";
1854						gpio-controller;
1855						#gpio-cells = <2>;
1856						gpio-ranges = <&ao_pinctrl 0 0 15>;
1857					};
1858
1859					i2c_ao_sck_pins: i2c_ao_sck_pins {
1860						mux {
1861							groups = "i2c_ao_sck";
1862							function = "i2c_ao";
1863							bias-disable;
1864							drive-strength-microamp = <3000>;
1865						};
1866					};
1867
1868					i2c_ao_sda_pins: i2c_ao_sda {
1869						mux {
1870							groups = "i2c_ao_sda";
1871							function = "i2c_ao";
1872							bias-disable;
1873							drive-strength-microamp = <3000>;
1874						};
1875					};
1876
1877					i2c_ao_sck_e_pins: i2c_ao_sck_e {
1878						mux {
1879							groups = "i2c_ao_sck_e";
1880							function = "i2c_ao";
1881							bias-disable;
1882							drive-strength-microamp = <3000>;
1883						};
1884					};
1885
1886					i2c_ao_sda_e_pins: i2c_ao_sda_e {
1887						mux {
1888							groups = "i2c_ao_sda_e";
1889							function = "i2c_ao";
1890							bias-disable;
1891							drive-strength-microamp = <3000>;
1892						};
1893					};
1894
1895					mclk0_ao_pins: mclk0-ao {
1896						mux {
1897							groups = "mclk0_ao";
1898							function = "mclk0_ao";
1899							bias-disable;
1900							drive-strength-microamp = <3000>;
1901						};
1902					};
1903
1904					tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1905						mux {
1906							groups = "tdm_ao_b_din0";
1907							function = "tdm_ao_b";
1908							bias-disable;
1909						};
1910					};
1911
1912					spdif_ao_out_pins: spdif-ao-out {
1913						mux {
1914							groups = "spdif_ao_out";
1915							function = "spdif_ao_out";
1916							drive-strength-microamp = <500>;
1917							bias-disable;
1918						};
1919					};
1920
1921					tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1922						mux {
1923							groups = "tdm_ao_b_din1";
1924							function = "tdm_ao_b";
1925							bias-disable;
1926						};
1927					};
1928
1929					tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1930						mux {
1931							groups = "tdm_ao_b_din2";
1932							function = "tdm_ao_b";
1933							bias-disable;
1934						};
1935					};
1936
1937					tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1938						mux {
1939							groups = "tdm_ao_b_dout0";
1940							function = "tdm_ao_b";
1941							bias-disable;
1942							drive-strength-microamp = <3000>;
1943						};
1944					};
1945
1946					tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1947						mux {
1948							groups = "tdm_ao_b_dout1";
1949							function = "tdm_ao_b";
1950							bias-disable;
1951							drive-strength-microamp = <3000>;
1952						};
1953					};
1954
1955					tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1956						mux {
1957							groups = "tdm_ao_b_dout2";
1958							function = "tdm_ao_b";
1959							bias-disable;
1960							drive-strength-microamp = <3000>;
1961						};
1962					};
1963
1964					tdm_ao_b_fs_pins: tdm-ao-b-fs {
1965						mux {
1966							groups = "tdm_ao_b_fs";
1967							function = "tdm_ao_b";
1968							bias-disable;
1969							drive-strength-microamp = <3000>;
1970						};
1971					};
1972
1973					tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1974						mux {
1975							groups = "tdm_ao_b_sclk";
1976							function = "tdm_ao_b";
1977							bias-disable;
1978							drive-strength-microamp = <3000>;
1979						};
1980					};
1981
1982					tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1983						mux {
1984							groups = "tdm_ao_b_slv_fs";
1985							function = "tdm_ao_b";
1986							bias-disable;
1987						};
1988					};
1989
1990					tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1991						mux {
1992							groups = "tdm_ao_b_slv_sclk";
1993							function = "tdm_ao_b";
1994							bias-disable;
1995						};
1996					};
1997
1998					uart_ao_a_pins: uart-a-ao {
1999						mux {
2000							groups = "uart_ao_a_tx",
2001								 "uart_ao_a_rx";
2002							function = "uart_ao_a";
2003							bias-disable;
2004						};
2005					};
2006
2007					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
2008						mux {
2009							groups = "uart_ao_a_cts",
2010								 "uart_ao_a_rts";
2011							function = "uart_ao_a";
2012							bias-disable;
2013						};
2014					};
2015
2016					pwm_ao_a_pins: pwm-ao-a {
2017						mux {
2018							groups = "pwm_ao_a";
2019							function = "pwm_ao_a";
2020							bias-disable;
2021						};
2022					};
2023
2024					pwm_ao_b_pins: pwm-ao-b {
2025						mux {
2026							groups = "pwm_ao_b";
2027							function = "pwm_ao_b";
2028							bias-disable;
2029						};
2030					};
2031
2032					pwm_ao_c_4_pins: pwm-ao-c-4 {
2033						mux {
2034							groups = "pwm_ao_c_4";
2035							function = "pwm_ao_c";
2036							bias-disable;
2037						};
2038					};
2039
2040					pwm_ao_c_6_pins: pwm-ao-c-6 {
2041						mux {
2042							groups = "pwm_ao_c_6";
2043							function = "pwm_ao_c";
2044							bias-disable;
2045						};
2046					};
2047
2048					pwm_ao_d_5_pins: pwm-ao-d-5 {
2049						mux {
2050							groups = "pwm_ao_d_5";
2051							function = "pwm_ao_d";
2052							bias-disable;
2053						};
2054					};
2055
2056					pwm_ao_d_10_pins: pwm-ao-d-10 {
2057						mux {
2058							groups = "pwm_ao_d_10";
2059							function = "pwm_ao_d";
2060							bias-disable;
2061						};
2062					};
2063
2064					pwm_ao_d_e_pins: pwm-ao-d-e {
2065						mux {
2066							groups = "pwm_ao_d_e";
2067							function = "pwm_ao_d";
2068						};
2069					};
2070
2071					remote_input_ao_pins: remote-input-ao {
2072						mux {
2073							groups = "remote_ao_input";
2074							function = "remote_ao_input";
2075							bias-disable;
2076						};
2077					};
2078				};
2079			};
2080
2081			cec_AO: cec@100 {
2082				compatible = "amlogic,meson-gx-ao-cec";
2083				reg = <0x0 0x00100 0x0 0x14>;
2084				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2085				clocks = <&clkc_AO CLKID_AO_CEC>;
2086				clock-names = "core";
2087				status = "disabled";
2088			};
2089
2090			sec_AO: ao-secure@140 {
2091				compatible = "amlogic,meson-gx-ao-secure", "syscon";
2092				reg = <0x0 0x140 0x0 0x140>;
2093				amlogic,has-chip-id;
2094			};
2095
2096			cecb_AO: cec@280 {
2097				compatible = "amlogic,meson-g12a-ao-cec";
2098				reg = <0x0 0x00280 0x0 0x1c>;
2099				interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2100				clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2101				clock-names = "oscin";
2102				status = "disabled";
2103			};
2104
2105			pwm_AO_cd: pwm@2000 {
2106				compatible = "amlogic,meson-g12a-ao-pwm-cd";
2107				reg = <0x0 0x2000 0x0 0x20>;
2108				#pwm-cells = <3>;
2109				status = "disabled";
2110			};
2111
2112			uart_AO: serial@3000 {
2113				compatible = "amlogic,meson-gx-uart",
2114					     "amlogic,meson-ao-uart";
2115				reg = <0x0 0x3000 0x0 0x18>;
2116				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2117				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2118				clock-names = "xtal", "pclk", "baud";
2119				status = "disabled";
2120			};
2121
2122			uart_AO_B: serial@4000 {
2123				compatible = "amlogic,meson-gx-uart",
2124					     "amlogic,meson-ao-uart";
2125				reg = <0x0 0x4000 0x0 0x18>;
2126				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2127				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2128				clock-names = "xtal", "pclk", "baud";
2129				status = "disabled";
2130			};
2131
2132			i2c_AO: i2c@5000 {
2133				compatible = "amlogic,meson-axg-i2c";
2134				status = "disabled";
2135				reg = <0x0 0x05000 0x0 0x20>;
2136				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2137				#address-cells = <1>;
2138				#size-cells = <0>;
2139				clocks = <&clkc CLKID_I2C>;
2140			};
2141
2142			pwm_AO_ab: pwm@7000 {
2143				compatible = "amlogic,meson-g12a-ao-pwm-ab";
2144				reg = <0x0 0x7000 0x0 0x20>;
2145				#pwm-cells = <3>;
2146				status = "disabled";
2147			};
2148
2149			ir: ir@8000 {
2150				compatible = "amlogic,meson-gxbb-ir";
2151				reg = <0x0 0x8000 0x0 0x20>;
2152				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2153				status = "disabled";
2154			};
2155
2156			saradc: adc@9000 {
2157				compatible = "amlogic,meson-g12a-saradc",
2158					     "amlogic,meson-saradc";
2159				reg = <0x0 0x9000 0x0 0x48>;
2160				#io-channel-cells = <1>;
2161				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2162				clocks = <&xtal>,
2163					 <&clkc_AO CLKID_AO_SAR_ADC>,
2164					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2165					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2166				clock-names = "clkin", "core", "adc_clk", "adc_sel";
2167				status = "disabled";
2168			};
2169		};
2170
2171		vpu: vpu@ff900000 {
2172			compatible = "amlogic,meson-g12a-vpu";
2173			reg = <0x0 0xff900000 0x0 0x100000>,
2174			      <0x0 0xff63c000 0x0 0x1000>;
2175			reg-names = "vpu", "hhi";
2176			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2177			#address-cells = <1>;
2178			#size-cells = <0>;
2179			amlogic,canvas = <&canvas>;
2180			power-domains = <&pwrc_vpu>;
2181
2182			/* CVBS VDAC output port */
2183			cvbs_vdac_port: port@0 {
2184				reg = <0>;
2185			};
2186
2187			/* HDMI-TX output port */
2188			hdmi_tx_port: port@1 {
2189				reg = <1>;
2190
2191				hdmi_tx_out: endpoint {
2192					remote-endpoint = <&hdmi_tx_in>;
2193				};
2194			};
2195		};
2196
2197		gic: interrupt-controller@ffc01000 {
2198			compatible = "arm,gic-400";
2199			reg = <0x0 0xffc01000 0 0x1000>,
2200			      <0x0 0xffc02000 0 0x2000>,
2201			      <0x0 0xffc04000 0 0x2000>,
2202			      <0x0 0xffc06000 0 0x2000>;
2203			interrupt-controller;
2204			interrupts = <GIC_PPI 9
2205				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2206			#interrupt-cells = <3>;
2207			#address-cells = <0>;
2208		};
2209
2210		cbus: bus@ffd00000 {
2211			compatible = "simple-bus";
2212			reg = <0x0 0xffd00000 0x0 0x100000>;
2213			#address-cells = <2>;
2214			#size-cells = <2>;
2215			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2216
2217			reset: reset-controller@1004 {
2218				compatible = "amlogic,meson-g12a-reset",
2219					     "amlogic,meson-axg-reset";
2220				reg = <0x0 0x1004 0x0 0x9c>;
2221				#reset-cells = <1>;
2222			};
2223
2224			gpio_intc: interrupt-controller@f080 {
2225				compatible = "amlogic,meson-g12a-gpio-intc",
2226					     "amlogic,meson-gpio-intc";
2227				reg = <0x0 0xf080 0x0 0x10>;
2228				interrupt-controller;
2229				#interrupt-cells = <2>;
2230				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2231			};
2232
2233			pwm_ef: pwm@19000 {
2234				compatible = "amlogic,meson-g12a-ee-pwm";
2235				reg = <0x0 0x19000 0x0 0x20>;
2236				#pwm-cells = <3>;
2237				status = "disabled";
2238			};
2239
2240			pwm_cd: pwm@1a000 {
2241				compatible = "amlogic,meson-g12a-ee-pwm";
2242				reg = <0x0 0x1a000 0x0 0x20>;
2243				#pwm-cells = <3>;
2244				status = "disabled";
2245			};
2246
2247			pwm_ab: pwm@1b000 {
2248				compatible = "amlogic,meson-g12a-ee-pwm";
2249				reg = <0x0 0x1b000 0x0 0x20>;
2250				#pwm-cells = <3>;
2251				status = "disabled";
2252			};
2253
2254			i2c3: i2c@1c000 {
2255				compatible = "amlogic,meson-axg-i2c";
2256				status = "disabled";
2257				reg = <0x0 0x1c000 0x0 0x20>;
2258				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2259				#address-cells = <1>;
2260				#size-cells = <0>;
2261				clocks = <&clkc CLKID_I2C>;
2262			};
2263
2264			i2c2: i2c@1d000 {
2265				compatible = "amlogic,meson-axg-i2c";
2266				status = "disabled";
2267				reg = <0x0 0x1d000 0x0 0x20>;
2268				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2269				#address-cells = <1>;
2270				#size-cells = <0>;
2271				clocks = <&clkc CLKID_I2C>;
2272			};
2273
2274			i2c1: i2c@1e000 {
2275				compatible = "amlogic,meson-axg-i2c";
2276				status = "disabled";
2277				reg = <0x0 0x1e000 0x0 0x20>;
2278				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2279				#address-cells = <1>;
2280				#size-cells = <0>;
2281				clocks = <&clkc CLKID_I2C>;
2282			};
2283
2284			i2c0: i2c@1f000 {
2285				compatible = "amlogic,meson-axg-i2c";
2286				status = "disabled";
2287				reg = <0x0 0x1f000 0x0 0x20>;
2288				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2289				#address-cells = <1>;
2290				#size-cells = <0>;
2291				clocks = <&clkc CLKID_I2C>;
2292			};
2293
2294			clk_msr: clock-measure@18000 {
2295				compatible = "amlogic,meson-g12a-clk-measure";
2296				reg = <0x0 0x18000 0x0 0x10>;
2297			};
2298
2299			uart_C: serial@22000 {
2300				compatible = "amlogic,meson-gx-uart";
2301				reg = <0x0 0x22000 0x0 0x18>;
2302				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2303				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2304				clock-names = "xtal", "pclk", "baud";
2305				status = "disabled";
2306			};
2307
2308			uart_B: serial@23000 {
2309				compatible = "amlogic,meson-gx-uart";
2310				reg = <0x0 0x23000 0x0 0x18>;
2311				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2312				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2313				clock-names = "xtal", "pclk", "baud";
2314				status = "disabled";
2315			};
2316
2317			uart_A: serial@24000 {
2318				compatible = "amlogic,meson-gx-uart";
2319				reg = <0x0 0x24000 0x0 0x18>;
2320				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2321				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2322				clock-names = "xtal", "pclk", "baud";
2323				status = "disabled";
2324			};
2325		};
2326
2327		sd_emmc_a: sd@ffe03000 {
2328			compatible = "amlogic,meson-axg-mmc";
2329			reg = <0x0 0xffe03000 0x0 0x800>;
2330			interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2331			status = "disabled";
2332			clocks = <&clkc CLKID_SD_EMMC_A>,
2333				 <&clkc CLKID_SD_EMMC_A_CLK0>,
2334				 <&clkc CLKID_FCLK_DIV2>;
2335			clock-names = "core", "clkin0", "clkin1";
2336			resets = <&reset RESET_SD_EMMC_A>;
2337			amlogic,dram-access-quirk;
2338		};
2339
2340		sd_emmc_b: sd@ffe05000 {
2341			compatible = "amlogic,meson-axg-mmc";
2342			reg = <0x0 0xffe05000 0x0 0x800>;
2343			interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2344			status = "disabled";
2345			clocks = <&clkc CLKID_SD_EMMC_B>,
2346				 <&clkc CLKID_SD_EMMC_B_CLK0>,
2347				 <&clkc CLKID_FCLK_DIV2>;
2348			clock-names = "core", "clkin0", "clkin1";
2349			resets = <&reset RESET_SD_EMMC_B>;
2350		};
2351
2352		sd_emmc_c: mmc@ffe07000 {
2353			compatible = "amlogic,meson-axg-mmc";
2354			reg = <0x0 0xffe07000 0x0 0x800>;
2355			interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2356			status = "disabled";
2357			clocks = <&clkc CLKID_SD_EMMC_C>,
2358				 <&clkc CLKID_SD_EMMC_C_CLK0>,
2359				 <&clkc CLKID_FCLK_DIV2>;
2360			clock-names = "core", "clkin0", "clkin1";
2361			resets = <&reset RESET_SD_EMMC_C>;
2362		};
2363
2364		usb: usb@ffe09000 {
2365			status = "disabled";
2366			compatible = "amlogic,meson-g12a-usb-ctrl";
2367			reg = <0x0 0xffe09000 0x0 0xa0>;
2368			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2369			#address-cells = <2>;
2370			#size-cells = <2>;
2371			ranges;
2372
2373			clocks = <&clkc CLKID_USB>;
2374			resets = <&reset RESET_USB>;
2375
2376			dr_mode = "otg";
2377
2378			phys = <&usb2_phy0>, <&usb2_phy1>,
2379			       <&usb3_pcie_phy PHY_TYPE_USB3>;
2380			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2381
2382			dwc2: usb@ff400000 {
2383				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2384				reg = <0x0 0xff400000 0x0 0x40000>;
2385				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2386				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2387				clock-names = "ddr";
2388				phys = <&usb2_phy1>;
2389				dr_mode = "peripheral";
2390				g-rx-fifo-size = <192>;
2391				g-np-tx-fifo-size = <128>;
2392				g-tx-fifo-size = <128 128 16 16 16>;
2393			};
2394
2395			dwc3: usb@ff500000 {
2396				compatible = "snps,dwc3";
2397				reg = <0x0 0xff500000 0x0 0x100000>;
2398				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2399				dr_mode = "host";
2400				snps,dis_u2_susphy_quirk;
2401				snps,quirk-frame-length-adjustment;
2402			};
2403		};
2404
2405		mali: gpu@ffe40000 {
2406			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2407			reg = <0x0 0xffe40000 0x0 0x40000>;
2408			interrupt-parent = <&gic>;
2409			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2410				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2411				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
2412			interrupt-names = "gpu", "mmu", "job";
2413			clocks = <&clkc CLKID_MALI>;
2414			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2415
2416			/*
2417			 * Mali clocking is provided by two identical clock paths
2418			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2419			 * free mux to safely change frequency while running.
2420			 */
2421			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2422					  <&clkc CLKID_MALI_0>,
2423					  <&clkc CLKID_MALI>; /* Glitch free mux */
2424			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2425						 <0>, /* Do Nothing */
2426						 <&clkc CLKID_MALI_0>;
2427			assigned-clock-rates = <0>, /* Do Nothing */
2428					       <800000000>,
2429					       <0>; /* Do Nothing */
2430		};
2431	};
2432
2433	timer {
2434		compatible = "arm,armv8-timer";
2435		interrupts = <GIC_PPI 13
2436			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2437			     <GIC_PPI 14
2438			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2439			     <GIC_PPI 11
2440			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2441			     <GIC_PPI 10
2442			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2443	};
2444
2445	xtal: xtal-clk {
2446		compatible = "fixed-clock";
2447		clock-frequency = <24000000>;
2448		clock-output-names = "xtal";
2449		#clock-cells = <0>;
2450	};
2451
2452};
2453